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radv: set the maximum number of IBs per submit to 192
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
373 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
374 (device->rad_info.chip_class >= VI &&
375 device->rad_info.me_fw_feature >= 41);
376
377 radv_physical_device_init_mem_types(device);
378 radv_fill_device_extension_table(device, &device->supported_extensions);
379
380 device->bus_info = *drm_device->businfo.pci;
381
382 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
383 ac_print_gpu_info(&device->rad_info);
384
385 /* The WSI is structured as a layer on top of the driver, so this has
386 * to be the last part of initialization (at least until we get other
387 * semi-layers).
388 */
389 result = radv_init_wsi(device);
390 if (result != VK_SUCCESS) {
391 device->ws->destroy(device->ws);
392 vk_error(instance, result);
393 goto fail;
394 }
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {"nobinning", RADV_DEBUG_NOBINNING},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 client_version = VK_API_VERSION_1_0;
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
743 .textureCompressionASTC_LDR = false,
744 .textureCompressionBC = true,
745 .occlusionQueryPrecise = true,
746 .pipelineStatisticsQuery = true,
747 .vertexPipelineStoresAndAtomics = true,
748 .fragmentStoresAndAtomics = true,
749 .shaderTessellationAndGeometryPointSize = true,
750 .shaderImageGatherExtended = true,
751 .shaderStorageImageExtendedFormats = true,
752 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
753 .shaderUniformBufferArrayDynamicIndexing = true,
754 .shaderSampledImageArrayDynamicIndexing = true,
755 .shaderStorageBufferArrayDynamicIndexing = true,
756 .shaderStorageImageArrayDynamicIndexing = true,
757 .shaderStorageImageReadWithoutFormat = true,
758 .shaderStorageImageWriteWithoutFormat = true,
759 .shaderClipDistance = true,
760 .shaderCullDistance = true,
761 .shaderFloat64 = true,
762 .shaderInt64 = true,
763 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
764 .sparseBinding = true,
765 .variableMultisampleRate = true,
766 .inheritedQueries = true,
767 };
768 }
769
770 void radv_GetPhysicalDeviceFeatures2(
771 VkPhysicalDevice physicalDevice,
772 VkPhysicalDeviceFeatures2 *pFeatures)
773 {
774 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
775 vk_foreach_struct(ext, pFeatures->pNext) {
776 switch (ext->sType) {
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
778 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
779 features->variablePointersStorageBuffer = true;
780 features->variablePointers = true;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
784 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
785 features->multiview = true;
786 features->multiviewGeometryShader = true;
787 features->multiviewTessellationShader = true;
788 break;
789 }
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
791 VkPhysicalDeviceShaderDrawParameterFeatures *features =
792 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
793 features->shaderDrawParameters = true;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
797 VkPhysicalDeviceProtectedMemoryFeatures *features =
798 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
799 features->protectedMemory = false;
800 break;
801 }
802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
803 VkPhysicalDevice16BitStorageFeatures *features =
804 (VkPhysicalDevice16BitStorageFeatures*)ext;
805 bool enabled = pdevice->rad_info.chip_class >= VI;
806 features->storageBuffer16BitAccess = enabled;
807 features->uniformAndStorageBuffer16BitAccess = enabled;
808 features->storagePushConstant16 = enabled;
809 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
810 break;
811 }
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
813 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
814 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
815 features->samplerYcbcrConversion = false;
816 break;
817 }
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
819 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
820 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
821 features->shaderInputAttachmentArrayDynamicIndexing = true;
822 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
823 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
824 features->shaderUniformBufferArrayNonUniformIndexing = false;
825 features->shaderSampledImageArrayNonUniformIndexing = false;
826 features->shaderStorageBufferArrayNonUniformIndexing = false;
827 features->shaderStorageImageArrayNonUniformIndexing = false;
828 features->shaderInputAttachmentArrayNonUniformIndexing = false;
829 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
830 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
831 features->descriptorBindingUniformBufferUpdateAfterBind = true;
832 features->descriptorBindingSampledImageUpdateAfterBind = true;
833 features->descriptorBindingStorageImageUpdateAfterBind = true;
834 features->descriptorBindingStorageBufferUpdateAfterBind = true;
835 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
836 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingUpdateUnusedWhilePending = true;
838 features->descriptorBindingPartiallyBound = true;
839 features->descriptorBindingVariableDescriptorCount = true;
840 features->runtimeDescriptorArray = true;
841 break;
842 }
843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
844 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
845 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
846 features->conditionalRendering = true;
847 features->inheritedConditionalRendering = false;
848 break;
849 }
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
851 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
852 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
853 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
854 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
858 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
859 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
860 features->transformFeedback = true;
861 features->geometryStreams = true;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
865 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
866 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
867 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
871 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
872 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
873 features->memoryPriority = VK_TRUE;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
877 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
878 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
879 features->bufferDeviceAddress = true;
880 features->bufferDeviceAddressCaptureReplay = false;
881 features->bufferDeviceAddressMultiDevice = false;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
885 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
886 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
887 features->depthClipEnable = true;
888 break;
889 }
890 default:
891 break;
892 }
893 }
894 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
895 }
896
897 void radv_GetPhysicalDeviceProperties(
898 VkPhysicalDevice physicalDevice,
899 VkPhysicalDeviceProperties* pProperties)
900 {
901 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
902 VkSampleCountFlags sample_counts = 0xf;
903
904 /* make sure that the entire descriptor set is addressable with a signed
905 * 32-bit int. So the sum of all limits scaled by descriptor size has to
906 * be at most 2 GiB. the combined image & samples object count as one of
907 * both. This limit is for the pipeline layout, not for the set layout, but
908 * there is no set limit, so we just set a pipeline limit. I don't think
909 * any app is going to hit this soon. */
910 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
911 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
912 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
913 32 /* sampler, largest when combined with image */ +
914 64 /* sampled image */ +
915 64 /* storage image */);
916
917 VkPhysicalDeviceLimits limits = {
918 .maxImageDimension1D = (1 << 14),
919 .maxImageDimension2D = (1 << 14),
920 .maxImageDimension3D = (1 << 11),
921 .maxImageDimensionCube = (1 << 14),
922 .maxImageArrayLayers = (1 << 11),
923 .maxTexelBufferElements = 128 * 1024 * 1024,
924 .maxUniformBufferRange = UINT32_MAX,
925 .maxStorageBufferRange = UINT32_MAX,
926 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
927 .maxMemoryAllocationCount = UINT32_MAX,
928 .maxSamplerAllocationCount = 64 * 1024,
929 .bufferImageGranularity = 64, /* A cache line */
930 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
931 .maxBoundDescriptorSets = MAX_SETS,
932 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
933 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
934 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
935 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
936 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
937 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
938 .maxPerStageResources = max_descriptor_set_size,
939 .maxDescriptorSetSamplers = max_descriptor_set_size,
940 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
941 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
942 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
943 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
944 .maxDescriptorSetSampledImages = max_descriptor_set_size,
945 .maxDescriptorSetStorageImages = max_descriptor_set_size,
946 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
947 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
948 .maxVertexInputBindings = MAX_VBS,
949 .maxVertexInputAttributeOffset = 2047,
950 .maxVertexInputBindingStride = 2048,
951 .maxVertexOutputComponents = 128,
952 .maxTessellationGenerationLevel = 64,
953 .maxTessellationPatchSize = 32,
954 .maxTessellationControlPerVertexInputComponents = 128,
955 .maxTessellationControlPerVertexOutputComponents = 128,
956 .maxTessellationControlPerPatchOutputComponents = 120,
957 .maxTessellationControlTotalOutputComponents = 4096,
958 .maxTessellationEvaluationInputComponents = 128,
959 .maxTessellationEvaluationOutputComponents = 128,
960 .maxGeometryShaderInvocations = 127,
961 .maxGeometryInputComponents = 64,
962 .maxGeometryOutputComponents = 128,
963 .maxGeometryOutputVertices = 256,
964 .maxGeometryTotalOutputComponents = 1024,
965 .maxFragmentInputComponents = 128,
966 .maxFragmentOutputAttachments = 8,
967 .maxFragmentDualSrcAttachments = 1,
968 .maxFragmentCombinedOutputResources = 8,
969 .maxComputeSharedMemorySize = 32768,
970 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
971 .maxComputeWorkGroupInvocations = 2048,
972 .maxComputeWorkGroupSize = {
973 2048,
974 2048,
975 2048
976 },
977 .subPixelPrecisionBits = 8,
978 .subTexelPrecisionBits = 8,
979 .mipmapPrecisionBits = 8,
980 .maxDrawIndexedIndexValue = UINT32_MAX,
981 .maxDrawIndirectCount = UINT32_MAX,
982 .maxSamplerLodBias = 16,
983 .maxSamplerAnisotropy = 16,
984 .maxViewports = MAX_VIEWPORTS,
985 .maxViewportDimensions = { (1 << 14), (1 << 14) },
986 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
987 .viewportSubPixelBits = 8,
988 .minMemoryMapAlignment = 4096, /* A page */
989 .minTexelBufferOffsetAlignment = 1,
990 .minUniformBufferOffsetAlignment = 4,
991 .minStorageBufferOffsetAlignment = 4,
992 .minTexelOffset = -32,
993 .maxTexelOffset = 31,
994 .minTexelGatherOffset = -32,
995 .maxTexelGatherOffset = 31,
996 .minInterpolationOffset = -2,
997 .maxInterpolationOffset = 2,
998 .subPixelInterpolationOffsetBits = 8,
999 .maxFramebufferWidth = (1 << 14),
1000 .maxFramebufferHeight = (1 << 14),
1001 .maxFramebufferLayers = (1 << 10),
1002 .framebufferColorSampleCounts = sample_counts,
1003 .framebufferDepthSampleCounts = sample_counts,
1004 .framebufferStencilSampleCounts = sample_counts,
1005 .framebufferNoAttachmentsSampleCounts = sample_counts,
1006 .maxColorAttachments = MAX_RTS,
1007 .sampledImageColorSampleCounts = sample_counts,
1008 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1009 .sampledImageDepthSampleCounts = sample_counts,
1010 .sampledImageStencilSampleCounts = sample_counts,
1011 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1012 .maxSampleMaskWords = 1,
1013 .timestampComputeAndGraphics = true,
1014 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1015 .maxClipDistances = 8,
1016 .maxCullDistances = 8,
1017 .maxCombinedClipAndCullDistances = 8,
1018 .discreteQueuePriorities = 2,
1019 .pointSizeRange = { 0.0, 8192.0 },
1020 .lineWidthRange = { 0.0, 7.9921875 },
1021 .pointSizeGranularity = (1.0 / 8.0),
1022 .lineWidthGranularity = (1.0 / 128.0),
1023 .strictLines = false, /* FINISHME */
1024 .standardSampleLocations = true,
1025 .optimalBufferCopyOffsetAlignment = 128,
1026 .optimalBufferCopyRowPitchAlignment = 128,
1027 .nonCoherentAtomSize = 64,
1028 };
1029
1030 *pProperties = (VkPhysicalDeviceProperties) {
1031 .apiVersion = radv_physical_device_api_version(pdevice),
1032 .driverVersion = vk_get_driver_version(),
1033 .vendorID = ATI_VENDOR_ID,
1034 .deviceID = pdevice->rad_info.pci_id,
1035 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1036 .limits = limits,
1037 .sparseProperties = {0},
1038 };
1039
1040 strcpy(pProperties->deviceName, pdevice->name);
1041 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1042 }
1043
1044 void radv_GetPhysicalDeviceProperties2(
1045 VkPhysicalDevice physicalDevice,
1046 VkPhysicalDeviceProperties2 *pProperties)
1047 {
1048 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1049 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1050
1051 vk_foreach_struct(ext, pProperties->pNext) {
1052 switch (ext->sType) {
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1054 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1055 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1056 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1057 break;
1058 }
1059 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1060 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1061 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1062 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1063 properties->deviceLUIDValid = false;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1067 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1068 properties->maxMultiviewViewCount = MAX_VIEWS;
1069 properties->maxMultiviewInstanceIndex = INT_MAX;
1070 break;
1071 }
1072 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1073 VkPhysicalDevicePointClippingProperties *properties =
1074 (VkPhysicalDevicePointClippingProperties*)ext;
1075 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1076 break;
1077 }
1078 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1079 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1080 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1081 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1082 break;
1083 }
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1085 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1086 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1087 properties->minImportedHostPointerAlignment = 4096;
1088 break;
1089 }
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1091 VkPhysicalDeviceSubgroupProperties *properties =
1092 (VkPhysicalDeviceSubgroupProperties*)ext;
1093 properties->subgroupSize = 64;
1094 properties->supportedStages = VK_SHADER_STAGE_ALL;
1095 properties->supportedOperations =
1096 VK_SUBGROUP_FEATURE_BASIC_BIT |
1097 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1098 VK_SUBGROUP_FEATURE_QUAD_BIT |
1099 VK_SUBGROUP_FEATURE_VOTE_BIT;
1100 if (pdevice->rad_info.chip_class >= VI) {
1101 properties->supportedOperations |=
1102 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1103 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1104 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1105 }
1106 properties->quadOperationsInAllStages = true;
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1110 VkPhysicalDeviceMaintenance3Properties *properties =
1111 (VkPhysicalDeviceMaintenance3Properties*)ext;
1112 /* Make sure everything is addressable by a signed 32-bit int, and
1113 * our largest descriptors are 96 bytes. */
1114 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1115 /* Our buffer size fields allow only this much */
1116 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1117 break;
1118 }
1119 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1120 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1121 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1122 /* GFX6-8 only support single channel min/max filter. */
1123 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1124 properties->filterMinmaxSingleComponentFormats = true;
1125 break;
1126 }
1127 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1128 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1129 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1130
1131 /* Shader engines. */
1132 properties->shaderEngineCount =
1133 pdevice->rad_info.max_se;
1134 properties->shaderArraysPerEngineCount =
1135 pdevice->rad_info.max_sh_per_se;
1136 properties->computeUnitsPerShaderArray =
1137 pdevice->rad_info.num_good_cu_per_sh;
1138 properties->simdPerComputeUnit = 4;
1139 properties->wavefrontsPerSimd =
1140 pdevice->rad_info.family == CHIP_TONGA ||
1141 pdevice->rad_info.family == CHIP_ICELAND ||
1142 pdevice->rad_info.family == CHIP_POLARIS10 ||
1143 pdevice->rad_info.family == CHIP_POLARIS11 ||
1144 pdevice->rad_info.family == CHIP_POLARIS12 ||
1145 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1146 properties->wavefrontSize = 64;
1147
1148 /* SGPR. */
1149 properties->sgprsPerSimd =
1150 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1151 properties->minSgprAllocation =
1152 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1153 properties->maxSgprAllocation =
1154 pdevice->rad_info.family == CHIP_TONGA ||
1155 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1156 properties->sgprAllocationGranularity =
1157 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1158
1159 /* VGPR. */
1160 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1161 properties->minVgprAllocation = 4;
1162 properties->maxVgprAllocation = 256;
1163 properties->vgprAllocationGranularity = 4;
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1167 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1168 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1169 properties->maxVertexAttribDivisor = UINT32_MAX;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1173 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1174 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1175 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1176 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1177 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1178 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1179 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1180 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1181 properties->robustBufferAccessUpdateAfterBind = false;
1182 properties->quadDivergentImplicitLod = false;
1183
1184 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1185 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1186 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1187 32 /* sampler, largest when combined with image */ +
1188 64 /* sampled image */ +
1189 64 /* storage image */);
1190 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1191 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1192 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1193 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1194 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1195 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1196 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1197 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1198 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1199 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1200 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1201 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1202 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1203 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1204 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1208 VkPhysicalDeviceProtectedMemoryProperties *properties =
1209 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1210 properties->protectedNoFault = false;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1214 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1215 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1216 properties->primitiveOverestimationSize = 0;
1217 properties->maxExtraPrimitiveOverestimationSize = 0;
1218 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1219 properties->primitiveUnderestimation = VK_FALSE;
1220 properties->conservativePointAndLineRasterization = VK_FALSE;
1221 properties->degenerateTrianglesRasterized = VK_FALSE;
1222 properties->degenerateLinesRasterized = VK_FALSE;
1223 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1224 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1225 break;
1226 }
1227 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1228 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1229 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1230 properties->pciDomain = pdevice->bus_info.domain;
1231 properties->pciBus = pdevice->bus_info.bus;
1232 properties->pciDevice = pdevice->bus_info.dev;
1233 properties->pciFunction = pdevice->bus_info.func;
1234 break;
1235 }
1236 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1237 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1238 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1239
1240 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1241 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1242 strcpy(driver_props->driverName, "radv");
1243
1244 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1245 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1246 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1247 " (LLVM %d.%d.%d)",
1248 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1249 MESA_LLVM_VERSION_PATCH);
1250
1251 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1252 .major = 1,
1253 .minor = 1,
1254 .subminor = 2,
1255 .patch = 0,
1256 };
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1260 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1261 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1262 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1263 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1264 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1265 properties->maxTransformFeedbackStreamDataSize = 512;
1266 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1267 properties->maxTransformFeedbackBufferDataStride = 512;
1268 properties->transformFeedbackQueries = true;
1269 properties->transformFeedbackStreamsLinesTriangles = false;
1270 properties->transformFeedbackRasterizationStreamSelect = false;
1271 properties->transformFeedbackDraw = true;
1272 break;
1273 }
1274 default:
1275 break;
1276 }
1277 }
1278 }
1279
1280 static void radv_get_physical_device_queue_family_properties(
1281 struct radv_physical_device* pdevice,
1282 uint32_t* pCount,
1283 VkQueueFamilyProperties** pQueueFamilyProperties)
1284 {
1285 int num_queue_families = 1;
1286 int idx;
1287 if (pdevice->rad_info.num_compute_rings > 0 &&
1288 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1289 num_queue_families++;
1290
1291 if (pQueueFamilyProperties == NULL) {
1292 *pCount = num_queue_families;
1293 return;
1294 }
1295
1296 if (!*pCount)
1297 return;
1298
1299 idx = 0;
1300 if (*pCount >= 1) {
1301 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1302 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1303 VK_QUEUE_COMPUTE_BIT |
1304 VK_QUEUE_TRANSFER_BIT |
1305 VK_QUEUE_SPARSE_BINDING_BIT,
1306 .queueCount = 1,
1307 .timestampValidBits = 64,
1308 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1309 };
1310 idx++;
1311 }
1312
1313 if (pdevice->rad_info.num_compute_rings > 0 &&
1314 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1315 if (*pCount > idx) {
1316 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1317 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1318 VK_QUEUE_TRANSFER_BIT |
1319 VK_QUEUE_SPARSE_BINDING_BIT,
1320 .queueCount = pdevice->rad_info.num_compute_rings,
1321 .timestampValidBits = 64,
1322 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1323 };
1324 idx++;
1325 }
1326 }
1327 *pCount = idx;
1328 }
1329
1330 void radv_GetPhysicalDeviceQueueFamilyProperties(
1331 VkPhysicalDevice physicalDevice,
1332 uint32_t* pCount,
1333 VkQueueFamilyProperties* pQueueFamilyProperties)
1334 {
1335 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1336 if (!pQueueFamilyProperties) {
1337 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1338 return;
1339 }
1340 VkQueueFamilyProperties *properties[] = {
1341 pQueueFamilyProperties + 0,
1342 pQueueFamilyProperties + 1,
1343 pQueueFamilyProperties + 2,
1344 };
1345 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1346 assert(*pCount <= 3);
1347 }
1348
1349 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1350 VkPhysicalDevice physicalDevice,
1351 uint32_t* pCount,
1352 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1353 {
1354 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1355 if (!pQueueFamilyProperties) {
1356 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1357 return;
1358 }
1359 VkQueueFamilyProperties *properties[] = {
1360 &pQueueFamilyProperties[0].queueFamilyProperties,
1361 &pQueueFamilyProperties[1].queueFamilyProperties,
1362 &pQueueFamilyProperties[2].queueFamilyProperties,
1363 };
1364 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1365 assert(*pCount <= 3);
1366 }
1367
1368 void radv_GetPhysicalDeviceMemoryProperties(
1369 VkPhysicalDevice physicalDevice,
1370 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1371 {
1372 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1373
1374 *pMemoryProperties = physical_device->memory_properties;
1375 }
1376
1377 static void
1378 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1379 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1380 {
1381 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1382 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1383 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1384 uint64_t vram_size = radv_get_vram_size(device);
1385 uint64_t gtt_size = device->rad_info.gart_size;
1386 uint64_t heap_budget, heap_usage;
1387
1388 /* For all memory heaps, the computation of budget is as follow:
1389 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1390 *
1391 * The Vulkan spec 1.1.97 says that the budget should include any
1392 * currently allocated device memory.
1393 *
1394 * Note that the application heap usages are not really accurate (eg.
1395 * in presence of shared buffers).
1396 */
1397 if (vram_size) {
1398 heap_usage = device->ws->query_value(device->ws,
1399 RADEON_ALLOCATED_VRAM);
1400
1401 heap_budget = vram_size -
1402 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1403 heap_usage;
1404
1405 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1406 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1407 }
1408
1409 if (visible_vram_size) {
1410 heap_usage = device->ws->query_value(device->ws,
1411 RADEON_ALLOCATED_VRAM_VIS);
1412
1413 heap_budget = visible_vram_size -
1414 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1415 heap_usage;
1416
1417 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1418 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1419 }
1420
1421 if (gtt_size) {
1422 heap_usage = device->ws->query_value(device->ws,
1423 RADEON_ALLOCATED_GTT);
1424
1425 heap_budget = gtt_size -
1426 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1427 heap_usage;
1428
1429 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1430 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1431 }
1432
1433 /* The heapBudget and heapUsage values must be zero for array elements
1434 * greater than or equal to
1435 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1436 */
1437 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1438 memoryBudget->heapBudget[i] = 0;
1439 memoryBudget->heapUsage[i] = 0;
1440 }
1441 }
1442
1443 void radv_GetPhysicalDeviceMemoryProperties2(
1444 VkPhysicalDevice physicalDevice,
1445 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1446 {
1447 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1448 &pMemoryProperties->memoryProperties);
1449
1450 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1451 vk_find_struct(pMemoryProperties->pNext,
1452 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1453 if (memory_budget)
1454 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1455 }
1456
1457 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1458 VkDevice _device,
1459 VkExternalMemoryHandleTypeFlagBits handleType,
1460 const void *pHostPointer,
1461 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1462 {
1463 RADV_FROM_HANDLE(radv_device, device, _device);
1464
1465 switch (handleType)
1466 {
1467 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1468 const struct radv_physical_device *physical_device = device->physical_device;
1469 uint32_t memoryTypeBits = 0;
1470 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1471 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1472 memoryTypeBits = (1 << i);
1473 break;
1474 }
1475 }
1476 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1477 return VK_SUCCESS;
1478 }
1479 default:
1480 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1481 }
1482 }
1483
1484 static enum radeon_ctx_priority
1485 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1486 {
1487 /* Default to MEDIUM when a specific global priority isn't requested */
1488 if (!pObj)
1489 return RADEON_CTX_PRIORITY_MEDIUM;
1490
1491 switch(pObj->globalPriority) {
1492 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1493 return RADEON_CTX_PRIORITY_REALTIME;
1494 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1495 return RADEON_CTX_PRIORITY_HIGH;
1496 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1497 return RADEON_CTX_PRIORITY_MEDIUM;
1498 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1499 return RADEON_CTX_PRIORITY_LOW;
1500 default:
1501 unreachable("Illegal global priority value");
1502 return RADEON_CTX_PRIORITY_INVALID;
1503 }
1504 }
1505
1506 static int
1507 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1508 uint32_t queue_family_index, int idx,
1509 VkDeviceQueueCreateFlags flags,
1510 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1511 {
1512 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1513 queue->device = device;
1514 queue->queue_family_index = queue_family_index;
1515 queue->queue_idx = idx;
1516 queue->priority = radv_get_queue_global_priority(global_priority);
1517 queue->flags = flags;
1518
1519 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1520 if (!queue->hw_ctx)
1521 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1522
1523 return VK_SUCCESS;
1524 }
1525
1526 static void
1527 radv_queue_finish(struct radv_queue *queue)
1528 {
1529 if (queue->hw_ctx)
1530 queue->device->ws->ctx_destroy(queue->hw_ctx);
1531
1532 if (queue->initial_full_flush_preamble_cs)
1533 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1534 if (queue->initial_preamble_cs)
1535 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1536 if (queue->continue_preamble_cs)
1537 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1538 if (queue->descriptor_bo)
1539 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1540 if (queue->scratch_bo)
1541 queue->device->ws->buffer_destroy(queue->scratch_bo);
1542 if (queue->esgs_ring_bo)
1543 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1544 if (queue->gsvs_ring_bo)
1545 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1546 if (queue->tess_rings_bo)
1547 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1548 if (queue->compute_scratch_bo)
1549 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1550 }
1551
1552 static void
1553 radv_bo_list_init(struct radv_bo_list *bo_list)
1554 {
1555 pthread_mutex_init(&bo_list->mutex, NULL);
1556 bo_list->list.count = bo_list->capacity = 0;
1557 bo_list->list.bos = NULL;
1558 }
1559
1560 static void
1561 radv_bo_list_finish(struct radv_bo_list *bo_list)
1562 {
1563 free(bo_list->list.bos);
1564 pthread_mutex_destroy(&bo_list->mutex);
1565 }
1566
1567 static VkResult radv_bo_list_add(struct radv_device *device,
1568 struct radeon_winsys_bo *bo)
1569 {
1570 struct radv_bo_list *bo_list = &device->bo_list;
1571
1572 if (bo->is_local)
1573 return VK_SUCCESS;
1574
1575 if (unlikely(!device->use_global_bo_list))
1576 return VK_SUCCESS;
1577
1578 pthread_mutex_lock(&bo_list->mutex);
1579 if (bo_list->list.count == bo_list->capacity) {
1580 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1581 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1582
1583 if (!data) {
1584 pthread_mutex_unlock(&bo_list->mutex);
1585 return VK_ERROR_OUT_OF_HOST_MEMORY;
1586 }
1587
1588 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1589 bo_list->capacity = capacity;
1590 }
1591
1592 bo_list->list.bos[bo_list->list.count++] = bo;
1593 pthread_mutex_unlock(&bo_list->mutex);
1594 return VK_SUCCESS;
1595 }
1596
1597 static void radv_bo_list_remove(struct radv_device *device,
1598 struct radeon_winsys_bo *bo)
1599 {
1600 struct radv_bo_list *bo_list = &device->bo_list;
1601
1602 if (bo->is_local)
1603 return;
1604
1605 if (unlikely(!device->use_global_bo_list))
1606 return;
1607
1608 pthread_mutex_lock(&bo_list->mutex);
1609 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1610 if (bo_list->list.bos[i] == bo) {
1611 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1612 --bo_list->list.count;
1613 break;
1614 }
1615 }
1616 pthread_mutex_unlock(&bo_list->mutex);
1617 }
1618
1619 static void
1620 radv_device_init_gs_info(struct radv_device *device)
1621 {
1622 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1623 device->physical_device->rad_info.family);
1624 }
1625
1626 static int radv_get_device_extension_index(const char *name)
1627 {
1628 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1629 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1630 return i;
1631 }
1632 return -1;
1633 }
1634
1635 static int
1636 radv_get_int_debug_option(const char *name, int default_value)
1637 {
1638 const char *str;
1639 int result;
1640
1641 str = getenv(name);
1642 if (!str) {
1643 result = default_value;
1644 } else {
1645 char *endptr;
1646
1647 result = strtol(str, &endptr, 0);
1648 if (str == endptr) {
1649 /* No digits founs. */
1650 result = default_value;
1651 }
1652 }
1653
1654 return result;
1655 }
1656
1657 VkResult radv_CreateDevice(
1658 VkPhysicalDevice physicalDevice,
1659 const VkDeviceCreateInfo* pCreateInfo,
1660 const VkAllocationCallbacks* pAllocator,
1661 VkDevice* pDevice)
1662 {
1663 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1664 VkResult result;
1665 struct radv_device *device;
1666
1667 bool keep_shader_info = false;
1668
1669 /* Check enabled features */
1670 if (pCreateInfo->pEnabledFeatures) {
1671 VkPhysicalDeviceFeatures supported_features;
1672 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1673 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1674 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1675 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1676 for (uint32_t i = 0; i < num_features; i++) {
1677 if (enabled_feature[i] && !supported_feature[i])
1678 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1679 }
1680 }
1681
1682 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1683 sizeof(*device), 8,
1684 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1685 if (!device)
1686 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1687
1688 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1689 device->instance = physical_device->instance;
1690 device->physical_device = physical_device;
1691
1692 device->ws = physical_device->ws;
1693 if (pAllocator)
1694 device->alloc = *pAllocator;
1695 else
1696 device->alloc = physical_device->instance->alloc;
1697
1698 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1699 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1700 int index = radv_get_device_extension_index(ext_name);
1701 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1702 vk_free(&device->alloc, device);
1703 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1704 }
1705
1706 device->enabled_extensions.extensions[index] = true;
1707 }
1708
1709 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1710
1711 /* With update after bind we can't attach bo's to the command buffer
1712 * from the descriptor set anymore, so we have to use a global BO list.
1713 */
1714 device->use_global_bo_list =
1715 device->enabled_extensions.EXT_descriptor_indexing ||
1716 device->enabled_extensions.EXT_buffer_device_address;
1717
1718 mtx_init(&device->shader_slab_mutex, mtx_plain);
1719 list_inithead(&device->shader_slabs);
1720
1721 radv_bo_list_init(&device->bo_list);
1722
1723 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1724 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1725 uint32_t qfi = queue_create->queueFamilyIndex;
1726 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1727 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1728
1729 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1730
1731 device->queues[qfi] = vk_alloc(&device->alloc,
1732 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1733 if (!device->queues[qfi]) {
1734 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1735 goto fail;
1736 }
1737
1738 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1739
1740 device->queue_count[qfi] = queue_create->queueCount;
1741
1742 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1743 result = radv_queue_init(device, &device->queues[qfi][q],
1744 qfi, q, queue_create->flags,
1745 global_priority);
1746 if (result != VK_SUCCESS)
1747 goto fail;
1748 }
1749 }
1750
1751 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1752 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1753
1754 /* Disabled and not implemented for now. */
1755 device->dfsm_allowed = device->pbb_allowed &&
1756 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1757 device->physical_device->rad_info.family == CHIP_RAVEN2);
1758
1759 #ifdef ANDROID
1760 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1761 #endif
1762
1763 /* The maximum number of scratch waves. Scratch space isn't divided
1764 * evenly between CUs. The number is only a function of the number of CUs.
1765 * We can decrease the constant to decrease the scratch buffer size.
1766 *
1767 * sctx->scratch_waves must be >= the maximum possible size of
1768 * 1 threadgroup, so that the hw doesn't hang from being unable
1769 * to start any.
1770 *
1771 * The recommended value is 4 per CU at most. Higher numbers don't
1772 * bring much benefit, but they still occupy chip resources (think
1773 * async compute). I've seen ~2% performance difference between 4 and 32.
1774 */
1775 uint32_t max_threads_per_block = 2048;
1776 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1777 max_threads_per_block / 64);
1778
1779 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1780
1781 if (device->physical_device->rad_info.chip_class >= CIK) {
1782 /* If the KMD allows it (there is a KMD hw register for it),
1783 * allow launching waves out-of-order.
1784 */
1785 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1786 }
1787
1788 radv_device_init_gs_info(device);
1789
1790 device->tess_offchip_block_dw_size =
1791 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1792 device->has_distributed_tess =
1793 device->physical_device->rad_info.chip_class >= VI &&
1794 device->physical_device->rad_info.max_se >= 2;
1795
1796 if (getenv("RADV_TRACE_FILE")) {
1797 const char *filename = getenv("RADV_TRACE_FILE");
1798
1799 keep_shader_info = true;
1800
1801 if (!radv_init_trace(device))
1802 goto fail;
1803
1804 fprintf(stderr, "*****************************************************************************\n");
1805 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1806 fprintf(stderr, "*****************************************************************************\n");
1807
1808 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1809 radv_dump_enabled_options(device, stderr);
1810 }
1811
1812 device->keep_shader_info = keep_shader_info;
1813
1814 result = radv_device_init_meta(device);
1815 if (result != VK_SUCCESS)
1816 goto fail;
1817
1818 radv_device_init_msaa(device);
1819
1820 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1821 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1822 switch (family) {
1823 case RADV_QUEUE_GENERAL:
1824 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1825 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1826 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1827 break;
1828 case RADV_QUEUE_COMPUTE:
1829 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1830 radeon_emit(device->empty_cs[family], 0);
1831 break;
1832 }
1833 device->ws->cs_finalize(device->empty_cs[family]);
1834 }
1835
1836 if (device->physical_device->rad_info.chip_class >= CIK)
1837 cik_create_gfx_config(device);
1838
1839 VkPipelineCacheCreateInfo ci;
1840 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1841 ci.pNext = NULL;
1842 ci.flags = 0;
1843 ci.pInitialData = NULL;
1844 ci.initialDataSize = 0;
1845 VkPipelineCache pc;
1846 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1847 &ci, NULL, &pc);
1848 if (result != VK_SUCCESS)
1849 goto fail_meta;
1850
1851 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1852
1853 device->force_aniso =
1854 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1855 if (device->force_aniso >= 0) {
1856 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1857 1 << util_logbase2(device->force_aniso));
1858 }
1859
1860 *pDevice = radv_device_to_handle(device);
1861 return VK_SUCCESS;
1862
1863 fail_meta:
1864 radv_device_finish_meta(device);
1865 fail:
1866 radv_bo_list_finish(&device->bo_list);
1867
1868 if (device->trace_bo)
1869 device->ws->buffer_destroy(device->trace_bo);
1870
1871 if (device->gfx_init)
1872 device->ws->buffer_destroy(device->gfx_init);
1873
1874 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1875 for (unsigned q = 0; q < device->queue_count[i]; q++)
1876 radv_queue_finish(&device->queues[i][q]);
1877 if (device->queue_count[i])
1878 vk_free(&device->alloc, device->queues[i]);
1879 }
1880
1881 vk_free(&device->alloc, device);
1882 return result;
1883 }
1884
1885 void radv_DestroyDevice(
1886 VkDevice _device,
1887 const VkAllocationCallbacks* pAllocator)
1888 {
1889 RADV_FROM_HANDLE(radv_device, device, _device);
1890
1891 if (!device)
1892 return;
1893
1894 if (device->trace_bo)
1895 device->ws->buffer_destroy(device->trace_bo);
1896
1897 if (device->gfx_init)
1898 device->ws->buffer_destroy(device->gfx_init);
1899
1900 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1901 for (unsigned q = 0; q < device->queue_count[i]; q++)
1902 radv_queue_finish(&device->queues[i][q]);
1903 if (device->queue_count[i])
1904 vk_free(&device->alloc, device->queues[i]);
1905 if (device->empty_cs[i])
1906 device->ws->cs_destroy(device->empty_cs[i]);
1907 }
1908 radv_device_finish_meta(device);
1909
1910 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1911 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1912
1913 radv_destroy_shader_slabs(device);
1914
1915 radv_bo_list_finish(&device->bo_list);
1916 vk_free(&device->alloc, device);
1917 }
1918
1919 VkResult radv_EnumerateInstanceLayerProperties(
1920 uint32_t* pPropertyCount,
1921 VkLayerProperties* pProperties)
1922 {
1923 if (pProperties == NULL) {
1924 *pPropertyCount = 0;
1925 return VK_SUCCESS;
1926 }
1927
1928 /* None supported at this time */
1929 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1930 }
1931
1932 VkResult radv_EnumerateDeviceLayerProperties(
1933 VkPhysicalDevice physicalDevice,
1934 uint32_t* pPropertyCount,
1935 VkLayerProperties* pProperties)
1936 {
1937 if (pProperties == NULL) {
1938 *pPropertyCount = 0;
1939 return VK_SUCCESS;
1940 }
1941
1942 /* None supported at this time */
1943 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1944 }
1945
1946 void radv_GetDeviceQueue2(
1947 VkDevice _device,
1948 const VkDeviceQueueInfo2* pQueueInfo,
1949 VkQueue* pQueue)
1950 {
1951 RADV_FROM_HANDLE(radv_device, device, _device);
1952 struct radv_queue *queue;
1953
1954 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1955 if (pQueueInfo->flags != queue->flags) {
1956 /* From the Vulkan 1.1.70 spec:
1957 *
1958 * "The queue returned by vkGetDeviceQueue2 must have the same
1959 * flags value from this structure as that used at device
1960 * creation time in a VkDeviceQueueCreateInfo instance. If no
1961 * matching flags were specified at device creation time then
1962 * pQueue will return VK_NULL_HANDLE."
1963 */
1964 *pQueue = VK_NULL_HANDLE;
1965 return;
1966 }
1967
1968 *pQueue = radv_queue_to_handle(queue);
1969 }
1970
1971 void radv_GetDeviceQueue(
1972 VkDevice _device,
1973 uint32_t queueFamilyIndex,
1974 uint32_t queueIndex,
1975 VkQueue* pQueue)
1976 {
1977 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1978 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1979 .queueFamilyIndex = queueFamilyIndex,
1980 .queueIndex = queueIndex
1981 };
1982
1983 radv_GetDeviceQueue2(_device, &info, pQueue);
1984 }
1985
1986 static void
1987 fill_geom_tess_rings(struct radv_queue *queue,
1988 uint32_t *map,
1989 bool add_sample_positions,
1990 uint32_t esgs_ring_size,
1991 struct radeon_winsys_bo *esgs_ring_bo,
1992 uint32_t gsvs_ring_size,
1993 struct radeon_winsys_bo *gsvs_ring_bo,
1994 uint32_t tess_factor_ring_size,
1995 uint32_t tess_offchip_ring_offset,
1996 uint32_t tess_offchip_ring_size,
1997 struct radeon_winsys_bo *tess_rings_bo)
1998 {
1999 uint32_t *desc = &map[4];
2000
2001 if (esgs_ring_bo) {
2002 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2003
2004 /* stride 0, num records - size, add tid, swizzle, elsize4,
2005 index stride 64 */
2006 desc[0] = esgs_va;
2007 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2008 S_008F04_STRIDE(0) |
2009 S_008F04_SWIZZLE_ENABLE(true);
2010 desc[2] = esgs_ring_size;
2011 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2012 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2013 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2014 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2015 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2016 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2017 S_008F0C_ELEMENT_SIZE(1) |
2018 S_008F0C_INDEX_STRIDE(3) |
2019 S_008F0C_ADD_TID_ENABLE(true);
2020
2021 /* GS entry for ES->GS ring */
2022 /* stride 0, num records - size, elsize0,
2023 index stride 0 */
2024 desc[4] = esgs_va;
2025 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2026 S_008F04_STRIDE(0) |
2027 S_008F04_SWIZZLE_ENABLE(false);
2028 desc[6] = esgs_ring_size;
2029 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2030 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2031 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2032 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2033 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2034 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2035 S_008F0C_ELEMENT_SIZE(0) |
2036 S_008F0C_INDEX_STRIDE(0) |
2037 S_008F0C_ADD_TID_ENABLE(false);
2038 }
2039
2040 desc += 8;
2041
2042 if (gsvs_ring_bo) {
2043 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2044
2045 /* VS entry for GS->VS ring */
2046 /* stride 0, num records - size, elsize0,
2047 index stride 0 */
2048 desc[0] = gsvs_va;
2049 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2050 S_008F04_STRIDE(0) |
2051 S_008F04_SWIZZLE_ENABLE(false);
2052 desc[2] = gsvs_ring_size;
2053 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2054 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2055 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2056 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2057 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2058 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2059 S_008F0C_ELEMENT_SIZE(0) |
2060 S_008F0C_INDEX_STRIDE(0) |
2061 S_008F0C_ADD_TID_ENABLE(false);
2062
2063 /* stride gsvs_itemsize, num records 64
2064 elsize 4, index stride 16 */
2065 /* shader will patch stride and desc[2] */
2066 desc[4] = gsvs_va;
2067 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2068 S_008F04_STRIDE(0) |
2069 S_008F04_SWIZZLE_ENABLE(true);
2070 desc[6] = 0;
2071 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2072 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2073 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2074 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2075 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2076 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2077 S_008F0C_ELEMENT_SIZE(1) |
2078 S_008F0C_INDEX_STRIDE(1) |
2079 S_008F0C_ADD_TID_ENABLE(true);
2080 }
2081
2082 desc += 8;
2083
2084 if (tess_rings_bo) {
2085 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2086 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2087
2088 desc[0] = tess_va;
2089 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2090 S_008F04_STRIDE(0) |
2091 S_008F04_SWIZZLE_ENABLE(false);
2092 desc[2] = tess_factor_ring_size;
2093 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2094 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2095 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2096 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2097 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2098 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2099 S_008F0C_ELEMENT_SIZE(0) |
2100 S_008F0C_INDEX_STRIDE(0) |
2101 S_008F0C_ADD_TID_ENABLE(false);
2102
2103 desc[4] = tess_offchip_va;
2104 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2105 S_008F04_STRIDE(0) |
2106 S_008F04_SWIZZLE_ENABLE(false);
2107 desc[6] = tess_offchip_ring_size;
2108 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2109 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2110 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2111 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2112 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2113 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2114 S_008F0C_ELEMENT_SIZE(0) |
2115 S_008F0C_INDEX_STRIDE(0) |
2116 S_008F0C_ADD_TID_ENABLE(false);
2117 }
2118
2119 desc += 8;
2120
2121 if (add_sample_positions) {
2122 /* add sample positions after all rings */
2123 memcpy(desc, queue->device->sample_locations_1x, 8);
2124 desc += 2;
2125 memcpy(desc, queue->device->sample_locations_2x, 16);
2126 desc += 4;
2127 memcpy(desc, queue->device->sample_locations_4x, 32);
2128 desc += 8;
2129 memcpy(desc, queue->device->sample_locations_8x, 64);
2130 }
2131 }
2132
2133 static unsigned
2134 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2135 {
2136 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2137 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2138 device->physical_device->rad_info.family != CHIP_STONEY;
2139 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2140 unsigned max_offchip_buffers;
2141 unsigned offchip_granularity;
2142 unsigned hs_offchip_param;
2143
2144 /*
2145 * Per RadeonSI:
2146 * This must be one less than the maximum number due to a hw limitation.
2147 * Various hardware bugs in SI, CIK, and GFX9 need this.
2148 *
2149 * Per AMDVLK:
2150 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2151 * Gfx7 should limit max_offchip_buffers to 508
2152 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2153 *
2154 * Follow AMDVLK here.
2155 */
2156 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2157 device->physical_device->rad_info.chip_class == CIK ||
2158 device->physical_device->rad_info.chip_class == SI)
2159 --max_offchip_buffers_per_se;
2160
2161 max_offchip_buffers = max_offchip_buffers_per_se *
2162 device->physical_device->rad_info.max_se;
2163
2164 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2165 * around by setting 4K granularity.
2166 */
2167 if (device->tess_offchip_block_dw_size == 4096) {
2168 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2169 offchip_granularity = V_03093C_X_4K_DWORDS;
2170 } else {
2171 assert(device->tess_offchip_block_dw_size == 8192);
2172 offchip_granularity = V_03093C_X_8K_DWORDS;
2173 }
2174
2175 switch (device->physical_device->rad_info.chip_class) {
2176 case SI:
2177 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2178 break;
2179 case CIK:
2180 case VI:
2181 case GFX9:
2182 default:
2183 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2184 break;
2185 }
2186
2187 *max_offchip_buffers_p = max_offchip_buffers;
2188 if (device->physical_device->rad_info.chip_class >= CIK) {
2189 if (device->physical_device->rad_info.chip_class >= VI)
2190 --max_offchip_buffers;
2191 hs_offchip_param =
2192 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2193 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2194 } else {
2195 hs_offchip_param =
2196 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2197 }
2198 return hs_offchip_param;
2199 }
2200
2201 static void
2202 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2203 struct radeon_winsys_bo *esgs_ring_bo,
2204 uint32_t esgs_ring_size,
2205 struct radeon_winsys_bo *gsvs_ring_bo,
2206 uint32_t gsvs_ring_size)
2207 {
2208 if (!esgs_ring_bo && !gsvs_ring_bo)
2209 return;
2210
2211 if (esgs_ring_bo)
2212 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2213
2214 if (gsvs_ring_bo)
2215 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2216
2217 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2218 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2219 radeon_emit(cs, esgs_ring_size >> 8);
2220 radeon_emit(cs, gsvs_ring_size >> 8);
2221 } else {
2222 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2223 radeon_emit(cs, esgs_ring_size >> 8);
2224 radeon_emit(cs, gsvs_ring_size >> 8);
2225 }
2226 }
2227
2228 static void
2229 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2230 unsigned hs_offchip_param, unsigned tf_ring_size,
2231 struct radeon_winsys_bo *tess_rings_bo)
2232 {
2233 uint64_t tf_va;
2234
2235 if (!tess_rings_bo)
2236 return;
2237
2238 tf_va = radv_buffer_get_va(tess_rings_bo);
2239
2240 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2241
2242 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2243 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2244 S_030938_SIZE(tf_ring_size / 4));
2245 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2246 tf_va >> 8);
2247 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2248 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2249 S_030944_BASE_HI(tf_va >> 40));
2250 }
2251 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2252 hs_offchip_param);
2253 } else {
2254 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2255 S_008988_SIZE(tf_ring_size / 4));
2256 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2257 tf_va >> 8);
2258 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2259 hs_offchip_param);
2260 }
2261 }
2262
2263 static void
2264 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2265 struct radeon_winsys_bo *compute_scratch_bo)
2266 {
2267 uint64_t scratch_va;
2268
2269 if (!compute_scratch_bo)
2270 return;
2271
2272 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2273
2274 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2275
2276 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2277 radeon_emit(cs, scratch_va);
2278 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2279 S_008F04_SWIZZLE_ENABLE(1));
2280 }
2281
2282 static void
2283 radv_emit_global_shader_pointers(struct radv_queue *queue,
2284 struct radeon_cmdbuf *cs,
2285 struct radeon_winsys_bo *descriptor_bo)
2286 {
2287 uint64_t va;
2288
2289 if (!descriptor_bo)
2290 return;
2291
2292 va = radv_buffer_get_va(descriptor_bo);
2293
2294 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2295
2296 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2297 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2298 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2299 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2300 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2301
2302 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2303 radv_emit_shader_pointer(queue->device, cs, regs[i],
2304 va, true);
2305 }
2306 } else {
2307 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2308 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2309 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2310 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2311 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2312 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2313
2314 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2315 radv_emit_shader_pointer(queue->device, cs, regs[i],
2316 va, true);
2317 }
2318 }
2319 }
2320
2321 static void
2322 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2323 {
2324 struct radv_device *device = queue->device;
2325
2326 if (device->gfx_init) {
2327 uint64_t va = radv_buffer_get_va(device->gfx_init);
2328
2329 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2330 radeon_emit(cs, va);
2331 radeon_emit(cs, va >> 32);
2332 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2333
2334 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2335 } else {
2336 struct radv_physical_device *physical_device = device->physical_device;
2337 si_emit_graphics(physical_device, cs);
2338 }
2339 }
2340
2341 static void
2342 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2343 {
2344 struct radv_physical_device *physical_device = queue->device->physical_device;
2345 si_emit_compute(physical_device, cs);
2346 }
2347
2348 static VkResult
2349 radv_get_preamble_cs(struct radv_queue *queue,
2350 uint32_t scratch_size,
2351 uint32_t compute_scratch_size,
2352 uint32_t esgs_ring_size,
2353 uint32_t gsvs_ring_size,
2354 bool needs_tess_rings,
2355 bool needs_sample_positions,
2356 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2357 struct radeon_cmdbuf **initial_preamble_cs,
2358 struct radeon_cmdbuf **continue_preamble_cs)
2359 {
2360 struct radeon_winsys_bo *scratch_bo = NULL;
2361 struct radeon_winsys_bo *descriptor_bo = NULL;
2362 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2363 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2364 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2365 struct radeon_winsys_bo *tess_rings_bo = NULL;
2366 struct radeon_cmdbuf *dest_cs[3] = {0};
2367 bool add_tess_rings = false, add_sample_positions = false;
2368 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2369 unsigned max_offchip_buffers;
2370 unsigned hs_offchip_param = 0;
2371 unsigned tess_offchip_ring_offset;
2372 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2373 if (!queue->has_tess_rings) {
2374 if (needs_tess_rings)
2375 add_tess_rings = true;
2376 }
2377 if (!queue->has_sample_positions) {
2378 if (needs_sample_positions)
2379 add_sample_positions = true;
2380 }
2381 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2382 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2383 &max_offchip_buffers);
2384 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2385 tess_offchip_ring_size = max_offchip_buffers *
2386 queue->device->tess_offchip_block_dw_size * 4;
2387
2388 if (scratch_size <= queue->scratch_size &&
2389 compute_scratch_size <= queue->compute_scratch_size &&
2390 esgs_ring_size <= queue->esgs_ring_size &&
2391 gsvs_ring_size <= queue->gsvs_ring_size &&
2392 !add_tess_rings && !add_sample_positions &&
2393 queue->initial_preamble_cs) {
2394 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2395 *initial_preamble_cs = queue->initial_preamble_cs;
2396 *continue_preamble_cs = queue->continue_preamble_cs;
2397 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2398 *continue_preamble_cs = NULL;
2399 return VK_SUCCESS;
2400 }
2401
2402 if (scratch_size > queue->scratch_size) {
2403 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2404 scratch_size,
2405 4096,
2406 RADEON_DOMAIN_VRAM,
2407 ring_bo_flags,
2408 RADV_BO_PRIORITY_SCRATCH);
2409 if (!scratch_bo)
2410 goto fail;
2411 } else
2412 scratch_bo = queue->scratch_bo;
2413
2414 if (compute_scratch_size > queue->compute_scratch_size) {
2415 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2416 compute_scratch_size,
2417 4096,
2418 RADEON_DOMAIN_VRAM,
2419 ring_bo_flags,
2420 RADV_BO_PRIORITY_SCRATCH);
2421 if (!compute_scratch_bo)
2422 goto fail;
2423
2424 } else
2425 compute_scratch_bo = queue->compute_scratch_bo;
2426
2427 if (esgs_ring_size > queue->esgs_ring_size) {
2428 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2429 esgs_ring_size,
2430 4096,
2431 RADEON_DOMAIN_VRAM,
2432 ring_bo_flags,
2433 RADV_BO_PRIORITY_SCRATCH);
2434 if (!esgs_ring_bo)
2435 goto fail;
2436 } else {
2437 esgs_ring_bo = queue->esgs_ring_bo;
2438 esgs_ring_size = queue->esgs_ring_size;
2439 }
2440
2441 if (gsvs_ring_size > queue->gsvs_ring_size) {
2442 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2443 gsvs_ring_size,
2444 4096,
2445 RADEON_DOMAIN_VRAM,
2446 ring_bo_flags,
2447 RADV_BO_PRIORITY_SCRATCH);
2448 if (!gsvs_ring_bo)
2449 goto fail;
2450 } else {
2451 gsvs_ring_bo = queue->gsvs_ring_bo;
2452 gsvs_ring_size = queue->gsvs_ring_size;
2453 }
2454
2455 if (add_tess_rings) {
2456 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2457 tess_offchip_ring_offset + tess_offchip_ring_size,
2458 256,
2459 RADEON_DOMAIN_VRAM,
2460 ring_bo_flags,
2461 RADV_BO_PRIORITY_SCRATCH);
2462 if (!tess_rings_bo)
2463 goto fail;
2464 } else {
2465 tess_rings_bo = queue->tess_rings_bo;
2466 }
2467
2468 if (scratch_bo != queue->scratch_bo ||
2469 esgs_ring_bo != queue->esgs_ring_bo ||
2470 gsvs_ring_bo != queue->gsvs_ring_bo ||
2471 tess_rings_bo != queue->tess_rings_bo ||
2472 add_sample_positions) {
2473 uint32_t size = 0;
2474 if (gsvs_ring_bo || esgs_ring_bo ||
2475 tess_rings_bo || add_sample_positions) {
2476 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2477 if (add_sample_positions)
2478 size += 128; /* 64+32+16+8 = 120 bytes */
2479 }
2480 else if (scratch_bo)
2481 size = 8; /* 2 dword */
2482
2483 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2484 size,
2485 4096,
2486 RADEON_DOMAIN_VRAM,
2487 RADEON_FLAG_CPU_ACCESS |
2488 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2489 RADEON_FLAG_READ_ONLY,
2490 RADV_BO_PRIORITY_DESCRIPTOR);
2491 if (!descriptor_bo)
2492 goto fail;
2493 } else
2494 descriptor_bo = queue->descriptor_bo;
2495
2496 if (descriptor_bo != queue->descriptor_bo) {
2497 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2498
2499 if (scratch_bo) {
2500 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2501 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2502 S_008F04_SWIZZLE_ENABLE(1);
2503 map[0] = scratch_va;
2504 map[1] = rsrc1;
2505 }
2506
2507 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2508 fill_geom_tess_rings(queue, map, add_sample_positions,
2509 esgs_ring_size, esgs_ring_bo,
2510 gsvs_ring_size, gsvs_ring_bo,
2511 tess_factor_ring_size,
2512 tess_offchip_ring_offset,
2513 tess_offchip_ring_size,
2514 tess_rings_bo);
2515
2516 queue->device->ws->buffer_unmap(descriptor_bo);
2517 }
2518
2519 for(int i = 0; i < 3; ++i) {
2520 struct radeon_cmdbuf *cs = NULL;
2521 cs = queue->device->ws->cs_create(queue->device->ws,
2522 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2523 if (!cs)
2524 goto fail;
2525
2526 dest_cs[i] = cs;
2527
2528 if (scratch_bo)
2529 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2530
2531 /* Emit initial configuration. */
2532 switch (queue->queue_family_index) {
2533 case RADV_QUEUE_GENERAL:
2534 radv_init_graphics_state(cs, queue);
2535 break;
2536 case RADV_QUEUE_COMPUTE:
2537 radv_init_compute_state(cs, queue);
2538 break;
2539 case RADV_QUEUE_TRANSFER:
2540 break;
2541 }
2542
2543 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2544 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2545 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2546 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2547 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2548 }
2549
2550 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2551 gsvs_ring_bo, gsvs_ring_size);
2552 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2553 tess_factor_ring_size, tess_rings_bo);
2554 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2555 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2556
2557 if (i == 0) {
2558 si_cs_emit_cache_flush(cs,
2559 queue->device->physical_device->rad_info.chip_class,
2560 NULL, 0,
2561 queue->queue_family_index == RING_COMPUTE &&
2562 queue->device->physical_device->rad_info.chip_class >= CIK,
2563 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2564 RADV_CMD_FLAG_INV_ICACHE |
2565 RADV_CMD_FLAG_INV_SMEM_L1 |
2566 RADV_CMD_FLAG_INV_VMEM_L1 |
2567 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2568 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2569 } else if (i == 1) {
2570 si_cs_emit_cache_flush(cs,
2571 queue->device->physical_device->rad_info.chip_class,
2572 NULL, 0,
2573 queue->queue_family_index == RING_COMPUTE &&
2574 queue->device->physical_device->rad_info.chip_class >= CIK,
2575 RADV_CMD_FLAG_INV_ICACHE |
2576 RADV_CMD_FLAG_INV_SMEM_L1 |
2577 RADV_CMD_FLAG_INV_VMEM_L1 |
2578 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2579 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2580 }
2581
2582 if (!queue->device->ws->cs_finalize(cs))
2583 goto fail;
2584 }
2585
2586 if (queue->initial_full_flush_preamble_cs)
2587 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2588
2589 if (queue->initial_preamble_cs)
2590 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2591
2592 if (queue->continue_preamble_cs)
2593 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2594
2595 queue->initial_full_flush_preamble_cs = dest_cs[0];
2596 queue->initial_preamble_cs = dest_cs[1];
2597 queue->continue_preamble_cs = dest_cs[2];
2598
2599 if (scratch_bo != queue->scratch_bo) {
2600 if (queue->scratch_bo)
2601 queue->device->ws->buffer_destroy(queue->scratch_bo);
2602 queue->scratch_bo = scratch_bo;
2603 queue->scratch_size = scratch_size;
2604 }
2605
2606 if (compute_scratch_bo != queue->compute_scratch_bo) {
2607 if (queue->compute_scratch_bo)
2608 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2609 queue->compute_scratch_bo = compute_scratch_bo;
2610 queue->compute_scratch_size = compute_scratch_size;
2611 }
2612
2613 if (esgs_ring_bo != queue->esgs_ring_bo) {
2614 if (queue->esgs_ring_bo)
2615 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2616 queue->esgs_ring_bo = esgs_ring_bo;
2617 queue->esgs_ring_size = esgs_ring_size;
2618 }
2619
2620 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2621 if (queue->gsvs_ring_bo)
2622 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2623 queue->gsvs_ring_bo = gsvs_ring_bo;
2624 queue->gsvs_ring_size = gsvs_ring_size;
2625 }
2626
2627 if (tess_rings_bo != queue->tess_rings_bo) {
2628 queue->tess_rings_bo = tess_rings_bo;
2629 queue->has_tess_rings = true;
2630 }
2631
2632 if (descriptor_bo != queue->descriptor_bo) {
2633 if (queue->descriptor_bo)
2634 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2635
2636 queue->descriptor_bo = descriptor_bo;
2637 }
2638
2639 if (add_sample_positions)
2640 queue->has_sample_positions = true;
2641
2642 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2643 *initial_preamble_cs = queue->initial_preamble_cs;
2644 *continue_preamble_cs = queue->continue_preamble_cs;
2645 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2646 *continue_preamble_cs = NULL;
2647 return VK_SUCCESS;
2648 fail:
2649 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2650 if (dest_cs[i])
2651 queue->device->ws->cs_destroy(dest_cs[i]);
2652 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2653 queue->device->ws->buffer_destroy(descriptor_bo);
2654 if (scratch_bo && scratch_bo != queue->scratch_bo)
2655 queue->device->ws->buffer_destroy(scratch_bo);
2656 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2657 queue->device->ws->buffer_destroy(compute_scratch_bo);
2658 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2659 queue->device->ws->buffer_destroy(esgs_ring_bo);
2660 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2661 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2662 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2663 queue->device->ws->buffer_destroy(tess_rings_bo);
2664 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2665 }
2666
2667 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2668 struct radv_winsys_sem_counts *counts,
2669 int num_sems,
2670 const VkSemaphore *sems,
2671 VkFence _fence,
2672 bool reset_temp)
2673 {
2674 int syncobj_idx = 0, sem_idx = 0;
2675
2676 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2677 return VK_SUCCESS;
2678
2679 for (uint32_t i = 0; i < num_sems; i++) {
2680 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2681
2682 if (sem->temp_syncobj || sem->syncobj)
2683 counts->syncobj_count++;
2684 else
2685 counts->sem_count++;
2686 }
2687
2688 if (_fence != VK_NULL_HANDLE) {
2689 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2690 if (fence->temp_syncobj || fence->syncobj)
2691 counts->syncobj_count++;
2692 }
2693
2694 if (counts->syncobj_count) {
2695 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2696 if (!counts->syncobj)
2697 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2698 }
2699
2700 if (counts->sem_count) {
2701 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2702 if (!counts->sem) {
2703 free(counts->syncobj);
2704 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2705 }
2706 }
2707
2708 for (uint32_t i = 0; i < num_sems; i++) {
2709 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2710
2711 if (sem->temp_syncobj) {
2712 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2713 }
2714 else if (sem->syncobj)
2715 counts->syncobj[syncobj_idx++] = sem->syncobj;
2716 else {
2717 assert(sem->sem);
2718 counts->sem[sem_idx++] = sem->sem;
2719 }
2720 }
2721
2722 if (_fence != VK_NULL_HANDLE) {
2723 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2724 if (fence->temp_syncobj)
2725 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2726 else if (fence->syncobj)
2727 counts->syncobj[syncobj_idx++] = fence->syncobj;
2728 }
2729
2730 return VK_SUCCESS;
2731 }
2732
2733 static void
2734 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2735 {
2736 free(sem_info->wait.syncobj);
2737 free(sem_info->wait.sem);
2738 free(sem_info->signal.syncobj);
2739 free(sem_info->signal.sem);
2740 }
2741
2742
2743 static void radv_free_temp_syncobjs(struct radv_device *device,
2744 int num_sems,
2745 const VkSemaphore *sems)
2746 {
2747 for (uint32_t i = 0; i < num_sems; i++) {
2748 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2749
2750 if (sem->temp_syncobj) {
2751 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2752 sem->temp_syncobj = 0;
2753 }
2754 }
2755 }
2756
2757 static VkResult
2758 radv_alloc_sem_info(struct radv_instance *instance,
2759 struct radv_winsys_sem_info *sem_info,
2760 int num_wait_sems,
2761 const VkSemaphore *wait_sems,
2762 int num_signal_sems,
2763 const VkSemaphore *signal_sems,
2764 VkFence fence)
2765 {
2766 VkResult ret;
2767 memset(sem_info, 0, sizeof(*sem_info));
2768
2769 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2770 if (ret)
2771 return ret;
2772 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2773 if (ret)
2774 radv_free_sem_info(sem_info);
2775
2776 /* caller can override these */
2777 sem_info->cs_emit_wait = true;
2778 sem_info->cs_emit_signal = true;
2779 return ret;
2780 }
2781
2782 /* Signals fence as soon as all the work currently put on queue is done. */
2783 static VkResult radv_signal_fence(struct radv_queue *queue,
2784 struct radv_fence *fence)
2785 {
2786 int ret;
2787 VkResult result;
2788 struct radv_winsys_sem_info sem_info;
2789
2790 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2791 radv_fence_to_handle(fence));
2792 if (result != VK_SUCCESS)
2793 return result;
2794
2795 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2796 &queue->device->empty_cs[queue->queue_family_index],
2797 1, NULL, NULL, &sem_info, NULL,
2798 false, fence->fence);
2799 radv_free_sem_info(&sem_info);
2800
2801 if (ret)
2802 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2803
2804 return VK_SUCCESS;
2805 }
2806
2807 VkResult radv_QueueSubmit(
2808 VkQueue _queue,
2809 uint32_t submitCount,
2810 const VkSubmitInfo* pSubmits,
2811 VkFence _fence)
2812 {
2813 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2814 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2815 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2816 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2817 int ret;
2818 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2819 uint32_t scratch_size = 0;
2820 uint32_t compute_scratch_size = 0;
2821 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2822 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2823 VkResult result;
2824 bool fence_emitted = false;
2825 bool tess_rings_needed = false;
2826 bool sample_positions_needed = false;
2827
2828 /* Do this first so failing to allocate scratch buffers can't result in
2829 * partially executed submissions. */
2830 for (uint32_t i = 0; i < submitCount; i++) {
2831 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2832 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2833 pSubmits[i].pCommandBuffers[j]);
2834
2835 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2836 compute_scratch_size = MAX2(compute_scratch_size,
2837 cmd_buffer->compute_scratch_size_needed);
2838 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2839 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2840 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2841 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2842 }
2843 }
2844
2845 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2846 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2847 sample_positions_needed, &initial_flush_preamble_cs,
2848 &initial_preamble_cs, &continue_preamble_cs);
2849 if (result != VK_SUCCESS)
2850 return result;
2851
2852 for (uint32_t i = 0; i < submitCount; i++) {
2853 struct radeon_cmdbuf **cs_array;
2854 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2855 bool can_patch = true;
2856 uint32_t advance;
2857 struct radv_winsys_sem_info sem_info;
2858
2859 result = radv_alloc_sem_info(queue->device->instance,
2860 &sem_info,
2861 pSubmits[i].waitSemaphoreCount,
2862 pSubmits[i].pWaitSemaphores,
2863 pSubmits[i].signalSemaphoreCount,
2864 pSubmits[i].pSignalSemaphores,
2865 _fence);
2866 if (result != VK_SUCCESS)
2867 return result;
2868
2869 if (!pSubmits[i].commandBufferCount) {
2870 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2871 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2872 &queue->device->empty_cs[queue->queue_family_index],
2873 1, NULL, NULL,
2874 &sem_info, NULL,
2875 false, base_fence);
2876 if (ret) {
2877 radv_loge("failed to submit CS %d\n", i);
2878 abort();
2879 }
2880 fence_emitted = true;
2881 }
2882 radv_free_sem_info(&sem_info);
2883 continue;
2884 }
2885
2886 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2887 (pSubmits[i].commandBufferCount));
2888
2889 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2890 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2891 pSubmits[i].pCommandBuffers[j]);
2892 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2893
2894 cs_array[j] = cmd_buffer->cs;
2895 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2896 can_patch = false;
2897
2898 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2899 }
2900
2901 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2902 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2903 const struct radv_winsys_bo_list *bo_list = NULL;
2904
2905 advance = MIN2(max_cs_submission,
2906 pSubmits[i].commandBufferCount - j);
2907
2908 if (queue->device->trace_bo)
2909 *queue->device->trace_id_ptr = 0;
2910
2911 sem_info.cs_emit_wait = j == 0;
2912 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2913
2914 if (unlikely(queue->device->use_global_bo_list)) {
2915 pthread_mutex_lock(&queue->device->bo_list.mutex);
2916 bo_list = &queue->device->bo_list.list;
2917 }
2918
2919 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2920 advance, initial_preamble, continue_preamble_cs,
2921 &sem_info, bo_list,
2922 can_patch, base_fence);
2923
2924 if (unlikely(queue->device->use_global_bo_list))
2925 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2926
2927 if (ret) {
2928 radv_loge("failed to submit CS %d\n", i);
2929 abort();
2930 }
2931 fence_emitted = true;
2932 if (queue->device->trace_bo) {
2933 radv_check_gpu_hangs(queue, cs_array[j]);
2934 }
2935 }
2936
2937 radv_free_temp_syncobjs(queue->device,
2938 pSubmits[i].waitSemaphoreCount,
2939 pSubmits[i].pWaitSemaphores);
2940 radv_free_sem_info(&sem_info);
2941 free(cs_array);
2942 }
2943
2944 if (fence) {
2945 if (!fence_emitted) {
2946 result = radv_signal_fence(queue, fence);
2947 if (result != VK_SUCCESS)
2948 return result;
2949 }
2950 fence->submitted = true;
2951 }
2952
2953 return VK_SUCCESS;
2954 }
2955
2956 VkResult radv_QueueWaitIdle(
2957 VkQueue _queue)
2958 {
2959 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2960
2961 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2962 radv_queue_family_to_ring(queue->queue_family_index),
2963 queue->queue_idx);
2964 return VK_SUCCESS;
2965 }
2966
2967 VkResult radv_DeviceWaitIdle(
2968 VkDevice _device)
2969 {
2970 RADV_FROM_HANDLE(radv_device, device, _device);
2971
2972 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2973 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2974 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2975 }
2976 }
2977 return VK_SUCCESS;
2978 }
2979
2980 VkResult radv_EnumerateInstanceExtensionProperties(
2981 const char* pLayerName,
2982 uint32_t* pPropertyCount,
2983 VkExtensionProperties* pProperties)
2984 {
2985 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2986
2987 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2988 if (radv_supported_instance_extensions.extensions[i]) {
2989 vk_outarray_append(&out, prop) {
2990 *prop = radv_instance_extensions[i];
2991 }
2992 }
2993 }
2994
2995 return vk_outarray_status(&out);
2996 }
2997
2998 VkResult radv_EnumerateDeviceExtensionProperties(
2999 VkPhysicalDevice physicalDevice,
3000 const char* pLayerName,
3001 uint32_t* pPropertyCount,
3002 VkExtensionProperties* pProperties)
3003 {
3004 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3005 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3006
3007 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3008 if (device->supported_extensions.extensions[i]) {
3009 vk_outarray_append(&out, prop) {
3010 *prop = radv_device_extensions[i];
3011 }
3012 }
3013 }
3014
3015 return vk_outarray_status(&out);
3016 }
3017
3018 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3019 VkInstance _instance,
3020 const char* pName)
3021 {
3022 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3023
3024 return radv_lookup_entrypoint_checked(pName,
3025 instance ? instance->apiVersion : 0,
3026 instance ? &instance->enabled_extensions : NULL,
3027 NULL);
3028 }
3029
3030 /* The loader wants us to expose a second GetInstanceProcAddr function
3031 * to work around certain LD_PRELOAD issues seen in apps.
3032 */
3033 PUBLIC
3034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3035 VkInstance instance,
3036 const char* pName);
3037
3038 PUBLIC
3039 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3040 VkInstance instance,
3041 const char* pName)
3042 {
3043 return radv_GetInstanceProcAddr(instance, pName);
3044 }
3045
3046 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3047 VkDevice _device,
3048 const char* pName)
3049 {
3050 RADV_FROM_HANDLE(radv_device, device, _device);
3051
3052 return radv_lookup_entrypoint_checked(pName,
3053 device->instance->apiVersion,
3054 &device->instance->enabled_extensions,
3055 &device->enabled_extensions);
3056 }
3057
3058 bool radv_get_memory_fd(struct radv_device *device,
3059 struct radv_device_memory *memory,
3060 int *pFD)
3061 {
3062 struct radeon_bo_metadata metadata;
3063
3064 if (memory->image) {
3065 radv_init_metadata(device, memory->image, &metadata);
3066 device->ws->buffer_set_metadata(memory->bo, &metadata);
3067 }
3068
3069 return device->ws->buffer_get_fd(device->ws, memory->bo,
3070 pFD);
3071 }
3072
3073 static VkResult radv_alloc_memory(struct radv_device *device,
3074 const VkMemoryAllocateInfo* pAllocateInfo,
3075 const VkAllocationCallbacks* pAllocator,
3076 VkDeviceMemory* pMem)
3077 {
3078 struct radv_device_memory *mem;
3079 VkResult result;
3080 enum radeon_bo_domain domain;
3081 uint32_t flags = 0;
3082 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3083
3084 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3085
3086 if (pAllocateInfo->allocationSize == 0) {
3087 /* Apparently, this is allowed */
3088 *pMem = VK_NULL_HANDLE;
3089 return VK_SUCCESS;
3090 }
3091
3092 const VkImportMemoryFdInfoKHR *import_info =
3093 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3094 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3095 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3096 const VkExportMemoryAllocateInfo *export_info =
3097 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3098 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3099 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3100
3101 const struct wsi_memory_allocate_info *wsi_info =
3102 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3103
3104 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3105 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3106 if (mem == NULL)
3107 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3108
3109 if (wsi_info && wsi_info->implicit_sync)
3110 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3111
3112 if (dedicate_info) {
3113 mem->image = radv_image_from_handle(dedicate_info->image);
3114 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3115 } else {
3116 mem->image = NULL;
3117 mem->buffer = NULL;
3118 }
3119
3120 float priority_float = 0.5;
3121 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3122 vk_find_struct_const(pAllocateInfo->pNext,
3123 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3124 if (priority_ext)
3125 priority_float = priority_ext->priority;
3126
3127 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3128 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3129
3130 mem->user_ptr = NULL;
3131
3132 if (import_info) {
3133 assert(import_info->handleType ==
3134 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3135 import_info->handleType ==
3136 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3137 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3138 priority, NULL, NULL);
3139 if (!mem->bo) {
3140 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3141 goto fail;
3142 } else {
3143 close(import_info->fd);
3144 }
3145 } else if (host_ptr_info) {
3146 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3147 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3148 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3149 pAllocateInfo->allocationSize,
3150 priority);
3151 if (!mem->bo) {
3152 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3153 goto fail;
3154 } else {
3155 mem->user_ptr = host_ptr_info->pHostPointer;
3156 }
3157 } else {
3158 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3159 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3160 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3161 domain = RADEON_DOMAIN_GTT;
3162 else
3163 domain = RADEON_DOMAIN_VRAM;
3164
3165 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3166 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3167 else
3168 flags |= RADEON_FLAG_CPU_ACCESS;
3169
3170 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3171 flags |= RADEON_FLAG_GTT_WC;
3172
3173 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3174 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3175
3176 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3177 domain, flags, priority);
3178
3179 if (!mem->bo) {
3180 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3181 goto fail;
3182 }
3183 mem->type_index = mem_type_index;
3184 }
3185
3186 result = radv_bo_list_add(device, mem->bo);
3187 if (result != VK_SUCCESS)
3188 goto fail_bo;
3189
3190 *pMem = radv_device_memory_to_handle(mem);
3191
3192 return VK_SUCCESS;
3193
3194 fail_bo:
3195 device->ws->buffer_destroy(mem->bo);
3196 fail:
3197 vk_free2(&device->alloc, pAllocator, mem);
3198
3199 return result;
3200 }
3201
3202 VkResult radv_AllocateMemory(
3203 VkDevice _device,
3204 const VkMemoryAllocateInfo* pAllocateInfo,
3205 const VkAllocationCallbacks* pAllocator,
3206 VkDeviceMemory* pMem)
3207 {
3208 RADV_FROM_HANDLE(radv_device, device, _device);
3209 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3210 }
3211
3212 void radv_FreeMemory(
3213 VkDevice _device,
3214 VkDeviceMemory _mem,
3215 const VkAllocationCallbacks* pAllocator)
3216 {
3217 RADV_FROM_HANDLE(radv_device, device, _device);
3218 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3219
3220 if (mem == NULL)
3221 return;
3222
3223 radv_bo_list_remove(device, mem->bo);
3224 device->ws->buffer_destroy(mem->bo);
3225 mem->bo = NULL;
3226
3227 vk_free2(&device->alloc, pAllocator, mem);
3228 }
3229
3230 VkResult radv_MapMemory(
3231 VkDevice _device,
3232 VkDeviceMemory _memory,
3233 VkDeviceSize offset,
3234 VkDeviceSize size,
3235 VkMemoryMapFlags flags,
3236 void** ppData)
3237 {
3238 RADV_FROM_HANDLE(radv_device, device, _device);
3239 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3240
3241 if (mem == NULL) {
3242 *ppData = NULL;
3243 return VK_SUCCESS;
3244 }
3245
3246 if (mem->user_ptr)
3247 *ppData = mem->user_ptr;
3248 else
3249 *ppData = device->ws->buffer_map(mem->bo);
3250
3251 if (*ppData) {
3252 *ppData += offset;
3253 return VK_SUCCESS;
3254 }
3255
3256 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3257 }
3258
3259 void radv_UnmapMemory(
3260 VkDevice _device,
3261 VkDeviceMemory _memory)
3262 {
3263 RADV_FROM_HANDLE(radv_device, device, _device);
3264 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3265
3266 if (mem == NULL)
3267 return;
3268
3269 if (mem->user_ptr == NULL)
3270 device->ws->buffer_unmap(mem->bo);
3271 }
3272
3273 VkResult radv_FlushMappedMemoryRanges(
3274 VkDevice _device,
3275 uint32_t memoryRangeCount,
3276 const VkMappedMemoryRange* pMemoryRanges)
3277 {
3278 return VK_SUCCESS;
3279 }
3280
3281 VkResult radv_InvalidateMappedMemoryRanges(
3282 VkDevice _device,
3283 uint32_t memoryRangeCount,
3284 const VkMappedMemoryRange* pMemoryRanges)
3285 {
3286 return VK_SUCCESS;
3287 }
3288
3289 void radv_GetBufferMemoryRequirements(
3290 VkDevice _device,
3291 VkBuffer _buffer,
3292 VkMemoryRequirements* pMemoryRequirements)
3293 {
3294 RADV_FROM_HANDLE(radv_device, device, _device);
3295 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3296
3297 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3298
3299 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3300 pMemoryRequirements->alignment = 4096;
3301 else
3302 pMemoryRequirements->alignment = 16;
3303
3304 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3305 }
3306
3307 void radv_GetBufferMemoryRequirements2(
3308 VkDevice device,
3309 const VkBufferMemoryRequirementsInfo2 *pInfo,
3310 VkMemoryRequirements2 *pMemoryRequirements)
3311 {
3312 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3313 &pMemoryRequirements->memoryRequirements);
3314 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3315 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3316 switch (ext->sType) {
3317 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3318 VkMemoryDedicatedRequirements *req =
3319 (VkMemoryDedicatedRequirements *) ext;
3320 req->requiresDedicatedAllocation = buffer->shareable;
3321 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3322 break;
3323 }
3324 default:
3325 break;
3326 }
3327 }
3328 }
3329
3330 void radv_GetImageMemoryRequirements(
3331 VkDevice _device,
3332 VkImage _image,
3333 VkMemoryRequirements* pMemoryRequirements)
3334 {
3335 RADV_FROM_HANDLE(radv_device, device, _device);
3336 RADV_FROM_HANDLE(radv_image, image, _image);
3337
3338 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3339
3340 pMemoryRequirements->size = image->size;
3341 pMemoryRequirements->alignment = image->alignment;
3342 }
3343
3344 void radv_GetImageMemoryRequirements2(
3345 VkDevice device,
3346 const VkImageMemoryRequirementsInfo2 *pInfo,
3347 VkMemoryRequirements2 *pMemoryRequirements)
3348 {
3349 radv_GetImageMemoryRequirements(device, pInfo->image,
3350 &pMemoryRequirements->memoryRequirements);
3351
3352 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3353
3354 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3355 switch (ext->sType) {
3356 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3357 VkMemoryDedicatedRequirements *req =
3358 (VkMemoryDedicatedRequirements *) ext;
3359 req->requiresDedicatedAllocation = image->shareable;
3360 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3361 break;
3362 }
3363 default:
3364 break;
3365 }
3366 }
3367 }
3368
3369 void radv_GetImageSparseMemoryRequirements(
3370 VkDevice device,
3371 VkImage image,
3372 uint32_t* pSparseMemoryRequirementCount,
3373 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3374 {
3375 stub();
3376 }
3377
3378 void radv_GetImageSparseMemoryRequirements2(
3379 VkDevice device,
3380 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3381 uint32_t* pSparseMemoryRequirementCount,
3382 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3383 {
3384 stub();
3385 }
3386
3387 void radv_GetDeviceMemoryCommitment(
3388 VkDevice device,
3389 VkDeviceMemory memory,
3390 VkDeviceSize* pCommittedMemoryInBytes)
3391 {
3392 *pCommittedMemoryInBytes = 0;
3393 }
3394
3395 VkResult radv_BindBufferMemory2(VkDevice device,
3396 uint32_t bindInfoCount,
3397 const VkBindBufferMemoryInfo *pBindInfos)
3398 {
3399 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3400 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3401 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3402
3403 if (mem) {
3404 buffer->bo = mem->bo;
3405 buffer->offset = pBindInfos[i].memoryOffset;
3406 } else {
3407 buffer->bo = NULL;
3408 }
3409 }
3410 return VK_SUCCESS;
3411 }
3412
3413 VkResult radv_BindBufferMemory(
3414 VkDevice device,
3415 VkBuffer buffer,
3416 VkDeviceMemory memory,
3417 VkDeviceSize memoryOffset)
3418 {
3419 const VkBindBufferMemoryInfo info = {
3420 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3421 .buffer = buffer,
3422 .memory = memory,
3423 .memoryOffset = memoryOffset
3424 };
3425
3426 return radv_BindBufferMemory2(device, 1, &info);
3427 }
3428
3429 VkResult radv_BindImageMemory2(VkDevice device,
3430 uint32_t bindInfoCount,
3431 const VkBindImageMemoryInfo *pBindInfos)
3432 {
3433 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3434 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3435 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3436
3437 if (mem) {
3438 image->bo = mem->bo;
3439 image->offset = pBindInfos[i].memoryOffset;
3440 } else {
3441 image->bo = NULL;
3442 image->offset = 0;
3443 }
3444 }
3445 return VK_SUCCESS;
3446 }
3447
3448
3449 VkResult radv_BindImageMemory(
3450 VkDevice device,
3451 VkImage image,
3452 VkDeviceMemory memory,
3453 VkDeviceSize memoryOffset)
3454 {
3455 const VkBindImageMemoryInfo info = {
3456 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3457 .image = image,
3458 .memory = memory,
3459 .memoryOffset = memoryOffset
3460 };
3461
3462 return radv_BindImageMemory2(device, 1, &info);
3463 }
3464
3465
3466 static void
3467 radv_sparse_buffer_bind_memory(struct radv_device *device,
3468 const VkSparseBufferMemoryBindInfo *bind)
3469 {
3470 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3471
3472 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3473 struct radv_device_memory *mem = NULL;
3474
3475 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3476 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3477
3478 device->ws->buffer_virtual_bind(buffer->bo,
3479 bind->pBinds[i].resourceOffset,
3480 bind->pBinds[i].size,
3481 mem ? mem->bo : NULL,
3482 bind->pBinds[i].memoryOffset);
3483 }
3484 }
3485
3486 static void
3487 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3488 const VkSparseImageOpaqueMemoryBindInfo *bind)
3489 {
3490 RADV_FROM_HANDLE(radv_image, image, bind->image);
3491
3492 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3493 struct radv_device_memory *mem = NULL;
3494
3495 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3496 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3497
3498 device->ws->buffer_virtual_bind(image->bo,
3499 bind->pBinds[i].resourceOffset,
3500 bind->pBinds[i].size,
3501 mem ? mem->bo : NULL,
3502 bind->pBinds[i].memoryOffset);
3503 }
3504 }
3505
3506 VkResult radv_QueueBindSparse(
3507 VkQueue _queue,
3508 uint32_t bindInfoCount,
3509 const VkBindSparseInfo* pBindInfo,
3510 VkFence _fence)
3511 {
3512 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3513 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3514 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3515 bool fence_emitted = false;
3516 VkResult result;
3517 int ret;
3518
3519 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3520 struct radv_winsys_sem_info sem_info;
3521 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3522 radv_sparse_buffer_bind_memory(queue->device,
3523 pBindInfo[i].pBufferBinds + j);
3524 }
3525
3526 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3527 radv_sparse_image_opaque_bind_memory(queue->device,
3528 pBindInfo[i].pImageOpaqueBinds + j);
3529 }
3530
3531 VkResult result;
3532 result = radv_alloc_sem_info(queue->device->instance,
3533 &sem_info,
3534 pBindInfo[i].waitSemaphoreCount,
3535 pBindInfo[i].pWaitSemaphores,
3536 pBindInfo[i].signalSemaphoreCount,
3537 pBindInfo[i].pSignalSemaphores,
3538 _fence);
3539 if (result != VK_SUCCESS)
3540 return result;
3541
3542 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3543 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3544 &queue->device->empty_cs[queue->queue_family_index],
3545 1, NULL, NULL,
3546 &sem_info, NULL,
3547 false, base_fence);
3548 if (ret) {
3549 radv_loge("failed to submit CS %d\n", i);
3550 abort();
3551 }
3552
3553 fence_emitted = true;
3554 if (fence)
3555 fence->submitted = true;
3556 }
3557
3558 radv_free_sem_info(&sem_info);
3559
3560 }
3561
3562 if (fence) {
3563 if (!fence_emitted) {
3564 result = radv_signal_fence(queue, fence);
3565 if (result != VK_SUCCESS)
3566 return result;
3567 }
3568 fence->submitted = true;
3569 }
3570
3571 return VK_SUCCESS;
3572 }
3573
3574 VkResult radv_CreateFence(
3575 VkDevice _device,
3576 const VkFenceCreateInfo* pCreateInfo,
3577 const VkAllocationCallbacks* pAllocator,
3578 VkFence* pFence)
3579 {
3580 RADV_FROM_HANDLE(radv_device, device, _device);
3581 const VkExportFenceCreateInfo *export =
3582 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3583 VkExternalFenceHandleTypeFlags handleTypes =
3584 export ? export->handleTypes : 0;
3585
3586 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3587 sizeof(*fence), 8,
3588 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3589
3590 if (!fence)
3591 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3592
3593 fence->fence_wsi = NULL;
3594 fence->submitted = false;
3595 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3596 fence->temp_syncobj = 0;
3597 if (device->always_use_syncobj || handleTypes) {
3598 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3599 if (ret) {
3600 vk_free2(&device->alloc, pAllocator, fence);
3601 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3602 }
3603 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3604 device->ws->signal_syncobj(device->ws, fence->syncobj);
3605 }
3606 fence->fence = NULL;
3607 } else {
3608 fence->fence = device->ws->create_fence();
3609 if (!fence->fence) {
3610 vk_free2(&device->alloc, pAllocator, fence);
3611 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3612 }
3613 fence->syncobj = 0;
3614 }
3615
3616 *pFence = radv_fence_to_handle(fence);
3617
3618 return VK_SUCCESS;
3619 }
3620
3621 void radv_DestroyFence(
3622 VkDevice _device,
3623 VkFence _fence,
3624 const VkAllocationCallbacks* pAllocator)
3625 {
3626 RADV_FROM_HANDLE(radv_device, device, _device);
3627 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3628
3629 if (!fence)
3630 return;
3631
3632 if (fence->temp_syncobj)
3633 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3634 if (fence->syncobj)
3635 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3636 if (fence->fence)
3637 device->ws->destroy_fence(fence->fence);
3638 if (fence->fence_wsi)
3639 fence->fence_wsi->destroy(fence->fence_wsi);
3640 vk_free2(&device->alloc, pAllocator, fence);
3641 }
3642
3643
3644 static uint64_t radv_get_current_time()
3645 {
3646 struct timespec tv;
3647 clock_gettime(CLOCK_MONOTONIC, &tv);
3648 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3649 }
3650
3651 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3652 {
3653 uint64_t current_time = radv_get_current_time();
3654
3655 timeout = MIN2(UINT64_MAX - current_time, timeout);
3656
3657 return current_time + timeout;
3658 }
3659
3660
3661 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3662 {
3663 for (uint32_t i = 0; i < fenceCount; ++i) {
3664 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3665 if (fence->fence == NULL || fence->syncobj ||
3666 fence->temp_syncobj ||
3667 (!fence->signalled && !fence->submitted))
3668 return false;
3669 }
3670 return true;
3671 }
3672
3673 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3674 {
3675 for (uint32_t i = 0; i < fenceCount; ++i) {
3676 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3677 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3678 return false;
3679 }
3680 return true;
3681 }
3682
3683 VkResult radv_WaitForFences(
3684 VkDevice _device,
3685 uint32_t fenceCount,
3686 const VkFence* pFences,
3687 VkBool32 waitAll,
3688 uint64_t timeout)
3689 {
3690 RADV_FROM_HANDLE(radv_device, device, _device);
3691 timeout = radv_get_absolute_timeout(timeout);
3692
3693 if (device->always_use_syncobj &&
3694 radv_all_fences_syncobj(fenceCount, pFences))
3695 {
3696 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3697 if (!handles)
3698 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3699
3700 for (uint32_t i = 0; i < fenceCount; ++i) {
3701 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3702 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3703 }
3704
3705 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3706
3707 free(handles);
3708 return success ? VK_SUCCESS : VK_TIMEOUT;
3709 }
3710
3711 if (!waitAll && fenceCount > 1) {
3712 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3713 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3714 uint32_t wait_count = 0;
3715 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3716 if (!fences)
3717 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3718
3719 for (uint32_t i = 0; i < fenceCount; ++i) {
3720 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3721
3722 if (fence->signalled) {
3723 free(fences);
3724 return VK_SUCCESS;
3725 }
3726
3727 fences[wait_count++] = fence->fence;
3728 }
3729
3730 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3731 waitAll, timeout - radv_get_current_time());
3732
3733 free(fences);
3734 return success ? VK_SUCCESS : VK_TIMEOUT;
3735 }
3736
3737 while(radv_get_current_time() <= timeout) {
3738 for (uint32_t i = 0; i < fenceCount; ++i) {
3739 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3740 return VK_SUCCESS;
3741 }
3742 }
3743 return VK_TIMEOUT;
3744 }
3745
3746 for (uint32_t i = 0; i < fenceCount; ++i) {
3747 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3748 bool expired = false;
3749
3750 if (fence->temp_syncobj) {
3751 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3752 return VK_TIMEOUT;
3753 continue;
3754 }
3755
3756 if (fence->syncobj) {
3757 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3758 return VK_TIMEOUT;
3759 continue;
3760 }
3761
3762 if (fence->signalled)
3763 continue;
3764
3765 if (fence->fence) {
3766 if (!fence->submitted) {
3767 while(radv_get_current_time() <= timeout &&
3768 !fence->submitted)
3769 /* Do nothing */;
3770
3771 if (!fence->submitted)
3772 return VK_TIMEOUT;
3773
3774 /* Recheck as it may have been set by
3775 * submitting operations. */
3776
3777 if (fence->signalled)
3778 continue;
3779 }
3780
3781 expired = device->ws->fence_wait(device->ws,
3782 fence->fence,
3783 true, timeout);
3784 if (!expired)
3785 return VK_TIMEOUT;
3786 }
3787
3788 if (fence->fence_wsi) {
3789 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3790 if (result != VK_SUCCESS)
3791 return result;
3792 }
3793
3794 fence->signalled = true;
3795 }
3796
3797 return VK_SUCCESS;
3798 }
3799
3800 VkResult radv_ResetFences(VkDevice _device,
3801 uint32_t fenceCount,
3802 const VkFence *pFences)
3803 {
3804 RADV_FROM_HANDLE(radv_device, device, _device);
3805
3806 for (unsigned i = 0; i < fenceCount; ++i) {
3807 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3808 fence->submitted = fence->signalled = false;
3809
3810 /* Per spec, we first restore the permanent payload, and then reset, so
3811 * having a temp syncobj should not skip resetting the permanent syncobj. */
3812 if (fence->temp_syncobj) {
3813 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3814 fence->temp_syncobj = 0;
3815 }
3816
3817 if (fence->syncobj) {
3818 device->ws->reset_syncobj(device->ws, fence->syncobj);
3819 }
3820 }
3821
3822 return VK_SUCCESS;
3823 }
3824
3825 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3826 {
3827 RADV_FROM_HANDLE(radv_device, device, _device);
3828 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3829
3830 if (fence->temp_syncobj) {
3831 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3832 return success ? VK_SUCCESS : VK_NOT_READY;
3833 }
3834
3835 if (fence->syncobj) {
3836 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3837 return success ? VK_SUCCESS : VK_NOT_READY;
3838 }
3839
3840 if (fence->signalled)
3841 return VK_SUCCESS;
3842 if (!fence->submitted)
3843 return VK_NOT_READY;
3844 if (fence->fence) {
3845 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3846 return VK_NOT_READY;
3847 }
3848 if (fence->fence_wsi) {
3849 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3850
3851 if (result != VK_SUCCESS) {
3852 if (result == VK_TIMEOUT)
3853 return VK_NOT_READY;
3854 return result;
3855 }
3856 }
3857 return VK_SUCCESS;
3858 }
3859
3860
3861 // Queue semaphore functions
3862
3863 VkResult radv_CreateSemaphore(
3864 VkDevice _device,
3865 const VkSemaphoreCreateInfo* pCreateInfo,
3866 const VkAllocationCallbacks* pAllocator,
3867 VkSemaphore* pSemaphore)
3868 {
3869 RADV_FROM_HANDLE(radv_device, device, _device);
3870 const VkExportSemaphoreCreateInfo *export =
3871 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3872 VkExternalSemaphoreHandleTypeFlags handleTypes =
3873 export ? export->handleTypes : 0;
3874
3875 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3876 sizeof(*sem), 8,
3877 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3878 if (!sem)
3879 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3880
3881 sem->temp_syncobj = 0;
3882 /* create a syncobject if we are going to export this semaphore */
3883 if (device->always_use_syncobj || handleTypes) {
3884 assert (device->physical_device->rad_info.has_syncobj);
3885 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3886 if (ret) {
3887 vk_free2(&device->alloc, pAllocator, sem);
3888 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3889 }
3890 sem->sem = NULL;
3891 } else {
3892 sem->sem = device->ws->create_sem(device->ws);
3893 if (!sem->sem) {
3894 vk_free2(&device->alloc, pAllocator, sem);
3895 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3896 }
3897 sem->syncobj = 0;
3898 }
3899
3900 *pSemaphore = radv_semaphore_to_handle(sem);
3901 return VK_SUCCESS;
3902 }
3903
3904 void radv_DestroySemaphore(
3905 VkDevice _device,
3906 VkSemaphore _semaphore,
3907 const VkAllocationCallbacks* pAllocator)
3908 {
3909 RADV_FROM_HANDLE(radv_device, device, _device);
3910 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3911 if (!_semaphore)
3912 return;
3913
3914 if (sem->syncobj)
3915 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3916 else
3917 device->ws->destroy_sem(sem->sem);
3918 vk_free2(&device->alloc, pAllocator, sem);
3919 }
3920
3921 VkResult radv_CreateEvent(
3922 VkDevice _device,
3923 const VkEventCreateInfo* pCreateInfo,
3924 const VkAllocationCallbacks* pAllocator,
3925 VkEvent* pEvent)
3926 {
3927 RADV_FROM_HANDLE(radv_device, device, _device);
3928 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3929 sizeof(*event), 8,
3930 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3931
3932 if (!event)
3933 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3934
3935 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3936 RADEON_DOMAIN_GTT,
3937 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3938 RADV_BO_PRIORITY_FENCE);
3939 if (!event->bo) {
3940 vk_free2(&device->alloc, pAllocator, event);
3941 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3942 }
3943
3944 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3945
3946 *pEvent = radv_event_to_handle(event);
3947
3948 return VK_SUCCESS;
3949 }
3950
3951 void radv_DestroyEvent(
3952 VkDevice _device,
3953 VkEvent _event,
3954 const VkAllocationCallbacks* pAllocator)
3955 {
3956 RADV_FROM_HANDLE(radv_device, device, _device);
3957 RADV_FROM_HANDLE(radv_event, event, _event);
3958
3959 if (!event)
3960 return;
3961 device->ws->buffer_destroy(event->bo);
3962 vk_free2(&device->alloc, pAllocator, event);
3963 }
3964
3965 VkResult radv_GetEventStatus(
3966 VkDevice _device,
3967 VkEvent _event)
3968 {
3969 RADV_FROM_HANDLE(radv_event, event, _event);
3970
3971 if (*event->map == 1)
3972 return VK_EVENT_SET;
3973 return VK_EVENT_RESET;
3974 }
3975
3976 VkResult radv_SetEvent(
3977 VkDevice _device,
3978 VkEvent _event)
3979 {
3980 RADV_FROM_HANDLE(radv_event, event, _event);
3981 *event->map = 1;
3982
3983 return VK_SUCCESS;
3984 }
3985
3986 VkResult radv_ResetEvent(
3987 VkDevice _device,
3988 VkEvent _event)
3989 {
3990 RADV_FROM_HANDLE(radv_event, event, _event);
3991 *event->map = 0;
3992
3993 return VK_SUCCESS;
3994 }
3995
3996 VkResult radv_CreateBuffer(
3997 VkDevice _device,
3998 const VkBufferCreateInfo* pCreateInfo,
3999 const VkAllocationCallbacks* pAllocator,
4000 VkBuffer* pBuffer)
4001 {
4002 RADV_FROM_HANDLE(radv_device, device, _device);
4003 struct radv_buffer *buffer;
4004
4005 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4006
4007 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4009 if (buffer == NULL)
4010 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4011
4012 buffer->size = pCreateInfo->size;
4013 buffer->usage = pCreateInfo->usage;
4014 buffer->bo = NULL;
4015 buffer->offset = 0;
4016 buffer->flags = pCreateInfo->flags;
4017
4018 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4019 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4020
4021 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4022 buffer->bo = device->ws->buffer_create(device->ws,
4023 align64(buffer->size, 4096),
4024 4096, 0, RADEON_FLAG_VIRTUAL,
4025 RADV_BO_PRIORITY_VIRTUAL);
4026 if (!buffer->bo) {
4027 vk_free2(&device->alloc, pAllocator, buffer);
4028 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4029 }
4030 }
4031
4032 *pBuffer = radv_buffer_to_handle(buffer);
4033
4034 return VK_SUCCESS;
4035 }
4036
4037 void radv_DestroyBuffer(
4038 VkDevice _device,
4039 VkBuffer _buffer,
4040 const VkAllocationCallbacks* pAllocator)
4041 {
4042 RADV_FROM_HANDLE(radv_device, device, _device);
4043 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4044
4045 if (!buffer)
4046 return;
4047
4048 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4049 device->ws->buffer_destroy(buffer->bo);
4050
4051 vk_free2(&device->alloc, pAllocator, buffer);
4052 }
4053
4054 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4055 VkDevice device,
4056 const VkBufferDeviceAddressInfoEXT* pInfo)
4057 {
4058 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4059 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4060 }
4061
4062
4063 static inline unsigned
4064 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4065 {
4066 if (stencil)
4067 return image->surface.u.legacy.stencil_tiling_index[level];
4068 else
4069 return image->surface.u.legacy.tiling_index[level];
4070 }
4071
4072 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4073 {
4074 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4075 }
4076
4077 static uint32_t
4078 radv_init_dcc_control_reg(struct radv_device *device,
4079 struct radv_image_view *iview)
4080 {
4081 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4082 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4083 unsigned max_compressed_block_size;
4084 unsigned independent_64b_blocks;
4085
4086 if (!radv_image_has_dcc(iview->image))
4087 return 0;
4088
4089 if (iview->image->info.samples > 1) {
4090 if (iview->image->surface.bpe == 1)
4091 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4092 else if (iview->image->surface.bpe == 2)
4093 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4094 }
4095
4096 if (!device->physical_device->rad_info.has_dedicated_vram) {
4097 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4098 * dGPU and 64 for APU because all of our APUs to date use
4099 * DIMMs which have a request granularity size of 64B while all
4100 * other chips have a 32B request size.
4101 */
4102 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4103 }
4104
4105 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4106 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4107 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4108 /* If this DCC image is potentially going to be used in texture
4109 * fetches, we need some special settings.
4110 */
4111 independent_64b_blocks = 1;
4112 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4113 } else {
4114 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4115 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4116 * big as possible for better compression state.
4117 */
4118 independent_64b_blocks = 0;
4119 max_compressed_block_size = max_uncompressed_block_size;
4120 }
4121
4122 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4123 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4124 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4125 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4126 }
4127
4128 static void
4129 radv_initialise_color_surface(struct radv_device *device,
4130 struct radv_color_buffer_info *cb,
4131 struct radv_image_view *iview)
4132 {
4133 const struct vk_format_description *desc;
4134 unsigned ntype, format, swap, endian;
4135 unsigned blend_clamp = 0, blend_bypass = 0;
4136 uint64_t va;
4137 const struct radeon_surf *surf = &iview->image->surface;
4138
4139 desc = vk_format_description(iview->vk_format);
4140
4141 memset(cb, 0, sizeof(*cb));
4142
4143 /* Intensity is implemented as Red, so treat it that way. */
4144 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4145
4146 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4147
4148 cb->cb_color_base = va >> 8;
4149
4150 if (device->physical_device->rad_info.chip_class >= GFX9) {
4151 struct gfx9_surf_meta_flags meta;
4152 if (iview->image->dcc_offset)
4153 meta = iview->image->surface.u.gfx9.dcc;
4154 else
4155 meta = iview->image->surface.u.gfx9.cmask;
4156
4157 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4158 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4159 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4160 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4161
4162 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4163 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4164 } else {
4165 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4166 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4167
4168 cb->cb_color_base += level_info->offset >> 8;
4169 if (level_info->mode == RADEON_SURF_MODE_2D)
4170 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4171
4172 pitch_tile_max = level_info->nblk_x / 8 - 1;
4173 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4174 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4175
4176 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4177 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4178 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4179
4180 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4181
4182 if (radv_image_has_fmask(iview->image)) {
4183 if (device->physical_device->rad_info.chip_class >= CIK)
4184 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4185 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4186 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4187 } else {
4188 /* This must be set for fast clear to work without FMASK. */
4189 if (device->physical_device->rad_info.chip_class >= CIK)
4190 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4191 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4192 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4193 }
4194 }
4195
4196 /* CMASK variables */
4197 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4198 va += iview->image->cmask.offset;
4199 cb->cb_color_cmask = va >> 8;
4200
4201 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4202 va += iview->image->dcc_offset;
4203 cb->cb_dcc_base = va >> 8;
4204 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4205
4206 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4207 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4208 S_028C6C_SLICE_MAX(max_slice);
4209
4210 if (iview->image->info.samples > 1) {
4211 unsigned log_samples = util_logbase2(iview->image->info.samples);
4212
4213 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4214 S_028C74_NUM_FRAGMENTS(log_samples);
4215 }
4216
4217 if (radv_image_has_fmask(iview->image)) {
4218 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4219 cb->cb_color_fmask = va >> 8;
4220 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4221 } else {
4222 cb->cb_color_fmask = cb->cb_color_base;
4223 }
4224
4225 ntype = radv_translate_color_numformat(iview->vk_format,
4226 desc,
4227 vk_format_get_first_non_void_channel(iview->vk_format));
4228 format = radv_translate_colorformat(iview->vk_format);
4229 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4230 radv_finishme("Illegal color\n");
4231 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4232 endian = radv_colorformat_endian_swap(format);
4233
4234 /* blend clamp should be set for all NORM/SRGB types */
4235 if (ntype == V_028C70_NUMBER_UNORM ||
4236 ntype == V_028C70_NUMBER_SNORM ||
4237 ntype == V_028C70_NUMBER_SRGB)
4238 blend_clamp = 1;
4239
4240 /* set blend bypass according to docs if SINT/UINT or
4241 8/24 COLOR variants */
4242 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4243 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4244 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4245 blend_clamp = 0;
4246 blend_bypass = 1;
4247 }
4248 #if 0
4249 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4250 (format == V_028C70_COLOR_8 ||
4251 format == V_028C70_COLOR_8_8 ||
4252 format == V_028C70_COLOR_8_8_8_8))
4253 ->color_is_int8 = true;
4254 #endif
4255 cb->cb_color_info = S_028C70_FORMAT(format) |
4256 S_028C70_COMP_SWAP(swap) |
4257 S_028C70_BLEND_CLAMP(blend_clamp) |
4258 S_028C70_BLEND_BYPASS(blend_bypass) |
4259 S_028C70_SIMPLE_FLOAT(1) |
4260 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4261 ntype != V_028C70_NUMBER_SNORM &&
4262 ntype != V_028C70_NUMBER_SRGB &&
4263 format != V_028C70_COLOR_8_24 &&
4264 format != V_028C70_COLOR_24_8) |
4265 S_028C70_NUMBER_TYPE(ntype) |
4266 S_028C70_ENDIAN(endian);
4267 if (radv_image_has_fmask(iview->image)) {
4268 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4269 if (device->physical_device->rad_info.chip_class == SI) {
4270 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4271 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4272 }
4273 }
4274
4275 if (radv_image_has_cmask(iview->image) &&
4276 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4277 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4278
4279 if (radv_dcc_enabled(iview->image, iview->base_mip))
4280 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4281
4282 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4283
4284 /* This must be set for fast clear to work without FMASK. */
4285 if (!radv_image_has_fmask(iview->image) &&
4286 device->physical_device->rad_info.chip_class == SI) {
4287 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4288 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4289 }
4290
4291 if (device->physical_device->rad_info.chip_class >= GFX9) {
4292 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4293 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4294
4295 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4296 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4297 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4298 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4299 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4300 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4301 }
4302 }
4303
4304 static unsigned
4305 radv_calc_decompress_on_z_planes(struct radv_device *device,
4306 struct radv_image_view *iview)
4307 {
4308 unsigned max_zplanes = 0;
4309
4310 assert(radv_image_is_tc_compat_htile(iview->image));
4311
4312 if (device->physical_device->rad_info.chip_class >= GFX9) {
4313 /* Default value for 32-bit depth surfaces. */
4314 max_zplanes = 4;
4315
4316 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4317 iview->image->info.samples > 1)
4318 max_zplanes = 2;
4319
4320 max_zplanes = max_zplanes + 1;
4321 } else {
4322 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4323 /* Do not enable Z plane compression for 16-bit depth
4324 * surfaces because isn't supported on GFX8. Only
4325 * 32-bit depth surfaces are supported by the hardware.
4326 * This allows to maintain shader compatibility and to
4327 * reduce the number of depth decompressions.
4328 */
4329 max_zplanes = 1;
4330 } else {
4331 if (iview->image->info.samples <= 1)
4332 max_zplanes = 5;
4333 else if (iview->image->info.samples <= 4)
4334 max_zplanes = 3;
4335 else
4336 max_zplanes = 2;
4337 }
4338 }
4339
4340 return max_zplanes;
4341 }
4342
4343 static void
4344 radv_initialise_ds_surface(struct radv_device *device,
4345 struct radv_ds_buffer_info *ds,
4346 struct radv_image_view *iview)
4347 {
4348 unsigned level = iview->base_mip;
4349 unsigned format, stencil_format;
4350 uint64_t va, s_offs, z_offs;
4351 bool stencil_only = false;
4352 memset(ds, 0, sizeof(*ds));
4353 switch (iview->image->vk_format) {
4354 case VK_FORMAT_D24_UNORM_S8_UINT:
4355 case VK_FORMAT_X8_D24_UNORM_PACK32:
4356 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4357 ds->offset_scale = 2.0f;
4358 break;
4359 case VK_FORMAT_D16_UNORM:
4360 case VK_FORMAT_D16_UNORM_S8_UINT:
4361 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4362 ds->offset_scale = 4.0f;
4363 break;
4364 case VK_FORMAT_D32_SFLOAT:
4365 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4366 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4367 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4368 ds->offset_scale = 1.0f;
4369 break;
4370 case VK_FORMAT_S8_UINT:
4371 stencil_only = true;
4372 break;
4373 default:
4374 break;
4375 }
4376
4377 format = radv_translate_dbformat(iview->image->vk_format);
4378 stencil_format = iview->image->surface.has_stencil ?
4379 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4380
4381 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4382 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4383 S_028008_SLICE_MAX(max_slice);
4384
4385 ds->db_htile_data_base = 0;
4386 ds->db_htile_surface = 0;
4387
4388 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4389 s_offs = z_offs = va;
4390
4391 if (device->physical_device->rad_info.chip_class >= GFX9) {
4392 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4393 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4394
4395 ds->db_z_info = S_028038_FORMAT(format) |
4396 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4397 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4398 S_028038_MAXMIP(iview->image->info.levels - 1) |
4399 S_028038_ZRANGE_PRECISION(1);
4400 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4401 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4402
4403 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4404 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4405 ds->db_depth_view |= S_028008_MIPID(level);
4406
4407 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4408 S_02801C_Y_MAX(iview->image->info.height - 1);
4409
4410 if (radv_htile_enabled(iview->image, level)) {
4411 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4412
4413 if (radv_image_is_tc_compat_htile(iview->image)) {
4414 unsigned max_zplanes =
4415 radv_calc_decompress_on_z_planes(device, iview);
4416
4417 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4418 S_028038_ITERATE_FLUSH(1);
4419 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4420 }
4421
4422 if (!iview->image->surface.has_stencil)
4423 /* Use all of the htile_buffer for depth if there's no stencil. */
4424 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4425 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4426 iview->image->htile_offset;
4427 ds->db_htile_data_base = va >> 8;
4428 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4429 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4430 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4431 }
4432 } else {
4433 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4434
4435 if (stencil_only)
4436 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4437
4438 z_offs += iview->image->surface.u.legacy.level[level].offset;
4439 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4440
4441 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4442 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4443 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4444
4445 if (iview->image->info.samples > 1)
4446 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4447
4448 if (device->physical_device->rad_info.chip_class >= CIK) {
4449 struct radeon_info *info = &device->physical_device->rad_info;
4450 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4451 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4452 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4453 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4454 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4455 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4456
4457 if (stencil_only)
4458 tile_mode = stencil_tile_mode;
4459
4460 ds->db_depth_info |=
4461 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4462 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4463 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4464 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4465 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4466 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4467 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4468 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4469 } else {
4470 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4471 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4472 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4473 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4474 if (stencil_only)
4475 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4476 }
4477
4478 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4479 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4480 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4481
4482 if (radv_htile_enabled(iview->image, level)) {
4483 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4484
4485 if (!iview->image->surface.has_stencil &&
4486 !radv_image_is_tc_compat_htile(iview->image))
4487 /* Use all of the htile_buffer for depth if there's no stencil. */
4488 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4489
4490 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4491 iview->image->htile_offset;
4492 ds->db_htile_data_base = va >> 8;
4493 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4494
4495 if (radv_image_is_tc_compat_htile(iview->image)) {
4496 unsigned max_zplanes =
4497 radv_calc_decompress_on_z_planes(device, iview);
4498
4499 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4500 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4501 }
4502 }
4503 }
4504
4505 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4506 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4507 }
4508
4509 VkResult radv_CreateFramebuffer(
4510 VkDevice _device,
4511 const VkFramebufferCreateInfo* pCreateInfo,
4512 const VkAllocationCallbacks* pAllocator,
4513 VkFramebuffer* pFramebuffer)
4514 {
4515 RADV_FROM_HANDLE(radv_device, device, _device);
4516 struct radv_framebuffer *framebuffer;
4517
4518 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4519
4520 size_t size = sizeof(*framebuffer) +
4521 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4522 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4523 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4524 if (framebuffer == NULL)
4525 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4526
4527 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4528 framebuffer->width = pCreateInfo->width;
4529 framebuffer->height = pCreateInfo->height;
4530 framebuffer->layers = pCreateInfo->layers;
4531 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4532 VkImageView _iview = pCreateInfo->pAttachments[i];
4533 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4534 framebuffer->attachments[i].attachment = iview;
4535 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4536 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4537 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4538 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4539 }
4540 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4541 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4542 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4543 }
4544
4545 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4546 return VK_SUCCESS;
4547 }
4548
4549 void radv_DestroyFramebuffer(
4550 VkDevice _device,
4551 VkFramebuffer _fb,
4552 const VkAllocationCallbacks* pAllocator)
4553 {
4554 RADV_FROM_HANDLE(radv_device, device, _device);
4555 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4556
4557 if (!fb)
4558 return;
4559 vk_free2(&device->alloc, pAllocator, fb);
4560 }
4561
4562 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4563 {
4564 switch (address_mode) {
4565 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4566 return V_008F30_SQ_TEX_WRAP;
4567 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4568 return V_008F30_SQ_TEX_MIRROR;
4569 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4570 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4571 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4572 return V_008F30_SQ_TEX_CLAMP_BORDER;
4573 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4574 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4575 default:
4576 unreachable("illegal tex wrap mode");
4577 break;
4578 }
4579 }
4580
4581 static unsigned
4582 radv_tex_compare(VkCompareOp op)
4583 {
4584 switch (op) {
4585 case VK_COMPARE_OP_NEVER:
4586 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4587 case VK_COMPARE_OP_LESS:
4588 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4589 case VK_COMPARE_OP_EQUAL:
4590 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4591 case VK_COMPARE_OP_LESS_OR_EQUAL:
4592 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4593 case VK_COMPARE_OP_GREATER:
4594 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4595 case VK_COMPARE_OP_NOT_EQUAL:
4596 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4597 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4598 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4599 case VK_COMPARE_OP_ALWAYS:
4600 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4601 default:
4602 unreachable("illegal compare mode");
4603 break;
4604 }
4605 }
4606
4607 static unsigned
4608 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4609 {
4610 switch (filter) {
4611 case VK_FILTER_NEAREST:
4612 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4613 V_008F38_SQ_TEX_XY_FILTER_POINT);
4614 case VK_FILTER_LINEAR:
4615 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4616 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4617 case VK_FILTER_CUBIC_IMG:
4618 default:
4619 fprintf(stderr, "illegal texture filter");
4620 return 0;
4621 }
4622 }
4623
4624 static unsigned
4625 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4626 {
4627 switch (mode) {
4628 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4629 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4630 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4631 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4632 default:
4633 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4634 }
4635 }
4636
4637 static unsigned
4638 radv_tex_bordercolor(VkBorderColor bcolor)
4639 {
4640 switch (bcolor) {
4641 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4642 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4643 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4644 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4645 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4646 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4647 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4648 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4649 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4650 default:
4651 break;
4652 }
4653 return 0;
4654 }
4655
4656 static unsigned
4657 radv_tex_aniso_filter(unsigned filter)
4658 {
4659 if (filter < 2)
4660 return 0;
4661 if (filter < 4)
4662 return 1;
4663 if (filter < 8)
4664 return 2;
4665 if (filter < 16)
4666 return 3;
4667 return 4;
4668 }
4669
4670 static unsigned
4671 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4672 {
4673 switch (mode) {
4674 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4675 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4676 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4677 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4678 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4679 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4680 default:
4681 break;
4682 }
4683 return 0;
4684 }
4685
4686 static uint32_t
4687 radv_get_max_anisotropy(struct radv_device *device,
4688 const VkSamplerCreateInfo *pCreateInfo)
4689 {
4690 if (device->force_aniso >= 0)
4691 return device->force_aniso;
4692
4693 if (pCreateInfo->anisotropyEnable &&
4694 pCreateInfo->maxAnisotropy > 1.0f)
4695 return (uint32_t)pCreateInfo->maxAnisotropy;
4696
4697 return 0;
4698 }
4699
4700 static void
4701 radv_init_sampler(struct radv_device *device,
4702 struct radv_sampler *sampler,
4703 const VkSamplerCreateInfo *pCreateInfo)
4704 {
4705 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4706 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4707 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4708 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4709
4710 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4711 vk_find_struct_const(pCreateInfo->pNext,
4712 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4713 if (sampler_reduction)
4714 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4715
4716 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4717 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4718 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4719 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4720 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4721 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4722 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4723 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4724 S_008F30_DISABLE_CUBE_WRAP(0) |
4725 S_008F30_COMPAT_MODE(is_vi) |
4726 S_008F30_FILTER_MODE(filter_mode));
4727 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4728 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4729 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4730 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4731 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4732 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4733 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4734 S_008F38_MIP_POINT_PRECLAMP(0) |
4735 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4736 S_008F38_FILTER_PREC_FIX(1) |
4737 S_008F38_ANISO_OVERRIDE(is_vi));
4738 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4739 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4740 }
4741
4742 VkResult radv_CreateSampler(
4743 VkDevice _device,
4744 const VkSamplerCreateInfo* pCreateInfo,
4745 const VkAllocationCallbacks* pAllocator,
4746 VkSampler* pSampler)
4747 {
4748 RADV_FROM_HANDLE(radv_device, device, _device);
4749 struct radv_sampler *sampler;
4750
4751 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4752
4753 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4754 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4755 if (!sampler)
4756 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4757
4758 radv_init_sampler(device, sampler, pCreateInfo);
4759 *pSampler = radv_sampler_to_handle(sampler);
4760
4761 return VK_SUCCESS;
4762 }
4763
4764 void radv_DestroySampler(
4765 VkDevice _device,
4766 VkSampler _sampler,
4767 const VkAllocationCallbacks* pAllocator)
4768 {
4769 RADV_FROM_HANDLE(radv_device, device, _device);
4770 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4771
4772 if (!sampler)
4773 return;
4774 vk_free2(&device->alloc, pAllocator, sampler);
4775 }
4776
4777 /* vk_icd.h does not declare this function, so we declare it here to
4778 * suppress Wmissing-prototypes.
4779 */
4780 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4781 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4782
4783 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4784 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4785 {
4786 /* For the full details on loader interface versioning, see
4787 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4788 * What follows is a condensed summary, to help you navigate the large and
4789 * confusing official doc.
4790 *
4791 * - Loader interface v0 is incompatible with later versions. We don't
4792 * support it.
4793 *
4794 * - In loader interface v1:
4795 * - The first ICD entrypoint called by the loader is
4796 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4797 * entrypoint.
4798 * - The ICD must statically expose no other Vulkan symbol unless it is
4799 * linked with -Bsymbolic.
4800 * - Each dispatchable Vulkan handle created by the ICD must be
4801 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4802 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4803 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4804 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4805 * such loader-managed surfaces.
4806 *
4807 * - Loader interface v2 differs from v1 in:
4808 * - The first ICD entrypoint called by the loader is
4809 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4810 * statically expose this entrypoint.
4811 *
4812 * - Loader interface v3 differs from v2 in:
4813 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4814 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4815 * because the loader no longer does so.
4816 */
4817 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4818 return VK_SUCCESS;
4819 }
4820
4821 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4822 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4823 int *pFD)
4824 {
4825 RADV_FROM_HANDLE(radv_device, device, _device);
4826 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4827
4828 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4829
4830 /* At the moment, we support only the below handle types. */
4831 assert(pGetFdInfo->handleType ==
4832 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4833 pGetFdInfo->handleType ==
4834 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4835
4836 bool ret = radv_get_memory_fd(device, memory, pFD);
4837 if (ret == false)
4838 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4839 return VK_SUCCESS;
4840 }
4841
4842 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4843 VkExternalMemoryHandleTypeFlagBits handleType,
4844 int fd,
4845 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4846 {
4847 RADV_FROM_HANDLE(radv_device, device, _device);
4848
4849 switch (handleType) {
4850 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4851 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4852 return VK_SUCCESS;
4853
4854 default:
4855 /* The valid usage section for this function says:
4856 *
4857 * "handleType must not be one of the handle types defined as
4858 * opaque."
4859 *
4860 * So opaque handle types fall into the default "unsupported" case.
4861 */
4862 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4863 }
4864 }
4865
4866 static VkResult radv_import_opaque_fd(struct radv_device *device,
4867 int fd,
4868 uint32_t *syncobj)
4869 {
4870 uint32_t syncobj_handle = 0;
4871 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4872 if (ret != 0)
4873 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4874
4875 if (*syncobj)
4876 device->ws->destroy_syncobj(device->ws, *syncobj);
4877
4878 *syncobj = syncobj_handle;
4879 close(fd);
4880
4881 return VK_SUCCESS;
4882 }
4883
4884 static VkResult radv_import_sync_fd(struct radv_device *device,
4885 int fd,
4886 uint32_t *syncobj)
4887 {
4888 /* If we create a syncobj we do it locally so that if we have an error, we don't
4889 * leave a syncobj in an undetermined state in the fence. */
4890 uint32_t syncobj_handle = *syncobj;
4891 if (!syncobj_handle) {
4892 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4893 if (ret) {
4894 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4895 }
4896 }
4897
4898 if (fd == -1) {
4899 device->ws->signal_syncobj(device->ws, syncobj_handle);
4900 } else {
4901 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4902 if (ret != 0)
4903 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4904 }
4905
4906 *syncobj = syncobj_handle;
4907 if (fd != -1)
4908 close(fd);
4909
4910 return VK_SUCCESS;
4911 }
4912
4913 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4914 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4915 {
4916 RADV_FROM_HANDLE(radv_device, device, _device);
4917 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4918 uint32_t *syncobj_dst = NULL;
4919
4920 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4921 syncobj_dst = &sem->temp_syncobj;
4922 } else {
4923 syncobj_dst = &sem->syncobj;
4924 }
4925
4926 switch(pImportSemaphoreFdInfo->handleType) {
4927 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4928 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4929 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4930 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4931 default:
4932 unreachable("Unhandled semaphore handle type");
4933 }
4934 }
4935
4936 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4937 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4938 int *pFd)
4939 {
4940 RADV_FROM_HANDLE(radv_device, device, _device);
4941 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4942 int ret;
4943 uint32_t syncobj_handle;
4944
4945 if (sem->temp_syncobj)
4946 syncobj_handle = sem->temp_syncobj;
4947 else
4948 syncobj_handle = sem->syncobj;
4949
4950 switch(pGetFdInfo->handleType) {
4951 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4952 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4953 break;
4954 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4955 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4956 if (!ret) {
4957 if (sem->temp_syncobj) {
4958 close (sem->temp_syncobj);
4959 sem->temp_syncobj = 0;
4960 } else {
4961 device->ws->reset_syncobj(device->ws, syncobj_handle);
4962 }
4963 }
4964 break;
4965 default:
4966 unreachable("Unhandled semaphore handle type");
4967 }
4968
4969 if (ret)
4970 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4971 return VK_SUCCESS;
4972 }
4973
4974 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4975 VkPhysicalDevice physicalDevice,
4976 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4977 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4978 {
4979 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4980
4981 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4982 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4983 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4984 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4985 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4986 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4987 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4988 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4989 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4990 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4991 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4992 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4993 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4994 } else {
4995 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4996 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4997 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4998 }
4999 }
5000
5001 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5002 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5003 {
5004 RADV_FROM_HANDLE(radv_device, device, _device);
5005 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5006 uint32_t *syncobj_dst = NULL;
5007
5008
5009 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5010 syncobj_dst = &fence->temp_syncobj;
5011 } else {
5012 syncobj_dst = &fence->syncobj;
5013 }
5014
5015 switch(pImportFenceFdInfo->handleType) {
5016 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5017 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5018 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5019 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5020 default:
5021 unreachable("Unhandled fence handle type");
5022 }
5023 }
5024
5025 VkResult radv_GetFenceFdKHR(VkDevice _device,
5026 const VkFenceGetFdInfoKHR *pGetFdInfo,
5027 int *pFd)
5028 {
5029 RADV_FROM_HANDLE(radv_device, device, _device);
5030 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5031 int ret;
5032 uint32_t syncobj_handle;
5033
5034 if (fence->temp_syncobj)
5035 syncobj_handle = fence->temp_syncobj;
5036 else
5037 syncobj_handle = fence->syncobj;
5038
5039 switch(pGetFdInfo->handleType) {
5040 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5041 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5042 break;
5043 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5044 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5045 if (!ret) {
5046 if (fence->temp_syncobj) {
5047 close (fence->temp_syncobj);
5048 fence->temp_syncobj = 0;
5049 } else {
5050 device->ws->reset_syncobj(device->ws, syncobj_handle);
5051 }
5052 }
5053 break;
5054 default:
5055 unreachable("Unhandled fence handle type");
5056 }
5057
5058 if (ret)
5059 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5060 return VK_SUCCESS;
5061 }
5062
5063 void radv_GetPhysicalDeviceExternalFenceProperties(
5064 VkPhysicalDevice physicalDevice,
5065 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5066 VkExternalFenceProperties *pExternalFenceProperties)
5067 {
5068 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5069
5070 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5071 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5072 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5073 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5074 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5075 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5076 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5077 } else {
5078 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5079 pExternalFenceProperties->compatibleHandleTypes = 0;
5080 pExternalFenceProperties->externalFenceFeatures = 0;
5081 }
5082 }
5083
5084 VkResult
5085 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5086 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5087 const VkAllocationCallbacks* pAllocator,
5088 VkDebugReportCallbackEXT* pCallback)
5089 {
5090 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5091 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5092 pCreateInfo, pAllocator, &instance->alloc,
5093 pCallback);
5094 }
5095
5096 void
5097 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5098 VkDebugReportCallbackEXT _callback,
5099 const VkAllocationCallbacks* pAllocator)
5100 {
5101 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5102 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5103 _callback, pAllocator, &instance->alloc);
5104 }
5105
5106 void
5107 radv_DebugReportMessageEXT(VkInstance _instance,
5108 VkDebugReportFlagsEXT flags,
5109 VkDebugReportObjectTypeEXT objectType,
5110 uint64_t object,
5111 size_t location,
5112 int32_t messageCode,
5113 const char* pLayerPrefix,
5114 const char* pMessage)
5115 {
5116 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5117 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5118 object, location, messageCode, pLayerPrefix, pMessage);
5119 }
5120
5121 void
5122 radv_GetDeviceGroupPeerMemoryFeatures(
5123 VkDevice device,
5124 uint32_t heapIndex,
5125 uint32_t localDeviceIndex,
5126 uint32_t remoteDeviceIndex,
5127 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5128 {
5129 assert(localDeviceIndex == remoteDeviceIndex);
5130
5131 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5132 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5133 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5134 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5135 }
5136
5137 static const VkTimeDomainEXT radv_time_domains[] = {
5138 VK_TIME_DOMAIN_DEVICE_EXT,
5139 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5140 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5141 };
5142
5143 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5144 VkPhysicalDevice physicalDevice,
5145 uint32_t *pTimeDomainCount,
5146 VkTimeDomainEXT *pTimeDomains)
5147 {
5148 int d;
5149 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5150
5151 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5152 vk_outarray_append(&out, i) {
5153 *i = radv_time_domains[d];
5154 }
5155 }
5156
5157 return vk_outarray_status(&out);
5158 }
5159
5160 static uint64_t
5161 radv_clock_gettime(clockid_t clock_id)
5162 {
5163 struct timespec current;
5164 int ret;
5165
5166 ret = clock_gettime(clock_id, &current);
5167 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5168 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5169 if (ret < 0)
5170 return 0;
5171
5172 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5173 }
5174
5175 VkResult radv_GetCalibratedTimestampsEXT(
5176 VkDevice _device,
5177 uint32_t timestampCount,
5178 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5179 uint64_t *pTimestamps,
5180 uint64_t *pMaxDeviation)
5181 {
5182 RADV_FROM_HANDLE(radv_device, device, _device);
5183 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5184 int d;
5185 uint64_t begin, end;
5186 uint64_t max_clock_period = 0;
5187
5188 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5189
5190 for (d = 0; d < timestampCount; d++) {
5191 switch (pTimestampInfos[d].timeDomain) {
5192 case VK_TIME_DOMAIN_DEVICE_EXT:
5193 pTimestamps[d] = device->ws->query_value(device->ws,
5194 RADEON_TIMESTAMP);
5195 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5196 max_clock_period = MAX2(max_clock_period, device_period);
5197 break;
5198 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5199 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5200 max_clock_period = MAX2(max_clock_period, 1);
5201 break;
5202
5203 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5204 pTimestamps[d] = begin;
5205 break;
5206 default:
5207 pTimestamps[d] = 0;
5208 break;
5209 }
5210 }
5211
5212 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5213
5214 /*
5215 * The maximum deviation is the sum of the interval over which we
5216 * perform the sampling and the maximum period of any sampled
5217 * clock. That's because the maximum skew between any two sampled
5218 * clock edges is when the sampled clock with the largest period is
5219 * sampled at the end of that period but right at the beginning of the
5220 * sampling interval and some other clock is sampled right at the
5221 * begining of its sampling period and right at the end of the
5222 * sampling interval. Let's assume the GPU has the longest clock
5223 * period and that the application is sampling GPU and monotonic:
5224 *
5225 * s e
5226 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5227 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5228 *
5229 * g
5230 * 0 1 2 3
5231 * GPU -----_____-----_____-----_____-----_____
5232 *
5233 * m
5234 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5235 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5236 *
5237 * Interval <----------------->
5238 * Deviation <-------------------------->
5239 *
5240 * s = read(raw) 2
5241 * g = read(GPU) 1
5242 * m = read(monotonic) 2
5243 * e = read(raw) b
5244 *
5245 * We round the sample interval up by one tick to cover sampling error
5246 * in the interval clock
5247 */
5248
5249 uint64_t sample_interval = end - begin + 1;
5250
5251 *pMaxDeviation = sample_interval + max_clock_period;
5252
5253 return VK_SUCCESS;
5254 }