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radv: Also set DCC params for sampling for input attachment usage.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 radv_physical_device_init_mem_types(device);
267
268 result = radv_init_wsi(device);
269 if (result != VK_SUCCESS) {
270 device->ws->destroy(device->ws);
271 goto fail;
272 }
273
274 return VK_SUCCESS;
275
276 fail:
277 close(fd);
278 return result;
279 }
280
281 static void
282 radv_physical_device_finish(struct radv_physical_device *device)
283 {
284 radv_finish_wsi(device);
285 device->ws->destroy(device->ws);
286 disk_cache_destroy(device->disk_cache);
287 close(device->local_fd);
288 }
289
290 static void *
291 default_alloc_func(void *pUserData, size_t size, size_t align,
292 VkSystemAllocationScope allocationScope)
293 {
294 return malloc(size);
295 }
296
297 static void *
298 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
299 size_t align, VkSystemAllocationScope allocationScope)
300 {
301 return realloc(pOriginal, size);
302 }
303
304 static void
305 default_free_func(void *pUserData, void *pMemory)
306 {
307 free(pMemory);
308 }
309
310 static const VkAllocationCallbacks default_alloc = {
311 .pUserData = NULL,
312 .pfnAllocation = default_alloc_func,
313 .pfnReallocation = default_realloc_func,
314 .pfnFree = default_free_func,
315 };
316
317 static const struct debug_control radv_debug_options[] = {
318 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
319 {"nodcc", RADV_DEBUG_NO_DCC},
320 {"shaders", RADV_DEBUG_DUMP_SHADERS},
321 {"nocache", RADV_DEBUG_NO_CACHE},
322 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
323 {"nohiz", RADV_DEBUG_NO_HIZ},
324 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
325 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
326 {"allbos", RADV_DEBUG_ALL_BOS},
327 {"noibs", RADV_DEBUG_NO_IBS},
328 {"spirv", RADV_DEBUG_DUMP_SPIRV},
329 {"vmfaults", RADV_DEBUG_VM_FAULTS},
330 {"zerovram", RADV_DEBUG_ZERO_VRAM},
331 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
332 {"nosisched", RADV_DEBUG_NO_SISCHED},
333 {NULL, 0}
334 };
335
336 const char *
337 radv_get_debug_option_name(int id)
338 {
339 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
340 return radv_debug_options[id].string;
341 }
342
343 static const struct debug_control radv_perftest_options[] = {
344 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
345 {"sisched", RADV_PERFTEST_SISCHED},
346 {"localbos", RADV_PERFTEST_LOCAL_BOS},
347 {NULL, 0}
348 };
349
350 const char *
351 radv_get_perftest_option_name(int id)
352 {
353 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
354 return radv_perftest_options[id].string;
355 }
356
357 static void
358 radv_handle_per_app_options(struct radv_instance *instance,
359 const VkApplicationInfo *info)
360 {
361 const char *name = info ? info->pApplicationName : NULL;
362
363 if (!name)
364 return;
365
366 if (!strcmp(name, "Talos - Linux - 32bit") ||
367 !strcmp(name, "Talos - Linux - 64bit")) {
368 /* Force enable LLVM sisched for Talos because it looks safe
369 * and it gives few more FPS.
370 */
371 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
372 }
373 }
374
375 VkResult radv_CreateInstance(
376 const VkInstanceCreateInfo* pCreateInfo,
377 const VkAllocationCallbacks* pAllocator,
378 VkInstance* pInstance)
379 {
380 struct radv_instance *instance;
381
382 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
383
384 uint32_t client_version;
385 if (pCreateInfo->pApplicationInfo &&
386 pCreateInfo->pApplicationInfo->apiVersion != 0) {
387 client_version = pCreateInfo->pApplicationInfo->apiVersion;
388 } else {
389 client_version = VK_MAKE_VERSION(1, 0, 0);
390 }
391
392 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
393 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
394 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
395 "Client requested version %d.%d.%d",
396 VK_VERSION_MAJOR(client_version),
397 VK_VERSION_MINOR(client_version),
398 VK_VERSION_PATCH(client_version));
399 }
400
401 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
402 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
403 if (!radv_instance_extension_supported(ext_name))
404 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
405 }
406
407 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
408 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
409 if (!instance)
410 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
411
412 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
413
414 if (pAllocator)
415 instance->alloc = *pAllocator;
416 else
417 instance->alloc = default_alloc;
418
419 instance->apiVersion = client_version;
420 instance->physicalDeviceCount = -1;
421
422 _mesa_locale_init();
423
424 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
425
426 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
427 radv_debug_options);
428
429 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
430 radv_perftest_options);
431
432 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
433
434 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
435 /* Disable sisched when the user requests it, this is mostly
436 * useful when the driver force-enable sisched for the given
437 * application.
438 */
439 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
440 }
441
442 *pInstance = radv_instance_to_handle(instance);
443
444 return VK_SUCCESS;
445 }
446
447 void radv_DestroyInstance(
448 VkInstance _instance,
449 const VkAllocationCallbacks* pAllocator)
450 {
451 RADV_FROM_HANDLE(radv_instance, instance, _instance);
452
453 if (!instance)
454 return;
455
456 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
457 radv_physical_device_finish(instance->physicalDevices + i);
458 }
459
460 VG(VALGRIND_DESTROY_MEMPOOL(instance));
461
462 _mesa_locale_fini();
463
464 vk_free(&instance->alloc, instance);
465 }
466
467 static VkResult
468 radv_enumerate_devices(struct radv_instance *instance)
469 {
470 /* TODO: Check for more devices ? */
471 drmDevicePtr devices[8];
472 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
473 int max_devices;
474
475 instance->physicalDeviceCount = 0;
476
477 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
478 if (max_devices < 1)
479 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
480
481 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
482 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
483 devices[i]->bustype == DRM_BUS_PCI &&
484 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
485
486 result = radv_physical_device_init(instance->physicalDevices +
487 instance->physicalDeviceCount,
488 instance,
489 devices[i]);
490 if (result == VK_SUCCESS)
491 ++instance->physicalDeviceCount;
492 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
493 break;
494 }
495 }
496 drmFreeDevices(devices, max_devices);
497
498 return result;
499 }
500
501 VkResult radv_EnumeratePhysicalDevices(
502 VkInstance _instance,
503 uint32_t* pPhysicalDeviceCount,
504 VkPhysicalDevice* pPhysicalDevices)
505 {
506 RADV_FROM_HANDLE(radv_instance, instance, _instance);
507 VkResult result;
508
509 if (instance->physicalDeviceCount < 0) {
510 result = radv_enumerate_devices(instance);
511 if (result != VK_SUCCESS &&
512 result != VK_ERROR_INCOMPATIBLE_DRIVER)
513 return result;
514 }
515
516 if (!pPhysicalDevices) {
517 *pPhysicalDeviceCount = instance->physicalDeviceCount;
518 } else {
519 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
520 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
521 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
522 }
523
524 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
525 : VK_SUCCESS;
526 }
527
528 void radv_GetPhysicalDeviceFeatures(
529 VkPhysicalDevice physicalDevice,
530 VkPhysicalDeviceFeatures* pFeatures)
531 {
532 memset(pFeatures, 0, sizeof(*pFeatures));
533
534 *pFeatures = (VkPhysicalDeviceFeatures) {
535 .robustBufferAccess = true,
536 .fullDrawIndexUint32 = true,
537 .imageCubeArray = true,
538 .independentBlend = true,
539 .geometryShader = true,
540 .tessellationShader = true,
541 .sampleRateShading = true,
542 .dualSrcBlend = true,
543 .logicOp = true,
544 .multiDrawIndirect = true,
545 .drawIndirectFirstInstance = true,
546 .depthClamp = true,
547 .depthBiasClamp = true,
548 .fillModeNonSolid = true,
549 .depthBounds = true,
550 .wideLines = true,
551 .largePoints = true,
552 .alphaToOne = true,
553 .multiViewport = true,
554 .samplerAnisotropy = true,
555 .textureCompressionETC2 = false,
556 .textureCompressionASTC_LDR = false,
557 .textureCompressionBC = true,
558 .occlusionQueryPrecise = true,
559 .pipelineStatisticsQuery = true,
560 .vertexPipelineStoresAndAtomics = true,
561 .fragmentStoresAndAtomics = true,
562 .shaderTessellationAndGeometryPointSize = true,
563 .shaderImageGatherExtended = true,
564 .shaderStorageImageExtendedFormats = true,
565 .shaderStorageImageMultisample = false,
566 .shaderUniformBufferArrayDynamicIndexing = true,
567 .shaderSampledImageArrayDynamicIndexing = true,
568 .shaderStorageBufferArrayDynamicIndexing = true,
569 .shaderStorageImageArrayDynamicIndexing = true,
570 .shaderStorageImageReadWithoutFormat = true,
571 .shaderStorageImageWriteWithoutFormat = true,
572 .shaderClipDistance = true,
573 .shaderCullDistance = true,
574 .shaderFloat64 = true,
575 .shaderInt64 = true,
576 .shaderInt16 = false,
577 .sparseBinding = true,
578 .variableMultisampleRate = true,
579 .inheritedQueries = true,
580 };
581 }
582
583 void radv_GetPhysicalDeviceFeatures2KHR(
584 VkPhysicalDevice physicalDevice,
585 VkPhysicalDeviceFeatures2KHR *pFeatures)
586 {
587 vk_foreach_struct(ext, pFeatures->pNext) {
588 switch (ext->sType) {
589 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
590 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
591 features->variablePointersStorageBuffer = true;
592 features->variablePointers = false;
593 break;
594 }
595 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
596 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
597 features->multiview = true;
598 features->multiviewGeometryShader = true;
599 features->multiviewTessellationShader = true;
600 break;
601 }
602 default:
603 break;
604 }
605 }
606 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
607 }
608
609 void radv_GetPhysicalDeviceProperties(
610 VkPhysicalDevice physicalDevice,
611 VkPhysicalDeviceProperties* pProperties)
612 {
613 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
614 VkSampleCountFlags sample_counts = 0xf;
615
616 /* make sure that the entire descriptor set is addressable with a signed
617 * 32-bit int. So the sum of all limits scaled by descriptor size has to
618 * be at most 2 GiB. the combined image & samples object count as one of
619 * both. This limit is for the pipeline layout, not for the set layout, but
620 * there is no set limit, so we just set a pipeline limit. I don't think
621 * any app is going to hit this soon. */
622 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
623 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
624 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
625 32 /* sampler, largest when combined with image */ +
626 64 /* sampled image */ +
627 64 /* storage image */);
628
629 VkPhysicalDeviceLimits limits = {
630 .maxImageDimension1D = (1 << 14),
631 .maxImageDimension2D = (1 << 14),
632 .maxImageDimension3D = (1 << 11),
633 .maxImageDimensionCube = (1 << 14),
634 .maxImageArrayLayers = (1 << 11),
635 .maxTexelBufferElements = 128 * 1024 * 1024,
636 .maxUniformBufferRange = UINT32_MAX,
637 .maxStorageBufferRange = UINT32_MAX,
638 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
639 .maxMemoryAllocationCount = UINT32_MAX,
640 .maxSamplerAllocationCount = 64 * 1024,
641 .bufferImageGranularity = 64, /* A cache line */
642 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
643 .maxBoundDescriptorSets = MAX_SETS,
644 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
645 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
646 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
647 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
648 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
649 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
650 .maxPerStageResources = max_descriptor_set_size,
651 .maxDescriptorSetSamplers = max_descriptor_set_size,
652 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
653 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
654 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
655 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
656 .maxDescriptorSetSampledImages = max_descriptor_set_size,
657 .maxDescriptorSetStorageImages = max_descriptor_set_size,
658 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
659 .maxVertexInputAttributes = 32,
660 .maxVertexInputBindings = 32,
661 .maxVertexInputAttributeOffset = 2047,
662 .maxVertexInputBindingStride = 2048,
663 .maxVertexOutputComponents = 128,
664 .maxTessellationGenerationLevel = 64,
665 .maxTessellationPatchSize = 32,
666 .maxTessellationControlPerVertexInputComponents = 128,
667 .maxTessellationControlPerVertexOutputComponents = 128,
668 .maxTessellationControlPerPatchOutputComponents = 120,
669 .maxTessellationControlTotalOutputComponents = 4096,
670 .maxTessellationEvaluationInputComponents = 128,
671 .maxTessellationEvaluationOutputComponents = 128,
672 .maxGeometryShaderInvocations = 127,
673 .maxGeometryInputComponents = 64,
674 .maxGeometryOutputComponents = 128,
675 .maxGeometryOutputVertices = 256,
676 .maxGeometryTotalOutputComponents = 1024,
677 .maxFragmentInputComponents = 128,
678 .maxFragmentOutputAttachments = 8,
679 .maxFragmentDualSrcAttachments = 1,
680 .maxFragmentCombinedOutputResources = 8,
681 .maxComputeSharedMemorySize = 32768,
682 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
683 .maxComputeWorkGroupInvocations = 2048,
684 .maxComputeWorkGroupSize = {
685 2048,
686 2048,
687 2048
688 },
689 .subPixelPrecisionBits = 4 /* FIXME */,
690 .subTexelPrecisionBits = 4 /* FIXME */,
691 .mipmapPrecisionBits = 4 /* FIXME */,
692 .maxDrawIndexedIndexValue = UINT32_MAX,
693 .maxDrawIndirectCount = UINT32_MAX,
694 .maxSamplerLodBias = 16,
695 .maxSamplerAnisotropy = 16,
696 .maxViewports = MAX_VIEWPORTS,
697 .maxViewportDimensions = { (1 << 14), (1 << 14) },
698 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
699 .viewportSubPixelBits = 13, /* We take a float? */
700 .minMemoryMapAlignment = 4096, /* A page */
701 .minTexelBufferOffsetAlignment = 1,
702 .minUniformBufferOffsetAlignment = 4,
703 .minStorageBufferOffsetAlignment = 4,
704 .minTexelOffset = -32,
705 .maxTexelOffset = 31,
706 .minTexelGatherOffset = -32,
707 .maxTexelGatherOffset = 31,
708 .minInterpolationOffset = -2,
709 .maxInterpolationOffset = 2,
710 .subPixelInterpolationOffsetBits = 8,
711 .maxFramebufferWidth = (1 << 14),
712 .maxFramebufferHeight = (1 << 14),
713 .maxFramebufferLayers = (1 << 10),
714 .framebufferColorSampleCounts = sample_counts,
715 .framebufferDepthSampleCounts = sample_counts,
716 .framebufferStencilSampleCounts = sample_counts,
717 .framebufferNoAttachmentsSampleCounts = sample_counts,
718 .maxColorAttachments = MAX_RTS,
719 .sampledImageColorSampleCounts = sample_counts,
720 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
721 .sampledImageDepthSampleCounts = sample_counts,
722 .sampledImageStencilSampleCounts = sample_counts,
723 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
724 .maxSampleMaskWords = 1,
725 .timestampComputeAndGraphics = true,
726 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
727 .maxClipDistances = 8,
728 .maxCullDistances = 8,
729 .maxCombinedClipAndCullDistances = 8,
730 .discreteQueuePriorities = 1,
731 .pointSizeRange = { 0.125, 255.875 },
732 .lineWidthRange = { 0.0, 7.9921875 },
733 .pointSizeGranularity = (1.0 / 8.0),
734 .lineWidthGranularity = (1.0 / 128.0),
735 .strictLines = false, /* FINISHME */
736 .standardSampleLocations = true,
737 .optimalBufferCopyOffsetAlignment = 128,
738 .optimalBufferCopyRowPitchAlignment = 128,
739 .nonCoherentAtomSize = 64,
740 };
741
742 *pProperties = (VkPhysicalDeviceProperties) {
743 .apiVersion = radv_physical_device_api_version(pdevice),
744 .driverVersion = vk_get_driver_version(),
745 .vendorID = ATI_VENDOR_ID,
746 .deviceID = pdevice->rad_info.pci_id,
747 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
748 .limits = limits,
749 .sparseProperties = {0},
750 };
751
752 strcpy(pProperties->deviceName, pdevice->name);
753 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
754 }
755
756 void radv_GetPhysicalDeviceProperties2KHR(
757 VkPhysicalDevice physicalDevice,
758 VkPhysicalDeviceProperties2KHR *pProperties)
759 {
760 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
761 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
762
763 vk_foreach_struct(ext, pProperties->pNext) {
764 switch (ext->sType) {
765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
766 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
767 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
768 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
769 break;
770 }
771 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
772 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
773 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
774 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
775 properties->deviceLUIDValid = false;
776 break;
777 }
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
779 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
780 properties->maxMultiviewViewCount = MAX_VIEWS;
781 properties->maxMultiviewInstanceIndex = INT_MAX;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
785 VkPhysicalDevicePointClippingPropertiesKHR *properties =
786 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
787 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
788 break;
789 }
790 default:
791 break;
792 }
793 }
794 }
795
796 static void radv_get_physical_device_queue_family_properties(
797 struct radv_physical_device* pdevice,
798 uint32_t* pCount,
799 VkQueueFamilyProperties** pQueueFamilyProperties)
800 {
801 int num_queue_families = 1;
802 int idx;
803 if (pdevice->rad_info.num_compute_rings > 0 &&
804 pdevice->rad_info.chip_class >= CIK &&
805 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
806 num_queue_families++;
807
808 if (pQueueFamilyProperties == NULL) {
809 *pCount = num_queue_families;
810 return;
811 }
812
813 if (!*pCount)
814 return;
815
816 idx = 0;
817 if (*pCount >= 1) {
818 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
819 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
820 VK_QUEUE_COMPUTE_BIT |
821 VK_QUEUE_TRANSFER_BIT |
822 VK_QUEUE_SPARSE_BINDING_BIT,
823 .queueCount = 1,
824 .timestampValidBits = 64,
825 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
826 };
827 idx++;
828 }
829
830 if (pdevice->rad_info.num_compute_rings > 0 &&
831 pdevice->rad_info.chip_class >= CIK &&
832 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
833 if (*pCount > idx) {
834 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
835 .queueFlags = VK_QUEUE_COMPUTE_BIT |
836 VK_QUEUE_TRANSFER_BIT |
837 VK_QUEUE_SPARSE_BINDING_BIT,
838 .queueCount = pdevice->rad_info.num_compute_rings,
839 .timestampValidBits = 64,
840 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
841 };
842 idx++;
843 }
844 }
845 *pCount = idx;
846 }
847
848 void radv_GetPhysicalDeviceQueueFamilyProperties(
849 VkPhysicalDevice physicalDevice,
850 uint32_t* pCount,
851 VkQueueFamilyProperties* pQueueFamilyProperties)
852 {
853 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
854 if (!pQueueFamilyProperties) {
855 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
856 return;
857 }
858 VkQueueFamilyProperties *properties[] = {
859 pQueueFamilyProperties + 0,
860 pQueueFamilyProperties + 1,
861 pQueueFamilyProperties + 2,
862 };
863 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
864 assert(*pCount <= 3);
865 }
866
867 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
868 VkPhysicalDevice physicalDevice,
869 uint32_t* pCount,
870 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
871 {
872 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
873 if (!pQueueFamilyProperties) {
874 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
875 return;
876 }
877 VkQueueFamilyProperties *properties[] = {
878 &pQueueFamilyProperties[0].queueFamilyProperties,
879 &pQueueFamilyProperties[1].queueFamilyProperties,
880 &pQueueFamilyProperties[2].queueFamilyProperties,
881 };
882 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
883 assert(*pCount <= 3);
884 }
885
886 void radv_GetPhysicalDeviceMemoryProperties(
887 VkPhysicalDevice physicalDevice,
888 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
889 {
890 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
891
892 *pMemoryProperties = physical_device->memory_properties;
893 }
894
895 void radv_GetPhysicalDeviceMemoryProperties2KHR(
896 VkPhysicalDevice physicalDevice,
897 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
898 {
899 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
900 &pMemoryProperties->memoryProperties);
901 }
902
903 static enum radeon_ctx_priority
904 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
905 {
906 /* Default to MEDIUM when a specific global priority isn't requested */
907 if (!pObj)
908 return RADEON_CTX_PRIORITY_MEDIUM;
909
910 switch(pObj->globalPriority) {
911 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
912 return RADEON_CTX_PRIORITY_REALTIME;
913 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
914 return RADEON_CTX_PRIORITY_HIGH;
915 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
916 return RADEON_CTX_PRIORITY_MEDIUM;
917 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
918 return RADEON_CTX_PRIORITY_LOW;
919 default:
920 unreachable("Illegal global priority value");
921 return RADEON_CTX_PRIORITY_INVALID;
922 }
923 }
924
925 static int
926 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
927 uint32_t queue_family_index, int idx,
928 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
929 {
930 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
931 queue->device = device;
932 queue->queue_family_index = queue_family_index;
933 queue->queue_idx = idx;
934 queue->priority = radv_get_queue_global_priority(global_priority);
935
936 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
937 if (!queue->hw_ctx)
938 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
939
940 return VK_SUCCESS;
941 }
942
943 static void
944 radv_queue_finish(struct radv_queue *queue)
945 {
946 if (queue->hw_ctx)
947 queue->device->ws->ctx_destroy(queue->hw_ctx);
948
949 if (queue->initial_full_flush_preamble_cs)
950 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
951 if (queue->initial_preamble_cs)
952 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
953 if (queue->continue_preamble_cs)
954 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
955 if (queue->descriptor_bo)
956 queue->device->ws->buffer_destroy(queue->descriptor_bo);
957 if (queue->scratch_bo)
958 queue->device->ws->buffer_destroy(queue->scratch_bo);
959 if (queue->esgs_ring_bo)
960 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
961 if (queue->gsvs_ring_bo)
962 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
963 if (queue->tess_factor_ring_bo)
964 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
965 if (queue->tess_offchip_ring_bo)
966 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
967 if (queue->compute_scratch_bo)
968 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
969 }
970
971 static void
972 radv_device_init_gs_info(struct radv_device *device)
973 {
974 switch (device->physical_device->rad_info.family) {
975 case CHIP_OLAND:
976 case CHIP_HAINAN:
977 case CHIP_KAVERI:
978 case CHIP_KABINI:
979 case CHIP_MULLINS:
980 case CHIP_ICELAND:
981 case CHIP_CARRIZO:
982 case CHIP_STONEY:
983 device->gs_table_depth = 16;
984 return;
985 case CHIP_TAHITI:
986 case CHIP_PITCAIRN:
987 case CHIP_VERDE:
988 case CHIP_BONAIRE:
989 case CHIP_HAWAII:
990 case CHIP_TONGA:
991 case CHIP_FIJI:
992 case CHIP_POLARIS10:
993 case CHIP_POLARIS11:
994 case CHIP_POLARIS12:
995 case CHIP_VEGA10:
996 case CHIP_RAVEN:
997 device->gs_table_depth = 32;
998 return;
999 default:
1000 unreachable("unknown GPU");
1001 }
1002 }
1003
1004 VkResult radv_CreateDevice(
1005 VkPhysicalDevice physicalDevice,
1006 const VkDeviceCreateInfo* pCreateInfo,
1007 const VkAllocationCallbacks* pAllocator,
1008 VkDevice* pDevice)
1009 {
1010 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1011 VkResult result;
1012 struct radv_device *device;
1013
1014 bool keep_shader_info = false;
1015
1016 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1017 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1018 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1019 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1020
1021 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1022 keep_shader_info = true;
1023 }
1024
1025 /* Check enabled features */
1026 if (pCreateInfo->pEnabledFeatures) {
1027 VkPhysicalDeviceFeatures supported_features;
1028 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1029 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1030 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1031 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1032 for (uint32_t i = 0; i < num_features; i++) {
1033 if (enabled_feature[i] && !supported_feature[i])
1034 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1035 }
1036 }
1037
1038 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1039 sizeof(*device), 8,
1040 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1041 if (!device)
1042 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1043
1044 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1045 device->instance = physical_device->instance;
1046 device->physical_device = physical_device;
1047
1048 device->ws = physical_device->ws;
1049 if (pAllocator)
1050 device->alloc = *pAllocator;
1051 else
1052 device->alloc = physical_device->instance->alloc;
1053
1054 mtx_init(&device->shader_slab_mutex, mtx_plain);
1055 list_inithead(&device->shader_slabs);
1056
1057 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1058 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1059 uint32_t qfi = queue_create->queueFamilyIndex;
1060 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1061 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1062
1063 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1064
1065 device->queues[qfi] = vk_alloc(&device->alloc,
1066 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1067 if (!device->queues[qfi]) {
1068 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1069 goto fail;
1070 }
1071
1072 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1073
1074 device->queue_count[qfi] = queue_create->queueCount;
1075
1076 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1077 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1078 if (result != VK_SUCCESS)
1079 goto fail;
1080 }
1081 }
1082
1083 #if HAVE_LLVM < 0x0400
1084 device->llvm_supports_spill = false;
1085 #else
1086 device->llvm_supports_spill = true;
1087 #endif
1088
1089 /* The maximum number of scratch waves. Scratch space isn't divided
1090 * evenly between CUs. The number is only a function of the number of CUs.
1091 * We can decrease the constant to decrease the scratch buffer size.
1092 *
1093 * sctx->scratch_waves must be >= the maximum posible size of
1094 * 1 threadgroup, so that the hw doesn't hang from being unable
1095 * to start any.
1096 *
1097 * The recommended value is 4 per CU at most. Higher numbers don't
1098 * bring much benefit, but they still occupy chip resources (think
1099 * async compute). I've seen ~2% performance difference between 4 and 32.
1100 */
1101 uint32_t max_threads_per_block = 2048;
1102 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1103 max_threads_per_block / 64);
1104
1105 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1106 S_00B800_FORCE_START_AT_000(1);
1107
1108 if (device->physical_device->rad_info.chip_class >= CIK) {
1109 /* If the KMD allows it (there is a KMD hw register for it),
1110 * allow launching waves out-of-order.
1111 */
1112 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1113 }
1114
1115 radv_device_init_gs_info(device);
1116
1117 device->tess_offchip_block_dw_size =
1118 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1119 device->has_distributed_tess =
1120 device->physical_device->rad_info.chip_class >= VI &&
1121 device->physical_device->rad_info.max_se >= 2;
1122
1123 if (getenv("RADV_TRACE_FILE")) {
1124 keep_shader_info = true;
1125
1126 if (!radv_init_trace(device))
1127 goto fail;
1128 }
1129
1130 device->keep_shader_info = keep_shader_info;
1131
1132 result = radv_device_init_meta(device);
1133 if (result != VK_SUCCESS)
1134 goto fail;
1135
1136 radv_device_init_msaa(device);
1137
1138 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1139 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1140 switch (family) {
1141 case RADV_QUEUE_GENERAL:
1142 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1143 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1144 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1145 break;
1146 case RADV_QUEUE_COMPUTE:
1147 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1148 radeon_emit(device->empty_cs[family], 0);
1149 break;
1150 }
1151 device->ws->cs_finalize(device->empty_cs[family]);
1152 }
1153
1154 if (device->physical_device->rad_info.chip_class >= CIK)
1155 cik_create_gfx_config(device);
1156
1157 VkPipelineCacheCreateInfo ci;
1158 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1159 ci.pNext = NULL;
1160 ci.flags = 0;
1161 ci.pInitialData = NULL;
1162 ci.initialDataSize = 0;
1163 VkPipelineCache pc;
1164 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1165 &ci, NULL, &pc);
1166 if (result != VK_SUCCESS)
1167 goto fail;
1168
1169 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1170
1171 *pDevice = radv_device_to_handle(device);
1172 return VK_SUCCESS;
1173
1174 fail:
1175 if (device->trace_bo)
1176 device->ws->buffer_destroy(device->trace_bo);
1177
1178 if (device->gfx_init)
1179 device->ws->buffer_destroy(device->gfx_init);
1180
1181 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1182 for (unsigned q = 0; q < device->queue_count[i]; q++)
1183 radv_queue_finish(&device->queues[i][q]);
1184 if (device->queue_count[i])
1185 vk_free(&device->alloc, device->queues[i]);
1186 }
1187
1188 vk_free(&device->alloc, device);
1189 return result;
1190 }
1191
1192 void radv_DestroyDevice(
1193 VkDevice _device,
1194 const VkAllocationCallbacks* pAllocator)
1195 {
1196 RADV_FROM_HANDLE(radv_device, device, _device);
1197
1198 if (!device)
1199 return;
1200
1201 if (device->trace_bo)
1202 device->ws->buffer_destroy(device->trace_bo);
1203
1204 if (device->gfx_init)
1205 device->ws->buffer_destroy(device->gfx_init);
1206
1207 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1208 for (unsigned q = 0; q < device->queue_count[i]; q++)
1209 radv_queue_finish(&device->queues[i][q]);
1210 if (device->queue_count[i])
1211 vk_free(&device->alloc, device->queues[i]);
1212 if (device->empty_cs[i])
1213 device->ws->cs_destroy(device->empty_cs[i]);
1214 }
1215 radv_device_finish_meta(device);
1216
1217 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1218 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1219
1220 radv_destroy_shader_slabs(device);
1221
1222 vk_free(&device->alloc, device);
1223 }
1224
1225 VkResult radv_EnumerateInstanceLayerProperties(
1226 uint32_t* pPropertyCount,
1227 VkLayerProperties* pProperties)
1228 {
1229 if (pProperties == NULL) {
1230 *pPropertyCount = 0;
1231 return VK_SUCCESS;
1232 }
1233
1234 /* None supported at this time */
1235 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1236 }
1237
1238 VkResult radv_EnumerateDeviceLayerProperties(
1239 VkPhysicalDevice physicalDevice,
1240 uint32_t* pPropertyCount,
1241 VkLayerProperties* pProperties)
1242 {
1243 if (pProperties == NULL) {
1244 *pPropertyCount = 0;
1245 return VK_SUCCESS;
1246 }
1247
1248 /* None supported at this time */
1249 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1250 }
1251
1252 void radv_GetDeviceQueue(
1253 VkDevice _device,
1254 uint32_t queueFamilyIndex,
1255 uint32_t queueIndex,
1256 VkQueue* pQueue)
1257 {
1258 RADV_FROM_HANDLE(radv_device, device, _device);
1259
1260 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1261 }
1262
1263 static void
1264 fill_geom_tess_rings(struct radv_queue *queue,
1265 uint32_t *map,
1266 bool add_sample_positions,
1267 uint32_t esgs_ring_size,
1268 struct radeon_winsys_bo *esgs_ring_bo,
1269 uint32_t gsvs_ring_size,
1270 struct radeon_winsys_bo *gsvs_ring_bo,
1271 uint32_t tess_factor_ring_size,
1272 struct radeon_winsys_bo *tess_factor_ring_bo,
1273 uint32_t tess_offchip_ring_size,
1274 struct radeon_winsys_bo *tess_offchip_ring_bo)
1275 {
1276 uint64_t esgs_va = 0, gsvs_va = 0;
1277 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1278 uint32_t *desc = &map[4];
1279
1280 if (esgs_ring_bo)
1281 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1282 if (gsvs_ring_bo)
1283 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1284 if (tess_factor_ring_bo)
1285 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1286 if (tess_offchip_ring_bo)
1287 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1288
1289 /* stride 0, num records - size, add tid, swizzle, elsize4,
1290 index stride 64 */
1291 desc[0] = esgs_va;
1292 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1293 S_008F04_STRIDE(0) |
1294 S_008F04_SWIZZLE_ENABLE(true);
1295 desc[2] = esgs_ring_size;
1296 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1297 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1298 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1299 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1300 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1301 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1302 S_008F0C_ELEMENT_SIZE(1) |
1303 S_008F0C_INDEX_STRIDE(3) |
1304 S_008F0C_ADD_TID_ENABLE(true);
1305
1306 desc += 4;
1307 /* GS entry for ES->GS ring */
1308 /* stride 0, num records - size, elsize0,
1309 index stride 0 */
1310 desc[0] = esgs_va;
1311 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1312 S_008F04_STRIDE(0) |
1313 S_008F04_SWIZZLE_ENABLE(false);
1314 desc[2] = esgs_ring_size;
1315 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1316 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1317 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1318 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1319 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1320 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1321 S_008F0C_ELEMENT_SIZE(0) |
1322 S_008F0C_INDEX_STRIDE(0) |
1323 S_008F0C_ADD_TID_ENABLE(false);
1324
1325 desc += 4;
1326 /* VS entry for GS->VS ring */
1327 /* stride 0, num records - size, elsize0,
1328 index stride 0 */
1329 desc[0] = gsvs_va;
1330 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1331 S_008F04_STRIDE(0) |
1332 S_008F04_SWIZZLE_ENABLE(false);
1333 desc[2] = gsvs_ring_size;
1334 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1335 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1336 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1337 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1338 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1339 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1340 S_008F0C_ELEMENT_SIZE(0) |
1341 S_008F0C_INDEX_STRIDE(0) |
1342 S_008F0C_ADD_TID_ENABLE(false);
1343 desc += 4;
1344
1345 /* stride gsvs_itemsize, num records 64
1346 elsize 4, index stride 16 */
1347 /* shader will patch stride and desc[2] */
1348 desc[0] = gsvs_va;
1349 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1350 S_008F04_STRIDE(0) |
1351 S_008F04_SWIZZLE_ENABLE(true);
1352 desc[2] = 0;
1353 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1354 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1355 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1356 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1357 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1358 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1359 S_008F0C_ELEMENT_SIZE(1) |
1360 S_008F0C_INDEX_STRIDE(1) |
1361 S_008F0C_ADD_TID_ENABLE(true);
1362 desc += 4;
1363
1364 desc[0] = tess_factor_va;
1365 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1366 S_008F04_STRIDE(0) |
1367 S_008F04_SWIZZLE_ENABLE(false);
1368 desc[2] = tess_factor_ring_size;
1369 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1370 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1371 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1372 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1373 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1374 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1375 S_008F0C_ELEMENT_SIZE(0) |
1376 S_008F0C_INDEX_STRIDE(0) |
1377 S_008F0C_ADD_TID_ENABLE(false);
1378 desc += 4;
1379
1380 desc[0] = tess_offchip_va;
1381 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1382 S_008F04_STRIDE(0) |
1383 S_008F04_SWIZZLE_ENABLE(false);
1384 desc[2] = tess_offchip_ring_size;
1385 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1386 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1387 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1388 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1389 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1391 S_008F0C_ELEMENT_SIZE(0) |
1392 S_008F0C_INDEX_STRIDE(0) |
1393 S_008F0C_ADD_TID_ENABLE(false);
1394 desc += 4;
1395
1396 /* add sample positions after all rings */
1397 memcpy(desc, queue->device->sample_locations_1x, 8);
1398 desc += 2;
1399 memcpy(desc, queue->device->sample_locations_2x, 16);
1400 desc += 4;
1401 memcpy(desc, queue->device->sample_locations_4x, 32);
1402 desc += 8;
1403 memcpy(desc, queue->device->sample_locations_8x, 64);
1404 desc += 16;
1405 memcpy(desc, queue->device->sample_locations_16x, 128);
1406 }
1407
1408 static unsigned
1409 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1410 {
1411 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1412 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1413 device->physical_device->rad_info.family != CHIP_STONEY;
1414 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1415 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1416 device->physical_device->rad_info.max_se;
1417 unsigned offchip_granularity;
1418 unsigned hs_offchip_param;
1419 switch (device->tess_offchip_block_dw_size) {
1420 default:
1421 assert(0);
1422 /* fall through */
1423 case 8192:
1424 offchip_granularity = V_03093C_X_8K_DWORDS;
1425 break;
1426 case 4096:
1427 offchip_granularity = V_03093C_X_4K_DWORDS;
1428 break;
1429 }
1430
1431 switch (device->physical_device->rad_info.chip_class) {
1432 case SI:
1433 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1434 break;
1435 case CIK:
1436 case VI:
1437 case GFX9:
1438 default:
1439 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1440 break;
1441 }
1442
1443 *max_offchip_buffers_p = max_offchip_buffers;
1444 if (device->physical_device->rad_info.chip_class >= CIK) {
1445 if (device->physical_device->rad_info.chip_class >= VI)
1446 --max_offchip_buffers;
1447 hs_offchip_param =
1448 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1449 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1450 } else {
1451 hs_offchip_param =
1452 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1453 }
1454 return hs_offchip_param;
1455 }
1456
1457 static VkResult
1458 radv_get_preamble_cs(struct radv_queue *queue,
1459 uint32_t scratch_size,
1460 uint32_t compute_scratch_size,
1461 uint32_t esgs_ring_size,
1462 uint32_t gsvs_ring_size,
1463 bool needs_tess_rings,
1464 bool needs_sample_positions,
1465 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1466 struct radeon_winsys_cs **initial_preamble_cs,
1467 struct radeon_winsys_cs **continue_preamble_cs)
1468 {
1469 struct radeon_winsys_bo *scratch_bo = NULL;
1470 struct radeon_winsys_bo *descriptor_bo = NULL;
1471 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1472 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1473 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1474 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1475 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1476 struct radeon_winsys_cs *dest_cs[3] = {0};
1477 bool add_tess_rings = false, add_sample_positions = false;
1478 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1479 unsigned max_offchip_buffers;
1480 unsigned hs_offchip_param = 0;
1481 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1482 if (!queue->has_tess_rings) {
1483 if (needs_tess_rings)
1484 add_tess_rings = true;
1485 }
1486 if (!queue->has_sample_positions) {
1487 if (needs_sample_positions)
1488 add_sample_positions = true;
1489 }
1490 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1491 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1492 &max_offchip_buffers);
1493 tess_offchip_ring_size = max_offchip_buffers *
1494 queue->device->tess_offchip_block_dw_size * 4;
1495
1496 if (scratch_size <= queue->scratch_size &&
1497 compute_scratch_size <= queue->compute_scratch_size &&
1498 esgs_ring_size <= queue->esgs_ring_size &&
1499 gsvs_ring_size <= queue->gsvs_ring_size &&
1500 !add_tess_rings && !add_sample_positions &&
1501 queue->initial_preamble_cs) {
1502 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1503 *initial_preamble_cs = queue->initial_preamble_cs;
1504 *continue_preamble_cs = queue->continue_preamble_cs;
1505 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1506 *continue_preamble_cs = NULL;
1507 return VK_SUCCESS;
1508 }
1509
1510 if (scratch_size > queue->scratch_size) {
1511 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1512 scratch_size,
1513 4096,
1514 RADEON_DOMAIN_VRAM,
1515 ring_bo_flags);
1516 if (!scratch_bo)
1517 goto fail;
1518 } else
1519 scratch_bo = queue->scratch_bo;
1520
1521 if (compute_scratch_size > queue->compute_scratch_size) {
1522 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1523 compute_scratch_size,
1524 4096,
1525 RADEON_DOMAIN_VRAM,
1526 ring_bo_flags);
1527 if (!compute_scratch_bo)
1528 goto fail;
1529
1530 } else
1531 compute_scratch_bo = queue->compute_scratch_bo;
1532
1533 if (esgs_ring_size > queue->esgs_ring_size) {
1534 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1535 esgs_ring_size,
1536 4096,
1537 RADEON_DOMAIN_VRAM,
1538 ring_bo_flags);
1539 if (!esgs_ring_bo)
1540 goto fail;
1541 } else {
1542 esgs_ring_bo = queue->esgs_ring_bo;
1543 esgs_ring_size = queue->esgs_ring_size;
1544 }
1545
1546 if (gsvs_ring_size > queue->gsvs_ring_size) {
1547 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1548 gsvs_ring_size,
1549 4096,
1550 RADEON_DOMAIN_VRAM,
1551 ring_bo_flags);
1552 if (!gsvs_ring_bo)
1553 goto fail;
1554 } else {
1555 gsvs_ring_bo = queue->gsvs_ring_bo;
1556 gsvs_ring_size = queue->gsvs_ring_size;
1557 }
1558
1559 if (add_tess_rings) {
1560 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1561 tess_factor_ring_size,
1562 256,
1563 RADEON_DOMAIN_VRAM,
1564 ring_bo_flags);
1565 if (!tess_factor_ring_bo)
1566 goto fail;
1567 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1568 tess_offchip_ring_size,
1569 256,
1570 RADEON_DOMAIN_VRAM,
1571 ring_bo_flags);
1572 if (!tess_offchip_ring_bo)
1573 goto fail;
1574 } else {
1575 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1576 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1577 }
1578
1579 if (scratch_bo != queue->scratch_bo ||
1580 esgs_ring_bo != queue->esgs_ring_bo ||
1581 gsvs_ring_bo != queue->gsvs_ring_bo ||
1582 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1583 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1584 uint32_t size = 0;
1585 if (gsvs_ring_bo || esgs_ring_bo ||
1586 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1587 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1588 if (add_sample_positions)
1589 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1590 }
1591 else if (scratch_bo)
1592 size = 8; /* 2 dword */
1593
1594 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1595 size,
1596 4096,
1597 RADEON_DOMAIN_VRAM,
1598 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1599 if (!descriptor_bo)
1600 goto fail;
1601 } else
1602 descriptor_bo = queue->descriptor_bo;
1603
1604 for(int i = 0; i < 3; ++i) {
1605 struct radeon_winsys_cs *cs = NULL;
1606 cs = queue->device->ws->cs_create(queue->device->ws,
1607 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1608 if (!cs)
1609 goto fail;
1610
1611 dest_cs[i] = cs;
1612
1613 if (scratch_bo)
1614 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1615
1616 if (esgs_ring_bo)
1617 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1618
1619 if (gsvs_ring_bo)
1620 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1621
1622 if (tess_factor_ring_bo)
1623 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1624
1625 if (tess_offchip_ring_bo)
1626 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1627
1628 if (descriptor_bo)
1629 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1630
1631 if (descriptor_bo != queue->descriptor_bo) {
1632 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1633
1634 if (scratch_bo) {
1635 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1636 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1637 S_008F04_SWIZZLE_ENABLE(1);
1638 map[0] = scratch_va;
1639 map[1] = rsrc1;
1640 }
1641
1642 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1643 add_sample_positions)
1644 fill_geom_tess_rings(queue, map, add_sample_positions,
1645 esgs_ring_size, esgs_ring_bo,
1646 gsvs_ring_size, gsvs_ring_bo,
1647 tess_factor_ring_size, tess_factor_ring_bo,
1648 tess_offchip_ring_size, tess_offchip_ring_bo);
1649
1650 queue->device->ws->buffer_unmap(descriptor_bo);
1651 }
1652
1653 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1654 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1655 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1656 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1657 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1658 }
1659
1660 if (esgs_ring_bo || gsvs_ring_bo) {
1661 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1662 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1663 radeon_emit(cs, esgs_ring_size >> 8);
1664 radeon_emit(cs, gsvs_ring_size >> 8);
1665 } else {
1666 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1667 radeon_emit(cs, esgs_ring_size >> 8);
1668 radeon_emit(cs, gsvs_ring_size >> 8);
1669 }
1670 }
1671
1672 if (tess_factor_ring_bo) {
1673 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1674 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1675 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1676 S_030938_SIZE(tess_factor_ring_size / 4));
1677 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1678 tf_va >> 8);
1679 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1680 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1681 tf_va >> 40);
1682 }
1683 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1684 } else {
1685 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1686 S_008988_SIZE(tess_factor_ring_size / 4));
1687 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1688 tf_va >> 8);
1689 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1690 hs_offchip_param);
1691 }
1692 }
1693
1694 if (descriptor_bo) {
1695 uint64_t va = radv_buffer_get_va(descriptor_bo);
1696 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1697 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1698 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1699 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1700 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1701
1702 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1703 radeon_set_sh_reg_seq(cs, regs[i], 2);
1704 radeon_emit(cs, va);
1705 radeon_emit(cs, va >> 32);
1706 }
1707 } else {
1708 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1709 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1710 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1711 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1712 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1713 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1714
1715 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1716 radeon_set_sh_reg_seq(cs, regs[i], 2);
1717 radeon_emit(cs, va);
1718 radeon_emit(cs, va >> 32);
1719 }
1720 }
1721 }
1722
1723 if (compute_scratch_bo) {
1724 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1725 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1726 S_008F04_SWIZZLE_ENABLE(1);
1727
1728 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1729
1730 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1731 radeon_emit(cs, scratch_va);
1732 radeon_emit(cs, rsrc1);
1733 }
1734
1735 if (i == 0) {
1736 si_cs_emit_cache_flush(cs,
1737 false,
1738 queue->device->physical_device->rad_info.chip_class,
1739 NULL, 0,
1740 queue->queue_family_index == RING_COMPUTE &&
1741 queue->device->physical_device->rad_info.chip_class >= CIK,
1742 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1743 RADV_CMD_FLAG_INV_ICACHE |
1744 RADV_CMD_FLAG_INV_SMEM_L1 |
1745 RADV_CMD_FLAG_INV_VMEM_L1 |
1746 RADV_CMD_FLAG_INV_GLOBAL_L2);
1747 } else if (i == 1) {
1748 si_cs_emit_cache_flush(cs,
1749 false,
1750 queue->device->physical_device->rad_info.chip_class,
1751 NULL, 0,
1752 queue->queue_family_index == RING_COMPUTE &&
1753 queue->device->physical_device->rad_info.chip_class >= CIK,
1754 RADV_CMD_FLAG_INV_ICACHE |
1755 RADV_CMD_FLAG_INV_SMEM_L1 |
1756 RADV_CMD_FLAG_INV_VMEM_L1 |
1757 RADV_CMD_FLAG_INV_GLOBAL_L2);
1758 }
1759
1760 if (!queue->device->ws->cs_finalize(cs))
1761 goto fail;
1762 }
1763
1764 if (queue->initial_full_flush_preamble_cs)
1765 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1766
1767 if (queue->initial_preamble_cs)
1768 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1769
1770 if (queue->continue_preamble_cs)
1771 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1772
1773 queue->initial_full_flush_preamble_cs = dest_cs[0];
1774 queue->initial_preamble_cs = dest_cs[1];
1775 queue->continue_preamble_cs = dest_cs[2];
1776
1777 if (scratch_bo != queue->scratch_bo) {
1778 if (queue->scratch_bo)
1779 queue->device->ws->buffer_destroy(queue->scratch_bo);
1780 queue->scratch_bo = scratch_bo;
1781 queue->scratch_size = scratch_size;
1782 }
1783
1784 if (compute_scratch_bo != queue->compute_scratch_bo) {
1785 if (queue->compute_scratch_bo)
1786 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1787 queue->compute_scratch_bo = compute_scratch_bo;
1788 queue->compute_scratch_size = compute_scratch_size;
1789 }
1790
1791 if (esgs_ring_bo != queue->esgs_ring_bo) {
1792 if (queue->esgs_ring_bo)
1793 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1794 queue->esgs_ring_bo = esgs_ring_bo;
1795 queue->esgs_ring_size = esgs_ring_size;
1796 }
1797
1798 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1799 if (queue->gsvs_ring_bo)
1800 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1801 queue->gsvs_ring_bo = gsvs_ring_bo;
1802 queue->gsvs_ring_size = gsvs_ring_size;
1803 }
1804
1805 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1806 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1807 }
1808
1809 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1810 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1811 queue->has_tess_rings = true;
1812 }
1813
1814 if (descriptor_bo != queue->descriptor_bo) {
1815 if (queue->descriptor_bo)
1816 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1817
1818 queue->descriptor_bo = descriptor_bo;
1819 }
1820
1821 if (add_sample_positions)
1822 queue->has_sample_positions = true;
1823
1824 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1825 *initial_preamble_cs = queue->initial_preamble_cs;
1826 *continue_preamble_cs = queue->continue_preamble_cs;
1827 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1828 *continue_preamble_cs = NULL;
1829 return VK_SUCCESS;
1830 fail:
1831 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1832 if (dest_cs[i])
1833 queue->device->ws->cs_destroy(dest_cs[i]);
1834 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1835 queue->device->ws->buffer_destroy(descriptor_bo);
1836 if (scratch_bo && scratch_bo != queue->scratch_bo)
1837 queue->device->ws->buffer_destroy(scratch_bo);
1838 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1839 queue->device->ws->buffer_destroy(compute_scratch_bo);
1840 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1841 queue->device->ws->buffer_destroy(esgs_ring_bo);
1842 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1843 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1844 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1845 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1846 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1847 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1848 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1849 }
1850
1851 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1852 int num_sems,
1853 const VkSemaphore *sems,
1854 VkFence _fence,
1855 bool reset_temp)
1856 {
1857 int syncobj_idx = 0, sem_idx = 0;
1858
1859 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1860 return VK_SUCCESS;
1861
1862 for (uint32_t i = 0; i < num_sems; i++) {
1863 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1864
1865 if (sem->temp_syncobj || sem->syncobj)
1866 counts->syncobj_count++;
1867 else
1868 counts->sem_count++;
1869 }
1870
1871 if (_fence != VK_NULL_HANDLE) {
1872 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1873 if (fence->temp_syncobj || fence->syncobj)
1874 counts->syncobj_count++;
1875 }
1876
1877 if (counts->syncobj_count) {
1878 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1879 if (!counts->syncobj)
1880 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1881 }
1882
1883 if (counts->sem_count) {
1884 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1885 if (!counts->sem) {
1886 free(counts->syncobj);
1887 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1888 }
1889 }
1890
1891 for (uint32_t i = 0; i < num_sems; i++) {
1892 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1893
1894 if (sem->temp_syncobj) {
1895 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1896 }
1897 else if (sem->syncobj)
1898 counts->syncobj[syncobj_idx++] = sem->syncobj;
1899 else {
1900 assert(sem->sem);
1901 counts->sem[sem_idx++] = sem->sem;
1902 }
1903 }
1904
1905 if (_fence != VK_NULL_HANDLE) {
1906 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1907 if (fence->temp_syncobj)
1908 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1909 else if (fence->syncobj)
1910 counts->syncobj[syncobj_idx++] = fence->syncobj;
1911 }
1912
1913 return VK_SUCCESS;
1914 }
1915
1916 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1917 {
1918 free(sem_info->wait.syncobj);
1919 free(sem_info->wait.sem);
1920 free(sem_info->signal.syncobj);
1921 free(sem_info->signal.sem);
1922 }
1923
1924
1925 static void radv_free_temp_syncobjs(struct radv_device *device,
1926 int num_sems,
1927 const VkSemaphore *sems)
1928 {
1929 for (uint32_t i = 0; i < num_sems; i++) {
1930 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1931
1932 if (sem->temp_syncobj) {
1933 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1934 sem->temp_syncobj = 0;
1935 }
1936 }
1937 }
1938
1939 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1940 int num_wait_sems,
1941 const VkSemaphore *wait_sems,
1942 int num_signal_sems,
1943 const VkSemaphore *signal_sems,
1944 VkFence fence)
1945 {
1946 VkResult ret;
1947 memset(sem_info, 0, sizeof(*sem_info));
1948
1949 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
1950 if (ret)
1951 return ret;
1952 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
1953 if (ret)
1954 radv_free_sem_info(sem_info);
1955
1956 /* caller can override these */
1957 sem_info->cs_emit_wait = true;
1958 sem_info->cs_emit_signal = true;
1959 return ret;
1960 }
1961
1962 VkResult radv_QueueSubmit(
1963 VkQueue _queue,
1964 uint32_t submitCount,
1965 const VkSubmitInfo* pSubmits,
1966 VkFence _fence)
1967 {
1968 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1969 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1970 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1971 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1972 int ret;
1973 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1974 uint32_t scratch_size = 0;
1975 uint32_t compute_scratch_size = 0;
1976 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1977 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1978 VkResult result;
1979 bool fence_emitted = false;
1980 bool tess_rings_needed = false;
1981 bool sample_positions_needed = false;
1982
1983 /* Do this first so failing to allocate scratch buffers can't result in
1984 * partially executed submissions. */
1985 for (uint32_t i = 0; i < submitCount; i++) {
1986 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1988 pSubmits[i].pCommandBuffers[j]);
1989
1990 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1991 compute_scratch_size = MAX2(compute_scratch_size,
1992 cmd_buffer->compute_scratch_size_needed);
1993 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1994 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1995 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1996 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1997 }
1998 }
1999
2000 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2001 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2002 sample_positions_needed, &initial_flush_preamble_cs,
2003 &initial_preamble_cs, &continue_preamble_cs);
2004 if (result != VK_SUCCESS)
2005 return result;
2006
2007 for (uint32_t i = 0; i < submitCount; i++) {
2008 struct radeon_winsys_cs **cs_array;
2009 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2010 bool can_patch = true;
2011 uint32_t advance;
2012 struct radv_winsys_sem_info sem_info;
2013
2014 result = radv_alloc_sem_info(&sem_info,
2015 pSubmits[i].waitSemaphoreCount,
2016 pSubmits[i].pWaitSemaphores,
2017 pSubmits[i].signalSemaphoreCount,
2018 pSubmits[i].pSignalSemaphores,
2019 _fence);
2020 if (result != VK_SUCCESS)
2021 return result;
2022
2023 if (!pSubmits[i].commandBufferCount) {
2024 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2025 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2026 &queue->device->empty_cs[queue->queue_family_index],
2027 1, NULL, NULL,
2028 &sem_info,
2029 false, base_fence);
2030 if (ret) {
2031 radv_loge("failed to submit CS %d\n", i);
2032 abort();
2033 }
2034 fence_emitted = true;
2035 }
2036 radv_free_sem_info(&sem_info);
2037 continue;
2038 }
2039
2040 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2041 (pSubmits[i].commandBufferCount));
2042
2043 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2044 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2045 pSubmits[i].pCommandBuffers[j]);
2046 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2047
2048 cs_array[j] = cmd_buffer->cs;
2049 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2050 can_patch = false;
2051
2052 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2053 }
2054
2055 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2056 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2057 advance = MIN2(max_cs_submission,
2058 pSubmits[i].commandBufferCount - j);
2059
2060 if (queue->device->trace_bo)
2061 *queue->device->trace_id_ptr = 0;
2062
2063 sem_info.cs_emit_wait = j == 0;
2064 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2065
2066 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2067 advance, initial_preamble, continue_preamble_cs,
2068 &sem_info,
2069 can_patch, base_fence);
2070
2071 if (ret) {
2072 radv_loge("failed to submit CS %d\n", i);
2073 abort();
2074 }
2075 fence_emitted = true;
2076 if (queue->device->trace_bo) {
2077 radv_check_gpu_hangs(queue, cs_array[j]);
2078 }
2079 }
2080
2081 radv_free_temp_syncobjs(queue->device,
2082 pSubmits[i].waitSemaphoreCount,
2083 pSubmits[i].pWaitSemaphores);
2084 radv_free_sem_info(&sem_info);
2085 free(cs_array);
2086 }
2087
2088 if (fence) {
2089 if (!fence_emitted) {
2090 struct radv_winsys_sem_info sem_info;
2091
2092 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2093 _fence);
2094 if (result != VK_SUCCESS)
2095 return result;
2096
2097 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2098 &queue->device->empty_cs[queue->queue_family_index],
2099 1, NULL, NULL, &sem_info,
2100 false, base_fence);
2101 radv_free_sem_info(&sem_info);
2102 }
2103 fence->submitted = true;
2104 }
2105
2106 return VK_SUCCESS;
2107 }
2108
2109 VkResult radv_QueueWaitIdle(
2110 VkQueue _queue)
2111 {
2112 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2113
2114 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2115 radv_queue_family_to_ring(queue->queue_family_index),
2116 queue->queue_idx);
2117 return VK_SUCCESS;
2118 }
2119
2120 VkResult radv_DeviceWaitIdle(
2121 VkDevice _device)
2122 {
2123 RADV_FROM_HANDLE(radv_device, device, _device);
2124
2125 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2126 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2127 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2128 }
2129 }
2130 return VK_SUCCESS;
2131 }
2132
2133 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2134 VkInstance instance,
2135 const char* pName)
2136 {
2137 return radv_lookup_entrypoint(pName);
2138 }
2139
2140 /* The loader wants us to expose a second GetInstanceProcAddr function
2141 * to work around certain LD_PRELOAD issues seen in apps.
2142 */
2143 PUBLIC
2144 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2145 VkInstance instance,
2146 const char* pName);
2147
2148 PUBLIC
2149 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2150 VkInstance instance,
2151 const char* pName)
2152 {
2153 return radv_GetInstanceProcAddr(instance, pName);
2154 }
2155
2156 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2157 VkDevice device,
2158 const char* pName)
2159 {
2160 return radv_lookup_entrypoint(pName);
2161 }
2162
2163 bool radv_get_memory_fd(struct radv_device *device,
2164 struct radv_device_memory *memory,
2165 int *pFD)
2166 {
2167 struct radeon_bo_metadata metadata;
2168
2169 if (memory->image) {
2170 radv_init_metadata(device, memory->image, &metadata);
2171 device->ws->buffer_set_metadata(memory->bo, &metadata);
2172 }
2173
2174 return device->ws->buffer_get_fd(device->ws, memory->bo,
2175 pFD);
2176 }
2177
2178 static VkResult radv_alloc_memory(struct radv_device *device,
2179 const VkMemoryAllocateInfo* pAllocateInfo,
2180 const VkAllocationCallbacks* pAllocator,
2181 VkDeviceMemory* pMem)
2182 {
2183 struct radv_device_memory *mem;
2184 VkResult result;
2185 enum radeon_bo_domain domain;
2186 uint32_t flags = 0;
2187 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2188
2189 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2190
2191 if (pAllocateInfo->allocationSize == 0) {
2192 /* Apparently, this is allowed */
2193 *pMem = VK_NULL_HANDLE;
2194 return VK_SUCCESS;
2195 }
2196
2197 const VkImportMemoryFdInfoKHR *import_info =
2198 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2199 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2200 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2201 const VkExportMemoryAllocateInfoKHR *export_info =
2202 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2203
2204 const struct wsi_memory_allocate_info *wsi_info =
2205 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2206
2207 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2208 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2209 if (mem == NULL)
2210 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2211
2212 if (wsi_info && wsi_info->implicit_sync)
2213 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2214
2215 if (dedicate_info) {
2216 mem->image = radv_image_from_handle(dedicate_info->image);
2217 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2218 } else {
2219 mem->image = NULL;
2220 mem->buffer = NULL;
2221 }
2222
2223 if (import_info) {
2224 assert(import_info->handleType ==
2225 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2226 import_info->handleType ==
2227 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2228 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2229 NULL, NULL);
2230 if (!mem->bo) {
2231 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2232 goto fail;
2233 } else {
2234 close(import_info->fd);
2235 goto out_success;
2236 }
2237 }
2238
2239 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2240 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2241 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2242 domain = RADEON_DOMAIN_GTT;
2243 else
2244 domain = RADEON_DOMAIN_VRAM;
2245
2246 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2247 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2248 else
2249 flags |= RADEON_FLAG_CPU_ACCESS;
2250
2251 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2252 flags |= RADEON_FLAG_GTT_WC;
2253
2254 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2255 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2256
2257 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2258 domain, flags);
2259
2260 if (!mem->bo) {
2261 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2262 goto fail;
2263 }
2264 mem->type_index = mem_type_index;
2265 out_success:
2266 *pMem = radv_device_memory_to_handle(mem);
2267
2268 return VK_SUCCESS;
2269
2270 fail:
2271 vk_free2(&device->alloc, pAllocator, mem);
2272
2273 return result;
2274 }
2275
2276 VkResult radv_AllocateMemory(
2277 VkDevice _device,
2278 const VkMemoryAllocateInfo* pAllocateInfo,
2279 const VkAllocationCallbacks* pAllocator,
2280 VkDeviceMemory* pMem)
2281 {
2282 RADV_FROM_HANDLE(radv_device, device, _device);
2283 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2284 }
2285
2286 void radv_FreeMemory(
2287 VkDevice _device,
2288 VkDeviceMemory _mem,
2289 const VkAllocationCallbacks* pAllocator)
2290 {
2291 RADV_FROM_HANDLE(radv_device, device, _device);
2292 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2293
2294 if (mem == NULL)
2295 return;
2296
2297 device->ws->buffer_destroy(mem->bo);
2298 mem->bo = NULL;
2299
2300 vk_free2(&device->alloc, pAllocator, mem);
2301 }
2302
2303 VkResult radv_MapMemory(
2304 VkDevice _device,
2305 VkDeviceMemory _memory,
2306 VkDeviceSize offset,
2307 VkDeviceSize size,
2308 VkMemoryMapFlags flags,
2309 void** ppData)
2310 {
2311 RADV_FROM_HANDLE(radv_device, device, _device);
2312 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2313
2314 if (mem == NULL) {
2315 *ppData = NULL;
2316 return VK_SUCCESS;
2317 }
2318
2319 *ppData = device->ws->buffer_map(mem->bo);
2320 if (*ppData) {
2321 *ppData += offset;
2322 return VK_SUCCESS;
2323 }
2324
2325 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2326 }
2327
2328 void radv_UnmapMemory(
2329 VkDevice _device,
2330 VkDeviceMemory _memory)
2331 {
2332 RADV_FROM_HANDLE(radv_device, device, _device);
2333 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2334
2335 if (mem == NULL)
2336 return;
2337
2338 device->ws->buffer_unmap(mem->bo);
2339 }
2340
2341 VkResult radv_FlushMappedMemoryRanges(
2342 VkDevice _device,
2343 uint32_t memoryRangeCount,
2344 const VkMappedMemoryRange* pMemoryRanges)
2345 {
2346 return VK_SUCCESS;
2347 }
2348
2349 VkResult radv_InvalidateMappedMemoryRanges(
2350 VkDevice _device,
2351 uint32_t memoryRangeCount,
2352 const VkMappedMemoryRange* pMemoryRanges)
2353 {
2354 return VK_SUCCESS;
2355 }
2356
2357 void radv_GetBufferMemoryRequirements(
2358 VkDevice _device,
2359 VkBuffer _buffer,
2360 VkMemoryRequirements* pMemoryRequirements)
2361 {
2362 RADV_FROM_HANDLE(radv_device, device, _device);
2363 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2364
2365 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2366
2367 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2368 pMemoryRequirements->alignment = 4096;
2369 else
2370 pMemoryRequirements->alignment = 16;
2371
2372 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2373 }
2374
2375 void radv_GetBufferMemoryRequirements2KHR(
2376 VkDevice device,
2377 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2378 VkMemoryRequirements2KHR* pMemoryRequirements)
2379 {
2380 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2381 &pMemoryRequirements->memoryRequirements);
2382 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2383 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2384 switch (ext->sType) {
2385 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2386 VkMemoryDedicatedRequirementsKHR *req =
2387 (VkMemoryDedicatedRequirementsKHR *) ext;
2388 req->requiresDedicatedAllocation = buffer->shareable;
2389 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2390 break;
2391 }
2392 default:
2393 break;
2394 }
2395 }
2396 }
2397
2398 void radv_GetImageMemoryRequirements(
2399 VkDevice _device,
2400 VkImage _image,
2401 VkMemoryRequirements* pMemoryRequirements)
2402 {
2403 RADV_FROM_HANDLE(radv_device, device, _device);
2404 RADV_FROM_HANDLE(radv_image, image, _image);
2405
2406 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2407
2408 pMemoryRequirements->size = image->size;
2409 pMemoryRequirements->alignment = image->alignment;
2410 }
2411
2412 void radv_GetImageMemoryRequirements2KHR(
2413 VkDevice device,
2414 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2415 VkMemoryRequirements2KHR* pMemoryRequirements)
2416 {
2417 radv_GetImageMemoryRequirements(device, pInfo->image,
2418 &pMemoryRequirements->memoryRequirements);
2419
2420 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2421
2422 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2423 switch (ext->sType) {
2424 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2425 VkMemoryDedicatedRequirementsKHR *req =
2426 (VkMemoryDedicatedRequirementsKHR *) ext;
2427 req->requiresDedicatedAllocation = image->shareable;
2428 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2429 break;
2430 }
2431 default:
2432 break;
2433 }
2434 }
2435 }
2436
2437 void radv_GetImageSparseMemoryRequirements(
2438 VkDevice device,
2439 VkImage image,
2440 uint32_t* pSparseMemoryRequirementCount,
2441 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2442 {
2443 stub();
2444 }
2445
2446 void radv_GetImageSparseMemoryRequirements2KHR(
2447 VkDevice device,
2448 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2449 uint32_t* pSparseMemoryRequirementCount,
2450 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2451 {
2452 stub();
2453 }
2454
2455 void radv_GetDeviceMemoryCommitment(
2456 VkDevice device,
2457 VkDeviceMemory memory,
2458 VkDeviceSize* pCommittedMemoryInBytes)
2459 {
2460 *pCommittedMemoryInBytes = 0;
2461 }
2462
2463 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2464 uint32_t bindInfoCount,
2465 const VkBindBufferMemoryInfoKHR *pBindInfos)
2466 {
2467 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2468 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2469 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2470
2471 if (mem) {
2472 buffer->bo = mem->bo;
2473 buffer->offset = pBindInfos[i].memoryOffset;
2474 } else {
2475 buffer->bo = NULL;
2476 }
2477 }
2478 return VK_SUCCESS;
2479 }
2480
2481 VkResult radv_BindBufferMemory(
2482 VkDevice device,
2483 VkBuffer buffer,
2484 VkDeviceMemory memory,
2485 VkDeviceSize memoryOffset)
2486 {
2487 const VkBindBufferMemoryInfoKHR info = {
2488 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2489 .buffer = buffer,
2490 .memory = memory,
2491 .memoryOffset = memoryOffset
2492 };
2493
2494 return radv_BindBufferMemory2KHR(device, 1, &info);
2495 }
2496
2497 VkResult radv_BindImageMemory2KHR(VkDevice device,
2498 uint32_t bindInfoCount,
2499 const VkBindImageMemoryInfoKHR *pBindInfos)
2500 {
2501 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2502 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2503 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2504
2505 if (mem) {
2506 image->bo = mem->bo;
2507 image->offset = pBindInfos[i].memoryOffset;
2508 } else {
2509 image->bo = NULL;
2510 image->offset = 0;
2511 }
2512 }
2513 return VK_SUCCESS;
2514 }
2515
2516
2517 VkResult radv_BindImageMemory(
2518 VkDevice device,
2519 VkImage image,
2520 VkDeviceMemory memory,
2521 VkDeviceSize memoryOffset)
2522 {
2523 const VkBindImageMemoryInfoKHR info = {
2524 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2525 .image = image,
2526 .memory = memory,
2527 .memoryOffset = memoryOffset
2528 };
2529
2530 return radv_BindImageMemory2KHR(device, 1, &info);
2531 }
2532
2533
2534 static void
2535 radv_sparse_buffer_bind_memory(struct radv_device *device,
2536 const VkSparseBufferMemoryBindInfo *bind)
2537 {
2538 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2539
2540 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2541 struct radv_device_memory *mem = NULL;
2542
2543 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2544 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2545
2546 device->ws->buffer_virtual_bind(buffer->bo,
2547 bind->pBinds[i].resourceOffset,
2548 bind->pBinds[i].size,
2549 mem ? mem->bo : NULL,
2550 bind->pBinds[i].memoryOffset);
2551 }
2552 }
2553
2554 static void
2555 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2556 const VkSparseImageOpaqueMemoryBindInfo *bind)
2557 {
2558 RADV_FROM_HANDLE(radv_image, image, bind->image);
2559
2560 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2561 struct radv_device_memory *mem = NULL;
2562
2563 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2564 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2565
2566 device->ws->buffer_virtual_bind(image->bo,
2567 bind->pBinds[i].resourceOffset,
2568 bind->pBinds[i].size,
2569 mem ? mem->bo : NULL,
2570 bind->pBinds[i].memoryOffset);
2571 }
2572 }
2573
2574 VkResult radv_QueueBindSparse(
2575 VkQueue _queue,
2576 uint32_t bindInfoCount,
2577 const VkBindSparseInfo* pBindInfo,
2578 VkFence _fence)
2579 {
2580 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2581 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2582 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2583 bool fence_emitted = false;
2584
2585 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2586 struct radv_winsys_sem_info sem_info;
2587 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2588 radv_sparse_buffer_bind_memory(queue->device,
2589 pBindInfo[i].pBufferBinds + j);
2590 }
2591
2592 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2593 radv_sparse_image_opaque_bind_memory(queue->device,
2594 pBindInfo[i].pImageOpaqueBinds + j);
2595 }
2596
2597 VkResult result;
2598 result = radv_alloc_sem_info(&sem_info,
2599 pBindInfo[i].waitSemaphoreCount,
2600 pBindInfo[i].pWaitSemaphores,
2601 pBindInfo[i].signalSemaphoreCount,
2602 pBindInfo[i].pSignalSemaphores,
2603 _fence);
2604 if (result != VK_SUCCESS)
2605 return result;
2606
2607 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2608 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2609 &queue->device->empty_cs[queue->queue_family_index],
2610 1, NULL, NULL,
2611 &sem_info,
2612 false, base_fence);
2613 fence_emitted = true;
2614 if (fence)
2615 fence->submitted = true;
2616 }
2617
2618 radv_free_sem_info(&sem_info);
2619
2620 }
2621
2622 if (fence && !fence_emitted) {
2623 fence->signalled = true;
2624 }
2625
2626 return VK_SUCCESS;
2627 }
2628
2629 VkResult radv_CreateFence(
2630 VkDevice _device,
2631 const VkFenceCreateInfo* pCreateInfo,
2632 const VkAllocationCallbacks* pAllocator,
2633 VkFence* pFence)
2634 {
2635 RADV_FROM_HANDLE(radv_device, device, _device);
2636 const VkExportFenceCreateInfoKHR *export =
2637 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2638 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2639 export ? export->handleTypes : 0;
2640
2641 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2642 sizeof(*fence), 8,
2643 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2644
2645 if (!fence)
2646 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2647
2648 fence->submitted = false;
2649 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2650 fence->temp_syncobj = 0;
2651 if (handleTypes) {
2652 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2653 if (ret) {
2654 vk_free2(&device->alloc, pAllocator, fence);
2655 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2656 }
2657 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2658 device->ws->signal_syncobj(device->ws, fence->syncobj);
2659 }
2660 fence->fence = NULL;
2661 } else {
2662 fence->fence = device->ws->create_fence();
2663 if (!fence->fence) {
2664 vk_free2(&device->alloc, pAllocator, fence);
2665 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2666 }
2667 fence->syncobj = 0;
2668 }
2669
2670 *pFence = radv_fence_to_handle(fence);
2671
2672 return VK_SUCCESS;
2673 }
2674
2675 void radv_DestroyFence(
2676 VkDevice _device,
2677 VkFence _fence,
2678 const VkAllocationCallbacks* pAllocator)
2679 {
2680 RADV_FROM_HANDLE(radv_device, device, _device);
2681 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2682
2683 if (!fence)
2684 return;
2685
2686 if (fence->temp_syncobj)
2687 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2688 if (fence->syncobj)
2689 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2690 if (fence->fence)
2691 device->ws->destroy_fence(fence->fence);
2692 vk_free2(&device->alloc, pAllocator, fence);
2693 }
2694
2695 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2696 {
2697 uint64_t current_time;
2698 struct timespec tv;
2699
2700 clock_gettime(CLOCK_MONOTONIC, &tv);
2701 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2702
2703 timeout = MIN2(UINT64_MAX - current_time, timeout);
2704
2705 return current_time + timeout;
2706 }
2707
2708 VkResult radv_WaitForFences(
2709 VkDevice _device,
2710 uint32_t fenceCount,
2711 const VkFence* pFences,
2712 VkBool32 waitAll,
2713 uint64_t timeout)
2714 {
2715 RADV_FROM_HANDLE(radv_device, device, _device);
2716 timeout = radv_get_absolute_timeout(timeout);
2717
2718 if (!waitAll && fenceCount > 1) {
2719 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2720 }
2721
2722 for (uint32_t i = 0; i < fenceCount; ++i) {
2723 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2724 bool expired = false;
2725
2726 if (fence->temp_syncobj) {
2727 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2728 return VK_TIMEOUT;
2729 continue;
2730 }
2731
2732 if (fence->syncobj) {
2733 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2734 return VK_TIMEOUT;
2735 continue;
2736 }
2737
2738 if (fence->signalled)
2739 continue;
2740
2741 if (!fence->submitted)
2742 return VK_TIMEOUT;
2743
2744 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2745 if (!expired)
2746 return VK_TIMEOUT;
2747
2748 fence->signalled = true;
2749 }
2750
2751 return VK_SUCCESS;
2752 }
2753
2754 VkResult radv_ResetFences(VkDevice _device,
2755 uint32_t fenceCount,
2756 const VkFence *pFences)
2757 {
2758 RADV_FROM_HANDLE(radv_device, device, _device);
2759
2760 for (unsigned i = 0; i < fenceCount; ++i) {
2761 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2762 fence->submitted = fence->signalled = false;
2763
2764 /* Per spec, we first restore the permanent payload, and then reset, so
2765 * having a temp syncobj should not skip resetting the permanent syncobj. */
2766 if (fence->temp_syncobj) {
2767 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2768 fence->temp_syncobj = 0;
2769 }
2770
2771 if (fence->syncobj) {
2772 device->ws->reset_syncobj(device->ws, fence->syncobj);
2773 }
2774 }
2775
2776 return VK_SUCCESS;
2777 }
2778
2779 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2780 {
2781 RADV_FROM_HANDLE(radv_device, device, _device);
2782 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2783
2784 if (fence->temp_syncobj) {
2785 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2786 return success ? VK_SUCCESS : VK_NOT_READY;
2787 }
2788
2789 if (fence->syncobj) {
2790 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2791 return success ? VK_SUCCESS : VK_NOT_READY;
2792 }
2793
2794 if (fence->signalled)
2795 return VK_SUCCESS;
2796 if (!fence->submitted)
2797 return VK_NOT_READY;
2798 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2799 return VK_NOT_READY;
2800
2801 return VK_SUCCESS;
2802 }
2803
2804
2805 // Queue semaphore functions
2806
2807 VkResult radv_CreateSemaphore(
2808 VkDevice _device,
2809 const VkSemaphoreCreateInfo* pCreateInfo,
2810 const VkAllocationCallbacks* pAllocator,
2811 VkSemaphore* pSemaphore)
2812 {
2813 RADV_FROM_HANDLE(radv_device, device, _device);
2814 const VkExportSemaphoreCreateInfoKHR *export =
2815 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2816 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2817 export ? export->handleTypes : 0;
2818
2819 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2820 sizeof(*sem), 8,
2821 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2822 if (!sem)
2823 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2824
2825 sem->temp_syncobj = 0;
2826 /* create a syncobject if we are going to export this semaphore */
2827 if (handleTypes) {
2828 assert (device->physical_device->rad_info.has_syncobj);
2829 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2830 if (ret) {
2831 vk_free2(&device->alloc, pAllocator, sem);
2832 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2833 }
2834 sem->sem = NULL;
2835 } else {
2836 sem->sem = device->ws->create_sem(device->ws);
2837 if (!sem->sem) {
2838 vk_free2(&device->alloc, pAllocator, sem);
2839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2840 }
2841 sem->syncobj = 0;
2842 }
2843
2844 *pSemaphore = radv_semaphore_to_handle(sem);
2845 return VK_SUCCESS;
2846 }
2847
2848 void radv_DestroySemaphore(
2849 VkDevice _device,
2850 VkSemaphore _semaphore,
2851 const VkAllocationCallbacks* pAllocator)
2852 {
2853 RADV_FROM_HANDLE(radv_device, device, _device);
2854 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2855 if (!_semaphore)
2856 return;
2857
2858 if (sem->syncobj)
2859 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2860 else
2861 device->ws->destroy_sem(sem->sem);
2862 vk_free2(&device->alloc, pAllocator, sem);
2863 }
2864
2865 VkResult radv_CreateEvent(
2866 VkDevice _device,
2867 const VkEventCreateInfo* pCreateInfo,
2868 const VkAllocationCallbacks* pAllocator,
2869 VkEvent* pEvent)
2870 {
2871 RADV_FROM_HANDLE(radv_device, device, _device);
2872 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2873 sizeof(*event), 8,
2874 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2875
2876 if (!event)
2877 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2878
2879 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2880 RADEON_DOMAIN_GTT,
2881 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2882 if (!event->bo) {
2883 vk_free2(&device->alloc, pAllocator, event);
2884 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2885 }
2886
2887 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2888
2889 *pEvent = radv_event_to_handle(event);
2890
2891 return VK_SUCCESS;
2892 }
2893
2894 void radv_DestroyEvent(
2895 VkDevice _device,
2896 VkEvent _event,
2897 const VkAllocationCallbacks* pAllocator)
2898 {
2899 RADV_FROM_HANDLE(radv_device, device, _device);
2900 RADV_FROM_HANDLE(radv_event, event, _event);
2901
2902 if (!event)
2903 return;
2904 device->ws->buffer_destroy(event->bo);
2905 vk_free2(&device->alloc, pAllocator, event);
2906 }
2907
2908 VkResult radv_GetEventStatus(
2909 VkDevice _device,
2910 VkEvent _event)
2911 {
2912 RADV_FROM_HANDLE(radv_event, event, _event);
2913
2914 if (*event->map == 1)
2915 return VK_EVENT_SET;
2916 return VK_EVENT_RESET;
2917 }
2918
2919 VkResult radv_SetEvent(
2920 VkDevice _device,
2921 VkEvent _event)
2922 {
2923 RADV_FROM_HANDLE(radv_event, event, _event);
2924 *event->map = 1;
2925
2926 return VK_SUCCESS;
2927 }
2928
2929 VkResult radv_ResetEvent(
2930 VkDevice _device,
2931 VkEvent _event)
2932 {
2933 RADV_FROM_HANDLE(radv_event, event, _event);
2934 *event->map = 0;
2935
2936 return VK_SUCCESS;
2937 }
2938
2939 VkResult radv_CreateBuffer(
2940 VkDevice _device,
2941 const VkBufferCreateInfo* pCreateInfo,
2942 const VkAllocationCallbacks* pAllocator,
2943 VkBuffer* pBuffer)
2944 {
2945 RADV_FROM_HANDLE(radv_device, device, _device);
2946 struct radv_buffer *buffer;
2947
2948 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2949
2950 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2951 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2952 if (buffer == NULL)
2953 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2954
2955 buffer->size = pCreateInfo->size;
2956 buffer->usage = pCreateInfo->usage;
2957 buffer->bo = NULL;
2958 buffer->offset = 0;
2959 buffer->flags = pCreateInfo->flags;
2960
2961 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2962 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2963
2964 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2965 buffer->bo = device->ws->buffer_create(device->ws,
2966 align64(buffer->size, 4096),
2967 4096, 0, RADEON_FLAG_VIRTUAL);
2968 if (!buffer->bo) {
2969 vk_free2(&device->alloc, pAllocator, buffer);
2970 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2971 }
2972 }
2973
2974 *pBuffer = radv_buffer_to_handle(buffer);
2975
2976 return VK_SUCCESS;
2977 }
2978
2979 void radv_DestroyBuffer(
2980 VkDevice _device,
2981 VkBuffer _buffer,
2982 const VkAllocationCallbacks* pAllocator)
2983 {
2984 RADV_FROM_HANDLE(radv_device, device, _device);
2985 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2986
2987 if (!buffer)
2988 return;
2989
2990 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2991 device->ws->buffer_destroy(buffer->bo);
2992
2993 vk_free2(&device->alloc, pAllocator, buffer);
2994 }
2995
2996 static inline unsigned
2997 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2998 {
2999 if (stencil)
3000 return image->surface.u.legacy.stencil_tiling_index[level];
3001 else
3002 return image->surface.u.legacy.tiling_index[level];
3003 }
3004
3005 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3006 {
3007 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3008 }
3009
3010 static void
3011 radv_initialise_color_surface(struct radv_device *device,
3012 struct radv_color_buffer_info *cb,
3013 struct radv_image_view *iview)
3014 {
3015 const struct vk_format_description *desc;
3016 unsigned ntype, format, swap, endian;
3017 unsigned blend_clamp = 0, blend_bypass = 0;
3018 uint64_t va;
3019 const struct radeon_surf *surf = &iview->image->surface;
3020
3021 desc = vk_format_description(iview->vk_format);
3022
3023 memset(cb, 0, sizeof(*cb));
3024
3025 /* Intensity is implemented as Red, so treat it that way. */
3026 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3027
3028 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3029
3030 cb->cb_color_base = va >> 8;
3031
3032 if (device->physical_device->rad_info.chip_class >= GFX9) {
3033 struct gfx9_surf_meta_flags meta;
3034 if (iview->image->dcc_offset)
3035 meta = iview->image->surface.u.gfx9.dcc;
3036 else
3037 meta = iview->image->surface.u.gfx9.cmask;
3038
3039 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3040 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3041 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3042 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3043
3044 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3045 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3046 } else {
3047 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3048 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3049
3050 cb->cb_color_base += level_info->offset >> 8;
3051 if (level_info->mode == RADEON_SURF_MODE_2D)
3052 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3053
3054 pitch_tile_max = level_info->nblk_x / 8 - 1;
3055 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3056 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3057
3058 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3059 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3060 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3061
3062 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3063
3064 if (iview->image->fmask.size) {
3065 if (device->physical_device->rad_info.chip_class >= CIK)
3066 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3067 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3068 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3069 } else {
3070 /* This must be set for fast clear to work without FMASK. */
3071 if (device->physical_device->rad_info.chip_class >= CIK)
3072 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3073 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3074 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3075 }
3076 }
3077
3078 /* CMASK variables */
3079 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3080 va += iview->image->cmask.offset;
3081 cb->cb_color_cmask = va >> 8;
3082
3083 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3084 va += iview->image->dcc_offset;
3085 cb->cb_dcc_base = va >> 8;
3086 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3087
3088 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3089 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3090 S_028C6C_SLICE_MAX(max_slice);
3091
3092 if (iview->image->info.samples > 1) {
3093 unsigned log_samples = util_logbase2(iview->image->info.samples);
3094
3095 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3096 S_028C74_NUM_FRAGMENTS(log_samples);
3097 }
3098
3099 if (iview->image->fmask.size) {
3100 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3101 cb->cb_color_fmask = va >> 8;
3102 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3103 } else {
3104 cb->cb_color_fmask = cb->cb_color_base;
3105 }
3106
3107 ntype = radv_translate_color_numformat(iview->vk_format,
3108 desc,
3109 vk_format_get_first_non_void_channel(iview->vk_format));
3110 format = radv_translate_colorformat(iview->vk_format);
3111 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3112 radv_finishme("Illegal color\n");
3113 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3114 endian = radv_colorformat_endian_swap(format);
3115
3116 /* blend clamp should be set for all NORM/SRGB types */
3117 if (ntype == V_028C70_NUMBER_UNORM ||
3118 ntype == V_028C70_NUMBER_SNORM ||
3119 ntype == V_028C70_NUMBER_SRGB)
3120 blend_clamp = 1;
3121
3122 /* set blend bypass according to docs if SINT/UINT or
3123 8/24 COLOR variants */
3124 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3125 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3126 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3127 blend_clamp = 0;
3128 blend_bypass = 1;
3129 }
3130 #if 0
3131 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3132 (format == V_028C70_COLOR_8 ||
3133 format == V_028C70_COLOR_8_8 ||
3134 format == V_028C70_COLOR_8_8_8_8))
3135 ->color_is_int8 = true;
3136 #endif
3137 cb->cb_color_info = S_028C70_FORMAT(format) |
3138 S_028C70_COMP_SWAP(swap) |
3139 S_028C70_BLEND_CLAMP(blend_clamp) |
3140 S_028C70_BLEND_BYPASS(blend_bypass) |
3141 S_028C70_SIMPLE_FLOAT(1) |
3142 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3143 ntype != V_028C70_NUMBER_SNORM &&
3144 ntype != V_028C70_NUMBER_SRGB &&
3145 format != V_028C70_COLOR_8_24 &&
3146 format != V_028C70_COLOR_24_8) |
3147 S_028C70_NUMBER_TYPE(ntype) |
3148 S_028C70_ENDIAN(endian);
3149 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3150 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3151 if (device->physical_device->rad_info.chip_class == SI) {
3152 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3153 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3154 }
3155 }
3156
3157 if (iview->image->cmask.size &&
3158 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3159 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3160
3161 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3162 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3163
3164 if (device->physical_device->rad_info.chip_class >= VI) {
3165 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3166 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3167 unsigned independent_64b_blocks = 0;
3168 unsigned max_compressed_block_size;
3169
3170 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3171 64 for APU because all of our APUs to date use DIMMs which have
3172 a request granularity size of 64B while all other chips have a
3173 32B request size */
3174 if (!device->physical_device->rad_info.has_dedicated_vram)
3175 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3176
3177 if (iview->image->info.samples > 1) {
3178 if (iview->image->surface.bpe == 1)
3179 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3180 else if (iview->image->surface.bpe == 2)
3181 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3182 }
3183
3184 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3185 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3186 independent_64b_blocks = 1;
3187 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3188 } else
3189 max_compressed_block_size = max_uncompressed_block_size;
3190
3191 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3192 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3193 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3194 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3195 }
3196
3197 /* This must be set for fast clear to work without FMASK. */
3198 if (!iview->image->fmask.size &&
3199 device->physical_device->rad_info.chip_class == SI) {
3200 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3201 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3202 }
3203
3204 if (device->physical_device->rad_info.chip_class >= GFX9) {
3205 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3206 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3207
3208 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3209 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3210 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3211 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3212 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3213 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3214 }
3215 }
3216
3217 static void
3218 radv_initialise_ds_surface(struct radv_device *device,
3219 struct radv_ds_buffer_info *ds,
3220 struct radv_image_view *iview)
3221 {
3222 unsigned level = iview->base_mip;
3223 unsigned format, stencil_format;
3224 uint64_t va, s_offs, z_offs;
3225 bool stencil_only = false;
3226 memset(ds, 0, sizeof(*ds));
3227 switch (iview->image->vk_format) {
3228 case VK_FORMAT_D24_UNORM_S8_UINT:
3229 case VK_FORMAT_X8_D24_UNORM_PACK32:
3230 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3231 ds->offset_scale = 2.0f;
3232 break;
3233 case VK_FORMAT_D16_UNORM:
3234 case VK_FORMAT_D16_UNORM_S8_UINT:
3235 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3236 ds->offset_scale = 4.0f;
3237 break;
3238 case VK_FORMAT_D32_SFLOAT:
3239 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3240 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3241 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3242 ds->offset_scale = 1.0f;
3243 break;
3244 case VK_FORMAT_S8_UINT:
3245 stencil_only = true;
3246 break;
3247 default:
3248 break;
3249 }
3250
3251 format = radv_translate_dbformat(iview->image->vk_format);
3252 stencil_format = iview->image->surface.has_stencil ?
3253 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3254
3255 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3256 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3257 S_028008_SLICE_MAX(max_slice);
3258
3259 ds->db_htile_data_base = 0;
3260 ds->db_htile_surface = 0;
3261
3262 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3263 s_offs = z_offs = va;
3264
3265 if (device->physical_device->rad_info.chip_class >= GFX9) {
3266 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3267 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3268
3269 ds->db_z_info = S_028038_FORMAT(format) |
3270 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3271 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3272 S_028038_MAXMIP(iview->image->info.levels - 1);
3273 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3274 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3275
3276 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3277 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3278 ds->db_depth_view |= S_028008_MIPID(level);
3279
3280 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3281 S_02801C_Y_MAX(iview->image->info.height - 1);
3282
3283 if (radv_htile_enabled(iview->image, level)) {
3284 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3285
3286 if (iview->image->tc_compatible_htile) {
3287 unsigned max_zplanes = 4;
3288
3289 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3290 iview->image->info.samples > 1)
3291 max_zplanes = 2;
3292
3293 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3294 S_028038_ITERATE_FLUSH(1);
3295 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3296 }
3297
3298 if (!iview->image->surface.has_stencil)
3299 /* Use all of the htile_buffer for depth if there's no stencil. */
3300 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3301 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3302 iview->image->htile_offset;
3303 ds->db_htile_data_base = va >> 8;
3304 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3305 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3306 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3307 }
3308 } else {
3309 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3310
3311 if (stencil_only)
3312 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3313
3314 z_offs += iview->image->surface.u.legacy.level[level].offset;
3315 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3316
3317 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3318 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3319 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3320
3321 if (iview->image->info.samples > 1)
3322 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3323
3324 if (device->physical_device->rad_info.chip_class >= CIK) {
3325 struct radeon_info *info = &device->physical_device->rad_info;
3326 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3327 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3328 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3329 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3330 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3331 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3332
3333 if (stencil_only)
3334 tile_mode = stencil_tile_mode;
3335
3336 ds->db_depth_info |=
3337 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3338 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3339 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3340 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3341 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3342 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3343 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3344 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3345 } else {
3346 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3347 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3348 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3349 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3350 if (stencil_only)
3351 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3352 }
3353
3354 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3355 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3356 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3357
3358 if (radv_htile_enabled(iview->image, level)) {
3359 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3360
3361 if (!iview->image->surface.has_stencil &&
3362 !iview->image->tc_compatible_htile)
3363 /* Use all of the htile_buffer for depth if there's no stencil. */
3364 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3365
3366 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3367 iview->image->htile_offset;
3368 ds->db_htile_data_base = va >> 8;
3369 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3370
3371 if (iview->image->tc_compatible_htile) {
3372 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3373
3374 if (iview->image->info.samples <= 1)
3375 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3376 else if (iview->image->info.samples <= 4)
3377 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3378 else
3379 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3380 }
3381 }
3382 }
3383
3384 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3385 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3386 }
3387
3388 VkResult radv_CreateFramebuffer(
3389 VkDevice _device,
3390 const VkFramebufferCreateInfo* pCreateInfo,
3391 const VkAllocationCallbacks* pAllocator,
3392 VkFramebuffer* pFramebuffer)
3393 {
3394 RADV_FROM_HANDLE(radv_device, device, _device);
3395 struct radv_framebuffer *framebuffer;
3396
3397 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3398
3399 size_t size = sizeof(*framebuffer) +
3400 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3401 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3402 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3403 if (framebuffer == NULL)
3404 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3405
3406 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3407 framebuffer->width = pCreateInfo->width;
3408 framebuffer->height = pCreateInfo->height;
3409 framebuffer->layers = pCreateInfo->layers;
3410 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3411 VkImageView _iview = pCreateInfo->pAttachments[i];
3412 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3413 framebuffer->attachments[i].attachment = iview;
3414 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3415 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3416 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3417 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3418 }
3419 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3420 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3421 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3422 }
3423
3424 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3425 return VK_SUCCESS;
3426 }
3427
3428 void radv_DestroyFramebuffer(
3429 VkDevice _device,
3430 VkFramebuffer _fb,
3431 const VkAllocationCallbacks* pAllocator)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3435
3436 if (!fb)
3437 return;
3438 vk_free2(&device->alloc, pAllocator, fb);
3439 }
3440
3441 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3442 {
3443 switch (address_mode) {
3444 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3445 return V_008F30_SQ_TEX_WRAP;
3446 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3447 return V_008F30_SQ_TEX_MIRROR;
3448 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3449 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3450 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3451 return V_008F30_SQ_TEX_CLAMP_BORDER;
3452 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3453 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3454 default:
3455 unreachable("illegal tex wrap mode");
3456 break;
3457 }
3458 }
3459
3460 static unsigned
3461 radv_tex_compare(VkCompareOp op)
3462 {
3463 switch (op) {
3464 case VK_COMPARE_OP_NEVER:
3465 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3466 case VK_COMPARE_OP_LESS:
3467 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3468 case VK_COMPARE_OP_EQUAL:
3469 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3470 case VK_COMPARE_OP_LESS_OR_EQUAL:
3471 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3472 case VK_COMPARE_OP_GREATER:
3473 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3474 case VK_COMPARE_OP_NOT_EQUAL:
3475 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3476 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3477 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3478 case VK_COMPARE_OP_ALWAYS:
3479 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3480 default:
3481 unreachable("illegal compare mode");
3482 break;
3483 }
3484 }
3485
3486 static unsigned
3487 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3488 {
3489 switch (filter) {
3490 case VK_FILTER_NEAREST:
3491 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3492 V_008F38_SQ_TEX_XY_FILTER_POINT);
3493 case VK_FILTER_LINEAR:
3494 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3495 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3496 case VK_FILTER_CUBIC_IMG:
3497 default:
3498 fprintf(stderr, "illegal texture filter");
3499 return 0;
3500 }
3501 }
3502
3503 static unsigned
3504 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3505 {
3506 switch (mode) {
3507 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3508 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3509 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3510 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3511 default:
3512 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3513 }
3514 }
3515
3516 static unsigned
3517 radv_tex_bordercolor(VkBorderColor bcolor)
3518 {
3519 switch (bcolor) {
3520 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3521 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3522 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3523 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3524 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3525 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3526 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3527 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3528 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3529 default:
3530 break;
3531 }
3532 return 0;
3533 }
3534
3535 static unsigned
3536 radv_tex_aniso_filter(unsigned filter)
3537 {
3538 if (filter < 2)
3539 return 0;
3540 if (filter < 4)
3541 return 1;
3542 if (filter < 8)
3543 return 2;
3544 if (filter < 16)
3545 return 3;
3546 return 4;
3547 }
3548
3549 static void
3550 radv_init_sampler(struct radv_device *device,
3551 struct radv_sampler *sampler,
3552 const VkSamplerCreateInfo *pCreateInfo)
3553 {
3554 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3555 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3556 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3557 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3558
3559 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3560 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3561 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3562 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3563 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3564 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3565 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3566 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3567 S_008F30_DISABLE_CUBE_WRAP(0) |
3568 S_008F30_COMPAT_MODE(is_vi));
3569 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3570 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3571 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3572 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3573 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3574 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3575 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3576 S_008F38_MIP_POINT_PRECLAMP(0) |
3577 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3578 S_008F38_FILTER_PREC_FIX(1) |
3579 S_008F38_ANISO_OVERRIDE(is_vi));
3580 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3581 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3582 }
3583
3584 VkResult radv_CreateSampler(
3585 VkDevice _device,
3586 const VkSamplerCreateInfo* pCreateInfo,
3587 const VkAllocationCallbacks* pAllocator,
3588 VkSampler* pSampler)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 struct radv_sampler *sampler;
3592
3593 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3594
3595 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3596 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3597 if (!sampler)
3598 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3599
3600 radv_init_sampler(device, sampler, pCreateInfo);
3601 *pSampler = radv_sampler_to_handle(sampler);
3602
3603 return VK_SUCCESS;
3604 }
3605
3606 void radv_DestroySampler(
3607 VkDevice _device,
3608 VkSampler _sampler,
3609 const VkAllocationCallbacks* pAllocator)
3610 {
3611 RADV_FROM_HANDLE(radv_device, device, _device);
3612 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3613
3614 if (!sampler)
3615 return;
3616 vk_free2(&device->alloc, pAllocator, sampler);
3617 }
3618
3619 /* vk_icd.h does not declare this function, so we declare it here to
3620 * suppress Wmissing-prototypes.
3621 */
3622 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3623 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3624
3625 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3626 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3627 {
3628 /* For the full details on loader interface versioning, see
3629 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3630 * What follows is a condensed summary, to help you navigate the large and
3631 * confusing official doc.
3632 *
3633 * - Loader interface v0 is incompatible with later versions. We don't
3634 * support it.
3635 *
3636 * - In loader interface v1:
3637 * - The first ICD entrypoint called by the loader is
3638 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3639 * entrypoint.
3640 * - The ICD must statically expose no other Vulkan symbol unless it is
3641 * linked with -Bsymbolic.
3642 * - Each dispatchable Vulkan handle created by the ICD must be
3643 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3644 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3645 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3646 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3647 * such loader-managed surfaces.
3648 *
3649 * - Loader interface v2 differs from v1 in:
3650 * - The first ICD entrypoint called by the loader is
3651 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3652 * statically expose this entrypoint.
3653 *
3654 * - Loader interface v3 differs from v2 in:
3655 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3656 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3657 * because the loader no longer does so.
3658 */
3659 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3660 return VK_SUCCESS;
3661 }
3662
3663 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3664 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3665 int *pFD)
3666 {
3667 RADV_FROM_HANDLE(radv_device, device, _device);
3668 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3669
3670 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3671
3672 /* At the moment, we support only the below handle types. */
3673 assert(pGetFdInfo->handleType ==
3674 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3675 pGetFdInfo->handleType ==
3676 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3677
3678 bool ret = radv_get_memory_fd(device, memory, pFD);
3679 if (ret == false)
3680 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3681 return VK_SUCCESS;
3682 }
3683
3684 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3685 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3686 int fd,
3687 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3688 {
3689 switch (handleType) {
3690 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3691 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3692 return VK_SUCCESS;
3693
3694 default:
3695 /* The valid usage section for this function says:
3696 *
3697 * "handleType must not be one of the handle types defined as
3698 * opaque."
3699 *
3700 * So opaque handle types fall into the default "unsupported" case.
3701 */
3702 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3703 }
3704 }
3705
3706 static VkResult radv_import_opaque_fd(struct radv_device *device,
3707 int fd,
3708 uint32_t *syncobj)
3709 {
3710 uint32_t syncobj_handle = 0;
3711 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3712 if (ret != 0)
3713 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3714
3715 if (*syncobj)
3716 device->ws->destroy_syncobj(device->ws, *syncobj);
3717
3718 *syncobj = syncobj_handle;
3719 close(fd);
3720
3721 return VK_SUCCESS;
3722 }
3723
3724 static VkResult radv_import_sync_fd(struct radv_device *device,
3725 int fd,
3726 uint32_t *syncobj)
3727 {
3728 /* If we create a syncobj we do it locally so that if we have an error, we don't
3729 * leave a syncobj in an undetermined state in the fence. */
3730 uint32_t syncobj_handle = *syncobj;
3731 if (!syncobj_handle) {
3732 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3733 if (ret) {
3734 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3735 }
3736 }
3737
3738 if (fd == -1) {
3739 device->ws->signal_syncobj(device->ws, syncobj_handle);
3740 } else {
3741 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3742 if (ret != 0)
3743 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3744 }
3745
3746 *syncobj = syncobj_handle;
3747 if (fd != -1)
3748 close(fd);
3749
3750 return VK_SUCCESS;
3751 }
3752
3753 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3754 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3755 {
3756 RADV_FROM_HANDLE(radv_device, device, _device);
3757 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3758 uint32_t *syncobj_dst = NULL;
3759
3760 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3761 syncobj_dst = &sem->temp_syncobj;
3762 } else {
3763 syncobj_dst = &sem->syncobj;
3764 }
3765
3766 switch(pImportSemaphoreFdInfo->handleType) {
3767 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3768 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3769 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3770 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3771 default:
3772 unreachable("Unhandled semaphore handle type");
3773 }
3774 }
3775
3776 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3777 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3778 int *pFd)
3779 {
3780 RADV_FROM_HANDLE(radv_device, device, _device);
3781 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3782 int ret;
3783 uint32_t syncobj_handle;
3784
3785 if (sem->temp_syncobj)
3786 syncobj_handle = sem->temp_syncobj;
3787 else
3788 syncobj_handle = sem->syncobj;
3789
3790 switch(pGetFdInfo->handleType) {
3791 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3792 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3793 break;
3794 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3795 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3796 break;
3797 default:
3798 unreachable("Unhandled semaphore handle type");
3799 }
3800
3801 if (ret)
3802 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3803 return VK_SUCCESS;
3804 }
3805
3806 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3807 VkPhysicalDevice physicalDevice,
3808 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3809 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3810 {
3811 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3812
3813 /* Require has_syncobj_wait for the syncobj signal ioctl introduced at virtually the same time */
3814 if (pdevice->rad_info.has_syncobj_wait &&
3815 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3816 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3817 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3818 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3819 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3820 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3821 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3822 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3823 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3824 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3825 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3826 } else {
3827 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3828 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3829 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3830 }
3831 }
3832
3833 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3834 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3835 {
3836 RADV_FROM_HANDLE(radv_device, device, _device);
3837 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3838 uint32_t *syncobj_dst = NULL;
3839
3840
3841 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3842 syncobj_dst = &fence->temp_syncobj;
3843 } else {
3844 syncobj_dst = &fence->syncobj;
3845 }
3846
3847 switch(pImportFenceFdInfo->handleType) {
3848 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3849 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3850 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3851 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3852 default:
3853 unreachable("Unhandled fence handle type");
3854 }
3855 }
3856
3857 VkResult radv_GetFenceFdKHR(VkDevice _device,
3858 const VkFenceGetFdInfoKHR *pGetFdInfo,
3859 int *pFd)
3860 {
3861 RADV_FROM_HANDLE(radv_device, device, _device);
3862 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3863 int ret;
3864 uint32_t syncobj_handle;
3865
3866 if (fence->temp_syncobj)
3867 syncobj_handle = fence->temp_syncobj;
3868 else
3869 syncobj_handle = fence->syncobj;
3870
3871 switch(pGetFdInfo->handleType) {
3872 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3873 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3874 break;
3875 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3876 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3877 break;
3878 default:
3879 unreachable("Unhandled fence handle type");
3880 }
3881
3882 if (ret)
3883 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3884 return VK_SUCCESS;
3885 }
3886
3887 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3888 VkPhysicalDevice physicalDevice,
3889 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
3890 VkExternalFencePropertiesKHR* pExternalFenceProperties)
3891 {
3892 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3893
3894 if (pdevice->rad_info.has_syncobj_wait &&
3895 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3896 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3897 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3898 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3899 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
3900 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3901 } else {
3902 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
3903 pExternalFenceProperties->compatibleHandleTypes = 0;
3904 pExternalFenceProperties->externalFenceFeatures = 0;
3905 }
3906 }