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ac: treat Mullins as Kabini, remove the enum
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
121 }
122
123 static uint64_t
124 radv_get_visible_vram_size(struct radv_physical_device *device)
125 {
126 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
127 }
128
129 static uint64_t
130 radv_get_vram_size(struct radv_physical_device *device)
131 {
132 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
133 }
134
135 static void
136 radv_physical_device_init_mem_types(struct radv_physical_device *device)
137 {
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
139 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
140 uint64_t vram_size = radv_get_vram_size(device);
141 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
142 device->memory_properties.memoryHeapCount = 0;
143 if (vram_size > 0) {
144 vram_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
146 .size = vram_size,
147 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150 if (visible_vram_size) {
151 visible_vram_index = device->memory_properties.memoryHeapCount++;
152 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
153 .size = visible_vram_size,
154 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
155 };
156 }
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
162 };
163 }
164
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
166 unsigned type_count = 0;
167 if (vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
185 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
186 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
189 .heapIndex = visible_vram_index,
190 };
191 }
192 if (gart_index >= 0) {
193 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
194 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
195 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
198 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 .heapIndex = gart_index,
200 };
201 }
202 device->memory_properties.memoryTypeCount = type_count;
203 }
204
205 static void
206 radv_handle_env_var_force_family(struct radv_physical_device *device)
207 {
208 const char *family = getenv("RADV_FORCE_FAMILY");
209 unsigned i;
210
211 if (!family)
212 return;
213
214 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
215 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
216 /* Override family and chip_class. */
217 device->rad_info.family = i;
218
219 if (i >= CHIP_VEGA10)
220 device->rad_info.chip_class = GFX9;
221 else if (i >= CHIP_TONGA)
222 device->rad_info.chip_class = GFX8;
223 else if (i >= CHIP_BONAIRE)
224 device->rad_info.chip_class = GFX7;
225 else
226 device->rad_info.chip_class = GFX6;
227
228 return;
229 }
230 }
231
232 fprintf(stderr, "radv: Unknown family: %s\n", family);
233 exit(1);
234 }
235
236 static VkResult
237 radv_physical_device_init(struct radv_physical_device *device,
238 struct radv_instance *instance,
239 drmDevicePtr drm_device)
240 {
241 const char *path = drm_device->nodes[DRM_NODE_RENDER];
242 VkResult result;
243 drmVersionPtr version;
244 int fd;
245 int master_fd = -1;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0) {
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Could not open device '%s'", path);
251
252 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
253 }
254
255 version = drmGetVersion(fd);
256 if (!version) {
257 close(fd);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not get the kernel driver version for device '%s'", path);
261
262 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
263 "failed to get version %s: %m", path);
264 }
265
266 if (strcmp(version->name, "amdgpu")) {
267 drmFreeVersion(version);
268 close(fd);
269
270 if (instance->debug_flags & RADV_DEBUG_STARTUP)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
272
273 return VK_ERROR_INCOMPATIBLE_DRIVER;
274 }
275 drmFreeVersion(version);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Found compatible device '%s'.", path);
279
280 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 device->instance = instance;
282
283 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
284 instance->perftest_flags);
285 if (!device->ws) {
286 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
287 goto fail;
288 }
289
290 if (instance->enabled_extensions.KHR_display) {
291 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
292 if (master_fd >= 0) {
293 uint32_t accel_working = 0;
294 struct drm_amdgpu_info request = {
295 .return_pointer = (uintptr_t)&accel_working,
296 .return_size = sizeof(accel_working),
297 .query = AMDGPU_INFO_ACCEL_WORKING
298 };
299
300 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
301 close(master_fd);
302 master_fd = -1;
303 }
304 }
305 }
306
307 device->master_fd = master_fd;
308 device->local_fd = fd;
309 device->ws->query_info(device->ws, &device->rad_info);
310
311 radv_handle_env_var_force_family(device);
312
313 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
314
315 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
316 device->ws->destroy(device->ws);
317 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags =
324 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
325 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
326
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
329 */
330 char buf[VK_UUID_SIZE * 2 + 1];
331 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
332 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
333
334 if (device->rad_info.chip_class < GFX8 ||
335 device->rad_info.chip_class > GFX9)
336 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337
338 radv_get_driver_uuid(&device->driver_uuid);
339 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
340
341 if (device->rad_info.family == CHIP_STONEY ||
342 device->rad_info.chip_class >= GFX9) {
343 device->has_rbplus = true;
344 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
345 device->rad_info.family == CHIP_VEGA12 ||
346 device->rad_info.family == CHIP_RAVEN ||
347 device->rad_info.family == CHIP_RAVEN2;
348 }
349
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
351 * on GFX6.
352 */
353 device->has_clear_state = device->rad_info.chip_class >= GFX7;
354
355 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
356
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
359 device->rad_info.family == CHIP_RAVEN;
360
361 /* Out-of-order primitive rasterization. */
362 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
363 device->rad_info.max_se >= 2;
364 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
365 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
366
367 device->dcc_msaa_allowed =
368 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
369
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
371 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
372 (device->rad_info.chip_class >= GFX8 &&
373 device->rad_info.me_fw_feature >= 41);
374
375 radv_physical_device_init_mem_types(device);
376 radv_fill_device_extension_table(device, &device->supported_extensions);
377
378 device->bus_info = *drm_device->businfo.pci;
379
380 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
381 ac_print_gpu_info(&device->rad_info);
382
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
385 * semi-layers).
386 */
387 result = radv_init_wsi(device);
388 if (result != VK_SUCCESS) {
389 device->ws->destroy(device->ws);
390 vk_error(instance, result);
391 goto fail;
392 }
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {"nobinning", RADV_DEBUG_NOBINNING},
466 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
482 {"bolist", RADV_PERFTEST_BO_LIST},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
514 /* Workaround for a WaW hazard when LLVM moves/merges
515 * load/store memory operations.
516 * See https://reviews.llvm.org/D61313
517 */
518 if (HAVE_LLVM < 0x900)
519 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
520 }
521 }
522
523 static int radv_get_instance_extension_index(const char *name)
524 {
525 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
526 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
527 return i;
528 }
529 return -1;
530 }
531
532 static const char radv_dri_options_xml[] =
533 DRI_CONF_BEGIN
534 DRI_CONF_SECTION_QUALITY
535 DRI_CONF_ADAPTIVE_SYNC("true")
536 DRI_CONF_SECTION_END
537 DRI_CONF_END;
538
539 static void radv_init_dri_options(struct radv_instance *instance)
540 {
541 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
542 driParseConfigFiles(&instance->dri_options,
543 &instance->available_dri_options,
544 0, "radv", NULL);
545 }
546
547 VkResult radv_CreateInstance(
548 const VkInstanceCreateInfo* pCreateInfo,
549 const VkAllocationCallbacks* pAllocator,
550 VkInstance* pInstance)
551 {
552 struct radv_instance *instance;
553 VkResult result;
554
555 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
556
557 uint32_t client_version;
558 if (pCreateInfo->pApplicationInfo &&
559 pCreateInfo->pApplicationInfo->apiVersion != 0) {
560 client_version = pCreateInfo->pApplicationInfo->apiVersion;
561 } else {
562 client_version = VK_API_VERSION_1_0;
563 }
564
565 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
566 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
567 if (!instance)
568 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
569
570 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
571
572 if (pAllocator)
573 instance->alloc = *pAllocator;
574 else
575 instance->alloc = default_alloc;
576
577 instance->apiVersion = client_version;
578 instance->physicalDeviceCount = -1;
579
580 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
581 radv_debug_options);
582
583 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
584 radv_perftest_options);
585
586
587 if (instance->debug_flags & RADV_DEBUG_STARTUP)
588 radv_logi("Created an instance");
589
590 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
591 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
592 int index = radv_get_instance_extension_index(ext_name);
593
594 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
595 vk_free2(&default_alloc, pAllocator, instance);
596 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
597 }
598
599 instance->enabled_extensions.extensions[index] = true;
600 }
601
602 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
603 if (result != VK_SUCCESS) {
604 vk_free2(&default_alloc, pAllocator, instance);
605 return vk_error(instance, result);
606 }
607
608 _mesa_locale_init();
609 glsl_type_singleton_init_or_ref();
610
611 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
612
613 radv_init_dri_options(instance);
614 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
615
616 *pInstance = radv_instance_to_handle(instance);
617
618 return VK_SUCCESS;
619 }
620
621 void radv_DestroyInstance(
622 VkInstance _instance,
623 const VkAllocationCallbacks* pAllocator)
624 {
625 RADV_FROM_HANDLE(radv_instance, instance, _instance);
626
627 if (!instance)
628 return;
629
630 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
631 radv_physical_device_finish(instance->physicalDevices + i);
632 }
633
634 VG(VALGRIND_DESTROY_MEMPOOL(instance));
635
636 glsl_type_singleton_decref();
637 _mesa_locale_fini();
638
639 driDestroyOptionCache(&instance->dri_options);
640 driDestroyOptionInfo(&instance->available_dri_options);
641
642 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
643
644 vk_free(&instance->alloc, instance);
645 }
646
647 static VkResult
648 radv_enumerate_devices(struct radv_instance *instance)
649 {
650 /* TODO: Check for more devices ? */
651 drmDevicePtr devices[8];
652 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
653 int max_devices;
654
655 instance->physicalDeviceCount = 0;
656
657 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
658
659 if (instance->debug_flags & RADV_DEBUG_STARTUP)
660 radv_logi("Found %d drm nodes", max_devices);
661
662 if (max_devices < 1)
663 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
664
665 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
666 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
667 devices[i]->bustype == DRM_BUS_PCI &&
668 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
669
670 result = radv_physical_device_init(instance->physicalDevices +
671 instance->physicalDeviceCount,
672 instance,
673 devices[i]);
674 if (result == VK_SUCCESS)
675 ++instance->physicalDeviceCount;
676 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
677 break;
678 }
679 }
680 drmFreeDevices(devices, max_devices);
681
682 return result;
683 }
684
685 VkResult radv_EnumeratePhysicalDevices(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceCount,
688 VkPhysicalDevice* pPhysicalDevices)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDevices) {
701 *pPhysicalDeviceCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
705 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
706 }
707
708 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
709 : VK_SUCCESS;
710 }
711
712 VkResult radv_EnumeratePhysicalDeviceGroups(
713 VkInstance _instance,
714 uint32_t* pPhysicalDeviceGroupCount,
715 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
716 {
717 RADV_FROM_HANDLE(radv_instance, instance, _instance);
718 VkResult result;
719
720 if (instance->physicalDeviceCount < 0) {
721 result = radv_enumerate_devices(instance);
722 if (result != VK_SUCCESS &&
723 result != VK_ERROR_INCOMPATIBLE_DRIVER)
724 return result;
725 }
726
727 if (!pPhysicalDeviceGroupProperties) {
728 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
729 } else {
730 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
731 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
732 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
733 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
734 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
735 }
736 }
737 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
738 : VK_SUCCESS;
739 }
740
741 void radv_GetPhysicalDeviceFeatures(
742 VkPhysicalDevice physicalDevice,
743 VkPhysicalDeviceFeatures* pFeatures)
744 {
745 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
746 memset(pFeatures, 0, sizeof(*pFeatures));
747
748 *pFeatures = (VkPhysicalDeviceFeatures) {
749 .robustBufferAccess = true,
750 .fullDrawIndexUint32 = true,
751 .imageCubeArray = true,
752 .independentBlend = true,
753 .geometryShader = true,
754 .tessellationShader = true,
755 .sampleRateShading = true,
756 .dualSrcBlend = true,
757 .logicOp = true,
758 .multiDrawIndirect = true,
759 .drawIndirectFirstInstance = true,
760 .depthClamp = true,
761 .depthBiasClamp = true,
762 .fillModeNonSolid = true,
763 .depthBounds = true,
764 .wideLines = true,
765 .largePoints = true,
766 .alphaToOne = true,
767 .multiViewport = true,
768 .samplerAnisotropy = true,
769 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
770 .textureCompressionASTC_LDR = false,
771 .textureCompressionBC = true,
772 .occlusionQueryPrecise = true,
773 .pipelineStatisticsQuery = true,
774 .vertexPipelineStoresAndAtomics = true,
775 .fragmentStoresAndAtomics = true,
776 .shaderTessellationAndGeometryPointSize = true,
777 .shaderImageGatherExtended = true,
778 .shaderStorageImageExtendedFormats = true,
779 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
780 .shaderUniformBufferArrayDynamicIndexing = true,
781 .shaderSampledImageArrayDynamicIndexing = true,
782 .shaderStorageBufferArrayDynamicIndexing = true,
783 .shaderStorageImageArrayDynamicIndexing = true,
784 .shaderStorageImageReadWithoutFormat = true,
785 .shaderStorageImageWriteWithoutFormat = true,
786 .shaderClipDistance = true,
787 .shaderCullDistance = true,
788 .shaderFloat64 = true,
789 .shaderInt64 = true,
790 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
791 .sparseBinding = true,
792 .variableMultisampleRate = true,
793 .inheritedQueries = true,
794 };
795 }
796
797 void radv_GetPhysicalDeviceFeatures2(
798 VkPhysicalDevice physicalDevice,
799 VkPhysicalDeviceFeatures2 *pFeatures)
800 {
801 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
802 vk_foreach_struct(ext, pFeatures->pNext) {
803 switch (ext->sType) {
804 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
805 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
806 features->variablePointersStorageBuffer = true;
807 features->variablePointers = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
811 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
812 features->multiview = true;
813 features->multiviewGeometryShader = true;
814 features->multiviewTessellationShader = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
818 VkPhysicalDeviceShaderDrawParametersFeatures *features =
819 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
820 features->shaderDrawParameters = true;
821 break;
822 }
823 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
824 VkPhysicalDeviceProtectedMemoryFeatures *features =
825 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
826 features->protectedMemory = false;
827 break;
828 }
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
830 VkPhysicalDevice16BitStorageFeatures *features =
831 (VkPhysicalDevice16BitStorageFeatures*)ext;
832 bool enabled = pdevice->rad_info.chip_class >= GFX8;
833 features->storageBuffer16BitAccess = enabled;
834 features->uniformAndStorageBuffer16BitAccess = enabled;
835 features->storagePushConstant16 = enabled;
836 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
840 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
841 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
842 features->samplerYcbcrConversion = true;
843 break;
844 }
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
846 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
847 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
848 features->shaderInputAttachmentArrayDynamicIndexing = true;
849 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
850 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
851 features->shaderUniformBufferArrayNonUniformIndexing = true;
852 features->shaderSampledImageArrayNonUniformIndexing = true;
853 features->shaderStorageBufferArrayNonUniformIndexing = true;
854 features->shaderStorageImageArrayNonUniformIndexing = true;
855 features->shaderInputAttachmentArrayNonUniformIndexing = true;
856 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
857 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
858 features->descriptorBindingUniformBufferUpdateAfterBind = true;
859 features->descriptorBindingSampledImageUpdateAfterBind = true;
860 features->descriptorBindingStorageImageUpdateAfterBind = true;
861 features->descriptorBindingStorageBufferUpdateAfterBind = true;
862 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
863 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
864 features->descriptorBindingUpdateUnusedWhilePending = true;
865 features->descriptorBindingPartiallyBound = true;
866 features->descriptorBindingVariableDescriptorCount = true;
867 features->runtimeDescriptorArray = true;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
871 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
872 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
873 features->conditionalRendering = true;
874 features->inheritedConditionalRendering = false;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
878 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
879 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
880 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
881 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
885 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
886 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
887 features->transformFeedback = true;
888 features->geometryStreams = true;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
892 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
893 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
894 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
895 break;
896 }
897 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
898 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
899 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
900 features->memoryPriority = VK_TRUE;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
904 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
905 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
906 features->bufferDeviceAddress = true;
907 features->bufferDeviceAddressCaptureReplay = false;
908 features->bufferDeviceAddressMultiDevice = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
912 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
913 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
914 features->depthClipEnable = true;
915 break;
916 }
917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
918 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
919 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
920 features->hostQueryReset = true;
921 break;
922 }
923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
924 VkPhysicalDevice8BitStorageFeaturesKHR *features =
925 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
926 bool enabled = pdevice->rad_info.chip_class >= GFX8;
927 features->storageBuffer8BitAccess = enabled;
928 features->uniformAndStorageBuffer8BitAccess = enabled;
929 features->storagePushConstant8 = enabled;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
933 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
934 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
935 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
936 features->shaderInt8 = true;
937 break;
938 }
939 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
940 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
941 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
942 /* TODO: Enable this once the driver supports 64-bit
943 * compare&swap atomic operations.
944 */
945 features->shaderBufferInt64Atomics = false;
946 features->shaderSharedInt64Atomics = false;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
950 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
951 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
952
953 features->inlineUniformBlock = true;
954 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
958 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
959 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
960 features->computeDerivativeGroupQuads = false;
961 features->computeDerivativeGroupLinear = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
965 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
966 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
967 features->ycbcrImageArrays = true;
968 break;
969 }
970 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
971 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
972 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
973 features->uniformBufferStandardLayout = true;
974 break;
975 }
976 default:
977 break;
978 }
979 }
980 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
981 }
982
983 void radv_GetPhysicalDeviceProperties(
984 VkPhysicalDevice physicalDevice,
985 VkPhysicalDeviceProperties* pProperties)
986 {
987 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
988 VkSampleCountFlags sample_counts = 0xf;
989
990 /* make sure that the entire descriptor set is addressable with a signed
991 * 32-bit int. So the sum of all limits scaled by descriptor size has to
992 * be at most 2 GiB. the combined image & samples object count as one of
993 * both. This limit is for the pipeline layout, not for the set layout, but
994 * there is no set limit, so we just set a pipeline limit. I don't think
995 * any app is going to hit this soon. */
996 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
997 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
998 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
999 32 /* sampler, largest when combined with image */ +
1000 64 /* sampled image */ +
1001 64 /* storage image */);
1002
1003 VkPhysicalDeviceLimits limits = {
1004 .maxImageDimension1D = (1 << 14),
1005 .maxImageDimension2D = (1 << 14),
1006 .maxImageDimension3D = (1 << 11),
1007 .maxImageDimensionCube = (1 << 14),
1008 .maxImageArrayLayers = (1 << 11),
1009 .maxTexelBufferElements = 128 * 1024 * 1024,
1010 .maxUniformBufferRange = UINT32_MAX,
1011 .maxStorageBufferRange = UINT32_MAX,
1012 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1013 .maxMemoryAllocationCount = UINT32_MAX,
1014 .maxSamplerAllocationCount = 64 * 1024,
1015 .bufferImageGranularity = 64, /* A cache line */
1016 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1017 .maxBoundDescriptorSets = MAX_SETS,
1018 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1019 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1020 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1021 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1022 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1023 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1024 .maxPerStageResources = max_descriptor_set_size,
1025 .maxDescriptorSetSamplers = max_descriptor_set_size,
1026 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1027 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1028 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1029 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1030 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1031 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1032 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1033 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1034 .maxVertexInputBindings = MAX_VBS,
1035 .maxVertexInputAttributeOffset = 2047,
1036 .maxVertexInputBindingStride = 2048,
1037 .maxVertexOutputComponents = 128,
1038 .maxTessellationGenerationLevel = 64,
1039 .maxTessellationPatchSize = 32,
1040 .maxTessellationControlPerVertexInputComponents = 128,
1041 .maxTessellationControlPerVertexOutputComponents = 128,
1042 .maxTessellationControlPerPatchOutputComponents = 120,
1043 .maxTessellationControlTotalOutputComponents = 4096,
1044 .maxTessellationEvaluationInputComponents = 128,
1045 .maxTessellationEvaluationOutputComponents = 128,
1046 .maxGeometryShaderInvocations = 127,
1047 .maxGeometryInputComponents = 64,
1048 .maxGeometryOutputComponents = 128,
1049 .maxGeometryOutputVertices = 256,
1050 .maxGeometryTotalOutputComponents = 1024,
1051 .maxFragmentInputComponents = 128,
1052 .maxFragmentOutputAttachments = 8,
1053 .maxFragmentDualSrcAttachments = 1,
1054 .maxFragmentCombinedOutputResources = 8,
1055 .maxComputeSharedMemorySize = 32768,
1056 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1057 .maxComputeWorkGroupInvocations = 2048,
1058 .maxComputeWorkGroupSize = {
1059 2048,
1060 2048,
1061 2048
1062 },
1063 .subPixelPrecisionBits = 8,
1064 .subTexelPrecisionBits = 8,
1065 .mipmapPrecisionBits = 8,
1066 .maxDrawIndexedIndexValue = UINT32_MAX,
1067 .maxDrawIndirectCount = UINT32_MAX,
1068 .maxSamplerLodBias = 16,
1069 .maxSamplerAnisotropy = 16,
1070 .maxViewports = MAX_VIEWPORTS,
1071 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1072 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1073 .viewportSubPixelBits = 8,
1074 .minMemoryMapAlignment = 4096, /* A page */
1075 .minTexelBufferOffsetAlignment = 1,
1076 .minUniformBufferOffsetAlignment = 4,
1077 .minStorageBufferOffsetAlignment = 4,
1078 .minTexelOffset = -32,
1079 .maxTexelOffset = 31,
1080 .minTexelGatherOffset = -32,
1081 .maxTexelGatherOffset = 31,
1082 .minInterpolationOffset = -2,
1083 .maxInterpolationOffset = 2,
1084 .subPixelInterpolationOffsetBits = 8,
1085 .maxFramebufferWidth = (1 << 14),
1086 .maxFramebufferHeight = (1 << 14),
1087 .maxFramebufferLayers = (1 << 10),
1088 .framebufferColorSampleCounts = sample_counts,
1089 .framebufferDepthSampleCounts = sample_counts,
1090 .framebufferStencilSampleCounts = sample_counts,
1091 .framebufferNoAttachmentsSampleCounts = sample_counts,
1092 .maxColorAttachments = MAX_RTS,
1093 .sampledImageColorSampleCounts = sample_counts,
1094 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1095 .sampledImageDepthSampleCounts = sample_counts,
1096 .sampledImageStencilSampleCounts = sample_counts,
1097 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1098 .maxSampleMaskWords = 1,
1099 .timestampComputeAndGraphics = true,
1100 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1101 .maxClipDistances = 8,
1102 .maxCullDistances = 8,
1103 .maxCombinedClipAndCullDistances = 8,
1104 .discreteQueuePriorities = 2,
1105 .pointSizeRange = { 0.0, 8192.0 },
1106 .lineWidthRange = { 0.0, 7.9921875 },
1107 .pointSizeGranularity = (1.0 / 8.0),
1108 .lineWidthGranularity = (1.0 / 128.0),
1109 .strictLines = false, /* FINISHME */
1110 .standardSampleLocations = true,
1111 .optimalBufferCopyOffsetAlignment = 128,
1112 .optimalBufferCopyRowPitchAlignment = 128,
1113 .nonCoherentAtomSize = 64,
1114 };
1115
1116 *pProperties = (VkPhysicalDeviceProperties) {
1117 .apiVersion = radv_physical_device_api_version(pdevice),
1118 .driverVersion = vk_get_driver_version(),
1119 .vendorID = ATI_VENDOR_ID,
1120 .deviceID = pdevice->rad_info.pci_id,
1121 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1122 .limits = limits,
1123 .sparseProperties = {0},
1124 };
1125
1126 strcpy(pProperties->deviceName, pdevice->name);
1127 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1128 }
1129
1130 void radv_GetPhysicalDeviceProperties2(
1131 VkPhysicalDevice physicalDevice,
1132 VkPhysicalDeviceProperties2 *pProperties)
1133 {
1134 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1135 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1136
1137 vk_foreach_struct(ext, pProperties->pNext) {
1138 switch (ext->sType) {
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1140 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1141 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1142 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1146 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1147 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1148 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1149 properties->deviceLUIDValid = false;
1150 break;
1151 }
1152 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1153 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1154 properties->maxMultiviewViewCount = MAX_VIEWS;
1155 properties->maxMultiviewInstanceIndex = INT_MAX;
1156 break;
1157 }
1158 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1159 VkPhysicalDevicePointClippingProperties *properties =
1160 (VkPhysicalDevicePointClippingProperties*)ext;
1161 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1162 break;
1163 }
1164 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1165 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1166 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1167 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1171 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1172 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1173 properties->minImportedHostPointerAlignment = 4096;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1177 VkPhysicalDeviceSubgroupProperties *properties =
1178 (VkPhysicalDeviceSubgroupProperties*)ext;
1179 properties->subgroupSize = 64;
1180 properties->supportedStages = VK_SHADER_STAGE_ALL;
1181 properties->supportedOperations =
1182 VK_SUBGROUP_FEATURE_BASIC_BIT |
1183 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1184 VK_SUBGROUP_FEATURE_QUAD_BIT |
1185 VK_SUBGROUP_FEATURE_VOTE_BIT;
1186 if (pdevice->rad_info.chip_class >= GFX8) {
1187 properties->supportedOperations |=
1188 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1189 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1190 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1191 }
1192 properties->quadOperationsInAllStages = true;
1193 break;
1194 }
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1196 VkPhysicalDeviceMaintenance3Properties *properties =
1197 (VkPhysicalDeviceMaintenance3Properties*)ext;
1198 /* Make sure everything is addressable by a signed 32-bit int, and
1199 * our largest descriptors are 96 bytes. */
1200 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1201 /* Our buffer size fields allow only this much */
1202 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1206 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1207 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1208 /* GFX6-8 only support single channel min/max filter. */
1209 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1210 properties->filterMinmaxSingleComponentFormats = true;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1214 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1215 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1216
1217 /* Shader engines. */
1218 properties->shaderEngineCount =
1219 pdevice->rad_info.max_se;
1220 properties->shaderArraysPerEngineCount =
1221 pdevice->rad_info.max_sh_per_se;
1222 properties->computeUnitsPerShaderArray =
1223 pdevice->rad_info.num_good_cu_per_sh;
1224 properties->simdPerComputeUnit = 4;
1225 properties->wavefrontsPerSimd =
1226 pdevice->rad_info.family == CHIP_TONGA ||
1227 pdevice->rad_info.family == CHIP_ICELAND ||
1228 pdevice->rad_info.family == CHIP_POLARIS10 ||
1229 pdevice->rad_info.family == CHIP_POLARIS11 ||
1230 pdevice->rad_info.family == CHIP_POLARIS12 ||
1231 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1232 properties->wavefrontSize = 64;
1233
1234 /* SGPR. */
1235 properties->sgprsPerSimd =
1236 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1237 properties->minSgprAllocation =
1238 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1239 properties->maxSgprAllocation =
1240 pdevice->rad_info.family == CHIP_TONGA ||
1241 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1242 properties->sgprAllocationGranularity =
1243 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1244
1245 /* VGPR. */
1246 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1247 properties->minVgprAllocation = 4;
1248 properties->maxVgprAllocation = 256;
1249 properties->vgprAllocationGranularity = 4;
1250 break;
1251 }
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1253 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1254 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1255 properties->maxVertexAttribDivisor = UINT32_MAX;
1256 break;
1257 }
1258 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1259 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1260 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1261 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1262 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1263 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1264 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1265 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1266 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1267 properties->robustBufferAccessUpdateAfterBind = false;
1268 properties->quadDivergentImplicitLod = false;
1269
1270 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1271 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1272 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1273 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1274 32 /* sampler, largest when combined with image */ +
1275 64 /* sampled image */ +
1276 64 /* storage image */);
1277 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1278 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1279 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1280 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1281 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1282 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1283 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1284 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1285 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1286 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1287 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1288 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1289 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1290 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1292 break;
1293 }
1294 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1295 VkPhysicalDeviceProtectedMemoryProperties *properties =
1296 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1297 properties->protectedNoFault = false;
1298 break;
1299 }
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1301 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1302 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1303 properties->primitiveOverestimationSize = 0;
1304 properties->maxExtraPrimitiveOverestimationSize = 0;
1305 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1306 properties->primitiveUnderestimation = VK_FALSE;
1307 properties->conservativePointAndLineRasterization = VK_FALSE;
1308 properties->degenerateTrianglesRasterized = VK_FALSE;
1309 properties->degenerateLinesRasterized = VK_FALSE;
1310 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1311 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1312 break;
1313 }
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1315 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1316 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1317 properties->pciDomain = pdevice->bus_info.domain;
1318 properties->pciBus = pdevice->bus_info.bus;
1319 properties->pciDevice = pdevice->bus_info.dev;
1320 properties->pciFunction = pdevice->bus_info.func;
1321 break;
1322 }
1323 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1324 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1325 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1326
1327 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1328 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1329 strcpy(driver_props->driverName, "radv");
1330
1331 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1332 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1333 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1334 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1335
1336 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1337 .major = 1,
1338 .minor = 1,
1339 .subminor = 2,
1340 .patch = 0,
1341 };
1342 break;
1343 }
1344 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1345 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1346 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1347 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1348 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1349 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1350 properties->maxTransformFeedbackStreamDataSize = 512;
1351 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1352 properties->maxTransformFeedbackBufferDataStride = 512;
1353 properties->transformFeedbackQueries = true;
1354 properties->transformFeedbackStreamsLinesTriangles = false;
1355 properties->transformFeedbackRasterizationStreamSelect = false;
1356 properties->transformFeedbackDraw = true;
1357 break;
1358 }
1359 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1360 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1361 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1362
1363 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1364 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1365 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1366 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1367 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1368 break;
1369 }
1370 default:
1371 break;
1372 }
1373 }
1374 }
1375
1376 static void radv_get_physical_device_queue_family_properties(
1377 struct radv_physical_device* pdevice,
1378 uint32_t* pCount,
1379 VkQueueFamilyProperties** pQueueFamilyProperties)
1380 {
1381 int num_queue_families = 1;
1382 int idx;
1383 if (pdevice->rad_info.num_compute_rings > 0 &&
1384 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1385 num_queue_families++;
1386
1387 if (pQueueFamilyProperties == NULL) {
1388 *pCount = num_queue_families;
1389 return;
1390 }
1391
1392 if (!*pCount)
1393 return;
1394
1395 idx = 0;
1396 if (*pCount >= 1) {
1397 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1398 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1399 VK_QUEUE_COMPUTE_BIT |
1400 VK_QUEUE_TRANSFER_BIT |
1401 VK_QUEUE_SPARSE_BINDING_BIT,
1402 .queueCount = 1,
1403 .timestampValidBits = 64,
1404 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1405 };
1406 idx++;
1407 }
1408
1409 if (pdevice->rad_info.num_compute_rings > 0 &&
1410 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1411 if (*pCount > idx) {
1412 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1413 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1414 VK_QUEUE_TRANSFER_BIT |
1415 VK_QUEUE_SPARSE_BINDING_BIT,
1416 .queueCount = pdevice->rad_info.num_compute_rings,
1417 .timestampValidBits = 64,
1418 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1419 };
1420 idx++;
1421 }
1422 }
1423 *pCount = idx;
1424 }
1425
1426 void radv_GetPhysicalDeviceQueueFamilyProperties(
1427 VkPhysicalDevice physicalDevice,
1428 uint32_t* pCount,
1429 VkQueueFamilyProperties* pQueueFamilyProperties)
1430 {
1431 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1432 if (!pQueueFamilyProperties) {
1433 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1434 return;
1435 }
1436 VkQueueFamilyProperties *properties[] = {
1437 pQueueFamilyProperties + 0,
1438 pQueueFamilyProperties + 1,
1439 pQueueFamilyProperties + 2,
1440 };
1441 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1442 assert(*pCount <= 3);
1443 }
1444
1445 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1446 VkPhysicalDevice physicalDevice,
1447 uint32_t* pCount,
1448 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1449 {
1450 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1451 if (!pQueueFamilyProperties) {
1452 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1453 return;
1454 }
1455 VkQueueFamilyProperties *properties[] = {
1456 &pQueueFamilyProperties[0].queueFamilyProperties,
1457 &pQueueFamilyProperties[1].queueFamilyProperties,
1458 &pQueueFamilyProperties[2].queueFamilyProperties,
1459 };
1460 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1461 assert(*pCount <= 3);
1462 }
1463
1464 void radv_GetPhysicalDeviceMemoryProperties(
1465 VkPhysicalDevice physicalDevice,
1466 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1467 {
1468 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1469
1470 *pMemoryProperties = physical_device->memory_properties;
1471 }
1472
1473 static void
1474 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1475 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1476 {
1477 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1478 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1479 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1480 uint64_t vram_size = radv_get_vram_size(device);
1481 uint64_t gtt_size = device->rad_info.gart_size;
1482 uint64_t heap_budget, heap_usage;
1483
1484 /* For all memory heaps, the computation of budget is as follow:
1485 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1486 *
1487 * The Vulkan spec 1.1.97 says that the budget should include any
1488 * currently allocated device memory.
1489 *
1490 * Note that the application heap usages are not really accurate (eg.
1491 * in presence of shared buffers).
1492 */
1493 if (vram_size) {
1494 heap_usage = device->ws->query_value(device->ws,
1495 RADEON_ALLOCATED_VRAM);
1496
1497 heap_budget = vram_size -
1498 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1499 heap_usage;
1500
1501 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1502 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1503 }
1504
1505 if (visible_vram_size) {
1506 heap_usage = device->ws->query_value(device->ws,
1507 RADEON_ALLOCATED_VRAM_VIS);
1508
1509 heap_budget = visible_vram_size -
1510 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1511 heap_usage;
1512
1513 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1514 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1515 }
1516
1517 if (gtt_size) {
1518 heap_usage = device->ws->query_value(device->ws,
1519 RADEON_ALLOCATED_GTT);
1520
1521 heap_budget = gtt_size -
1522 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1523 heap_usage;
1524
1525 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1526 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1527 }
1528
1529 /* The heapBudget and heapUsage values must be zero for array elements
1530 * greater than or equal to
1531 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1532 */
1533 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1534 memoryBudget->heapBudget[i] = 0;
1535 memoryBudget->heapUsage[i] = 0;
1536 }
1537 }
1538
1539 void radv_GetPhysicalDeviceMemoryProperties2(
1540 VkPhysicalDevice physicalDevice,
1541 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1542 {
1543 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1544 &pMemoryProperties->memoryProperties);
1545
1546 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1547 vk_find_struct(pMemoryProperties->pNext,
1548 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1549 if (memory_budget)
1550 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1551 }
1552
1553 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1554 VkDevice _device,
1555 VkExternalMemoryHandleTypeFlagBits handleType,
1556 const void *pHostPointer,
1557 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1558 {
1559 RADV_FROM_HANDLE(radv_device, device, _device);
1560
1561 switch (handleType)
1562 {
1563 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1564 const struct radv_physical_device *physical_device = device->physical_device;
1565 uint32_t memoryTypeBits = 0;
1566 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1567 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1568 memoryTypeBits = (1 << i);
1569 break;
1570 }
1571 }
1572 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1573 return VK_SUCCESS;
1574 }
1575 default:
1576 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1577 }
1578 }
1579
1580 static enum radeon_ctx_priority
1581 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1582 {
1583 /* Default to MEDIUM when a specific global priority isn't requested */
1584 if (!pObj)
1585 return RADEON_CTX_PRIORITY_MEDIUM;
1586
1587 switch(pObj->globalPriority) {
1588 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1589 return RADEON_CTX_PRIORITY_REALTIME;
1590 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1591 return RADEON_CTX_PRIORITY_HIGH;
1592 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1593 return RADEON_CTX_PRIORITY_MEDIUM;
1594 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1595 return RADEON_CTX_PRIORITY_LOW;
1596 default:
1597 unreachable("Illegal global priority value");
1598 return RADEON_CTX_PRIORITY_INVALID;
1599 }
1600 }
1601
1602 static int
1603 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1604 uint32_t queue_family_index, int idx,
1605 VkDeviceQueueCreateFlags flags,
1606 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1607 {
1608 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1609 queue->device = device;
1610 queue->queue_family_index = queue_family_index;
1611 queue->queue_idx = idx;
1612 queue->priority = radv_get_queue_global_priority(global_priority);
1613 queue->flags = flags;
1614
1615 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1616 if (!queue->hw_ctx)
1617 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1618
1619 return VK_SUCCESS;
1620 }
1621
1622 static void
1623 radv_queue_finish(struct radv_queue *queue)
1624 {
1625 if (queue->hw_ctx)
1626 queue->device->ws->ctx_destroy(queue->hw_ctx);
1627
1628 if (queue->initial_full_flush_preamble_cs)
1629 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1630 if (queue->initial_preamble_cs)
1631 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1632 if (queue->continue_preamble_cs)
1633 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1634 if (queue->descriptor_bo)
1635 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1636 if (queue->scratch_bo)
1637 queue->device->ws->buffer_destroy(queue->scratch_bo);
1638 if (queue->esgs_ring_bo)
1639 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1640 if (queue->gsvs_ring_bo)
1641 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1642 if (queue->tess_rings_bo)
1643 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1644 if (queue->compute_scratch_bo)
1645 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1646 }
1647
1648 static void
1649 radv_bo_list_init(struct radv_bo_list *bo_list)
1650 {
1651 pthread_mutex_init(&bo_list->mutex, NULL);
1652 bo_list->list.count = bo_list->capacity = 0;
1653 bo_list->list.bos = NULL;
1654 }
1655
1656 static void
1657 radv_bo_list_finish(struct radv_bo_list *bo_list)
1658 {
1659 free(bo_list->list.bos);
1660 pthread_mutex_destroy(&bo_list->mutex);
1661 }
1662
1663 static VkResult radv_bo_list_add(struct radv_device *device,
1664 struct radeon_winsys_bo *bo)
1665 {
1666 struct radv_bo_list *bo_list = &device->bo_list;
1667
1668 if (bo->is_local)
1669 return VK_SUCCESS;
1670
1671 if (unlikely(!device->use_global_bo_list))
1672 return VK_SUCCESS;
1673
1674 pthread_mutex_lock(&bo_list->mutex);
1675 if (bo_list->list.count == bo_list->capacity) {
1676 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1677 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1678
1679 if (!data) {
1680 pthread_mutex_unlock(&bo_list->mutex);
1681 return VK_ERROR_OUT_OF_HOST_MEMORY;
1682 }
1683
1684 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1685 bo_list->capacity = capacity;
1686 }
1687
1688 bo_list->list.bos[bo_list->list.count++] = bo;
1689 pthread_mutex_unlock(&bo_list->mutex);
1690 return VK_SUCCESS;
1691 }
1692
1693 static void radv_bo_list_remove(struct radv_device *device,
1694 struct radeon_winsys_bo *bo)
1695 {
1696 struct radv_bo_list *bo_list = &device->bo_list;
1697
1698 if (bo->is_local)
1699 return;
1700
1701 if (unlikely(!device->use_global_bo_list))
1702 return;
1703
1704 pthread_mutex_lock(&bo_list->mutex);
1705 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1706 if (bo_list->list.bos[i] == bo) {
1707 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1708 --bo_list->list.count;
1709 break;
1710 }
1711 }
1712 pthread_mutex_unlock(&bo_list->mutex);
1713 }
1714
1715 static void
1716 radv_device_init_gs_info(struct radv_device *device)
1717 {
1718 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1719 device->physical_device->rad_info.family);
1720 }
1721
1722 static int radv_get_device_extension_index(const char *name)
1723 {
1724 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1725 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1726 return i;
1727 }
1728 return -1;
1729 }
1730
1731 static int
1732 radv_get_int_debug_option(const char *name, int default_value)
1733 {
1734 const char *str;
1735 int result;
1736
1737 str = getenv(name);
1738 if (!str) {
1739 result = default_value;
1740 } else {
1741 char *endptr;
1742
1743 result = strtol(str, &endptr, 0);
1744 if (str == endptr) {
1745 /* No digits founs. */
1746 result = default_value;
1747 }
1748 }
1749
1750 return result;
1751 }
1752
1753 VkResult radv_CreateDevice(
1754 VkPhysicalDevice physicalDevice,
1755 const VkDeviceCreateInfo* pCreateInfo,
1756 const VkAllocationCallbacks* pAllocator,
1757 VkDevice* pDevice)
1758 {
1759 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1760 VkResult result;
1761 struct radv_device *device;
1762
1763 bool keep_shader_info = false;
1764
1765 /* Check enabled features */
1766 if (pCreateInfo->pEnabledFeatures) {
1767 VkPhysicalDeviceFeatures supported_features;
1768 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1769 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1770 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1771 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1772 for (uint32_t i = 0; i < num_features; i++) {
1773 if (enabled_feature[i] && !supported_feature[i])
1774 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1775 }
1776 }
1777
1778 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1779 sizeof(*device), 8,
1780 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1781 if (!device)
1782 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1783
1784 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1785 device->instance = physical_device->instance;
1786 device->physical_device = physical_device;
1787
1788 device->ws = physical_device->ws;
1789 if (pAllocator)
1790 device->alloc = *pAllocator;
1791 else
1792 device->alloc = physical_device->instance->alloc;
1793
1794 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1795 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1796 int index = radv_get_device_extension_index(ext_name);
1797 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1798 vk_free(&device->alloc, device);
1799 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1800 }
1801
1802 device->enabled_extensions.extensions[index] = true;
1803 }
1804
1805 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1806
1807 /* With update after bind we can't attach bo's to the command buffer
1808 * from the descriptor set anymore, so we have to use a global BO list.
1809 */
1810 device->use_global_bo_list =
1811 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1812 device->enabled_extensions.EXT_descriptor_indexing ||
1813 device->enabled_extensions.EXT_buffer_device_address;
1814
1815 mtx_init(&device->shader_slab_mutex, mtx_plain);
1816 list_inithead(&device->shader_slabs);
1817
1818 radv_bo_list_init(&device->bo_list);
1819
1820 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1821 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1822 uint32_t qfi = queue_create->queueFamilyIndex;
1823 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1824 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1825
1826 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1827
1828 device->queues[qfi] = vk_alloc(&device->alloc,
1829 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1830 if (!device->queues[qfi]) {
1831 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1832 goto fail;
1833 }
1834
1835 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1836
1837 device->queue_count[qfi] = queue_create->queueCount;
1838
1839 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1840 result = radv_queue_init(device, &device->queues[qfi][q],
1841 qfi, q, queue_create->flags,
1842 global_priority);
1843 if (result != VK_SUCCESS)
1844 goto fail;
1845 }
1846 }
1847
1848 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1849 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1850
1851 /* Disabled and not implemented for now. */
1852 device->dfsm_allowed = device->pbb_allowed &&
1853 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1854 device->physical_device->rad_info.family == CHIP_RAVEN2);
1855
1856 #ifdef ANDROID
1857 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1858 #endif
1859
1860 /* The maximum number of scratch waves. Scratch space isn't divided
1861 * evenly between CUs. The number is only a function of the number of CUs.
1862 * We can decrease the constant to decrease the scratch buffer size.
1863 *
1864 * sctx->scratch_waves must be >= the maximum possible size of
1865 * 1 threadgroup, so that the hw doesn't hang from being unable
1866 * to start any.
1867 *
1868 * The recommended value is 4 per CU at most. Higher numbers don't
1869 * bring much benefit, but they still occupy chip resources (think
1870 * async compute). I've seen ~2% performance difference between 4 and 32.
1871 */
1872 uint32_t max_threads_per_block = 2048;
1873 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1874 max_threads_per_block / 64);
1875
1876 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1877
1878 if (device->physical_device->rad_info.chip_class >= GFX7) {
1879 /* If the KMD allows it (there is a KMD hw register for it),
1880 * allow launching waves out-of-order.
1881 */
1882 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1883 }
1884
1885 radv_device_init_gs_info(device);
1886
1887 device->tess_offchip_block_dw_size =
1888 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1889 device->has_distributed_tess =
1890 device->physical_device->rad_info.chip_class >= GFX8 &&
1891 device->physical_device->rad_info.max_se >= 2;
1892
1893 if (getenv("RADV_TRACE_FILE")) {
1894 const char *filename = getenv("RADV_TRACE_FILE");
1895
1896 keep_shader_info = true;
1897
1898 if (!radv_init_trace(device))
1899 goto fail;
1900
1901 fprintf(stderr, "*****************************************************************************\n");
1902 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1903 fprintf(stderr, "*****************************************************************************\n");
1904
1905 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1906 radv_dump_enabled_options(device, stderr);
1907 }
1908
1909 device->keep_shader_info = keep_shader_info;
1910
1911 result = radv_device_init_meta(device);
1912 if (result != VK_SUCCESS)
1913 goto fail;
1914
1915 radv_device_init_msaa(device);
1916
1917 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1918 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1919 switch (family) {
1920 case RADV_QUEUE_GENERAL:
1921 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1922 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1923 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1924 break;
1925 case RADV_QUEUE_COMPUTE:
1926 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1927 radeon_emit(device->empty_cs[family], 0);
1928 break;
1929 }
1930 device->ws->cs_finalize(device->empty_cs[family]);
1931 }
1932
1933 if (device->physical_device->rad_info.chip_class >= GFX7)
1934 cik_create_gfx_config(device);
1935
1936 VkPipelineCacheCreateInfo ci;
1937 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1938 ci.pNext = NULL;
1939 ci.flags = 0;
1940 ci.pInitialData = NULL;
1941 ci.initialDataSize = 0;
1942 VkPipelineCache pc;
1943 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1944 &ci, NULL, &pc);
1945 if (result != VK_SUCCESS)
1946 goto fail_meta;
1947
1948 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1949
1950 device->force_aniso =
1951 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1952 if (device->force_aniso >= 0) {
1953 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1954 1 << util_logbase2(device->force_aniso));
1955 }
1956
1957 *pDevice = radv_device_to_handle(device);
1958 return VK_SUCCESS;
1959
1960 fail_meta:
1961 radv_device_finish_meta(device);
1962 fail:
1963 radv_bo_list_finish(&device->bo_list);
1964
1965 if (device->trace_bo)
1966 device->ws->buffer_destroy(device->trace_bo);
1967
1968 if (device->gfx_init)
1969 device->ws->buffer_destroy(device->gfx_init);
1970
1971 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1972 for (unsigned q = 0; q < device->queue_count[i]; q++)
1973 radv_queue_finish(&device->queues[i][q]);
1974 if (device->queue_count[i])
1975 vk_free(&device->alloc, device->queues[i]);
1976 }
1977
1978 vk_free(&device->alloc, device);
1979 return result;
1980 }
1981
1982 void radv_DestroyDevice(
1983 VkDevice _device,
1984 const VkAllocationCallbacks* pAllocator)
1985 {
1986 RADV_FROM_HANDLE(radv_device, device, _device);
1987
1988 if (!device)
1989 return;
1990
1991 if (device->trace_bo)
1992 device->ws->buffer_destroy(device->trace_bo);
1993
1994 if (device->gfx_init)
1995 device->ws->buffer_destroy(device->gfx_init);
1996
1997 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1998 for (unsigned q = 0; q < device->queue_count[i]; q++)
1999 radv_queue_finish(&device->queues[i][q]);
2000 if (device->queue_count[i])
2001 vk_free(&device->alloc, device->queues[i]);
2002 if (device->empty_cs[i])
2003 device->ws->cs_destroy(device->empty_cs[i]);
2004 }
2005 radv_device_finish_meta(device);
2006
2007 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2008 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2009
2010 radv_destroy_shader_slabs(device);
2011
2012 radv_bo_list_finish(&device->bo_list);
2013 vk_free(&device->alloc, device);
2014 }
2015
2016 VkResult radv_EnumerateInstanceLayerProperties(
2017 uint32_t* pPropertyCount,
2018 VkLayerProperties* pProperties)
2019 {
2020 if (pProperties == NULL) {
2021 *pPropertyCount = 0;
2022 return VK_SUCCESS;
2023 }
2024
2025 /* None supported at this time */
2026 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2027 }
2028
2029 VkResult radv_EnumerateDeviceLayerProperties(
2030 VkPhysicalDevice physicalDevice,
2031 uint32_t* pPropertyCount,
2032 VkLayerProperties* pProperties)
2033 {
2034 if (pProperties == NULL) {
2035 *pPropertyCount = 0;
2036 return VK_SUCCESS;
2037 }
2038
2039 /* None supported at this time */
2040 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2041 }
2042
2043 void radv_GetDeviceQueue2(
2044 VkDevice _device,
2045 const VkDeviceQueueInfo2* pQueueInfo,
2046 VkQueue* pQueue)
2047 {
2048 RADV_FROM_HANDLE(radv_device, device, _device);
2049 struct radv_queue *queue;
2050
2051 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2052 if (pQueueInfo->flags != queue->flags) {
2053 /* From the Vulkan 1.1.70 spec:
2054 *
2055 * "The queue returned by vkGetDeviceQueue2 must have the same
2056 * flags value from this structure as that used at device
2057 * creation time in a VkDeviceQueueCreateInfo instance. If no
2058 * matching flags were specified at device creation time then
2059 * pQueue will return VK_NULL_HANDLE."
2060 */
2061 *pQueue = VK_NULL_HANDLE;
2062 return;
2063 }
2064
2065 *pQueue = radv_queue_to_handle(queue);
2066 }
2067
2068 void radv_GetDeviceQueue(
2069 VkDevice _device,
2070 uint32_t queueFamilyIndex,
2071 uint32_t queueIndex,
2072 VkQueue* pQueue)
2073 {
2074 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2075 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2076 .queueFamilyIndex = queueFamilyIndex,
2077 .queueIndex = queueIndex
2078 };
2079
2080 radv_GetDeviceQueue2(_device, &info, pQueue);
2081 }
2082
2083 static void
2084 fill_geom_tess_rings(struct radv_queue *queue,
2085 uint32_t *map,
2086 bool add_sample_positions,
2087 uint32_t esgs_ring_size,
2088 struct radeon_winsys_bo *esgs_ring_bo,
2089 uint32_t gsvs_ring_size,
2090 struct radeon_winsys_bo *gsvs_ring_bo,
2091 uint32_t tess_factor_ring_size,
2092 uint32_t tess_offchip_ring_offset,
2093 uint32_t tess_offchip_ring_size,
2094 struct radeon_winsys_bo *tess_rings_bo)
2095 {
2096 uint32_t *desc = &map[4];
2097
2098 if (esgs_ring_bo) {
2099 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2100
2101 /* stride 0, num records - size, add tid, swizzle, elsize4,
2102 index stride 64 */
2103 desc[0] = esgs_va;
2104 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2105 S_008F04_STRIDE(0) |
2106 S_008F04_SWIZZLE_ENABLE(true);
2107 desc[2] = esgs_ring_size;
2108 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2109 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2110 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2111 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2112 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2113 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2114 S_008F0C_ELEMENT_SIZE(1) |
2115 S_008F0C_INDEX_STRIDE(3) |
2116 S_008F0C_ADD_TID_ENABLE(true);
2117
2118 /* GS entry for ES->GS ring */
2119 /* stride 0, num records - size, elsize0,
2120 index stride 0 */
2121 desc[4] = esgs_va;
2122 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2123 S_008F04_STRIDE(0) |
2124 S_008F04_SWIZZLE_ENABLE(false);
2125 desc[6] = esgs_ring_size;
2126 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2127 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2128 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2129 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2130 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2131 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2132 S_008F0C_ELEMENT_SIZE(0) |
2133 S_008F0C_INDEX_STRIDE(0) |
2134 S_008F0C_ADD_TID_ENABLE(false);
2135 }
2136
2137 desc += 8;
2138
2139 if (gsvs_ring_bo) {
2140 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2141
2142 /* VS entry for GS->VS ring */
2143 /* stride 0, num records - size, elsize0,
2144 index stride 0 */
2145 desc[0] = gsvs_va;
2146 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2147 S_008F04_STRIDE(0) |
2148 S_008F04_SWIZZLE_ENABLE(false);
2149 desc[2] = gsvs_ring_size;
2150 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2151 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2152 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2153 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2154 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2155 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2156 S_008F0C_ELEMENT_SIZE(0) |
2157 S_008F0C_INDEX_STRIDE(0) |
2158 S_008F0C_ADD_TID_ENABLE(false);
2159
2160 /* stride gsvs_itemsize, num records 64
2161 elsize 4, index stride 16 */
2162 /* shader will patch stride and desc[2] */
2163 desc[4] = gsvs_va;
2164 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2165 S_008F04_STRIDE(0) |
2166 S_008F04_SWIZZLE_ENABLE(true);
2167 desc[6] = 0;
2168 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2169 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2170 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2171 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2172 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2173 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2174 S_008F0C_ELEMENT_SIZE(1) |
2175 S_008F0C_INDEX_STRIDE(1) |
2176 S_008F0C_ADD_TID_ENABLE(true);
2177 }
2178
2179 desc += 8;
2180
2181 if (tess_rings_bo) {
2182 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2183 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2184
2185 desc[0] = tess_va;
2186 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2187 S_008F04_STRIDE(0) |
2188 S_008F04_SWIZZLE_ENABLE(false);
2189 desc[2] = tess_factor_ring_size;
2190 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2191 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2192 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2193 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2194 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2196 S_008F0C_ELEMENT_SIZE(0) |
2197 S_008F0C_INDEX_STRIDE(0) |
2198 S_008F0C_ADD_TID_ENABLE(false);
2199
2200 desc[4] = tess_offchip_va;
2201 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2202 S_008F04_STRIDE(0) |
2203 S_008F04_SWIZZLE_ENABLE(false);
2204 desc[6] = tess_offchip_ring_size;
2205 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2206 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2207 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2208 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2209 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2210 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2211 S_008F0C_ELEMENT_SIZE(0) |
2212 S_008F0C_INDEX_STRIDE(0) |
2213 S_008F0C_ADD_TID_ENABLE(false);
2214 }
2215
2216 desc += 8;
2217
2218 if (add_sample_positions) {
2219 /* add sample positions after all rings */
2220 memcpy(desc, queue->device->sample_locations_1x, 8);
2221 desc += 2;
2222 memcpy(desc, queue->device->sample_locations_2x, 16);
2223 desc += 4;
2224 memcpy(desc, queue->device->sample_locations_4x, 32);
2225 desc += 8;
2226 memcpy(desc, queue->device->sample_locations_8x, 64);
2227 }
2228 }
2229
2230 static unsigned
2231 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2232 {
2233 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2234 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2235 device->physical_device->rad_info.family != CHIP_STONEY;
2236 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2237 unsigned max_offchip_buffers;
2238 unsigned offchip_granularity;
2239 unsigned hs_offchip_param;
2240
2241 /*
2242 * Per RadeonSI:
2243 * This must be one less than the maximum number due to a hw limitation.
2244 * Various hardware bugs need thGFX7
2245 *
2246 * Per AMDVLK:
2247 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2248 * Gfx7 should limit max_offchip_buffers to 508
2249 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2250 *
2251 * Follow AMDVLK here.
2252 */
2253 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2254 device->physical_device->rad_info.chip_class == GFX7 ||
2255 device->physical_device->rad_info.chip_class == GFX6)
2256 --max_offchip_buffers_per_se;
2257
2258 max_offchip_buffers = max_offchip_buffers_per_se *
2259 device->physical_device->rad_info.max_se;
2260
2261 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2262 * around by setting 4K granularity.
2263 */
2264 if (device->tess_offchip_block_dw_size == 4096) {
2265 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2266 offchip_granularity = V_03093C_X_4K_DWORDS;
2267 } else {
2268 assert(device->tess_offchip_block_dw_size == 8192);
2269 offchip_granularity = V_03093C_X_8K_DWORDS;
2270 }
2271
2272 switch (device->physical_device->rad_info.chip_class) {
2273 case GFX6:
2274 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2275 break;
2276 case GFX7:
2277 case GFX8:
2278 case GFX9:
2279 default:
2280 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2281 break;
2282 }
2283
2284 *max_offchip_buffers_p = max_offchip_buffers;
2285 if (device->physical_device->rad_info.chip_class >= GFX7) {
2286 if (device->physical_device->rad_info.chip_class >= GFX8)
2287 --max_offchip_buffers;
2288 hs_offchip_param =
2289 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2290 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2291 } else {
2292 hs_offchip_param =
2293 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2294 }
2295 return hs_offchip_param;
2296 }
2297
2298 static void
2299 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2300 struct radeon_winsys_bo *esgs_ring_bo,
2301 uint32_t esgs_ring_size,
2302 struct radeon_winsys_bo *gsvs_ring_bo,
2303 uint32_t gsvs_ring_size)
2304 {
2305 if (!esgs_ring_bo && !gsvs_ring_bo)
2306 return;
2307
2308 if (esgs_ring_bo)
2309 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2310
2311 if (gsvs_ring_bo)
2312 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2313
2314 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2315 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2316 radeon_emit(cs, esgs_ring_size >> 8);
2317 radeon_emit(cs, gsvs_ring_size >> 8);
2318 } else {
2319 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2320 radeon_emit(cs, esgs_ring_size >> 8);
2321 radeon_emit(cs, gsvs_ring_size >> 8);
2322 }
2323 }
2324
2325 static void
2326 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2327 unsigned hs_offchip_param, unsigned tf_ring_size,
2328 struct radeon_winsys_bo *tess_rings_bo)
2329 {
2330 uint64_t tf_va;
2331
2332 if (!tess_rings_bo)
2333 return;
2334
2335 tf_va = radv_buffer_get_va(tess_rings_bo);
2336
2337 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2338
2339 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2340 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2341 S_030938_SIZE(tf_ring_size / 4));
2342 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2343 tf_va >> 8);
2344 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2345 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2346 S_030944_BASE_HI(tf_va >> 40));
2347 }
2348 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2349 hs_offchip_param);
2350 } else {
2351 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2352 S_008988_SIZE(tf_ring_size / 4));
2353 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2354 tf_va >> 8);
2355 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2356 hs_offchip_param);
2357 }
2358 }
2359
2360 static void
2361 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2362 struct radeon_winsys_bo *compute_scratch_bo)
2363 {
2364 uint64_t scratch_va;
2365
2366 if (!compute_scratch_bo)
2367 return;
2368
2369 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2370
2371 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2372
2373 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2374 radeon_emit(cs, scratch_va);
2375 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2376 S_008F04_SWIZZLE_ENABLE(1));
2377 }
2378
2379 static void
2380 radv_emit_global_shader_pointers(struct radv_queue *queue,
2381 struct radeon_cmdbuf *cs,
2382 struct radeon_winsys_bo *descriptor_bo)
2383 {
2384 uint64_t va;
2385
2386 if (!descriptor_bo)
2387 return;
2388
2389 va = radv_buffer_get_va(descriptor_bo);
2390
2391 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2392
2393 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2394 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2395 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2396 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2397 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2398
2399 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2400 radv_emit_shader_pointer(queue->device, cs, regs[i],
2401 va, true);
2402 }
2403 } else {
2404 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2405 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2406 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2407 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2408 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2409 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2410
2411 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2412 radv_emit_shader_pointer(queue->device, cs, regs[i],
2413 va, true);
2414 }
2415 }
2416 }
2417
2418 static void
2419 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2420 {
2421 struct radv_device *device = queue->device;
2422
2423 if (device->gfx_init) {
2424 uint64_t va = radv_buffer_get_va(device->gfx_init);
2425
2426 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2427 radeon_emit(cs, va);
2428 radeon_emit(cs, va >> 32);
2429 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2430
2431 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2432 } else {
2433 struct radv_physical_device *physical_device = device->physical_device;
2434 si_emit_graphics(physical_device, cs);
2435 }
2436 }
2437
2438 static void
2439 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2440 {
2441 struct radv_physical_device *physical_device = queue->device->physical_device;
2442 si_emit_compute(physical_device, cs);
2443 }
2444
2445 static VkResult
2446 radv_get_preamble_cs(struct radv_queue *queue,
2447 uint32_t scratch_size,
2448 uint32_t compute_scratch_size,
2449 uint32_t esgs_ring_size,
2450 uint32_t gsvs_ring_size,
2451 bool needs_tess_rings,
2452 bool needs_sample_positions,
2453 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2454 struct radeon_cmdbuf **initial_preamble_cs,
2455 struct radeon_cmdbuf **continue_preamble_cs)
2456 {
2457 struct radeon_winsys_bo *scratch_bo = NULL;
2458 struct radeon_winsys_bo *descriptor_bo = NULL;
2459 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2460 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2461 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2462 struct radeon_winsys_bo *tess_rings_bo = NULL;
2463 struct radeon_cmdbuf *dest_cs[3] = {0};
2464 bool add_tess_rings = false, add_sample_positions = false;
2465 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2466 unsigned max_offchip_buffers;
2467 unsigned hs_offchip_param = 0;
2468 unsigned tess_offchip_ring_offset;
2469 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2470 if (!queue->has_tess_rings) {
2471 if (needs_tess_rings)
2472 add_tess_rings = true;
2473 }
2474 if (!queue->has_sample_positions) {
2475 if (needs_sample_positions)
2476 add_sample_positions = true;
2477 }
2478 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2479 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2480 &max_offchip_buffers);
2481 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2482 tess_offchip_ring_size = max_offchip_buffers *
2483 queue->device->tess_offchip_block_dw_size * 4;
2484
2485 if (scratch_size <= queue->scratch_size &&
2486 compute_scratch_size <= queue->compute_scratch_size &&
2487 esgs_ring_size <= queue->esgs_ring_size &&
2488 gsvs_ring_size <= queue->gsvs_ring_size &&
2489 !add_tess_rings && !add_sample_positions &&
2490 queue->initial_preamble_cs) {
2491 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2492 *initial_preamble_cs = queue->initial_preamble_cs;
2493 *continue_preamble_cs = queue->continue_preamble_cs;
2494 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2495 *continue_preamble_cs = NULL;
2496 return VK_SUCCESS;
2497 }
2498
2499 if (scratch_size > queue->scratch_size) {
2500 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2501 scratch_size,
2502 4096,
2503 RADEON_DOMAIN_VRAM,
2504 ring_bo_flags,
2505 RADV_BO_PRIORITY_SCRATCH);
2506 if (!scratch_bo)
2507 goto fail;
2508 } else
2509 scratch_bo = queue->scratch_bo;
2510
2511 if (compute_scratch_size > queue->compute_scratch_size) {
2512 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2513 compute_scratch_size,
2514 4096,
2515 RADEON_DOMAIN_VRAM,
2516 ring_bo_flags,
2517 RADV_BO_PRIORITY_SCRATCH);
2518 if (!compute_scratch_bo)
2519 goto fail;
2520
2521 } else
2522 compute_scratch_bo = queue->compute_scratch_bo;
2523
2524 if (esgs_ring_size > queue->esgs_ring_size) {
2525 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2526 esgs_ring_size,
2527 4096,
2528 RADEON_DOMAIN_VRAM,
2529 ring_bo_flags,
2530 RADV_BO_PRIORITY_SCRATCH);
2531 if (!esgs_ring_bo)
2532 goto fail;
2533 } else {
2534 esgs_ring_bo = queue->esgs_ring_bo;
2535 esgs_ring_size = queue->esgs_ring_size;
2536 }
2537
2538 if (gsvs_ring_size > queue->gsvs_ring_size) {
2539 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2540 gsvs_ring_size,
2541 4096,
2542 RADEON_DOMAIN_VRAM,
2543 ring_bo_flags,
2544 RADV_BO_PRIORITY_SCRATCH);
2545 if (!gsvs_ring_bo)
2546 goto fail;
2547 } else {
2548 gsvs_ring_bo = queue->gsvs_ring_bo;
2549 gsvs_ring_size = queue->gsvs_ring_size;
2550 }
2551
2552 if (add_tess_rings) {
2553 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2554 tess_offchip_ring_offset + tess_offchip_ring_size,
2555 256,
2556 RADEON_DOMAIN_VRAM,
2557 ring_bo_flags,
2558 RADV_BO_PRIORITY_SCRATCH);
2559 if (!tess_rings_bo)
2560 goto fail;
2561 } else {
2562 tess_rings_bo = queue->tess_rings_bo;
2563 }
2564
2565 if (scratch_bo != queue->scratch_bo ||
2566 esgs_ring_bo != queue->esgs_ring_bo ||
2567 gsvs_ring_bo != queue->gsvs_ring_bo ||
2568 tess_rings_bo != queue->tess_rings_bo ||
2569 add_sample_positions) {
2570 uint32_t size = 0;
2571 if (gsvs_ring_bo || esgs_ring_bo ||
2572 tess_rings_bo || add_sample_positions) {
2573 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2574 if (add_sample_positions)
2575 size += 128; /* 64+32+16+8 = 120 bytes */
2576 }
2577 else if (scratch_bo)
2578 size = 8; /* 2 dword */
2579
2580 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2581 size,
2582 4096,
2583 RADEON_DOMAIN_VRAM,
2584 RADEON_FLAG_CPU_ACCESS |
2585 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2586 RADEON_FLAG_READ_ONLY,
2587 RADV_BO_PRIORITY_DESCRIPTOR);
2588 if (!descriptor_bo)
2589 goto fail;
2590 } else
2591 descriptor_bo = queue->descriptor_bo;
2592
2593 if (descriptor_bo != queue->descriptor_bo) {
2594 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2595
2596 if (scratch_bo) {
2597 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2598 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2599 S_008F04_SWIZZLE_ENABLE(1);
2600 map[0] = scratch_va;
2601 map[1] = rsrc1;
2602 }
2603
2604 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2605 fill_geom_tess_rings(queue, map, add_sample_positions,
2606 esgs_ring_size, esgs_ring_bo,
2607 gsvs_ring_size, gsvs_ring_bo,
2608 tess_factor_ring_size,
2609 tess_offchip_ring_offset,
2610 tess_offchip_ring_size,
2611 tess_rings_bo);
2612
2613 queue->device->ws->buffer_unmap(descriptor_bo);
2614 }
2615
2616 for(int i = 0; i < 3; ++i) {
2617 struct radeon_cmdbuf *cs = NULL;
2618 cs = queue->device->ws->cs_create(queue->device->ws,
2619 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2620 if (!cs)
2621 goto fail;
2622
2623 dest_cs[i] = cs;
2624
2625 if (scratch_bo)
2626 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2627
2628 /* Emit initial configuration. */
2629 switch (queue->queue_family_index) {
2630 case RADV_QUEUE_GENERAL:
2631 radv_init_graphics_state(cs, queue);
2632 break;
2633 case RADV_QUEUE_COMPUTE:
2634 radv_init_compute_state(cs, queue);
2635 break;
2636 case RADV_QUEUE_TRANSFER:
2637 break;
2638 }
2639
2640 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2641 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2642 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2643 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2644 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2645 }
2646
2647 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2648 gsvs_ring_bo, gsvs_ring_size);
2649 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2650 tess_factor_ring_size, tess_rings_bo);
2651 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2652 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2653
2654 if (i == 0) {
2655 si_cs_emit_cache_flush(cs,
2656 queue->device->physical_device->rad_info.chip_class,
2657 NULL, 0,
2658 queue->queue_family_index == RING_COMPUTE &&
2659 queue->device->physical_device->rad_info.chip_class >= GFX7,
2660 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2661 RADV_CMD_FLAG_INV_ICACHE |
2662 RADV_CMD_FLAG_INV_SMEM_L1 |
2663 RADV_CMD_FLAG_INV_VMEM_L1 |
2664 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2665 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2666 } else if (i == 1) {
2667 si_cs_emit_cache_flush(cs,
2668 queue->device->physical_device->rad_info.chip_class,
2669 NULL, 0,
2670 queue->queue_family_index == RING_COMPUTE &&
2671 queue->device->physical_device->rad_info.chip_class >= GFX7,
2672 RADV_CMD_FLAG_INV_ICACHE |
2673 RADV_CMD_FLAG_INV_SMEM_L1 |
2674 RADV_CMD_FLAG_INV_VMEM_L1 |
2675 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2676 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2677 }
2678
2679 if (!queue->device->ws->cs_finalize(cs))
2680 goto fail;
2681 }
2682
2683 if (queue->initial_full_flush_preamble_cs)
2684 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2685
2686 if (queue->initial_preamble_cs)
2687 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2688
2689 if (queue->continue_preamble_cs)
2690 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2691
2692 queue->initial_full_flush_preamble_cs = dest_cs[0];
2693 queue->initial_preamble_cs = dest_cs[1];
2694 queue->continue_preamble_cs = dest_cs[2];
2695
2696 if (scratch_bo != queue->scratch_bo) {
2697 if (queue->scratch_bo)
2698 queue->device->ws->buffer_destroy(queue->scratch_bo);
2699 queue->scratch_bo = scratch_bo;
2700 queue->scratch_size = scratch_size;
2701 }
2702
2703 if (compute_scratch_bo != queue->compute_scratch_bo) {
2704 if (queue->compute_scratch_bo)
2705 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2706 queue->compute_scratch_bo = compute_scratch_bo;
2707 queue->compute_scratch_size = compute_scratch_size;
2708 }
2709
2710 if (esgs_ring_bo != queue->esgs_ring_bo) {
2711 if (queue->esgs_ring_bo)
2712 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2713 queue->esgs_ring_bo = esgs_ring_bo;
2714 queue->esgs_ring_size = esgs_ring_size;
2715 }
2716
2717 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2718 if (queue->gsvs_ring_bo)
2719 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2720 queue->gsvs_ring_bo = gsvs_ring_bo;
2721 queue->gsvs_ring_size = gsvs_ring_size;
2722 }
2723
2724 if (tess_rings_bo != queue->tess_rings_bo) {
2725 queue->tess_rings_bo = tess_rings_bo;
2726 queue->has_tess_rings = true;
2727 }
2728
2729 if (descriptor_bo != queue->descriptor_bo) {
2730 if (queue->descriptor_bo)
2731 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2732
2733 queue->descriptor_bo = descriptor_bo;
2734 }
2735
2736 if (add_sample_positions)
2737 queue->has_sample_positions = true;
2738
2739 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2740 *initial_preamble_cs = queue->initial_preamble_cs;
2741 *continue_preamble_cs = queue->continue_preamble_cs;
2742 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2743 *continue_preamble_cs = NULL;
2744 return VK_SUCCESS;
2745 fail:
2746 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2747 if (dest_cs[i])
2748 queue->device->ws->cs_destroy(dest_cs[i]);
2749 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2750 queue->device->ws->buffer_destroy(descriptor_bo);
2751 if (scratch_bo && scratch_bo != queue->scratch_bo)
2752 queue->device->ws->buffer_destroy(scratch_bo);
2753 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2754 queue->device->ws->buffer_destroy(compute_scratch_bo);
2755 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2756 queue->device->ws->buffer_destroy(esgs_ring_bo);
2757 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2758 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2759 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2760 queue->device->ws->buffer_destroy(tess_rings_bo);
2761 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2762 }
2763
2764 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2765 struct radv_winsys_sem_counts *counts,
2766 int num_sems,
2767 const VkSemaphore *sems,
2768 VkFence _fence,
2769 bool reset_temp)
2770 {
2771 int syncobj_idx = 0, sem_idx = 0;
2772
2773 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2774 return VK_SUCCESS;
2775
2776 for (uint32_t i = 0; i < num_sems; i++) {
2777 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2778
2779 if (sem->temp_syncobj || sem->syncobj)
2780 counts->syncobj_count++;
2781 else
2782 counts->sem_count++;
2783 }
2784
2785 if (_fence != VK_NULL_HANDLE) {
2786 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2787 if (fence->temp_syncobj || fence->syncobj)
2788 counts->syncobj_count++;
2789 }
2790
2791 if (counts->syncobj_count) {
2792 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2793 if (!counts->syncobj)
2794 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2795 }
2796
2797 if (counts->sem_count) {
2798 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2799 if (!counts->sem) {
2800 free(counts->syncobj);
2801 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2802 }
2803 }
2804
2805 for (uint32_t i = 0; i < num_sems; i++) {
2806 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2807
2808 if (sem->temp_syncobj) {
2809 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2810 }
2811 else if (sem->syncobj)
2812 counts->syncobj[syncobj_idx++] = sem->syncobj;
2813 else {
2814 assert(sem->sem);
2815 counts->sem[sem_idx++] = sem->sem;
2816 }
2817 }
2818
2819 if (_fence != VK_NULL_HANDLE) {
2820 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2821 if (fence->temp_syncobj)
2822 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2823 else if (fence->syncobj)
2824 counts->syncobj[syncobj_idx++] = fence->syncobj;
2825 }
2826
2827 return VK_SUCCESS;
2828 }
2829
2830 static void
2831 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2832 {
2833 free(sem_info->wait.syncobj);
2834 free(sem_info->wait.sem);
2835 free(sem_info->signal.syncobj);
2836 free(sem_info->signal.sem);
2837 }
2838
2839
2840 static void radv_free_temp_syncobjs(struct radv_device *device,
2841 int num_sems,
2842 const VkSemaphore *sems)
2843 {
2844 for (uint32_t i = 0; i < num_sems; i++) {
2845 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2846
2847 if (sem->temp_syncobj) {
2848 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2849 sem->temp_syncobj = 0;
2850 }
2851 }
2852 }
2853
2854 static VkResult
2855 radv_alloc_sem_info(struct radv_instance *instance,
2856 struct radv_winsys_sem_info *sem_info,
2857 int num_wait_sems,
2858 const VkSemaphore *wait_sems,
2859 int num_signal_sems,
2860 const VkSemaphore *signal_sems,
2861 VkFence fence)
2862 {
2863 VkResult ret;
2864 memset(sem_info, 0, sizeof(*sem_info));
2865
2866 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2867 if (ret)
2868 return ret;
2869 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2870 if (ret)
2871 radv_free_sem_info(sem_info);
2872
2873 /* caller can override these */
2874 sem_info->cs_emit_wait = true;
2875 sem_info->cs_emit_signal = true;
2876 return ret;
2877 }
2878
2879 /* Signals fence as soon as all the work currently put on queue is done. */
2880 static VkResult radv_signal_fence(struct radv_queue *queue,
2881 struct radv_fence *fence)
2882 {
2883 int ret;
2884 VkResult result;
2885 struct radv_winsys_sem_info sem_info;
2886
2887 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2888 radv_fence_to_handle(fence));
2889 if (result != VK_SUCCESS)
2890 return result;
2891
2892 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2893 &queue->device->empty_cs[queue->queue_family_index],
2894 1, NULL, NULL, &sem_info, NULL,
2895 false, fence->fence);
2896 radv_free_sem_info(&sem_info);
2897
2898 if (ret)
2899 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2900
2901 return VK_SUCCESS;
2902 }
2903
2904 VkResult radv_QueueSubmit(
2905 VkQueue _queue,
2906 uint32_t submitCount,
2907 const VkSubmitInfo* pSubmits,
2908 VkFence _fence)
2909 {
2910 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2911 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2912 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2913 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2914 int ret;
2915 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2916 uint32_t scratch_size = 0;
2917 uint32_t compute_scratch_size = 0;
2918 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2919 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2920 VkResult result;
2921 bool fence_emitted = false;
2922 bool tess_rings_needed = false;
2923 bool sample_positions_needed = false;
2924
2925 /* Do this first so failing to allocate scratch buffers can't result in
2926 * partially executed submissions. */
2927 for (uint32_t i = 0; i < submitCount; i++) {
2928 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2929 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2930 pSubmits[i].pCommandBuffers[j]);
2931
2932 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2933 compute_scratch_size = MAX2(compute_scratch_size,
2934 cmd_buffer->compute_scratch_size_needed);
2935 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2936 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2937 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2938 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2939 }
2940 }
2941
2942 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2943 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2944 sample_positions_needed, &initial_flush_preamble_cs,
2945 &initial_preamble_cs, &continue_preamble_cs);
2946 if (result != VK_SUCCESS)
2947 return result;
2948
2949 for (uint32_t i = 0; i < submitCount; i++) {
2950 struct radeon_cmdbuf **cs_array;
2951 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2952 bool can_patch = true;
2953 uint32_t advance;
2954 struct radv_winsys_sem_info sem_info;
2955
2956 result = radv_alloc_sem_info(queue->device->instance,
2957 &sem_info,
2958 pSubmits[i].waitSemaphoreCount,
2959 pSubmits[i].pWaitSemaphores,
2960 pSubmits[i].signalSemaphoreCount,
2961 pSubmits[i].pSignalSemaphores,
2962 _fence);
2963 if (result != VK_SUCCESS)
2964 return result;
2965
2966 if (!pSubmits[i].commandBufferCount) {
2967 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2968 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2969 &queue->device->empty_cs[queue->queue_family_index],
2970 1, NULL, NULL,
2971 &sem_info, NULL,
2972 false, base_fence);
2973 if (ret) {
2974 radv_loge("failed to submit CS %d\n", i);
2975 abort();
2976 }
2977 fence_emitted = true;
2978 }
2979 radv_free_sem_info(&sem_info);
2980 continue;
2981 }
2982
2983 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2984 (pSubmits[i].commandBufferCount));
2985
2986 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2987 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2988 pSubmits[i].pCommandBuffers[j]);
2989 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2990
2991 cs_array[j] = cmd_buffer->cs;
2992 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2993 can_patch = false;
2994
2995 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2996 }
2997
2998 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2999 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3000 const struct radv_winsys_bo_list *bo_list = NULL;
3001
3002 advance = MIN2(max_cs_submission,
3003 pSubmits[i].commandBufferCount - j);
3004
3005 if (queue->device->trace_bo)
3006 *queue->device->trace_id_ptr = 0;
3007
3008 sem_info.cs_emit_wait = j == 0;
3009 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3010
3011 if (unlikely(queue->device->use_global_bo_list)) {
3012 pthread_mutex_lock(&queue->device->bo_list.mutex);
3013 bo_list = &queue->device->bo_list.list;
3014 }
3015
3016 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3017 advance, initial_preamble, continue_preamble_cs,
3018 &sem_info, bo_list,
3019 can_patch, base_fence);
3020
3021 if (unlikely(queue->device->use_global_bo_list))
3022 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3023
3024 if (ret) {
3025 radv_loge("failed to submit CS %d\n", i);
3026 abort();
3027 }
3028 fence_emitted = true;
3029 if (queue->device->trace_bo) {
3030 radv_check_gpu_hangs(queue, cs_array[j]);
3031 }
3032 }
3033
3034 radv_free_temp_syncobjs(queue->device,
3035 pSubmits[i].waitSemaphoreCount,
3036 pSubmits[i].pWaitSemaphores);
3037 radv_free_sem_info(&sem_info);
3038 free(cs_array);
3039 }
3040
3041 if (fence) {
3042 if (!fence_emitted) {
3043 result = radv_signal_fence(queue, fence);
3044 if (result != VK_SUCCESS)
3045 return result;
3046 }
3047 }
3048
3049 return VK_SUCCESS;
3050 }
3051
3052 VkResult radv_QueueWaitIdle(
3053 VkQueue _queue)
3054 {
3055 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3056
3057 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3058 radv_queue_family_to_ring(queue->queue_family_index),
3059 queue->queue_idx);
3060 return VK_SUCCESS;
3061 }
3062
3063 VkResult radv_DeviceWaitIdle(
3064 VkDevice _device)
3065 {
3066 RADV_FROM_HANDLE(radv_device, device, _device);
3067
3068 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3069 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3070 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3071 }
3072 }
3073 return VK_SUCCESS;
3074 }
3075
3076 VkResult radv_EnumerateInstanceExtensionProperties(
3077 const char* pLayerName,
3078 uint32_t* pPropertyCount,
3079 VkExtensionProperties* pProperties)
3080 {
3081 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3082
3083 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3084 if (radv_supported_instance_extensions.extensions[i]) {
3085 vk_outarray_append(&out, prop) {
3086 *prop = radv_instance_extensions[i];
3087 }
3088 }
3089 }
3090
3091 return vk_outarray_status(&out);
3092 }
3093
3094 VkResult radv_EnumerateDeviceExtensionProperties(
3095 VkPhysicalDevice physicalDevice,
3096 const char* pLayerName,
3097 uint32_t* pPropertyCount,
3098 VkExtensionProperties* pProperties)
3099 {
3100 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3101 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3102
3103 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3104 if (device->supported_extensions.extensions[i]) {
3105 vk_outarray_append(&out, prop) {
3106 *prop = radv_device_extensions[i];
3107 }
3108 }
3109 }
3110
3111 return vk_outarray_status(&out);
3112 }
3113
3114 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3115 VkInstance _instance,
3116 const char* pName)
3117 {
3118 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3119
3120 return radv_lookup_entrypoint_checked(pName,
3121 instance ? instance->apiVersion : 0,
3122 instance ? &instance->enabled_extensions : NULL,
3123 NULL);
3124 }
3125
3126 /* The loader wants us to expose a second GetInstanceProcAddr function
3127 * to work around certain LD_PRELOAD issues seen in apps.
3128 */
3129 PUBLIC
3130 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3131 VkInstance instance,
3132 const char* pName);
3133
3134 PUBLIC
3135 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3136 VkInstance instance,
3137 const char* pName)
3138 {
3139 return radv_GetInstanceProcAddr(instance, pName);
3140 }
3141
3142 PUBLIC
3143 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3144 VkInstance _instance,
3145 const char* pName);
3146
3147 PUBLIC
3148 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3149 VkInstance _instance,
3150 const char* pName)
3151 {
3152 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3153
3154 return radv_lookup_physical_device_entrypoint_checked(pName,
3155 instance ? instance->apiVersion : 0,
3156 instance ? &instance->enabled_extensions : NULL);
3157 }
3158
3159 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3160 VkDevice _device,
3161 const char* pName)
3162 {
3163 RADV_FROM_HANDLE(radv_device, device, _device);
3164
3165 return radv_lookup_entrypoint_checked(pName,
3166 device->instance->apiVersion,
3167 &device->instance->enabled_extensions,
3168 &device->enabled_extensions);
3169 }
3170
3171 bool radv_get_memory_fd(struct radv_device *device,
3172 struct radv_device_memory *memory,
3173 int *pFD)
3174 {
3175 struct radeon_bo_metadata metadata;
3176
3177 if (memory->image) {
3178 radv_init_metadata(device, memory->image, &metadata);
3179 device->ws->buffer_set_metadata(memory->bo, &metadata);
3180 }
3181
3182 return device->ws->buffer_get_fd(device->ws, memory->bo,
3183 pFD);
3184 }
3185
3186 static VkResult radv_alloc_memory(struct radv_device *device,
3187 const VkMemoryAllocateInfo* pAllocateInfo,
3188 const VkAllocationCallbacks* pAllocator,
3189 VkDeviceMemory* pMem)
3190 {
3191 struct radv_device_memory *mem;
3192 VkResult result;
3193 enum radeon_bo_domain domain;
3194 uint32_t flags = 0;
3195 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3196
3197 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3198
3199 if (pAllocateInfo->allocationSize == 0) {
3200 /* Apparently, this is allowed */
3201 *pMem = VK_NULL_HANDLE;
3202 return VK_SUCCESS;
3203 }
3204
3205 const VkImportMemoryFdInfoKHR *import_info =
3206 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3207 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3208 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3209 const VkExportMemoryAllocateInfo *export_info =
3210 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3211 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3212 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3213
3214 const struct wsi_memory_allocate_info *wsi_info =
3215 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3216
3217 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3218 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3219 if (mem == NULL)
3220 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3221
3222 if (wsi_info && wsi_info->implicit_sync)
3223 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3224
3225 if (dedicate_info) {
3226 mem->image = radv_image_from_handle(dedicate_info->image);
3227 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3228 } else {
3229 mem->image = NULL;
3230 mem->buffer = NULL;
3231 }
3232
3233 float priority_float = 0.5;
3234 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3235 vk_find_struct_const(pAllocateInfo->pNext,
3236 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3237 if (priority_ext)
3238 priority_float = priority_ext->priority;
3239
3240 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3241 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3242
3243 mem->user_ptr = NULL;
3244
3245 if (import_info) {
3246 assert(import_info->handleType ==
3247 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3248 import_info->handleType ==
3249 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3250 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3251 priority, NULL, NULL);
3252 if (!mem->bo) {
3253 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3254 goto fail;
3255 } else {
3256 close(import_info->fd);
3257 }
3258 } else if (host_ptr_info) {
3259 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3260 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3261 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3262 pAllocateInfo->allocationSize,
3263 priority);
3264 if (!mem->bo) {
3265 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3266 goto fail;
3267 } else {
3268 mem->user_ptr = host_ptr_info->pHostPointer;
3269 }
3270 } else {
3271 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3272 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3273 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3274 domain = RADEON_DOMAIN_GTT;
3275 else
3276 domain = RADEON_DOMAIN_VRAM;
3277
3278 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3279 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3280 else
3281 flags |= RADEON_FLAG_CPU_ACCESS;
3282
3283 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3284 flags |= RADEON_FLAG_GTT_WC;
3285
3286 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3287 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3288 if (device->use_global_bo_list) {
3289 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3290 }
3291 }
3292
3293 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3294 domain, flags, priority);
3295
3296 if (!mem->bo) {
3297 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3298 goto fail;
3299 }
3300 mem->type_index = mem_type_index;
3301 }
3302
3303 result = radv_bo_list_add(device, mem->bo);
3304 if (result != VK_SUCCESS)
3305 goto fail_bo;
3306
3307 *pMem = radv_device_memory_to_handle(mem);
3308
3309 return VK_SUCCESS;
3310
3311 fail_bo:
3312 device->ws->buffer_destroy(mem->bo);
3313 fail:
3314 vk_free2(&device->alloc, pAllocator, mem);
3315
3316 return result;
3317 }
3318
3319 VkResult radv_AllocateMemory(
3320 VkDevice _device,
3321 const VkMemoryAllocateInfo* pAllocateInfo,
3322 const VkAllocationCallbacks* pAllocator,
3323 VkDeviceMemory* pMem)
3324 {
3325 RADV_FROM_HANDLE(radv_device, device, _device);
3326 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3327 }
3328
3329 void radv_FreeMemory(
3330 VkDevice _device,
3331 VkDeviceMemory _mem,
3332 const VkAllocationCallbacks* pAllocator)
3333 {
3334 RADV_FROM_HANDLE(radv_device, device, _device);
3335 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3336
3337 if (mem == NULL)
3338 return;
3339
3340 radv_bo_list_remove(device, mem->bo);
3341 device->ws->buffer_destroy(mem->bo);
3342 mem->bo = NULL;
3343
3344 vk_free2(&device->alloc, pAllocator, mem);
3345 }
3346
3347 VkResult radv_MapMemory(
3348 VkDevice _device,
3349 VkDeviceMemory _memory,
3350 VkDeviceSize offset,
3351 VkDeviceSize size,
3352 VkMemoryMapFlags flags,
3353 void** ppData)
3354 {
3355 RADV_FROM_HANDLE(radv_device, device, _device);
3356 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3357
3358 if (mem == NULL) {
3359 *ppData = NULL;
3360 return VK_SUCCESS;
3361 }
3362
3363 if (mem->user_ptr)
3364 *ppData = mem->user_ptr;
3365 else
3366 *ppData = device->ws->buffer_map(mem->bo);
3367
3368 if (*ppData) {
3369 *ppData += offset;
3370 return VK_SUCCESS;
3371 }
3372
3373 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3374 }
3375
3376 void radv_UnmapMemory(
3377 VkDevice _device,
3378 VkDeviceMemory _memory)
3379 {
3380 RADV_FROM_HANDLE(radv_device, device, _device);
3381 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3382
3383 if (mem == NULL)
3384 return;
3385
3386 if (mem->user_ptr == NULL)
3387 device->ws->buffer_unmap(mem->bo);
3388 }
3389
3390 VkResult radv_FlushMappedMemoryRanges(
3391 VkDevice _device,
3392 uint32_t memoryRangeCount,
3393 const VkMappedMemoryRange* pMemoryRanges)
3394 {
3395 return VK_SUCCESS;
3396 }
3397
3398 VkResult radv_InvalidateMappedMemoryRanges(
3399 VkDevice _device,
3400 uint32_t memoryRangeCount,
3401 const VkMappedMemoryRange* pMemoryRanges)
3402 {
3403 return VK_SUCCESS;
3404 }
3405
3406 void radv_GetBufferMemoryRequirements(
3407 VkDevice _device,
3408 VkBuffer _buffer,
3409 VkMemoryRequirements* pMemoryRequirements)
3410 {
3411 RADV_FROM_HANDLE(radv_device, device, _device);
3412 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3413
3414 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3415
3416 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3417 pMemoryRequirements->alignment = 4096;
3418 else
3419 pMemoryRequirements->alignment = 16;
3420
3421 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3422 }
3423
3424 void radv_GetBufferMemoryRequirements2(
3425 VkDevice device,
3426 const VkBufferMemoryRequirementsInfo2 *pInfo,
3427 VkMemoryRequirements2 *pMemoryRequirements)
3428 {
3429 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3430 &pMemoryRequirements->memoryRequirements);
3431 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3432 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3433 switch (ext->sType) {
3434 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3435 VkMemoryDedicatedRequirements *req =
3436 (VkMemoryDedicatedRequirements *) ext;
3437 req->requiresDedicatedAllocation = buffer->shareable;
3438 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3439 break;
3440 }
3441 default:
3442 break;
3443 }
3444 }
3445 }
3446
3447 void radv_GetImageMemoryRequirements(
3448 VkDevice _device,
3449 VkImage _image,
3450 VkMemoryRequirements* pMemoryRequirements)
3451 {
3452 RADV_FROM_HANDLE(radv_device, device, _device);
3453 RADV_FROM_HANDLE(radv_image, image, _image);
3454
3455 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3456
3457 pMemoryRequirements->size = image->size;
3458 pMemoryRequirements->alignment = image->alignment;
3459 }
3460
3461 void radv_GetImageMemoryRequirements2(
3462 VkDevice device,
3463 const VkImageMemoryRequirementsInfo2 *pInfo,
3464 VkMemoryRequirements2 *pMemoryRequirements)
3465 {
3466 radv_GetImageMemoryRequirements(device, pInfo->image,
3467 &pMemoryRequirements->memoryRequirements);
3468
3469 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3470
3471 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3472 switch (ext->sType) {
3473 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3474 VkMemoryDedicatedRequirements *req =
3475 (VkMemoryDedicatedRequirements *) ext;
3476 req->requiresDedicatedAllocation = image->shareable;
3477 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3478 break;
3479 }
3480 default:
3481 break;
3482 }
3483 }
3484 }
3485
3486 void radv_GetImageSparseMemoryRequirements(
3487 VkDevice device,
3488 VkImage image,
3489 uint32_t* pSparseMemoryRequirementCount,
3490 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3491 {
3492 stub();
3493 }
3494
3495 void radv_GetImageSparseMemoryRequirements2(
3496 VkDevice device,
3497 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3498 uint32_t* pSparseMemoryRequirementCount,
3499 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3500 {
3501 stub();
3502 }
3503
3504 void radv_GetDeviceMemoryCommitment(
3505 VkDevice device,
3506 VkDeviceMemory memory,
3507 VkDeviceSize* pCommittedMemoryInBytes)
3508 {
3509 *pCommittedMemoryInBytes = 0;
3510 }
3511
3512 VkResult radv_BindBufferMemory2(VkDevice device,
3513 uint32_t bindInfoCount,
3514 const VkBindBufferMemoryInfo *pBindInfos)
3515 {
3516 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3517 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3518 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3519
3520 if (mem) {
3521 buffer->bo = mem->bo;
3522 buffer->offset = pBindInfos[i].memoryOffset;
3523 } else {
3524 buffer->bo = NULL;
3525 }
3526 }
3527 return VK_SUCCESS;
3528 }
3529
3530 VkResult radv_BindBufferMemory(
3531 VkDevice device,
3532 VkBuffer buffer,
3533 VkDeviceMemory memory,
3534 VkDeviceSize memoryOffset)
3535 {
3536 const VkBindBufferMemoryInfo info = {
3537 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3538 .buffer = buffer,
3539 .memory = memory,
3540 .memoryOffset = memoryOffset
3541 };
3542
3543 return radv_BindBufferMemory2(device, 1, &info);
3544 }
3545
3546 VkResult radv_BindImageMemory2(VkDevice device,
3547 uint32_t bindInfoCount,
3548 const VkBindImageMemoryInfo *pBindInfos)
3549 {
3550 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3551 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3552 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3553
3554 if (mem) {
3555 image->bo = mem->bo;
3556 image->offset = pBindInfos[i].memoryOffset;
3557 } else {
3558 image->bo = NULL;
3559 image->offset = 0;
3560 }
3561 }
3562 return VK_SUCCESS;
3563 }
3564
3565
3566 VkResult radv_BindImageMemory(
3567 VkDevice device,
3568 VkImage image,
3569 VkDeviceMemory memory,
3570 VkDeviceSize memoryOffset)
3571 {
3572 const VkBindImageMemoryInfo info = {
3573 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3574 .image = image,
3575 .memory = memory,
3576 .memoryOffset = memoryOffset
3577 };
3578
3579 return radv_BindImageMemory2(device, 1, &info);
3580 }
3581
3582
3583 static void
3584 radv_sparse_buffer_bind_memory(struct radv_device *device,
3585 const VkSparseBufferMemoryBindInfo *bind)
3586 {
3587 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3588
3589 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3590 struct radv_device_memory *mem = NULL;
3591
3592 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3593 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3594
3595 device->ws->buffer_virtual_bind(buffer->bo,
3596 bind->pBinds[i].resourceOffset,
3597 bind->pBinds[i].size,
3598 mem ? mem->bo : NULL,
3599 bind->pBinds[i].memoryOffset);
3600 }
3601 }
3602
3603 static void
3604 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3605 const VkSparseImageOpaqueMemoryBindInfo *bind)
3606 {
3607 RADV_FROM_HANDLE(radv_image, image, bind->image);
3608
3609 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3610 struct radv_device_memory *mem = NULL;
3611
3612 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3613 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3614
3615 device->ws->buffer_virtual_bind(image->bo,
3616 bind->pBinds[i].resourceOffset,
3617 bind->pBinds[i].size,
3618 mem ? mem->bo : NULL,
3619 bind->pBinds[i].memoryOffset);
3620 }
3621 }
3622
3623 VkResult radv_QueueBindSparse(
3624 VkQueue _queue,
3625 uint32_t bindInfoCount,
3626 const VkBindSparseInfo* pBindInfo,
3627 VkFence _fence)
3628 {
3629 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3630 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3631 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3632 bool fence_emitted = false;
3633 VkResult result;
3634 int ret;
3635
3636 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3637 struct radv_winsys_sem_info sem_info;
3638 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3639 radv_sparse_buffer_bind_memory(queue->device,
3640 pBindInfo[i].pBufferBinds + j);
3641 }
3642
3643 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3644 radv_sparse_image_opaque_bind_memory(queue->device,
3645 pBindInfo[i].pImageOpaqueBinds + j);
3646 }
3647
3648 VkResult result;
3649 result = radv_alloc_sem_info(queue->device->instance,
3650 &sem_info,
3651 pBindInfo[i].waitSemaphoreCount,
3652 pBindInfo[i].pWaitSemaphores,
3653 pBindInfo[i].signalSemaphoreCount,
3654 pBindInfo[i].pSignalSemaphores,
3655 _fence);
3656 if (result != VK_SUCCESS)
3657 return result;
3658
3659 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3660 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3661 &queue->device->empty_cs[queue->queue_family_index],
3662 1, NULL, NULL,
3663 &sem_info, NULL,
3664 false, base_fence);
3665 if (ret) {
3666 radv_loge("failed to submit CS %d\n", i);
3667 abort();
3668 }
3669
3670 fence_emitted = true;
3671 }
3672
3673 radv_free_sem_info(&sem_info);
3674
3675 }
3676
3677 if (fence) {
3678 if (!fence_emitted) {
3679 result = radv_signal_fence(queue, fence);
3680 if (result != VK_SUCCESS)
3681 return result;
3682 }
3683 }
3684
3685 return VK_SUCCESS;
3686 }
3687
3688 VkResult radv_CreateFence(
3689 VkDevice _device,
3690 const VkFenceCreateInfo* pCreateInfo,
3691 const VkAllocationCallbacks* pAllocator,
3692 VkFence* pFence)
3693 {
3694 RADV_FROM_HANDLE(radv_device, device, _device);
3695 const VkExportFenceCreateInfo *export =
3696 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3697 VkExternalFenceHandleTypeFlags handleTypes =
3698 export ? export->handleTypes : 0;
3699
3700 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3701 sizeof(*fence), 8,
3702 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3703
3704 if (!fence)
3705 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3706
3707 fence->fence_wsi = NULL;
3708 fence->temp_syncobj = 0;
3709 if (device->always_use_syncobj || handleTypes) {
3710 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3711 if (ret) {
3712 vk_free2(&device->alloc, pAllocator, fence);
3713 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3714 }
3715 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3716 device->ws->signal_syncobj(device->ws, fence->syncobj);
3717 }
3718 fence->fence = NULL;
3719 } else {
3720 fence->fence = device->ws->create_fence();
3721 if (!fence->fence) {
3722 vk_free2(&device->alloc, pAllocator, fence);
3723 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3724 }
3725 fence->syncobj = 0;
3726 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3727 device->ws->signal_fence(fence->fence);
3728 }
3729
3730 *pFence = radv_fence_to_handle(fence);
3731
3732 return VK_SUCCESS;
3733 }
3734
3735 void radv_DestroyFence(
3736 VkDevice _device,
3737 VkFence _fence,
3738 const VkAllocationCallbacks* pAllocator)
3739 {
3740 RADV_FROM_HANDLE(radv_device, device, _device);
3741 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3742
3743 if (!fence)
3744 return;
3745
3746 if (fence->temp_syncobj)
3747 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3748 if (fence->syncobj)
3749 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3750 if (fence->fence)
3751 device->ws->destroy_fence(fence->fence);
3752 if (fence->fence_wsi)
3753 fence->fence_wsi->destroy(fence->fence_wsi);
3754 vk_free2(&device->alloc, pAllocator, fence);
3755 }
3756
3757
3758 uint64_t radv_get_current_time(void)
3759 {
3760 struct timespec tv;
3761 clock_gettime(CLOCK_MONOTONIC, &tv);
3762 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3763 }
3764
3765 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3766 {
3767 uint64_t current_time = radv_get_current_time();
3768
3769 timeout = MIN2(UINT64_MAX - current_time, timeout);
3770
3771 return current_time + timeout;
3772 }
3773
3774
3775 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3776 uint32_t fenceCount, const VkFence *pFences)
3777 {
3778 for (uint32_t i = 0; i < fenceCount; ++i) {
3779 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3780 if (fence->fence == NULL || fence->syncobj ||
3781 fence->temp_syncobj || fence->fence_wsi ||
3782 (!device->ws->is_fence_waitable(fence->fence)))
3783 return false;
3784 }
3785 return true;
3786 }
3787
3788 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3789 {
3790 for (uint32_t i = 0; i < fenceCount; ++i) {
3791 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3792 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3793 return false;
3794 }
3795 return true;
3796 }
3797
3798 VkResult radv_WaitForFences(
3799 VkDevice _device,
3800 uint32_t fenceCount,
3801 const VkFence* pFences,
3802 VkBool32 waitAll,
3803 uint64_t timeout)
3804 {
3805 RADV_FROM_HANDLE(radv_device, device, _device);
3806 timeout = radv_get_absolute_timeout(timeout);
3807
3808 if (device->always_use_syncobj &&
3809 radv_all_fences_syncobj(fenceCount, pFences))
3810 {
3811 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3812 if (!handles)
3813 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3814
3815 for (uint32_t i = 0; i < fenceCount; ++i) {
3816 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3817 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3818 }
3819
3820 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3821
3822 free(handles);
3823 return success ? VK_SUCCESS : VK_TIMEOUT;
3824 }
3825
3826 if (!waitAll && fenceCount > 1) {
3827 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3828 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3829 uint32_t wait_count = 0;
3830 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3831 if (!fences)
3832 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3833
3834 for (uint32_t i = 0; i < fenceCount; ++i) {
3835 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3836
3837 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3838 free(fences);
3839 return VK_SUCCESS;
3840 }
3841
3842 fences[wait_count++] = fence->fence;
3843 }
3844
3845 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3846 waitAll, timeout - radv_get_current_time());
3847
3848 free(fences);
3849 return success ? VK_SUCCESS : VK_TIMEOUT;
3850 }
3851
3852 while(radv_get_current_time() <= timeout) {
3853 for (uint32_t i = 0; i < fenceCount; ++i) {
3854 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3855 return VK_SUCCESS;
3856 }
3857 }
3858 return VK_TIMEOUT;
3859 }
3860
3861 for (uint32_t i = 0; i < fenceCount; ++i) {
3862 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3863 bool expired = false;
3864
3865 if (fence->temp_syncobj) {
3866 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3867 return VK_TIMEOUT;
3868 continue;
3869 }
3870
3871 if (fence->syncobj) {
3872 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3873 return VK_TIMEOUT;
3874 continue;
3875 }
3876
3877 if (fence->fence) {
3878 if (!device->ws->is_fence_waitable(fence->fence)) {
3879 while(!device->ws->is_fence_waitable(fence->fence) &&
3880 radv_get_current_time() <= timeout)
3881 /* Do nothing */;
3882 }
3883
3884 expired = device->ws->fence_wait(device->ws,
3885 fence->fence,
3886 true, timeout);
3887 if (!expired)
3888 return VK_TIMEOUT;
3889 }
3890
3891 if (fence->fence_wsi) {
3892 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3893 if (result != VK_SUCCESS)
3894 return result;
3895 }
3896 }
3897
3898 return VK_SUCCESS;
3899 }
3900
3901 VkResult radv_ResetFences(VkDevice _device,
3902 uint32_t fenceCount,
3903 const VkFence *pFences)
3904 {
3905 RADV_FROM_HANDLE(radv_device, device, _device);
3906
3907 for (unsigned i = 0; i < fenceCount; ++i) {
3908 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3909 if (fence->fence)
3910 device->ws->reset_fence(fence->fence);
3911
3912 /* Per spec, we first restore the permanent payload, and then reset, so
3913 * having a temp syncobj should not skip resetting the permanent syncobj. */
3914 if (fence->temp_syncobj) {
3915 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3916 fence->temp_syncobj = 0;
3917 }
3918
3919 if (fence->syncobj) {
3920 device->ws->reset_syncobj(device->ws, fence->syncobj);
3921 }
3922 }
3923
3924 return VK_SUCCESS;
3925 }
3926
3927 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3928 {
3929 RADV_FROM_HANDLE(radv_device, device, _device);
3930 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3931
3932 if (fence->temp_syncobj) {
3933 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3934 return success ? VK_SUCCESS : VK_NOT_READY;
3935 }
3936
3937 if (fence->syncobj) {
3938 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3939 return success ? VK_SUCCESS : VK_NOT_READY;
3940 }
3941
3942 if (fence->fence) {
3943 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3944 return VK_NOT_READY;
3945 }
3946 if (fence->fence_wsi) {
3947 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3948
3949 if (result != VK_SUCCESS) {
3950 if (result == VK_TIMEOUT)
3951 return VK_NOT_READY;
3952 return result;
3953 }
3954 }
3955 return VK_SUCCESS;
3956 }
3957
3958
3959 // Queue semaphore functions
3960
3961 VkResult radv_CreateSemaphore(
3962 VkDevice _device,
3963 const VkSemaphoreCreateInfo* pCreateInfo,
3964 const VkAllocationCallbacks* pAllocator,
3965 VkSemaphore* pSemaphore)
3966 {
3967 RADV_FROM_HANDLE(radv_device, device, _device);
3968 const VkExportSemaphoreCreateInfo *export =
3969 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3970 VkExternalSemaphoreHandleTypeFlags handleTypes =
3971 export ? export->handleTypes : 0;
3972
3973 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3974 sizeof(*sem), 8,
3975 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3976 if (!sem)
3977 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3978
3979 sem->temp_syncobj = 0;
3980 /* create a syncobject if we are going to export this semaphore */
3981 if (device->always_use_syncobj || handleTypes) {
3982 assert (device->physical_device->rad_info.has_syncobj);
3983 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3984 if (ret) {
3985 vk_free2(&device->alloc, pAllocator, sem);
3986 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3987 }
3988 sem->sem = NULL;
3989 } else {
3990 sem->sem = device->ws->create_sem(device->ws);
3991 if (!sem->sem) {
3992 vk_free2(&device->alloc, pAllocator, sem);
3993 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3994 }
3995 sem->syncobj = 0;
3996 }
3997
3998 *pSemaphore = radv_semaphore_to_handle(sem);
3999 return VK_SUCCESS;
4000 }
4001
4002 void radv_DestroySemaphore(
4003 VkDevice _device,
4004 VkSemaphore _semaphore,
4005 const VkAllocationCallbacks* pAllocator)
4006 {
4007 RADV_FROM_HANDLE(radv_device, device, _device);
4008 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4009 if (!_semaphore)
4010 return;
4011
4012 if (sem->syncobj)
4013 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4014 else
4015 device->ws->destroy_sem(sem->sem);
4016 vk_free2(&device->alloc, pAllocator, sem);
4017 }
4018
4019 VkResult radv_CreateEvent(
4020 VkDevice _device,
4021 const VkEventCreateInfo* pCreateInfo,
4022 const VkAllocationCallbacks* pAllocator,
4023 VkEvent* pEvent)
4024 {
4025 RADV_FROM_HANDLE(radv_device, device, _device);
4026 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4027 sizeof(*event), 8,
4028 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4029
4030 if (!event)
4031 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4032
4033 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4034 RADEON_DOMAIN_GTT,
4035 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4036 RADV_BO_PRIORITY_FENCE);
4037 if (!event->bo) {
4038 vk_free2(&device->alloc, pAllocator, event);
4039 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4040 }
4041
4042 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4043
4044 *pEvent = radv_event_to_handle(event);
4045
4046 return VK_SUCCESS;
4047 }
4048
4049 void radv_DestroyEvent(
4050 VkDevice _device,
4051 VkEvent _event,
4052 const VkAllocationCallbacks* pAllocator)
4053 {
4054 RADV_FROM_HANDLE(radv_device, device, _device);
4055 RADV_FROM_HANDLE(radv_event, event, _event);
4056
4057 if (!event)
4058 return;
4059 device->ws->buffer_destroy(event->bo);
4060 vk_free2(&device->alloc, pAllocator, event);
4061 }
4062
4063 VkResult radv_GetEventStatus(
4064 VkDevice _device,
4065 VkEvent _event)
4066 {
4067 RADV_FROM_HANDLE(radv_event, event, _event);
4068
4069 if (*event->map == 1)
4070 return VK_EVENT_SET;
4071 return VK_EVENT_RESET;
4072 }
4073
4074 VkResult radv_SetEvent(
4075 VkDevice _device,
4076 VkEvent _event)
4077 {
4078 RADV_FROM_HANDLE(radv_event, event, _event);
4079 *event->map = 1;
4080
4081 return VK_SUCCESS;
4082 }
4083
4084 VkResult radv_ResetEvent(
4085 VkDevice _device,
4086 VkEvent _event)
4087 {
4088 RADV_FROM_HANDLE(radv_event, event, _event);
4089 *event->map = 0;
4090
4091 return VK_SUCCESS;
4092 }
4093
4094 VkResult radv_CreateBuffer(
4095 VkDevice _device,
4096 const VkBufferCreateInfo* pCreateInfo,
4097 const VkAllocationCallbacks* pAllocator,
4098 VkBuffer* pBuffer)
4099 {
4100 RADV_FROM_HANDLE(radv_device, device, _device);
4101 struct radv_buffer *buffer;
4102
4103 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4104
4105 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4106 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4107 if (buffer == NULL)
4108 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4109
4110 buffer->size = pCreateInfo->size;
4111 buffer->usage = pCreateInfo->usage;
4112 buffer->bo = NULL;
4113 buffer->offset = 0;
4114 buffer->flags = pCreateInfo->flags;
4115
4116 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4117 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4118
4119 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4120 buffer->bo = device->ws->buffer_create(device->ws,
4121 align64(buffer->size, 4096),
4122 4096, 0, RADEON_FLAG_VIRTUAL,
4123 RADV_BO_PRIORITY_VIRTUAL);
4124 if (!buffer->bo) {
4125 vk_free2(&device->alloc, pAllocator, buffer);
4126 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4127 }
4128 }
4129
4130 *pBuffer = radv_buffer_to_handle(buffer);
4131
4132 return VK_SUCCESS;
4133 }
4134
4135 void radv_DestroyBuffer(
4136 VkDevice _device,
4137 VkBuffer _buffer,
4138 const VkAllocationCallbacks* pAllocator)
4139 {
4140 RADV_FROM_HANDLE(radv_device, device, _device);
4141 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4142
4143 if (!buffer)
4144 return;
4145
4146 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4147 device->ws->buffer_destroy(buffer->bo);
4148
4149 vk_free2(&device->alloc, pAllocator, buffer);
4150 }
4151
4152 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4153 VkDevice device,
4154 const VkBufferDeviceAddressInfoEXT* pInfo)
4155 {
4156 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4157 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4158 }
4159
4160
4161 static inline unsigned
4162 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4163 {
4164 if (stencil)
4165 return plane->surface.u.legacy.stencil_tiling_index[level];
4166 else
4167 return plane->surface.u.legacy.tiling_index[level];
4168 }
4169
4170 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4171 {
4172 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4173 }
4174
4175 static uint32_t
4176 radv_init_dcc_control_reg(struct radv_device *device,
4177 struct radv_image_view *iview)
4178 {
4179 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4180 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4181 unsigned max_compressed_block_size;
4182 unsigned independent_64b_blocks;
4183
4184 if (!radv_image_has_dcc(iview->image))
4185 return 0;
4186
4187 if (iview->image->info.samples > 1) {
4188 if (iview->image->planes[0].surface.bpe == 1)
4189 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4190 else if (iview->image->planes[0].surface.bpe == 2)
4191 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4192 }
4193
4194 if (!device->physical_device->rad_info.has_dedicated_vram) {
4195 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4196 * dGPU and 64 for APU because all of our APUs to date use
4197 * DIMMs which have a request granularity size of 64B while all
4198 * other chips have a 32B request size.
4199 */
4200 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4201 }
4202
4203 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4204 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4205 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4206 /* If this DCC image is potentially going to be used in texture
4207 * fetches, we need some special settings.
4208 */
4209 independent_64b_blocks = 1;
4210 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4211 } else {
4212 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4213 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4214 * big as possible for better compression state.
4215 */
4216 independent_64b_blocks = 0;
4217 max_compressed_block_size = max_uncompressed_block_size;
4218 }
4219
4220 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4221 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4222 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4223 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4224 }
4225
4226 static void
4227 radv_initialise_color_surface(struct radv_device *device,
4228 struct radv_color_buffer_info *cb,
4229 struct radv_image_view *iview)
4230 {
4231 const struct vk_format_description *desc;
4232 unsigned ntype, format, swap, endian;
4233 unsigned blend_clamp = 0, blend_bypass = 0;
4234 uint64_t va;
4235 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4236 const struct radeon_surf *surf = &plane->surface;
4237
4238 desc = vk_format_description(iview->vk_format);
4239
4240 memset(cb, 0, sizeof(*cb));
4241
4242 /* Intensity is implemented as Red, so treat it that way. */
4243 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4244
4245 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4246
4247 cb->cb_color_base = va >> 8;
4248
4249 if (device->physical_device->rad_info.chip_class >= GFX9) {
4250 struct gfx9_surf_meta_flags meta;
4251 if (iview->image->dcc_offset)
4252 meta = surf->u.gfx9.dcc;
4253 else
4254 meta = surf->u.gfx9.cmask;
4255
4256 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4257 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4258 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4259 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4260
4261 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4262 cb->cb_color_base |= surf->tile_swizzle;
4263
4264 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4265 } else {
4266 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4267 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4268
4269 cb->cb_color_base += level_info->offset >> 8;
4270 if (level_info->mode == RADEON_SURF_MODE_2D)
4271 cb->cb_color_base |= surf->tile_swizzle;
4272
4273 pitch_tile_max = level_info->nblk_x / 8 - 1;
4274 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4275 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4276
4277 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4278 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4279 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4280
4281 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4282
4283 if (radv_image_has_fmask(iview->image)) {
4284 if (device->physical_device->rad_info.chip_class >= GFX7)
4285 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4286 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4287 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4288 } else {
4289 /* This must be set for fast clear to work without FMASK. */
4290 if (device->physical_device->rad_info.chip_class >= GFX7)
4291 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4292 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4293 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4294 }
4295 }
4296
4297 /* CMASK variables */
4298 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4299 va += iview->image->cmask.offset;
4300 cb->cb_color_cmask = va >> 8;
4301
4302 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4303 va += iview->image->dcc_offset;
4304 cb->cb_dcc_base = va >> 8;
4305 cb->cb_dcc_base |= surf->tile_swizzle;
4306
4307 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4308 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4309 S_028C6C_SLICE_MAX(max_slice);
4310
4311 if (iview->image->info.samples > 1) {
4312 unsigned log_samples = util_logbase2(iview->image->info.samples);
4313
4314 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4315 S_028C74_NUM_FRAGMENTS(log_samples);
4316 }
4317
4318 if (radv_image_has_fmask(iview->image)) {
4319 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4320 cb->cb_color_fmask = va >> 8;
4321 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4322 } else {
4323 cb->cb_color_fmask = cb->cb_color_base;
4324 }
4325
4326 ntype = radv_translate_color_numformat(iview->vk_format,
4327 desc,
4328 vk_format_get_first_non_void_channel(iview->vk_format));
4329 format = radv_translate_colorformat(iview->vk_format);
4330 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4331 radv_finishme("Illegal color\n");
4332 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4333 endian = radv_colorformat_endian_swap(format);
4334
4335 /* blend clamp should be set for all NORM/SRGB types */
4336 if (ntype == V_028C70_NUMBER_UNORM ||
4337 ntype == V_028C70_NUMBER_SNORM ||
4338 ntype == V_028C70_NUMBER_SRGB)
4339 blend_clamp = 1;
4340
4341 /* set blend bypass according to docs if SINT/UINT or
4342 8/24 COLOR variants */
4343 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4344 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4345 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4346 blend_clamp = 0;
4347 blend_bypass = 1;
4348 }
4349 #if 0
4350 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4351 (format == V_028C70_COLOR_8 ||
4352 format == V_028C70_COLOR_8_8 ||
4353 format == V_028C70_COLOR_8_8_8_8))
4354 ->color_is_int8 = true;
4355 #endif
4356 cb->cb_color_info = S_028C70_FORMAT(format) |
4357 S_028C70_COMP_SWAP(swap) |
4358 S_028C70_BLEND_CLAMP(blend_clamp) |
4359 S_028C70_BLEND_BYPASS(blend_bypass) |
4360 S_028C70_SIMPLE_FLOAT(1) |
4361 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4362 ntype != V_028C70_NUMBER_SNORM &&
4363 ntype != V_028C70_NUMBER_SRGB &&
4364 format != V_028C70_COLOR_8_24 &&
4365 format != V_028C70_COLOR_24_8) |
4366 S_028C70_NUMBER_TYPE(ntype) |
4367 S_028C70_ENDIAN(endian);
4368 if (radv_image_has_fmask(iview->image)) {
4369 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4370 if (device->physical_device->rad_info.chip_class == GFX6) {
4371 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4372 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4373 }
4374 }
4375
4376 if (radv_image_has_cmask(iview->image) &&
4377 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4378 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4379
4380 if (radv_dcc_enabled(iview->image, iview->base_mip))
4381 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4382
4383 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4384
4385 /* This must be set for fast clear to work without FMASK. */
4386 if (!radv_image_has_fmask(iview->image) &&
4387 device->physical_device->rad_info.chip_class == GFX6) {
4388 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4389 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4390 }
4391
4392 if (device->physical_device->rad_info.chip_class >= GFX9) {
4393 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4394
4395 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4396 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4397 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4398 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4399
4400 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4401 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4402 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4403 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4404 S_028C68_MIP0_HEIGHT(height - 1) |
4405 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4406 }
4407 }
4408
4409 static unsigned
4410 radv_calc_decompress_on_z_planes(struct radv_device *device,
4411 struct radv_image_view *iview)
4412 {
4413 unsigned max_zplanes = 0;
4414
4415 assert(radv_image_is_tc_compat_htile(iview->image));
4416
4417 if (device->physical_device->rad_info.chip_class >= GFX9) {
4418 /* Default value for 32-bit depth surfaces. */
4419 max_zplanes = 4;
4420
4421 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4422 iview->image->info.samples > 1)
4423 max_zplanes = 2;
4424
4425 max_zplanes = max_zplanes + 1;
4426 } else {
4427 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4428 /* Do not enable Z plane compression for 16-bit depth
4429 * surfaces because isn't supported on GFX8. Only
4430 * 32-bit depth surfaces are supported by the hardware.
4431 * This allows to maintain shader compatibility and to
4432 * reduce the number of depth decompressions.
4433 */
4434 max_zplanes = 1;
4435 } else {
4436 if (iview->image->info.samples <= 1)
4437 max_zplanes = 5;
4438 else if (iview->image->info.samples <= 4)
4439 max_zplanes = 3;
4440 else
4441 max_zplanes = 2;
4442 }
4443 }
4444
4445 return max_zplanes;
4446 }
4447
4448 static void
4449 radv_initialise_ds_surface(struct radv_device *device,
4450 struct radv_ds_buffer_info *ds,
4451 struct radv_image_view *iview)
4452 {
4453 unsigned level = iview->base_mip;
4454 unsigned format, stencil_format;
4455 uint64_t va, s_offs, z_offs;
4456 bool stencil_only = false;
4457 const struct radv_image_plane *plane = &iview->image->planes[0];
4458 const struct radeon_surf *surf = &plane->surface;
4459
4460 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4461
4462 memset(ds, 0, sizeof(*ds));
4463 switch (iview->image->vk_format) {
4464 case VK_FORMAT_D24_UNORM_S8_UINT:
4465 case VK_FORMAT_X8_D24_UNORM_PACK32:
4466 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4467 ds->offset_scale = 2.0f;
4468 break;
4469 case VK_FORMAT_D16_UNORM:
4470 case VK_FORMAT_D16_UNORM_S8_UINT:
4471 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4472 ds->offset_scale = 4.0f;
4473 break;
4474 case VK_FORMAT_D32_SFLOAT:
4475 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4476 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4477 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4478 ds->offset_scale = 1.0f;
4479 break;
4480 case VK_FORMAT_S8_UINT:
4481 stencil_only = true;
4482 break;
4483 default:
4484 break;
4485 }
4486
4487 format = radv_translate_dbformat(iview->image->vk_format);
4488 stencil_format = surf->has_stencil ?
4489 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4490
4491 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4492 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4493 S_028008_SLICE_MAX(max_slice);
4494
4495 ds->db_htile_data_base = 0;
4496 ds->db_htile_surface = 0;
4497
4498 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4499 s_offs = z_offs = va;
4500
4501 if (device->physical_device->rad_info.chip_class >= GFX9) {
4502 assert(surf->u.gfx9.surf_offset == 0);
4503 s_offs += surf->u.gfx9.stencil_offset;
4504
4505 ds->db_z_info = S_028038_FORMAT(format) |
4506 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4507 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4508 S_028038_MAXMIP(iview->image->info.levels - 1) |
4509 S_028038_ZRANGE_PRECISION(1);
4510 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4511 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4512
4513 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4514 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4515 ds->db_depth_view |= S_028008_MIPID(level);
4516
4517 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4518 S_02801C_Y_MAX(iview->image->info.height - 1);
4519
4520 if (radv_htile_enabled(iview->image, level)) {
4521 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4522
4523 if (radv_image_is_tc_compat_htile(iview->image)) {
4524 unsigned max_zplanes =
4525 radv_calc_decompress_on_z_planes(device, iview);
4526
4527 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4528 S_028038_ITERATE_FLUSH(1);
4529 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4530 }
4531
4532 if (!surf->has_stencil)
4533 /* Use all of the htile_buffer for depth if there's no stencil. */
4534 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4535 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4536 iview->image->htile_offset;
4537 ds->db_htile_data_base = va >> 8;
4538 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4539 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4540 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4541 }
4542 } else {
4543 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4544
4545 if (stencil_only)
4546 level_info = &surf->u.legacy.stencil_level[level];
4547
4548 z_offs += surf->u.legacy.level[level].offset;
4549 s_offs += surf->u.legacy.stencil_level[level].offset;
4550
4551 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4552 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4553 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4554
4555 if (iview->image->info.samples > 1)
4556 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4557
4558 if (device->physical_device->rad_info.chip_class >= GFX7) {
4559 struct radeon_info *info = &device->physical_device->rad_info;
4560 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4561 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4562 unsigned macro_index = surf->u.legacy.macro_tile_index;
4563 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4564 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4565 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4566
4567 if (stencil_only)
4568 tile_mode = stencil_tile_mode;
4569
4570 ds->db_depth_info |=
4571 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4572 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4573 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4574 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4575 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4576 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4577 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4578 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4579 } else {
4580 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4581 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4582 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4583 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4584 if (stencil_only)
4585 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4586 }
4587
4588 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4589 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4590 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4591
4592 if (radv_htile_enabled(iview->image, level)) {
4593 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4594
4595 if (!surf->has_stencil &&
4596 !radv_image_is_tc_compat_htile(iview->image))
4597 /* Use all of the htile_buffer for depth if there's no stencil. */
4598 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4599
4600 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4601 iview->image->htile_offset;
4602 ds->db_htile_data_base = va >> 8;
4603 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4604
4605 if (radv_image_is_tc_compat_htile(iview->image)) {
4606 unsigned max_zplanes =
4607 radv_calc_decompress_on_z_planes(device, iview);
4608
4609 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4610 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4611 }
4612 }
4613 }
4614
4615 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4616 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4617 }
4618
4619 VkResult radv_CreateFramebuffer(
4620 VkDevice _device,
4621 const VkFramebufferCreateInfo* pCreateInfo,
4622 const VkAllocationCallbacks* pAllocator,
4623 VkFramebuffer* pFramebuffer)
4624 {
4625 RADV_FROM_HANDLE(radv_device, device, _device);
4626 struct radv_framebuffer *framebuffer;
4627
4628 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4629
4630 size_t size = sizeof(*framebuffer) +
4631 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4632 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4633 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4634 if (framebuffer == NULL)
4635 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4636
4637 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4638 framebuffer->width = pCreateInfo->width;
4639 framebuffer->height = pCreateInfo->height;
4640 framebuffer->layers = pCreateInfo->layers;
4641 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4642 VkImageView _iview = pCreateInfo->pAttachments[i];
4643 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4644 framebuffer->attachments[i].attachment = iview;
4645 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4646 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4647 } else {
4648 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4649 }
4650 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4651 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4652 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4653 }
4654
4655 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4656 return VK_SUCCESS;
4657 }
4658
4659 void radv_DestroyFramebuffer(
4660 VkDevice _device,
4661 VkFramebuffer _fb,
4662 const VkAllocationCallbacks* pAllocator)
4663 {
4664 RADV_FROM_HANDLE(radv_device, device, _device);
4665 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4666
4667 if (!fb)
4668 return;
4669 vk_free2(&device->alloc, pAllocator, fb);
4670 }
4671
4672 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4673 {
4674 switch (address_mode) {
4675 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4676 return V_008F30_SQ_TEX_WRAP;
4677 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4678 return V_008F30_SQ_TEX_MIRROR;
4679 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4680 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4681 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4682 return V_008F30_SQ_TEX_CLAMP_BORDER;
4683 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4684 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4685 default:
4686 unreachable("illegal tex wrap mode");
4687 break;
4688 }
4689 }
4690
4691 static unsigned
4692 radv_tex_compare(VkCompareOp op)
4693 {
4694 switch (op) {
4695 case VK_COMPARE_OP_NEVER:
4696 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4697 case VK_COMPARE_OP_LESS:
4698 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4699 case VK_COMPARE_OP_EQUAL:
4700 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4701 case VK_COMPARE_OP_LESS_OR_EQUAL:
4702 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4703 case VK_COMPARE_OP_GREATER:
4704 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4705 case VK_COMPARE_OP_NOT_EQUAL:
4706 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4707 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4708 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4709 case VK_COMPARE_OP_ALWAYS:
4710 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4711 default:
4712 unreachable("illegal compare mode");
4713 break;
4714 }
4715 }
4716
4717 static unsigned
4718 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4719 {
4720 switch (filter) {
4721 case VK_FILTER_NEAREST:
4722 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4723 V_008F38_SQ_TEX_XY_FILTER_POINT);
4724 case VK_FILTER_LINEAR:
4725 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4726 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4727 case VK_FILTER_CUBIC_IMG:
4728 default:
4729 fprintf(stderr, "illegal texture filter");
4730 return 0;
4731 }
4732 }
4733
4734 static unsigned
4735 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4736 {
4737 switch (mode) {
4738 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4739 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4740 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4741 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4742 default:
4743 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4744 }
4745 }
4746
4747 static unsigned
4748 radv_tex_bordercolor(VkBorderColor bcolor)
4749 {
4750 switch (bcolor) {
4751 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4752 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4753 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4754 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4755 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4756 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4757 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4758 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4759 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4760 default:
4761 break;
4762 }
4763 return 0;
4764 }
4765
4766 static unsigned
4767 radv_tex_aniso_filter(unsigned filter)
4768 {
4769 if (filter < 2)
4770 return 0;
4771 if (filter < 4)
4772 return 1;
4773 if (filter < 8)
4774 return 2;
4775 if (filter < 16)
4776 return 3;
4777 return 4;
4778 }
4779
4780 static unsigned
4781 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4782 {
4783 switch (mode) {
4784 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4785 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4786 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4787 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4788 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4789 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4790 default:
4791 break;
4792 }
4793 return 0;
4794 }
4795
4796 static uint32_t
4797 radv_get_max_anisotropy(struct radv_device *device,
4798 const VkSamplerCreateInfo *pCreateInfo)
4799 {
4800 if (device->force_aniso >= 0)
4801 return device->force_aniso;
4802
4803 if (pCreateInfo->anisotropyEnable &&
4804 pCreateInfo->maxAnisotropy > 1.0f)
4805 return (uint32_t)pCreateInfo->maxAnisotropy;
4806
4807 return 0;
4808 }
4809
4810 static void
4811 radv_init_sampler(struct radv_device *device,
4812 struct radv_sampler *sampler,
4813 const VkSamplerCreateInfo *pCreateInfo)
4814 {
4815 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4816 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4817 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4818 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4819
4820 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4821 vk_find_struct_const(pCreateInfo->pNext,
4822 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4823 if (sampler_reduction)
4824 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4825
4826 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4827 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4828 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4829 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4830 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4831 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4832 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4833 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4834 S_008F30_DISABLE_CUBE_WRAP(0) |
4835 S_008F30_COMPAT_MODE(is_vi) |
4836 S_008F30_FILTER_MODE(filter_mode));
4837 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4838 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4839 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4840 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4841 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4842 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4843 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4844 S_008F38_MIP_POINT_PRECLAMP(0) |
4845 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4846 S_008F38_FILTER_PREC_FIX(1) |
4847 S_008F38_ANISO_OVERRIDE(is_vi));
4848 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4849 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4850 }
4851
4852 VkResult radv_CreateSampler(
4853 VkDevice _device,
4854 const VkSamplerCreateInfo* pCreateInfo,
4855 const VkAllocationCallbacks* pAllocator,
4856 VkSampler* pSampler)
4857 {
4858 RADV_FROM_HANDLE(radv_device, device, _device);
4859 struct radv_sampler *sampler;
4860
4861 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4862 vk_find_struct_const(pCreateInfo->pNext,
4863 SAMPLER_YCBCR_CONVERSION_INFO);
4864
4865 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4866
4867 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4869 if (!sampler)
4870 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4871
4872 radv_init_sampler(device, sampler, pCreateInfo);
4873
4874 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4875 *pSampler = radv_sampler_to_handle(sampler);
4876
4877 return VK_SUCCESS;
4878 }
4879
4880 void radv_DestroySampler(
4881 VkDevice _device,
4882 VkSampler _sampler,
4883 const VkAllocationCallbacks* pAllocator)
4884 {
4885 RADV_FROM_HANDLE(radv_device, device, _device);
4886 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4887
4888 if (!sampler)
4889 return;
4890 vk_free2(&device->alloc, pAllocator, sampler);
4891 }
4892
4893 /* vk_icd.h does not declare this function, so we declare it here to
4894 * suppress Wmissing-prototypes.
4895 */
4896 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4897 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4898
4899 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4900 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4901 {
4902 /* For the full details on loader interface versioning, see
4903 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4904 * What follows is a condensed summary, to help you navigate the large and
4905 * confusing official doc.
4906 *
4907 * - Loader interface v0 is incompatible with later versions. We don't
4908 * support it.
4909 *
4910 * - In loader interface v1:
4911 * - The first ICD entrypoint called by the loader is
4912 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4913 * entrypoint.
4914 * - The ICD must statically expose no other Vulkan symbol unless it is
4915 * linked with -Bsymbolic.
4916 * - Each dispatchable Vulkan handle created by the ICD must be
4917 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4918 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4919 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4920 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4921 * such loader-managed surfaces.
4922 *
4923 * - Loader interface v2 differs from v1 in:
4924 * - The first ICD entrypoint called by the loader is
4925 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4926 * statically expose this entrypoint.
4927 *
4928 * - Loader interface v3 differs from v2 in:
4929 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4930 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4931 * because the loader no longer does so.
4932 */
4933 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4934 return VK_SUCCESS;
4935 }
4936
4937 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4938 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4939 int *pFD)
4940 {
4941 RADV_FROM_HANDLE(radv_device, device, _device);
4942 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4943
4944 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4945
4946 /* At the moment, we support only the below handle types. */
4947 assert(pGetFdInfo->handleType ==
4948 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4949 pGetFdInfo->handleType ==
4950 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4951
4952 bool ret = radv_get_memory_fd(device, memory, pFD);
4953 if (ret == false)
4954 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4955 return VK_SUCCESS;
4956 }
4957
4958 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4959 VkExternalMemoryHandleTypeFlagBits handleType,
4960 int fd,
4961 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4962 {
4963 RADV_FROM_HANDLE(radv_device, device, _device);
4964
4965 switch (handleType) {
4966 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4967 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4968 return VK_SUCCESS;
4969
4970 default:
4971 /* The valid usage section for this function says:
4972 *
4973 * "handleType must not be one of the handle types defined as
4974 * opaque."
4975 *
4976 * So opaque handle types fall into the default "unsupported" case.
4977 */
4978 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4979 }
4980 }
4981
4982 static VkResult radv_import_opaque_fd(struct radv_device *device,
4983 int fd,
4984 uint32_t *syncobj)
4985 {
4986 uint32_t syncobj_handle = 0;
4987 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4988 if (ret != 0)
4989 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4990
4991 if (*syncobj)
4992 device->ws->destroy_syncobj(device->ws, *syncobj);
4993
4994 *syncobj = syncobj_handle;
4995 close(fd);
4996
4997 return VK_SUCCESS;
4998 }
4999
5000 static VkResult radv_import_sync_fd(struct radv_device *device,
5001 int fd,
5002 uint32_t *syncobj)
5003 {
5004 /* If we create a syncobj we do it locally so that if we have an error, we don't
5005 * leave a syncobj in an undetermined state in the fence. */
5006 uint32_t syncobj_handle = *syncobj;
5007 if (!syncobj_handle) {
5008 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5009 if (ret) {
5010 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5011 }
5012 }
5013
5014 if (fd == -1) {
5015 device->ws->signal_syncobj(device->ws, syncobj_handle);
5016 } else {
5017 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5018 if (ret != 0)
5019 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5020 }
5021
5022 *syncobj = syncobj_handle;
5023 if (fd != -1)
5024 close(fd);
5025
5026 return VK_SUCCESS;
5027 }
5028
5029 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5030 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5031 {
5032 RADV_FROM_HANDLE(radv_device, device, _device);
5033 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5034 uint32_t *syncobj_dst = NULL;
5035
5036 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5037 syncobj_dst = &sem->temp_syncobj;
5038 } else {
5039 syncobj_dst = &sem->syncobj;
5040 }
5041
5042 switch(pImportSemaphoreFdInfo->handleType) {
5043 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5044 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5045 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5046 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5047 default:
5048 unreachable("Unhandled semaphore handle type");
5049 }
5050 }
5051
5052 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5053 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5054 int *pFd)
5055 {
5056 RADV_FROM_HANDLE(radv_device, device, _device);
5057 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5058 int ret;
5059 uint32_t syncobj_handle;
5060
5061 if (sem->temp_syncobj)
5062 syncobj_handle = sem->temp_syncobj;
5063 else
5064 syncobj_handle = sem->syncobj;
5065
5066 switch(pGetFdInfo->handleType) {
5067 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5068 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5069 break;
5070 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5071 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5072 if (!ret) {
5073 if (sem->temp_syncobj) {
5074 close (sem->temp_syncobj);
5075 sem->temp_syncobj = 0;
5076 } else {
5077 device->ws->reset_syncobj(device->ws, syncobj_handle);
5078 }
5079 }
5080 break;
5081 default:
5082 unreachable("Unhandled semaphore handle type");
5083 }
5084
5085 if (ret)
5086 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5087 return VK_SUCCESS;
5088 }
5089
5090 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5091 VkPhysicalDevice physicalDevice,
5092 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5093 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5094 {
5095 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5096
5097 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5098 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5099 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5100 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5101 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5102 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5103 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5104 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5105 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5106 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5107 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5108 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5109 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5110 } else {
5111 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5112 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5113 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5114 }
5115 }
5116
5117 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5118 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5119 {
5120 RADV_FROM_HANDLE(radv_device, device, _device);
5121 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5122 uint32_t *syncobj_dst = NULL;
5123
5124
5125 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5126 syncobj_dst = &fence->temp_syncobj;
5127 } else {
5128 syncobj_dst = &fence->syncobj;
5129 }
5130
5131 switch(pImportFenceFdInfo->handleType) {
5132 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5133 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5134 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5135 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5136 default:
5137 unreachable("Unhandled fence handle type");
5138 }
5139 }
5140
5141 VkResult radv_GetFenceFdKHR(VkDevice _device,
5142 const VkFenceGetFdInfoKHR *pGetFdInfo,
5143 int *pFd)
5144 {
5145 RADV_FROM_HANDLE(radv_device, device, _device);
5146 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5147 int ret;
5148 uint32_t syncobj_handle;
5149
5150 if (fence->temp_syncobj)
5151 syncobj_handle = fence->temp_syncobj;
5152 else
5153 syncobj_handle = fence->syncobj;
5154
5155 switch(pGetFdInfo->handleType) {
5156 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5157 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5158 break;
5159 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5160 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5161 if (!ret) {
5162 if (fence->temp_syncobj) {
5163 close (fence->temp_syncobj);
5164 fence->temp_syncobj = 0;
5165 } else {
5166 device->ws->reset_syncobj(device->ws, syncobj_handle);
5167 }
5168 }
5169 break;
5170 default:
5171 unreachable("Unhandled fence handle type");
5172 }
5173
5174 if (ret)
5175 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5176 return VK_SUCCESS;
5177 }
5178
5179 void radv_GetPhysicalDeviceExternalFenceProperties(
5180 VkPhysicalDevice physicalDevice,
5181 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5182 VkExternalFenceProperties *pExternalFenceProperties)
5183 {
5184 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5185
5186 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5187 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5188 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5189 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5190 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5191 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5192 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5193 } else {
5194 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5195 pExternalFenceProperties->compatibleHandleTypes = 0;
5196 pExternalFenceProperties->externalFenceFeatures = 0;
5197 }
5198 }
5199
5200 VkResult
5201 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5202 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5203 const VkAllocationCallbacks* pAllocator,
5204 VkDebugReportCallbackEXT* pCallback)
5205 {
5206 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5207 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5208 pCreateInfo, pAllocator, &instance->alloc,
5209 pCallback);
5210 }
5211
5212 void
5213 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5214 VkDebugReportCallbackEXT _callback,
5215 const VkAllocationCallbacks* pAllocator)
5216 {
5217 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5218 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5219 _callback, pAllocator, &instance->alloc);
5220 }
5221
5222 void
5223 radv_DebugReportMessageEXT(VkInstance _instance,
5224 VkDebugReportFlagsEXT flags,
5225 VkDebugReportObjectTypeEXT objectType,
5226 uint64_t object,
5227 size_t location,
5228 int32_t messageCode,
5229 const char* pLayerPrefix,
5230 const char* pMessage)
5231 {
5232 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5233 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5234 object, location, messageCode, pLayerPrefix, pMessage);
5235 }
5236
5237 void
5238 radv_GetDeviceGroupPeerMemoryFeatures(
5239 VkDevice device,
5240 uint32_t heapIndex,
5241 uint32_t localDeviceIndex,
5242 uint32_t remoteDeviceIndex,
5243 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5244 {
5245 assert(localDeviceIndex == remoteDeviceIndex);
5246
5247 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5248 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5249 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5250 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5251 }
5252
5253 static const VkTimeDomainEXT radv_time_domains[] = {
5254 VK_TIME_DOMAIN_DEVICE_EXT,
5255 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5256 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5257 };
5258
5259 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5260 VkPhysicalDevice physicalDevice,
5261 uint32_t *pTimeDomainCount,
5262 VkTimeDomainEXT *pTimeDomains)
5263 {
5264 int d;
5265 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5266
5267 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5268 vk_outarray_append(&out, i) {
5269 *i = radv_time_domains[d];
5270 }
5271 }
5272
5273 return vk_outarray_status(&out);
5274 }
5275
5276 static uint64_t
5277 radv_clock_gettime(clockid_t clock_id)
5278 {
5279 struct timespec current;
5280 int ret;
5281
5282 ret = clock_gettime(clock_id, &current);
5283 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5284 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5285 if (ret < 0)
5286 return 0;
5287
5288 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5289 }
5290
5291 VkResult radv_GetCalibratedTimestampsEXT(
5292 VkDevice _device,
5293 uint32_t timestampCount,
5294 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5295 uint64_t *pTimestamps,
5296 uint64_t *pMaxDeviation)
5297 {
5298 RADV_FROM_HANDLE(radv_device, device, _device);
5299 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5300 int d;
5301 uint64_t begin, end;
5302 uint64_t max_clock_period = 0;
5303
5304 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5305
5306 for (d = 0; d < timestampCount; d++) {
5307 switch (pTimestampInfos[d].timeDomain) {
5308 case VK_TIME_DOMAIN_DEVICE_EXT:
5309 pTimestamps[d] = device->ws->query_value(device->ws,
5310 RADEON_TIMESTAMP);
5311 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5312 max_clock_period = MAX2(max_clock_period, device_period);
5313 break;
5314 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5315 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5316 max_clock_period = MAX2(max_clock_period, 1);
5317 break;
5318
5319 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5320 pTimestamps[d] = begin;
5321 break;
5322 default:
5323 pTimestamps[d] = 0;
5324 break;
5325 }
5326 }
5327
5328 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5329
5330 /*
5331 * The maximum deviation is the sum of the interval over which we
5332 * perform the sampling and the maximum period of any sampled
5333 * clock. That's because the maximum skew between any two sampled
5334 * clock edges is when the sampled clock with the largest period is
5335 * sampled at the end of that period but right at the beginning of the
5336 * sampling interval and some other clock is sampled right at the
5337 * begining of its sampling period and right at the end of the
5338 * sampling interval. Let's assume the GPU has the longest clock
5339 * period and that the application is sampling GPU and monotonic:
5340 *
5341 * s e
5342 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5343 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5344 *
5345 * g
5346 * 0 1 2 3
5347 * GPU -----_____-----_____-----_____-----_____
5348 *
5349 * m
5350 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5351 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5352 *
5353 * Interval <----------------->
5354 * Deviation <-------------------------->
5355 *
5356 * s = read(raw) 2
5357 * g = read(GPU) 1
5358 * m = read(monotonic) 2
5359 * e = read(raw) b
5360 *
5361 * We round the sample interval up by one tick to cover sampling error
5362 * in the interval clock
5363 */
5364
5365 uint64_t sample_interval = end - begin + 1;
5366
5367 *pMaxDeviation = sample_interval + max_clock_period;
5368
5369 return VK_SUCCESS;
5370 }