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radv: Add startup debug option.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0) {
231 if (instance->debug_flags & RADV_DEBUG_STARTUP)
232 radv_logi("Could not open device '%s'", path);
233
234 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
235 }
236
237 version = drmGetVersion(fd);
238 if (!version) {
239 close(fd);
240
241 if (instance->debug_flags & RADV_DEBUG_STARTUP)
242 radv_logi("Could not get the kernel driver version for device '%s'", path);
243
244 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
245 "failed to get version %s: %m", path);
246 }
247
248 if (strcmp(version->name, "amdgpu")) {
249 drmFreeVersion(version);
250 close(fd);
251
252 if (instance->debug_flags & RADV_DEBUG_STARTUP)
253 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
254
255 return VK_ERROR_INCOMPATIBLE_DRIVER;
256 }
257 drmFreeVersion(version);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Found compatible device '%s'.", path);
261
262 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
263 device->instance = instance;
264 assert(strlen(path) < ARRAY_SIZE(device->path));
265 strncpy(device->path, path, ARRAY_SIZE(device->path));
266
267 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
268 instance->perftest_flags);
269 if (!device->ws) {
270 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
271 goto fail;
272 }
273
274 device->local_fd = fd;
275 device->ws->query_info(device->ws, &device->rad_info);
276
277 radv_handle_env_var_force_family(device);
278
279 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
280
281 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
282 device->ws->destroy(device->ws);
283 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
284 "cannot generate UUID");
285 goto fail;
286 }
287
288 /* These flags affect shader compilation. */
289 uint64_t shader_env_flags =
290 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
291 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
292
293 /* The gpu id is already embedded in the uuid so we just pass "radv"
294 * when creating the cache.
295 */
296 char buf[VK_UUID_SIZE * 2 + 1];
297 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
298 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
299
300 if (device->rad_info.chip_class < VI ||
301 device->rad_info.chip_class > GFX9)
302 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
303
304 radv_get_driver_uuid(&device->device_uuid);
305 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
306
307 if (device->rad_info.family == CHIP_STONEY ||
308 device->rad_info.chip_class >= GFX9) {
309 device->has_rbplus = true;
310 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
311 device->rad_info.family == CHIP_VEGA12 ||
312 device->rad_info.family == CHIP_RAVEN;
313 }
314
315 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
316 * on SI.
317 */
318 device->has_clear_state = device->rad_info.chip_class >= CIK;
319
320 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
321
322 /* Vega10/Raven need a special workaround for a hardware bug. */
323 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
324 device->rad_info.family == CHIP_RAVEN;
325
326 /* Out-of-order primitive rasterization. */
327 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
328 device->rad_info.max_se >= 2;
329 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
330 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
331
332 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
333 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
334
335 radv_physical_device_init_mem_types(device);
336 radv_fill_device_extension_table(device, &device->supported_extensions);
337
338 result = radv_init_wsi(device);
339 if (result != VK_SUCCESS) {
340 device->ws->destroy(device->ws);
341 vk_error(instance, result);
342 goto fail;
343 }
344
345 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
346 ac_print_gpu_info(&device->rad_info);
347
348 return VK_SUCCESS;
349
350 fail:
351 close(fd);
352 return result;
353 }
354
355 static void
356 radv_physical_device_finish(struct radv_physical_device *device)
357 {
358 radv_finish_wsi(device);
359 device->ws->destroy(device->ws);
360 disk_cache_destroy(device->disk_cache);
361 close(device->local_fd);
362 }
363
364 static void *
365 default_alloc_func(void *pUserData, size_t size, size_t align,
366 VkSystemAllocationScope allocationScope)
367 {
368 return malloc(size);
369 }
370
371 static void *
372 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
373 size_t align, VkSystemAllocationScope allocationScope)
374 {
375 return realloc(pOriginal, size);
376 }
377
378 static void
379 default_free_func(void *pUserData, void *pMemory)
380 {
381 free(pMemory);
382 }
383
384 static const VkAllocationCallbacks default_alloc = {
385 .pUserData = NULL,
386 .pfnAllocation = default_alloc_func,
387 .pfnReallocation = default_realloc_func,
388 .pfnFree = default_free_func,
389 };
390
391 static const struct debug_control radv_debug_options[] = {
392 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
393 {"nodcc", RADV_DEBUG_NO_DCC},
394 {"shaders", RADV_DEBUG_DUMP_SHADERS},
395 {"nocache", RADV_DEBUG_NO_CACHE},
396 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
397 {"nohiz", RADV_DEBUG_NO_HIZ},
398 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
399 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
400 {"allbos", RADV_DEBUG_ALL_BOS},
401 {"noibs", RADV_DEBUG_NO_IBS},
402 {"spirv", RADV_DEBUG_DUMP_SPIRV},
403 {"vmfaults", RADV_DEBUG_VM_FAULTS},
404 {"zerovram", RADV_DEBUG_ZERO_VRAM},
405 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
406 {"nosisched", RADV_DEBUG_NO_SISCHED},
407 {"preoptir", RADV_DEBUG_PREOPTIR},
408 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
409 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
410 {"info", RADV_DEBUG_INFO},
411 {"errors", RADV_DEBUG_ERRORS},
412 {"startup", RADV_DEBUG_STARTUP},
413 {NULL, 0}
414 };
415
416 const char *
417 radv_get_debug_option_name(int id)
418 {
419 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
420 return radv_debug_options[id].string;
421 }
422
423 static const struct debug_control radv_perftest_options[] = {
424 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
425 {"sisched", RADV_PERFTEST_SISCHED},
426 {"localbos", RADV_PERFTEST_LOCAL_BOS},
427 {"binning", RADV_PERFTEST_BINNING},
428 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
429 {NULL, 0}
430 };
431
432 const char *
433 radv_get_perftest_option_name(int id)
434 {
435 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
436 return radv_perftest_options[id].string;
437 }
438
439 static void
440 radv_handle_per_app_options(struct radv_instance *instance,
441 const VkApplicationInfo *info)
442 {
443 const char *name = info ? info->pApplicationName : NULL;
444
445 if (!name)
446 return;
447
448 if (!strcmp(name, "Talos - Linux - 32bit") ||
449 !strcmp(name, "Talos - Linux - 64bit")) {
450 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
451 /* Force enable LLVM sisched for Talos because it looks
452 * safe and it gives few more FPS.
453 */
454 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
455 }
456 }
457 }
458
459 static int radv_get_instance_extension_index(const char *name)
460 {
461 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
462 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
463 return i;
464 }
465 return -1;
466 }
467
468
469 VkResult radv_CreateInstance(
470 const VkInstanceCreateInfo* pCreateInfo,
471 const VkAllocationCallbacks* pAllocator,
472 VkInstance* pInstance)
473 {
474 struct radv_instance *instance;
475 VkResult result;
476
477 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
478
479 uint32_t client_version;
480 if (pCreateInfo->pApplicationInfo &&
481 pCreateInfo->pApplicationInfo->apiVersion != 0) {
482 client_version = pCreateInfo->pApplicationInfo->apiVersion;
483 } else {
484 radv_EnumerateInstanceVersion(&client_version);
485 }
486
487 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
488 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
489 if (!instance)
490 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
491
492 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
493
494 if (pAllocator)
495 instance->alloc = *pAllocator;
496 else
497 instance->alloc = default_alloc;
498
499 instance->apiVersion = client_version;
500 instance->physicalDeviceCount = -1;
501
502 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
503 radv_debug_options);
504
505 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
506 radv_perftest_options);
507
508
509 if (instance->debug_flags & RADV_DEBUG_STARTUP)
510 radv_logi("Created an instance");
511
512 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
513 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
514 int index = radv_get_instance_extension_index(ext_name);
515
516 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
517 vk_free2(&default_alloc, pAllocator, instance);
518 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
519 }
520
521 instance->enabled_extensions.extensions[index] = true;
522 }
523
524 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
525 if (result != VK_SUCCESS) {
526 vk_free2(&default_alloc, pAllocator, instance);
527 return vk_error(instance, result);
528 }
529
530 _mesa_locale_init();
531
532 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
533
534 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
535
536 *pInstance = radv_instance_to_handle(instance);
537
538 return VK_SUCCESS;
539 }
540
541 void radv_DestroyInstance(
542 VkInstance _instance,
543 const VkAllocationCallbacks* pAllocator)
544 {
545 RADV_FROM_HANDLE(radv_instance, instance, _instance);
546
547 if (!instance)
548 return;
549
550 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
551 radv_physical_device_finish(instance->physicalDevices + i);
552 }
553
554 VG(VALGRIND_DESTROY_MEMPOOL(instance));
555
556 _mesa_locale_fini();
557
558 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
559
560 vk_free(&instance->alloc, instance);
561 }
562
563 static VkResult
564 radv_enumerate_devices(struct radv_instance *instance)
565 {
566 /* TODO: Check for more devices ? */
567 drmDevicePtr devices[8];
568 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
569 int max_devices;
570
571 instance->physicalDeviceCount = 0;
572
573 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
574
575 if (instance->debug_flags & RADV_DEBUG_STARTUP)
576 radv_logi("Found %d drm nodes", max_devices);
577
578 if (max_devices < 1)
579 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
580
581 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
582 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
583 devices[i]->bustype == DRM_BUS_PCI &&
584 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
585
586 result = radv_physical_device_init(instance->physicalDevices +
587 instance->physicalDeviceCount,
588 instance,
589 devices[i]);
590 if (result == VK_SUCCESS)
591 ++instance->physicalDeviceCount;
592 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
593 break;
594 }
595 }
596 drmFreeDevices(devices, max_devices);
597
598 return result;
599 }
600
601 VkResult radv_EnumeratePhysicalDevices(
602 VkInstance _instance,
603 uint32_t* pPhysicalDeviceCount,
604 VkPhysicalDevice* pPhysicalDevices)
605 {
606 RADV_FROM_HANDLE(radv_instance, instance, _instance);
607 VkResult result;
608
609 if (instance->physicalDeviceCount < 0) {
610 result = radv_enumerate_devices(instance);
611 if (result != VK_SUCCESS &&
612 result != VK_ERROR_INCOMPATIBLE_DRIVER)
613 return result;
614 }
615
616 if (!pPhysicalDevices) {
617 *pPhysicalDeviceCount = instance->physicalDeviceCount;
618 } else {
619 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
620 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
621 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
622 }
623
624 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
625 : VK_SUCCESS;
626 }
627
628 VkResult radv_EnumeratePhysicalDeviceGroups(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceGroupCount,
631 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDeviceGroupProperties) {
644 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
648 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
649 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
650 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
651 }
652 }
653 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
654 : VK_SUCCESS;
655 }
656
657 void radv_GetPhysicalDeviceFeatures(
658 VkPhysicalDevice physicalDevice,
659 VkPhysicalDeviceFeatures* pFeatures)
660 {
661 memset(pFeatures, 0, sizeof(*pFeatures));
662
663 *pFeatures = (VkPhysicalDeviceFeatures) {
664 .robustBufferAccess = true,
665 .fullDrawIndexUint32 = true,
666 .imageCubeArray = true,
667 .independentBlend = true,
668 .geometryShader = true,
669 .tessellationShader = true,
670 .sampleRateShading = true,
671 .dualSrcBlend = true,
672 .logicOp = true,
673 .multiDrawIndirect = true,
674 .drawIndirectFirstInstance = true,
675 .depthClamp = true,
676 .depthBiasClamp = true,
677 .fillModeNonSolid = true,
678 .depthBounds = true,
679 .wideLines = true,
680 .largePoints = true,
681 .alphaToOne = true,
682 .multiViewport = true,
683 .samplerAnisotropy = true,
684 .textureCompressionETC2 = false,
685 .textureCompressionASTC_LDR = false,
686 .textureCompressionBC = true,
687 .occlusionQueryPrecise = true,
688 .pipelineStatisticsQuery = true,
689 .vertexPipelineStoresAndAtomics = true,
690 .fragmentStoresAndAtomics = true,
691 .shaderTessellationAndGeometryPointSize = true,
692 .shaderImageGatherExtended = true,
693 .shaderStorageImageExtendedFormats = true,
694 .shaderStorageImageMultisample = false,
695 .shaderUniformBufferArrayDynamicIndexing = true,
696 .shaderSampledImageArrayDynamicIndexing = true,
697 .shaderStorageBufferArrayDynamicIndexing = true,
698 .shaderStorageImageArrayDynamicIndexing = true,
699 .shaderStorageImageReadWithoutFormat = true,
700 .shaderStorageImageWriteWithoutFormat = true,
701 .shaderClipDistance = true,
702 .shaderCullDistance = true,
703 .shaderFloat64 = true,
704 .shaderInt64 = true,
705 .shaderInt16 = false,
706 .sparseBinding = true,
707 .variableMultisampleRate = true,
708 .inheritedQueries = true,
709 };
710 }
711
712 void radv_GetPhysicalDeviceFeatures2(
713 VkPhysicalDevice physicalDevice,
714 VkPhysicalDeviceFeatures2KHR *pFeatures)
715 {
716 vk_foreach_struct(ext, pFeatures->pNext) {
717 switch (ext->sType) {
718 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
719 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
720 features->variablePointersStorageBuffer = true;
721 features->variablePointers = false;
722 break;
723 }
724 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
725 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
726 features->multiview = true;
727 features->multiviewGeometryShader = true;
728 features->multiviewTessellationShader = true;
729 break;
730 }
731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
732 VkPhysicalDeviceShaderDrawParameterFeatures *features =
733 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
734 features->shaderDrawParameters = true;
735 break;
736 }
737 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
738 VkPhysicalDeviceProtectedMemoryFeatures *features =
739 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
740 features->protectedMemory = false;
741 break;
742 }
743 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
744 VkPhysicalDevice16BitStorageFeatures *features =
745 (VkPhysicalDevice16BitStorageFeatures*)ext;
746 features->storageBuffer16BitAccess = false;
747 features->uniformAndStorageBuffer16BitAccess = false;
748 features->storagePushConstant16 = false;
749 features->storageInputOutput16 = false;
750 break;
751 }
752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
753 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
754 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
755 features->samplerYcbcrConversion = false;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
759 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
760 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
761 features->shaderInputAttachmentArrayDynamicIndexing = true;
762 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
763 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
764 features->shaderUniformBufferArrayNonUniformIndexing = false;
765 features->shaderSampledImageArrayNonUniformIndexing = false;
766 features->shaderStorageBufferArrayNonUniformIndexing = false;
767 features->shaderStorageImageArrayNonUniformIndexing = false;
768 features->shaderInputAttachmentArrayNonUniformIndexing = false;
769 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
770 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
771 features->descriptorBindingUniformBufferUpdateAfterBind = true;
772 features->descriptorBindingSampledImageUpdateAfterBind = true;
773 features->descriptorBindingStorageImageUpdateAfterBind = true;
774 features->descriptorBindingStorageBufferUpdateAfterBind = true;
775 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
776 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
777 features->descriptorBindingUpdateUnusedWhilePending = true;
778 features->descriptorBindingPartiallyBound = true;
779 features->descriptorBindingVariableDescriptorCount = true;
780 features->runtimeDescriptorArray = true;
781 break;
782 }
783 default:
784 break;
785 }
786 }
787 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
788 }
789
790 void radv_GetPhysicalDeviceProperties(
791 VkPhysicalDevice physicalDevice,
792 VkPhysicalDeviceProperties* pProperties)
793 {
794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
795 VkSampleCountFlags sample_counts = 0xf;
796
797 /* make sure that the entire descriptor set is addressable with a signed
798 * 32-bit int. So the sum of all limits scaled by descriptor size has to
799 * be at most 2 GiB. the combined image & samples object count as one of
800 * both. This limit is for the pipeline layout, not for the set layout, but
801 * there is no set limit, so we just set a pipeline limit. I don't think
802 * any app is going to hit this soon. */
803 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
804 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
805 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
806 32 /* sampler, largest when combined with image */ +
807 64 /* sampled image */ +
808 64 /* storage image */);
809
810 VkPhysicalDeviceLimits limits = {
811 .maxImageDimension1D = (1 << 14),
812 .maxImageDimension2D = (1 << 14),
813 .maxImageDimension3D = (1 << 11),
814 .maxImageDimensionCube = (1 << 14),
815 .maxImageArrayLayers = (1 << 11),
816 .maxTexelBufferElements = 128 * 1024 * 1024,
817 .maxUniformBufferRange = UINT32_MAX,
818 .maxStorageBufferRange = UINT32_MAX,
819 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
820 .maxMemoryAllocationCount = UINT32_MAX,
821 .maxSamplerAllocationCount = 64 * 1024,
822 .bufferImageGranularity = 64, /* A cache line */
823 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
824 .maxBoundDescriptorSets = MAX_SETS,
825 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
826 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
827 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
828 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
829 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
830 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
831 .maxPerStageResources = max_descriptor_set_size,
832 .maxDescriptorSetSamplers = max_descriptor_set_size,
833 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
834 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
835 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
836 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
837 .maxDescriptorSetSampledImages = max_descriptor_set_size,
838 .maxDescriptorSetStorageImages = max_descriptor_set_size,
839 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
840 .maxVertexInputAttributes = 32,
841 .maxVertexInputBindings = 32,
842 .maxVertexInputAttributeOffset = 2047,
843 .maxVertexInputBindingStride = 2048,
844 .maxVertexOutputComponents = 128,
845 .maxTessellationGenerationLevel = 64,
846 .maxTessellationPatchSize = 32,
847 .maxTessellationControlPerVertexInputComponents = 128,
848 .maxTessellationControlPerVertexOutputComponents = 128,
849 .maxTessellationControlPerPatchOutputComponents = 120,
850 .maxTessellationControlTotalOutputComponents = 4096,
851 .maxTessellationEvaluationInputComponents = 128,
852 .maxTessellationEvaluationOutputComponents = 128,
853 .maxGeometryShaderInvocations = 127,
854 .maxGeometryInputComponents = 64,
855 .maxGeometryOutputComponents = 128,
856 .maxGeometryOutputVertices = 256,
857 .maxGeometryTotalOutputComponents = 1024,
858 .maxFragmentInputComponents = 128,
859 .maxFragmentOutputAttachments = 8,
860 .maxFragmentDualSrcAttachments = 1,
861 .maxFragmentCombinedOutputResources = 8,
862 .maxComputeSharedMemorySize = 32768,
863 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
864 .maxComputeWorkGroupInvocations = 2048,
865 .maxComputeWorkGroupSize = {
866 2048,
867 2048,
868 2048
869 },
870 .subPixelPrecisionBits = 4 /* FIXME */,
871 .subTexelPrecisionBits = 4 /* FIXME */,
872 .mipmapPrecisionBits = 4 /* FIXME */,
873 .maxDrawIndexedIndexValue = UINT32_MAX,
874 .maxDrawIndirectCount = UINT32_MAX,
875 .maxSamplerLodBias = 16,
876 .maxSamplerAnisotropy = 16,
877 .maxViewports = MAX_VIEWPORTS,
878 .maxViewportDimensions = { (1 << 14), (1 << 14) },
879 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
880 .viewportSubPixelBits = 8,
881 .minMemoryMapAlignment = 4096, /* A page */
882 .minTexelBufferOffsetAlignment = 1,
883 .minUniformBufferOffsetAlignment = 4,
884 .minStorageBufferOffsetAlignment = 4,
885 .minTexelOffset = -32,
886 .maxTexelOffset = 31,
887 .minTexelGatherOffset = -32,
888 .maxTexelGatherOffset = 31,
889 .minInterpolationOffset = -2,
890 .maxInterpolationOffset = 2,
891 .subPixelInterpolationOffsetBits = 8,
892 .maxFramebufferWidth = (1 << 14),
893 .maxFramebufferHeight = (1 << 14),
894 .maxFramebufferLayers = (1 << 10),
895 .framebufferColorSampleCounts = sample_counts,
896 .framebufferDepthSampleCounts = sample_counts,
897 .framebufferStencilSampleCounts = sample_counts,
898 .framebufferNoAttachmentsSampleCounts = sample_counts,
899 .maxColorAttachments = MAX_RTS,
900 .sampledImageColorSampleCounts = sample_counts,
901 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
902 .sampledImageDepthSampleCounts = sample_counts,
903 .sampledImageStencilSampleCounts = sample_counts,
904 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
905 .maxSampleMaskWords = 1,
906 .timestampComputeAndGraphics = true,
907 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
908 .maxClipDistances = 8,
909 .maxCullDistances = 8,
910 .maxCombinedClipAndCullDistances = 8,
911 .discreteQueuePriorities = 1,
912 .pointSizeRange = { 0.125, 255.875 },
913 .lineWidthRange = { 0.0, 7.9921875 },
914 .pointSizeGranularity = (1.0 / 8.0),
915 .lineWidthGranularity = (1.0 / 128.0),
916 .strictLines = false, /* FINISHME */
917 .standardSampleLocations = true,
918 .optimalBufferCopyOffsetAlignment = 128,
919 .optimalBufferCopyRowPitchAlignment = 128,
920 .nonCoherentAtomSize = 64,
921 };
922
923 *pProperties = (VkPhysicalDeviceProperties) {
924 .apiVersion = radv_physical_device_api_version(pdevice),
925 .driverVersion = vk_get_driver_version(),
926 .vendorID = ATI_VENDOR_ID,
927 .deviceID = pdevice->rad_info.pci_id,
928 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
929 .limits = limits,
930 .sparseProperties = {0},
931 };
932
933 strcpy(pProperties->deviceName, pdevice->name);
934 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
935 }
936
937 void radv_GetPhysicalDeviceProperties2(
938 VkPhysicalDevice physicalDevice,
939 VkPhysicalDeviceProperties2KHR *pProperties)
940 {
941 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
942 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
943
944 vk_foreach_struct(ext, pProperties->pNext) {
945 switch (ext->sType) {
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
947 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
948 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
949 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
950 break;
951 }
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
953 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
954 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
955 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
956 properties->deviceLUIDValid = false;
957 break;
958 }
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
960 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
961 properties->maxMultiviewViewCount = MAX_VIEWS;
962 properties->maxMultiviewInstanceIndex = INT_MAX;
963 break;
964 }
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
966 VkPhysicalDevicePointClippingPropertiesKHR *properties =
967 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
968 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
972 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
973 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
974 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
975 break;
976 }
977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
978 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
979 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
980 properties->minImportedHostPointerAlignment = 4096;
981 break;
982 }
983 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
984 VkPhysicalDeviceSubgroupProperties *properties =
985 (VkPhysicalDeviceSubgroupProperties*)ext;
986 properties->subgroupSize = 64;
987 properties->supportedStages = VK_SHADER_STAGE_ALL;
988 properties->supportedOperations =
989 VK_SUBGROUP_FEATURE_BASIC_BIT |
990 VK_SUBGROUP_FEATURE_BALLOT_BIT |
991 VK_SUBGROUP_FEATURE_QUAD_BIT |
992 VK_SUBGROUP_FEATURE_VOTE_BIT;
993 if (pdevice->rad_info.chip_class >= VI) {
994 properties->supportedOperations |=
995 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
996 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
997 }
998 properties->quadOperationsInAllStages = true;
999 break;
1000 }
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1002 VkPhysicalDeviceMaintenance3Properties *properties =
1003 (VkPhysicalDeviceMaintenance3Properties*)ext;
1004 /* Make sure everything is addressable by a signed 32-bit int, and
1005 * our largest descriptors are 96 bytes. */
1006 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1007 /* Our buffer size fields allow only this much */
1008 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1012 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1013 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1014 /* GFX6-8 only support single channel min/max filter. */
1015 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1016 properties->filterMinmaxSingleComponentFormats = true;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1020 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1021 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1022
1023 /* Shader engines. */
1024 properties->shaderEngineCount =
1025 pdevice->rad_info.max_se;
1026 properties->shaderArraysPerEngineCount =
1027 pdevice->rad_info.max_sh_per_se;
1028 properties->computeUnitsPerShaderArray =
1029 pdevice->rad_info.num_good_compute_units /
1030 (pdevice->rad_info.max_se *
1031 pdevice->rad_info.max_sh_per_se);
1032 properties->simdPerComputeUnit = 4;
1033 properties->wavefrontsPerSimd =
1034 pdevice->rad_info.family == CHIP_TONGA ||
1035 pdevice->rad_info.family == CHIP_ICELAND ||
1036 pdevice->rad_info.family == CHIP_POLARIS10 ||
1037 pdevice->rad_info.family == CHIP_POLARIS11 ||
1038 pdevice->rad_info.family == CHIP_POLARIS12 ||
1039 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1040 properties->wavefrontSize = 64;
1041
1042 /* SGPR. */
1043 properties->sgprsPerSimd =
1044 radv_get_num_physical_sgprs(pdevice);
1045 properties->minSgprAllocation =
1046 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1047 properties->maxSgprAllocation =
1048 pdevice->rad_info.family == CHIP_TONGA ||
1049 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1050 properties->sgprAllocationGranularity =
1051 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1052
1053 /* VGPR. */
1054 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1055 properties->minVgprAllocation = 4;
1056 properties->maxVgprAllocation = 256;
1057 properties->vgprAllocationGranularity = 4;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1061 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1062 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1063 properties->maxVertexAttribDivisor = UINT32_MAX;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1067 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1068 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1069 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1070 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1071 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1072 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1073 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1074 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1075 properties->robustBufferAccessUpdateAfterBind = false;
1076 properties->quadDivergentImplicitLod = false;
1077
1078 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1079 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1080 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1081 32 /* sampler, largest when combined with image */ +
1082 64 /* sampled image */ +
1083 64 /* storage image */);
1084 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1085 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1086 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1087 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1088 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1089 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1090 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1091 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1092 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1093 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1094 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1095 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1096 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1097 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1098 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1099 break;
1100 }
1101 default:
1102 break;
1103 }
1104 }
1105 }
1106
1107 static void radv_get_physical_device_queue_family_properties(
1108 struct radv_physical_device* pdevice,
1109 uint32_t* pCount,
1110 VkQueueFamilyProperties** pQueueFamilyProperties)
1111 {
1112 int num_queue_families = 1;
1113 int idx;
1114 if (pdevice->rad_info.num_compute_rings > 0 &&
1115 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1116 num_queue_families++;
1117
1118 if (pQueueFamilyProperties == NULL) {
1119 *pCount = num_queue_families;
1120 return;
1121 }
1122
1123 if (!*pCount)
1124 return;
1125
1126 idx = 0;
1127 if (*pCount >= 1) {
1128 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1129 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1130 VK_QUEUE_COMPUTE_BIT |
1131 VK_QUEUE_TRANSFER_BIT |
1132 VK_QUEUE_SPARSE_BINDING_BIT,
1133 .queueCount = 1,
1134 .timestampValidBits = 64,
1135 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1136 };
1137 idx++;
1138 }
1139
1140 if (pdevice->rad_info.num_compute_rings > 0 &&
1141 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1142 if (*pCount > idx) {
1143 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1144 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1145 VK_QUEUE_TRANSFER_BIT |
1146 VK_QUEUE_SPARSE_BINDING_BIT,
1147 .queueCount = pdevice->rad_info.num_compute_rings,
1148 .timestampValidBits = 64,
1149 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1150 };
1151 idx++;
1152 }
1153 }
1154 *pCount = idx;
1155 }
1156
1157 void radv_GetPhysicalDeviceQueueFamilyProperties(
1158 VkPhysicalDevice physicalDevice,
1159 uint32_t* pCount,
1160 VkQueueFamilyProperties* pQueueFamilyProperties)
1161 {
1162 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1163 if (!pQueueFamilyProperties) {
1164 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1165 return;
1166 }
1167 VkQueueFamilyProperties *properties[] = {
1168 pQueueFamilyProperties + 0,
1169 pQueueFamilyProperties + 1,
1170 pQueueFamilyProperties + 2,
1171 };
1172 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1173 assert(*pCount <= 3);
1174 }
1175
1176 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1177 VkPhysicalDevice physicalDevice,
1178 uint32_t* pCount,
1179 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1180 {
1181 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1182 if (!pQueueFamilyProperties) {
1183 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1184 return;
1185 }
1186 VkQueueFamilyProperties *properties[] = {
1187 &pQueueFamilyProperties[0].queueFamilyProperties,
1188 &pQueueFamilyProperties[1].queueFamilyProperties,
1189 &pQueueFamilyProperties[2].queueFamilyProperties,
1190 };
1191 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1192 assert(*pCount <= 3);
1193 }
1194
1195 void radv_GetPhysicalDeviceMemoryProperties(
1196 VkPhysicalDevice physicalDevice,
1197 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1198 {
1199 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1200
1201 *pMemoryProperties = physical_device->memory_properties;
1202 }
1203
1204 void radv_GetPhysicalDeviceMemoryProperties2(
1205 VkPhysicalDevice physicalDevice,
1206 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1207 {
1208 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1209 &pMemoryProperties->memoryProperties);
1210 }
1211
1212 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1213 VkDevice _device,
1214 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1215 const void *pHostPointer,
1216 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1217 {
1218 RADV_FROM_HANDLE(radv_device, device, _device);
1219
1220 switch (handleType)
1221 {
1222 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1223 const struct radv_physical_device *physical_device = device->physical_device;
1224 uint32_t memoryTypeBits = 0;
1225 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1226 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1227 memoryTypeBits = (1 << i);
1228 break;
1229 }
1230 }
1231 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1232 return VK_SUCCESS;
1233 }
1234 default:
1235 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1236 }
1237 }
1238
1239 static enum radeon_ctx_priority
1240 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1241 {
1242 /* Default to MEDIUM when a specific global priority isn't requested */
1243 if (!pObj)
1244 return RADEON_CTX_PRIORITY_MEDIUM;
1245
1246 switch(pObj->globalPriority) {
1247 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1248 return RADEON_CTX_PRIORITY_REALTIME;
1249 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1250 return RADEON_CTX_PRIORITY_HIGH;
1251 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1252 return RADEON_CTX_PRIORITY_MEDIUM;
1253 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1254 return RADEON_CTX_PRIORITY_LOW;
1255 default:
1256 unreachable("Illegal global priority value");
1257 return RADEON_CTX_PRIORITY_INVALID;
1258 }
1259 }
1260
1261 static int
1262 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1263 uint32_t queue_family_index, int idx,
1264 VkDeviceQueueCreateFlags flags,
1265 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1266 {
1267 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1268 queue->device = device;
1269 queue->queue_family_index = queue_family_index;
1270 queue->queue_idx = idx;
1271 queue->priority = radv_get_queue_global_priority(global_priority);
1272 queue->flags = flags;
1273
1274 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1275 if (!queue->hw_ctx)
1276 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1277
1278 return VK_SUCCESS;
1279 }
1280
1281 static void
1282 radv_queue_finish(struct radv_queue *queue)
1283 {
1284 if (queue->hw_ctx)
1285 queue->device->ws->ctx_destroy(queue->hw_ctx);
1286
1287 if (queue->initial_full_flush_preamble_cs)
1288 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1289 if (queue->initial_preamble_cs)
1290 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1291 if (queue->continue_preamble_cs)
1292 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1293 if (queue->descriptor_bo)
1294 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1295 if (queue->scratch_bo)
1296 queue->device->ws->buffer_destroy(queue->scratch_bo);
1297 if (queue->esgs_ring_bo)
1298 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1299 if (queue->gsvs_ring_bo)
1300 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1301 if (queue->tess_rings_bo)
1302 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1303 if (queue->compute_scratch_bo)
1304 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1305 }
1306
1307 static void
1308 radv_bo_list_init(struct radv_bo_list *bo_list)
1309 {
1310 pthread_mutex_init(&bo_list->mutex, NULL);
1311 bo_list->list.count = bo_list->capacity = 0;
1312 bo_list->list.bos = NULL;
1313 }
1314
1315 static void
1316 radv_bo_list_finish(struct radv_bo_list *bo_list)
1317 {
1318 free(bo_list->list.bos);
1319 pthread_mutex_destroy(&bo_list->mutex);
1320 }
1321
1322 static VkResult radv_bo_list_add(struct radv_device *device,
1323 struct radeon_winsys_bo *bo)
1324 {
1325 struct radv_bo_list *bo_list = &device->bo_list;
1326
1327 if (unlikely(!device->use_global_bo_list))
1328 return VK_SUCCESS;
1329
1330 pthread_mutex_lock(&bo_list->mutex);
1331 if (bo_list->list.count == bo_list->capacity) {
1332 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1333 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1334
1335 if (!data) {
1336 pthread_mutex_unlock(&bo_list->mutex);
1337 return VK_ERROR_OUT_OF_HOST_MEMORY;
1338 }
1339
1340 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1341 bo_list->capacity = capacity;
1342 }
1343
1344 bo_list->list.bos[bo_list->list.count++] = bo;
1345 pthread_mutex_unlock(&bo_list->mutex);
1346 return VK_SUCCESS;
1347 }
1348
1349 static void radv_bo_list_remove(struct radv_device *device,
1350 struct radeon_winsys_bo *bo)
1351 {
1352 struct radv_bo_list *bo_list = &device->bo_list;
1353
1354 if (unlikely(!device->use_global_bo_list))
1355 return;
1356
1357 pthread_mutex_lock(&bo_list->mutex);
1358 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1359 if (bo_list->list.bos[i] == bo) {
1360 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1361 --bo_list->list.count;
1362 break;
1363 }
1364 }
1365 pthread_mutex_unlock(&bo_list->mutex);
1366 }
1367
1368 static void
1369 radv_device_init_gs_info(struct radv_device *device)
1370 {
1371 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1372 device->physical_device->rad_info.family);
1373 }
1374
1375 static int radv_get_device_extension_index(const char *name)
1376 {
1377 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1378 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1379 return i;
1380 }
1381 return -1;
1382 }
1383
1384 VkResult radv_CreateDevice(
1385 VkPhysicalDevice physicalDevice,
1386 const VkDeviceCreateInfo* pCreateInfo,
1387 const VkAllocationCallbacks* pAllocator,
1388 VkDevice* pDevice)
1389 {
1390 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1391 VkResult result;
1392 struct radv_device *device;
1393
1394 bool keep_shader_info = false;
1395
1396 /* Check enabled features */
1397 if (pCreateInfo->pEnabledFeatures) {
1398 VkPhysicalDeviceFeatures supported_features;
1399 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1400 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1401 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1402 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1403 for (uint32_t i = 0; i < num_features; i++) {
1404 if (enabled_feature[i] && !supported_feature[i])
1405 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1406 }
1407 }
1408
1409 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1410 sizeof(*device), 8,
1411 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1412 if (!device)
1413 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1414
1415 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1416 device->instance = physical_device->instance;
1417 device->physical_device = physical_device;
1418
1419 device->ws = physical_device->ws;
1420 if (pAllocator)
1421 device->alloc = *pAllocator;
1422 else
1423 device->alloc = physical_device->instance->alloc;
1424
1425 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1426 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1427 int index = radv_get_device_extension_index(ext_name);
1428 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1429 vk_free(&device->alloc, device);
1430 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1431 }
1432
1433 device->enabled_extensions.extensions[index] = true;
1434 }
1435
1436 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1437
1438 /* With update after bind we can't attach bo's to the command buffer
1439 * from the descriptor set anymore, so we have to use a global BO list.
1440 */
1441 device->use_global_bo_list =
1442 device->enabled_extensions.EXT_descriptor_indexing;
1443
1444 mtx_init(&device->shader_slab_mutex, mtx_plain);
1445 list_inithead(&device->shader_slabs);
1446
1447 radv_bo_list_init(&device->bo_list);
1448
1449 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1450 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1451 uint32_t qfi = queue_create->queueFamilyIndex;
1452 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1453 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1454
1455 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1456
1457 device->queues[qfi] = vk_alloc(&device->alloc,
1458 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1459 if (!device->queues[qfi]) {
1460 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1461 goto fail;
1462 }
1463
1464 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1465
1466 device->queue_count[qfi] = queue_create->queueCount;
1467
1468 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1469 result = radv_queue_init(device, &device->queues[qfi][q],
1470 qfi, q, queue_create->flags,
1471 global_priority);
1472 if (result != VK_SUCCESS)
1473 goto fail;
1474 }
1475 }
1476
1477 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1478 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1479
1480 /* Disabled and not implemented for now. */
1481 device->dfsm_allowed = device->pbb_allowed && false;
1482
1483 #ifdef ANDROID
1484 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1485 #endif
1486
1487 /* The maximum number of scratch waves. Scratch space isn't divided
1488 * evenly between CUs. The number is only a function of the number of CUs.
1489 * We can decrease the constant to decrease the scratch buffer size.
1490 *
1491 * sctx->scratch_waves must be >= the maximum possible size of
1492 * 1 threadgroup, so that the hw doesn't hang from being unable
1493 * to start any.
1494 *
1495 * The recommended value is 4 per CU at most. Higher numbers don't
1496 * bring much benefit, but they still occupy chip resources (think
1497 * async compute). I've seen ~2% performance difference between 4 and 32.
1498 */
1499 uint32_t max_threads_per_block = 2048;
1500 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1501 max_threads_per_block / 64);
1502
1503 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1504
1505 if (device->physical_device->rad_info.chip_class >= CIK) {
1506 /* If the KMD allows it (there is a KMD hw register for it),
1507 * allow launching waves out-of-order.
1508 */
1509 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1510 }
1511
1512 radv_device_init_gs_info(device);
1513
1514 device->tess_offchip_block_dw_size =
1515 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1516 device->has_distributed_tess =
1517 device->physical_device->rad_info.chip_class >= VI &&
1518 device->physical_device->rad_info.max_se >= 2;
1519
1520 if (getenv("RADV_TRACE_FILE")) {
1521 const char *filename = getenv("RADV_TRACE_FILE");
1522
1523 keep_shader_info = true;
1524
1525 if (!radv_init_trace(device))
1526 goto fail;
1527
1528 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1529 radv_dump_enabled_options(device, stderr);
1530 }
1531
1532 device->keep_shader_info = keep_shader_info;
1533
1534 result = radv_device_init_meta(device);
1535 if (result != VK_SUCCESS)
1536 goto fail;
1537
1538 radv_device_init_msaa(device);
1539
1540 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1541 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1542 switch (family) {
1543 case RADV_QUEUE_GENERAL:
1544 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1545 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1546 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1547 break;
1548 case RADV_QUEUE_COMPUTE:
1549 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1550 radeon_emit(device->empty_cs[family], 0);
1551 break;
1552 }
1553 device->ws->cs_finalize(device->empty_cs[family]);
1554 }
1555
1556 if (device->physical_device->rad_info.chip_class >= CIK)
1557 cik_create_gfx_config(device);
1558
1559 VkPipelineCacheCreateInfo ci;
1560 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1561 ci.pNext = NULL;
1562 ci.flags = 0;
1563 ci.pInitialData = NULL;
1564 ci.initialDataSize = 0;
1565 VkPipelineCache pc;
1566 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1567 &ci, NULL, &pc);
1568 if (result != VK_SUCCESS)
1569 goto fail_meta;
1570
1571 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1572
1573 *pDevice = radv_device_to_handle(device);
1574 return VK_SUCCESS;
1575
1576 fail_meta:
1577 radv_device_finish_meta(device);
1578 fail:
1579 radv_bo_list_finish(&device->bo_list);
1580
1581 if (device->trace_bo)
1582 device->ws->buffer_destroy(device->trace_bo);
1583
1584 if (device->gfx_init)
1585 device->ws->buffer_destroy(device->gfx_init);
1586
1587 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1588 for (unsigned q = 0; q < device->queue_count[i]; q++)
1589 radv_queue_finish(&device->queues[i][q]);
1590 if (device->queue_count[i])
1591 vk_free(&device->alloc, device->queues[i]);
1592 }
1593
1594 vk_free(&device->alloc, device);
1595 return result;
1596 }
1597
1598 void radv_DestroyDevice(
1599 VkDevice _device,
1600 const VkAllocationCallbacks* pAllocator)
1601 {
1602 RADV_FROM_HANDLE(radv_device, device, _device);
1603
1604 if (!device)
1605 return;
1606
1607 if (device->trace_bo)
1608 device->ws->buffer_destroy(device->trace_bo);
1609
1610 if (device->gfx_init)
1611 device->ws->buffer_destroy(device->gfx_init);
1612
1613 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1614 for (unsigned q = 0; q < device->queue_count[i]; q++)
1615 radv_queue_finish(&device->queues[i][q]);
1616 if (device->queue_count[i])
1617 vk_free(&device->alloc, device->queues[i]);
1618 if (device->empty_cs[i])
1619 device->ws->cs_destroy(device->empty_cs[i]);
1620 }
1621 radv_device_finish_meta(device);
1622
1623 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1624 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1625
1626 radv_destroy_shader_slabs(device);
1627
1628 radv_bo_list_finish(&device->bo_list);
1629 vk_free(&device->alloc, device);
1630 }
1631
1632 VkResult radv_EnumerateInstanceLayerProperties(
1633 uint32_t* pPropertyCount,
1634 VkLayerProperties* pProperties)
1635 {
1636 if (pProperties == NULL) {
1637 *pPropertyCount = 0;
1638 return VK_SUCCESS;
1639 }
1640
1641 /* None supported at this time */
1642 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1643 }
1644
1645 VkResult radv_EnumerateDeviceLayerProperties(
1646 VkPhysicalDevice physicalDevice,
1647 uint32_t* pPropertyCount,
1648 VkLayerProperties* pProperties)
1649 {
1650 if (pProperties == NULL) {
1651 *pPropertyCount = 0;
1652 return VK_SUCCESS;
1653 }
1654
1655 /* None supported at this time */
1656 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1657 }
1658
1659 void radv_GetDeviceQueue2(
1660 VkDevice _device,
1661 const VkDeviceQueueInfo2* pQueueInfo,
1662 VkQueue* pQueue)
1663 {
1664 RADV_FROM_HANDLE(radv_device, device, _device);
1665 struct radv_queue *queue;
1666
1667 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1668 if (pQueueInfo->flags != queue->flags) {
1669 /* From the Vulkan 1.1.70 spec:
1670 *
1671 * "The queue returned by vkGetDeviceQueue2 must have the same
1672 * flags value from this structure as that used at device
1673 * creation time in a VkDeviceQueueCreateInfo instance. If no
1674 * matching flags were specified at device creation time then
1675 * pQueue will return VK_NULL_HANDLE."
1676 */
1677 *pQueue = VK_NULL_HANDLE;
1678 return;
1679 }
1680
1681 *pQueue = radv_queue_to_handle(queue);
1682 }
1683
1684 void radv_GetDeviceQueue(
1685 VkDevice _device,
1686 uint32_t queueFamilyIndex,
1687 uint32_t queueIndex,
1688 VkQueue* pQueue)
1689 {
1690 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1691 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1692 .queueFamilyIndex = queueFamilyIndex,
1693 .queueIndex = queueIndex
1694 };
1695
1696 radv_GetDeviceQueue2(_device, &info, pQueue);
1697 }
1698
1699 static void
1700 fill_geom_tess_rings(struct radv_queue *queue,
1701 uint32_t *map,
1702 bool add_sample_positions,
1703 uint32_t esgs_ring_size,
1704 struct radeon_winsys_bo *esgs_ring_bo,
1705 uint32_t gsvs_ring_size,
1706 struct radeon_winsys_bo *gsvs_ring_bo,
1707 uint32_t tess_factor_ring_size,
1708 uint32_t tess_offchip_ring_offset,
1709 uint32_t tess_offchip_ring_size,
1710 struct radeon_winsys_bo *tess_rings_bo)
1711 {
1712 uint64_t esgs_va = 0, gsvs_va = 0;
1713 uint64_t tess_va = 0, tess_offchip_va = 0;
1714 uint32_t *desc = &map[4];
1715
1716 if (esgs_ring_bo)
1717 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1718 if (gsvs_ring_bo)
1719 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1720 if (tess_rings_bo) {
1721 tess_va = radv_buffer_get_va(tess_rings_bo);
1722 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1723 }
1724
1725 /* stride 0, num records - size, add tid, swizzle, elsize4,
1726 index stride 64 */
1727 desc[0] = esgs_va;
1728 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1729 S_008F04_STRIDE(0) |
1730 S_008F04_SWIZZLE_ENABLE(true);
1731 desc[2] = esgs_ring_size;
1732 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1733 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1734 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1735 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1736 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1737 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1738 S_008F0C_ELEMENT_SIZE(1) |
1739 S_008F0C_INDEX_STRIDE(3) |
1740 S_008F0C_ADD_TID_ENABLE(true);
1741
1742 desc += 4;
1743 /* GS entry for ES->GS ring */
1744 /* stride 0, num records - size, elsize0,
1745 index stride 0 */
1746 desc[0] = esgs_va;
1747 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1748 S_008F04_STRIDE(0) |
1749 S_008F04_SWIZZLE_ENABLE(false);
1750 desc[2] = esgs_ring_size;
1751 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1752 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1753 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1754 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1755 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1756 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1757 S_008F0C_ELEMENT_SIZE(0) |
1758 S_008F0C_INDEX_STRIDE(0) |
1759 S_008F0C_ADD_TID_ENABLE(false);
1760
1761 desc += 4;
1762 /* VS entry for GS->VS ring */
1763 /* stride 0, num records - size, elsize0,
1764 index stride 0 */
1765 desc[0] = gsvs_va;
1766 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1767 S_008F04_STRIDE(0) |
1768 S_008F04_SWIZZLE_ENABLE(false);
1769 desc[2] = gsvs_ring_size;
1770 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1771 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1772 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1773 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1774 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1775 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1776 S_008F0C_ELEMENT_SIZE(0) |
1777 S_008F0C_INDEX_STRIDE(0) |
1778 S_008F0C_ADD_TID_ENABLE(false);
1779 desc += 4;
1780
1781 /* stride gsvs_itemsize, num records 64
1782 elsize 4, index stride 16 */
1783 /* shader will patch stride and desc[2] */
1784 desc[0] = gsvs_va;
1785 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1786 S_008F04_STRIDE(0) |
1787 S_008F04_SWIZZLE_ENABLE(true);
1788 desc[2] = 0;
1789 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1790 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1791 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1792 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1793 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1794 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1795 S_008F0C_ELEMENT_SIZE(1) |
1796 S_008F0C_INDEX_STRIDE(1) |
1797 S_008F0C_ADD_TID_ENABLE(true);
1798 desc += 4;
1799
1800 desc[0] = tess_va;
1801 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1802 S_008F04_STRIDE(0) |
1803 S_008F04_SWIZZLE_ENABLE(false);
1804 desc[2] = tess_factor_ring_size;
1805 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1806 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1807 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1808 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1809 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1810 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1811 S_008F0C_ELEMENT_SIZE(0) |
1812 S_008F0C_INDEX_STRIDE(0) |
1813 S_008F0C_ADD_TID_ENABLE(false);
1814 desc += 4;
1815
1816 desc[0] = tess_offchip_va;
1817 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1818 S_008F04_STRIDE(0) |
1819 S_008F04_SWIZZLE_ENABLE(false);
1820 desc[2] = tess_offchip_ring_size;
1821 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1822 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1823 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1824 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1825 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1826 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1827 S_008F0C_ELEMENT_SIZE(0) |
1828 S_008F0C_INDEX_STRIDE(0) |
1829 S_008F0C_ADD_TID_ENABLE(false);
1830 desc += 4;
1831
1832 /* add sample positions after all rings */
1833 memcpy(desc, queue->device->sample_locations_1x, 8);
1834 desc += 2;
1835 memcpy(desc, queue->device->sample_locations_2x, 16);
1836 desc += 4;
1837 memcpy(desc, queue->device->sample_locations_4x, 32);
1838 desc += 8;
1839 memcpy(desc, queue->device->sample_locations_8x, 64);
1840 desc += 16;
1841 memcpy(desc, queue->device->sample_locations_16x, 128);
1842 }
1843
1844 static unsigned
1845 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1846 {
1847 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1848 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1849 device->physical_device->rad_info.family != CHIP_STONEY;
1850 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1851 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1852 device->physical_device->rad_info.max_se;
1853 unsigned offchip_granularity;
1854 unsigned hs_offchip_param;
1855 switch (device->tess_offchip_block_dw_size) {
1856 default:
1857 assert(0);
1858 /* fall through */
1859 case 8192:
1860 offchip_granularity = V_03093C_X_8K_DWORDS;
1861 break;
1862 case 4096:
1863 offchip_granularity = V_03093C_X_4K_DWORDS;
1864 break;
1865 }
1866
1867 switch (device->physical_device->rad_info.chip_class) {
1868 case SI:
1869 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1870 break;
1871 case CIK:
1872 case VI:
1873 case GFX9:
1874 default:
1875 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1876 break;
1877 }
1878
1879 *max_offchip_buffers_p = max_offchip_buffers;
1880 if (device->physical_device->rad_info.chip_class >= CIK) {
1881 if (device->physical_device->rad_info.chip_class >= VI)
1882 --max_offchip_buffers;
1883 hs_offchip_param =
1884 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1885 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1886 } else {
1887 hs_offchip_param =
1888 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1889 }
1890 return hs_offchip_param;
1891 }
1892
1893 static void
1894 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1895 struct radeon_winsys_bo *esgs_ring_bo,
1896 uint32_t esgs_ring_size,
1897 struct radeon_winsys_bo *gsvs_ring_bo,
1898 uint32_t gsvs_ring_size)
1899 {
1900 if (!esgs_ring_bo && !gsvs_ring_bo)
1901 return;
1902
1903 if (esgs_ring_bo)
1904 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1905
1906 if (gsvs_ring_bo)
1907 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1908
1909 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1910 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1911 radeon_emit(cs, esgs_ring_size >> 8);
1912 radeon_emit(cs, gsvs_ring_size >> 8);
1913 } else {
1914 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1915 radeon_emit(cs, esgs_ring_size >> 8);
1916 radeon_emit(cs, gsvs_ring_size >> 8);
1917 }
1918 }
1919
1920 static void
1921 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1922 unsigned hs_offchip_param, unsigned tf_ring_size,
1923 struct radeon_winsys_bo *tess_rings_bo)
1924 {
1925 uint64_t tf_va;
1926
1927 if (!tess_rings_bo)
1928 return;
1929
1930 tf_va = radv_buffer_get_va(tess_rings_bo);
1931
1932 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1933
1934 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1935 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1936 S_030938_SIZE(tf_ring_size / 4));
1937 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1938 tf_va >> 8);
1939 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1940 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1941 S_030944_BASE_HI(tf_va >> 40));
1942 }
1943 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1944 hs_offchip_param);
1945 } else {
1946 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1947 S_008988_SIZE(tf_ring_size / 4));
1948 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1949 tf_va >> 8);
1950 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1951 hs_offchip_param);
1952 }
1953 }
1954
1955 static void
1956 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs *cs,
1957 struct radeon_winsys_bo *compute_scratch_bo)
1958 {
1959 uint64_t scratch_va;
1960
1961 if (!compute_scratch_bo)
1962 return;
1963
1964 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1965
1966 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1967
1968 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1969 radeon_emit(cs, scratch_va);
1970 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1971 S_008F04_SWIZZLE_ENABLE(1));
1972 }
1973
1974 static void
1975 radv_emit_global_shader_pointers(struct radv_queue *queue,
1976 struct radeon_winsys_cs *cs,
1977 struct radeon_winsys_bo *descriptor_bo)
1978 {
1979 uint64_t va;
1980
1981 if (!descriptor_bo)
1982 return;
1983
1984 va = radv_buffer_get_va(descriptor_bo);
1985
1986 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1987
1988 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1989 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1990 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1991 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1992 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1993
1994 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1995 radv_emit_shader_pointer(queue->device, cs, regs[i],
1996 va, true);
1997 }
1998 } else {
1999 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2000 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2001 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2002 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2003 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2004 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2005
2006 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2007 radv_emit_shader_pointer(queue->device, cs, regs[i],
2008 va, true);
2009 }
2010 }
2011 }
2012
2013 static VkResult
2014 radv_get_preamble_cs(struct radv_queue *queue,
2015 uint32_t scratch_size,
2016 uint32_t compute_scratch_size,
2017 uint32_t esgs_ring_size,
2018 uint32_t gsvs_ring_size,
2019 bool needs_tess_rings,
2020 bool needs_sample_positions,
2021 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
2022 struct radeon_winsys_cs **initial_preamble_cs,
2023 struct radeon_winsys_cs **continue_preamble_cs)
2024 {
2025 struct radeon_winsys_bo *scratch_bo = NULL;
2026 struct radeon_winsys_bo *descriptor_bo = NULL;
2027 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2028 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2029 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2030 struct radeon_winsys_bo *tess_rings_bo = NULL;
2031 struct radeon_winsys_cs *dest_cs[3] = {0};
2032 bool add_tess_rings = false, add_sample_positions = false;
2033 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2034 unsigned max_offchip_buffers;
2035 unsigned hs_offchip_param = 0;
2036 unsigned tess_offchip_ring_offset;
2037 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2038 if (!queue->has_tess_rings) {
2039 if (needs_tess_rings)
2040 add_tess_rings = true;
2041 }
2042 if (!queue->has_sample_positions) {
2043 if (needs_sample_positions)
2044 add_sample_positions = true;
2045 }
2046 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2047 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2048 &max_offchip_buffers);
2049 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2050 tess_offchip_ring_size = max_offchip_buffers *
2051 queue->device->tess_offchip_block_dw_size * 4;
2052
2053 if (scratch_size <= queue->scratch_size &&
2054 compute_scratch_size <= queue->compute_scratch_size &&
2055 esgs_ring_size <= queue->esgs_ring_size &&
2056 gsvs_ring_size <= queue->gsvs_ring_size &&
2057 !add_tess_rings && !add_sample_positions &&
2058 queue->initial_preamble_cs) {
2059 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2060 *initial_preamble_cs = queue->initial_preamble_cs;
2061 *continue_preamble_cs = queue->continue_preamble_cs;
2062 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2063 *continue_preamble_cs = NULL;
2064 return VK_SUCCESS;
2065 }
2066
2067 if (scratch_size > queue->scratch_size) {
2068 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2069 scratch_size,
2070 4096,
2071 RADEON_DOMAIN_VRAM,
2072 ring_bo_flags);
2073 if (!scratch_bo)
2074 goto fail;
2075 } else
2076 scratch_bo = queue->scratch_bo;
2077
2078 if (compute_scratch_size > queue->compute_scratch_size) {
2079 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2080 compute_scratch_size,
2081 4096,
2082 RADEON_DOMAIN_VRAM,
2083 ring_bo_flags);
2084 if (!compute_scratch_bo)
2085 goto fail;
2086
2087 } else
2088 compute_scratch_bo = queue->compute_scratch_bo;
2089
2090 if (esgs_ring_size > queue->esgs_ring_size) {
2091 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2092 esgs_ring_size,
2093 4096,
2094 RADEON_DOMAIN_VRAM,
2095 ring_bo_flags);
2096 if (!esgs_ring_bo)
2097 goto fail;
2098 } else {
2099 esgs_ring_bo = queue->esgs_ring_bo;
2100 esgs_ring_size = queue->esgs_ring_size;
2101 }
2102
2103 if (gsvs_ring_size > queue->gsvs_ring_size) {
2104 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2105 gsvs_ring_size,
2106 4096,
2107 RADEON_DOMAIN_VRAM,
2108 ring_bo_flags);
2109 if (!gsvs_ring_bo)
2110 goto fail;
2111 } else {
2112 gsvs_ring_bo = queue->gsvs_ring_bo;
2113 gsvs_ring_size = queue->gsvs_ring_size;
2114 }
2115
2116 if (add_tess_rings) {
2117 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2118 tess_offchip_ring_offset + tess_offchip_ring_size,
2119 256,
2120 RADEON_DOMAIN_VRAM,
2121 ring_bo_flags);
2122 if (!tess_rings_bo)
2123 goto fail;
2124 } else {
2125 tess_rings_bo = queue->tess_rings_bo;
2126 }
2127
2128 if (scratch_bo != queue->scratch_bo ||
2129 esgs_ring_bo != queue->esgs_ring_bo ||
2130 gsvs_ring_bo != queue->gsvs_ring_bo ||
2131 tess_rings_bo != queue->tess_rings_bo ||
2132 add_sample_positions) {
2133 uint32_t size = 0;
2134 if (gsvs_ring_bo || esgs_ring_bo ||
2135 tess_rings_bo || add_sample_positions) {
2136 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2137 if (add_sample_positions)
2138 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2139 }
2140 else if (scratch_bo)
2141 size = 8; /* 2 dword */
2142
2143 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2144 size,
2145 4096,
2146 RADEON_DOMAIN_VRAM,
2147 RADEON_FLAG_CPU_ACCESS |
2148 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2149 RADEON_FLAG_READ_ONLY);
2150 if (!descriptor_bo)
2151 goto fail;
2152 } else
2153 descriptor_bo = queue->descriptor_bo;
2154
2155 for(int i = 0; i < 3; ++i) {
2156 struct radeon_winsys_cs *cs = NULL;
2157 cs = queue->device->ws->cs_create(queue->device->ws,
2158 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2159 if (!cs)
2160 goto fail;
2161
2162 dest_cs[i] = cs;
2163
2164 if (scratch_bo)
2165 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2166
2167 if (descriptor_bo != queue->descriptor_bo) {
2168 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2169
2170 if (scratch_bo) {
2171 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2172 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2173 S_008F04_SWIZZLE_ENABLE(1);
2174 map[0] = scratch_va;
2175 map[1] = rsrc1;
2176 }
2177
2178 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2179 add_sample_positions)
2180 fill_geom_tess_rings(queue, map, add_sample_positions,
2181 esgs_ring_size, esgs_ring_bo,
2182 gsvs_ring_size, gsvs_ring_bo,
2183 tess_factor_ring_size,
2184 tess_offchip_ring_offset,
2185 tess_offchip_ring_size,
2186 tess_rings_bo);
2187
2188 queue->device->ws->buffer_unmap(descriptor_bo);
2189 }
2190
2191 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2192 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2193 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2194 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2195 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2196 }
2197
2198 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2199 gsvs_ring_bo, gsvs_ring_size);
2200 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2201 tess_factor_ring_size, tess_rings_bo);
2202 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2203 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2204
2205 if (i == 0) {
2206 si_cs_emit_cache_flush(cs,
2207 queue->device->physical_device->rad_info.chip_class,
2208 NULL, 0,
2209 queue->queue_family_index == RING_COMPUTE &&
2210 queue->device->physical_device->rad_info.chip_class >= CIK,
2211 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2212 RADV_CMD_FLAG_INV_ICACHE |
2213 RADV_CMD_FLAG_INV_SMEM_L1 |
2214 RADV_CMD_FLAG_INV_VMEM_L1 |
2215 RADV_CMD_FLAG_INV_GLOBAL_L2);
2216 } else if (i == 1) {
2217 si_cs_emit_cache_flush(cs,
2218 queue->device->physical_device->rad_info.chip_class,
2219 NULL, 0,
2220 queue->queue_family_index == RING_COMPUTE &&
2221 queue->device->physical_device->rad_info.chip_class >= CIK,
2222 RADV_CMD_FLAG_INV_ICACHE |
2223 RADV_CMD_FLAG_INV_SMEM_L1 |
2224 RADV_CMD_FLAG_INV_VMEM_L1 |
2225 RADV_CMD_FLAG_INV_GLOBAL_L2);
2226 }
2227
2228 if (!queue->device->ws->cs_finalize(cs))
2229 goto fail;
2230 }
2231
2232 if (queue->initial_full_flush_preamble_cs)
2233 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2234
2235 if (queue->initial_preamble_cs)
2236 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2237
2238 if (queue->continue_preamble_cs)
2239 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2240
2241 queue->initial_full_flush_preamble_cs = dest_cs[0];
2242 queue->initial_preamble_cs = dest_cs[1];
2243 queue->continue_preamble_cs = dest_cs[2];
2244
2245 if (scratch_bo != queue->scratch_bo) {
2246 if (queue->scratch_bo)
2247 queue->device->ws->buffer_destroy(queue->scratch_bo);
2248 queue->scratch_bo = scratch_bo;
2249 queue->scratch_size = scratch_size;
2250 }
2251
2252 if (compute_scratch_bo != queue->compute_scratch_bo) {
2253 if (queue->compute_scratch_bo)
2254 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2255 queue->compute_scratch_bo = compute_scratch_bo;
2256 queue->compute_scratch_size = compute_scratch_size;
2257 }
2258
2259 if (esgs_ring_bo != queue->esgs_ring_bo) {
2260 if (queue->esgs_ring_bo)
2261 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2262 queue->esgs_ring_bo = esgs_ring_bo;
2263 queue->esgs_ring_size = esgs_ring_size;
2264 }
2265
2266 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2267 if (queue->gsvs_ring_bo)
2268 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2269 queue->gsvs_ring_bo = gsvs_ring_bo;
2270 queue->gsvs_ring_size = gsvs_ring_size;
2271 }
2272
2273 if (tess_rings_bo != queue->tess_rings_bo) {
2274 queue->tess_rings_bo = tess_rings_bo;
2275 queue->has_tess_rings = true;
2276 }
2277
2278 if (descriptor_bo != queue->descriptor_bo) {
2279 if (queue->descriptor_bo)
2280 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2281
2282 queue->descriptor_bo = descriptor_bo;
2283 }
2284
2285 if (add_sample_positions)
2286 queue->has_sample_positions = true;
2287
2288 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2289 *initial_preamble_cs = queue->initial_preamble_cs;
2290 *continue_preamble_cs = queue->continue_preamble_cs;
2291 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2292 *continue_preamble_cs = NULL;
2293 return VK_SUCCESS;
2294 fail:
2295 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2296 if (dest_cs[i])
2297 queue->device->ws->cs_destroy(dest_cs[i]);
2298 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2299 queue->device->ws->buffer_destroy(descriptor_bo);
2300 if (scratch_bo && scratch_bo != queue->scratch_bo)
2301 queue->device->ws->buffer_destroy(scratch_bo);
2302 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2303 queue->device->ws->buffer_destroy(compute_scratch_bo);
2304 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2305 queue->device->ws->buffer_destroy(esgs_ring_bo);
2306 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2307 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2308 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2309 queue->device->ws->buffer_destroy(tess_rings_bo);
2310 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2311 }
2312
2313 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2314 struct radv_winsys_sem_counts *counts,
2315 int num_sems,
2316 const VkSemaphore *sems,
2317 VkFence _fence,
2318 bool reset_temp)
2319 {
2320 int syncobj_idx = 0, sem_idx = 0;
2321
2322 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2323 return VK_SUCCESS;
2324
2325 for (uint32_t i = 0; i < num_sems; i++) {
2326 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2327
2328 if (sem->temp_syncobj || sem->syncobj)
2329 counts->syncobj_count++;
2330 else
2331 counts->sem_count++;
2332 }
2333
2334 if (_fence != VK_NULL_HANDLE) {
2335 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2336 if (fence->temp_syncobj || fence->syncobj)
2337 counts->syncobj_count++;
2338 }
2339
2340 if (counts->syncobj_count) {
2341 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2342 if (!counts->syncobj)
2343 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2344 }
2345
2346 if (counts->sem_count) {
2347 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2348 if (!counts->sem) {
2349 free(counts->syncobj);
2350 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2351 }
2352 }
2353
2354 for (uint32_t i = 0; i < num_sems; i++) {
2355 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2356
2357 if (sem->temp_syncobj) {
2358 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2359 }
2360 else if (sem->syncobj)
2361 counts->syncobj[syncobj_idx++] = sem->syncobj;
2362 else {
2363 assert(sem->sem);
2364 counts->sem[sem_idx++] = sem->sem;
2365 }
2366 }
2367
2368 if (_fence != VK_NULL_HANDLE) {
2369 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2370 if (fence->temp_syncobj)
2371 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2372 else if (fence->syncobj)
2373 counts->syncobj[syncobj_idx++] = fence->syncobj;
2374 }
2375
2376 return VK_SUCCESS;
2377 }
2378
2379 static void
2380 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2381 {
2382 free(sem_info->wait.syncobj);
2383 free(sem_info->wait.sem);
2384 free(sem_info->signal.syncobj);
2385 free(sem_info->signal.sem);
2386 }
2387
2388
2389 static void radv_free_temp_syncobjs(struct radv_device *device,
2390 int num_sems,
2391 const VkSemaphore *sems)
2392 {
2393 for (uint32_t i = 0; i < num_sems; i++) {
2394 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2395
2396 if (sem->temp_syncobj) {
2397 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2398 sem->temp_syncobj = 0;
2399 }
2400 }
2401 }
2402
2403 static VkResult
2404 radv_alloc_sem_info(struct radv_instance *instance,
2405 struct radv_winsys_sem_info *sem_info,
2406 int num_wait_sems,
2407 const VkSemaphore *wait_sems,
2408 int num_signal_sems,
2409 const VkSemaphore *signal_sems,
2410 VkFence fence)
2411 {
2412 VkResult ret;
2413 memset(sem_info, 0, sizeof(*sem_info));
2414
2415 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2416 if (ret)
2417 return ret;
2418 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2419 if (ret)
2420 radv_free_sem_info(sem_info);
2421
2422 /* caller can override these */
2423 sem_info->cs_emit_wait = true;
2424 sem_info->cs_emit_signal = true;
2425 return ret;
2426 }
2427
2428 /* Signals fence as soon as all the work currently put on queue is done. */
2429 static VkResult radv_signal_fence(struct radv_queue *queue,
2430 struct radv_fence *fence)
2431 {
2432 int ret;
2433 VkResult result;
2434 struct radv_winsys_sem_info sem_info;
2435
2436 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2437 radv_fence_to_handle(fence));
2438 if (result != VK_SUCCESS)
2439 return result;
2440
2441 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2442 &queue->device->empty_cs[queue->queue_family_index],
2443 1, NULL, NULL, &sem_info, NULL,
2444 false, fence->fence);
2445 radv_free_sem_info(&sem_info);
2446
2447 /* TODO: find a better error */
2448 if (ret)
2449 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2450
2451 return VK_SUCCESS;
2452 }
2453
2454 VkResult radv_QueueSubmit(
2455 VkQueue _queue,
2456 uint32_t submitCount,
2457 const VkSubmitInfo* pSubmits,
2458 VkFence _fence)
2459 {
2460 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2461 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2462 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2463 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2464 int ret;
2465 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2466 uint32_t scratch_size = 0;
2467 uint32_t compute_scratch_size = 0;
2468 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2469 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2470 VkResult result;
2471 bool fence_emitted = false;
2472 bool tess_rings_needed = false;
2473 bool sample_positions_needed = false;
2474
2475 /* Do this first so failing to allocate scratch buffers can't result in
2476 * partially executed submissions. */
2477 for (uint32_t i = 0; i < submitCount; i++) {
2478 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2480 pSubmits[i].pCommandBuffers[j]);
2481
2482 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2483 compute_scratch_size = MAX2(compute_scratch_size,
2484 cmd_buffer->compute_scratch_size_needed);
2485 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2486 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2487 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2488 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2489 }
2490 }
2491
2492 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2493 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2494 sample_positions_needed, &initial_flush_preamble_cs,
2495 &initial_preamble_cs, &continue_preamble_cs);
2496 if (result != VK_SUCCESS)
2497 return result;
2498
2499 for (uint32_t i = 0; i < submitCount; i++) {
2500 struct radeon_winsys_cs **cs_array;
2501 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2502 bool can_patch = true;
2503 uint32_t advance;
2504 struct radv_winsys_sem_info sem_info;
2505
2506 result = radv_alloc_sem_info(queue->device->instance,
2507 &sem_info,
2508 pSubmits[i].waitSemaphoreCount,
2509 pSubmits[i].pWaitSemaphores,
2510 pSubmits[i].signalSemaphoreCount,
2511 pSubmits[i].pSignalSemaphores,
2512 _fence);
2513 if (result != VK_SUCCESS)
2514 return result;
2515
2516 if (!pSubmits[i].commandBufferCount) {
2517 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2518 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2519 &queue->device->empty_cs[queue->queue_family_index],
2520 1, NULL, NULL,
2521 &sem_info, NULL,
2522 false, base_fence);
2523 if (ret) {
2524 radv_loge("failed to submit CS %d\n", i);
2525 abort();
2526 }
2527 fence_emitted = true;
2528 }
2529 radv_free_sem_info(&sem_info);
2530 continue;
2531 }
2532
2533 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2534 (pSubmits[i].commandBufferCount));
2535
2536 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2537 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2538 pSubmits[i].pCommandBuffers[j]);
2539 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2540
2541 cs_array[j] = cmd_buffer->cs;
2542 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2543 can_patch = false;
2544
2545 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2546 }
2547
2548 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2549 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2550 const struct radv_winsys_bo_list *bo_list = NULL;
2551
2552 advance = MIN2(max_cs_submission,
2553 pSubmits[i].commandBufferCount - j);
2554
2555 if (queue->device->trace_bo)
2556 *queue->device->trace_id_ptr = 0;
2557
2558 sem_info.cs_emit_wait = j == 0;
2559 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2560
2561 if (unlikely(queue->device->use_global_bo_list)) {
2562 pthread_mutex_lock(&queue->device->bo_list.mutex);
2563 bo_list = &queue->device->bo_list.list;
2564 }
2565
2566 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2567 advance, initial_preamble, continue_preamble_cs,
2568 &sem_info, bo_list,
2569 can_patch, base_fence);
2570
2571 if (unlikely(queue->device->use_global_bo_list))
2572 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2573
2574 if (ret) {
2575 radv_loge("failed to submit CS %d\n", i);
2576 abort();
2577 }
2578 fence_emitted = true;
2579 if (queue->device->trace_bo) {
2580 radv_check_gpu_hangs(queue, cs_array[j]);
2581 }
2582 }
2583
2584 radv_free_temp_syncobjs(queue->device,
2585 pSubmits[i].waitSemaphoreCount,
2586 pSubmits[i].pWaitSemaphores);
2587 radv_free_sem_info(&sem_info);
2588 free(cs_array);
2589 }
2590
2591 if (fence) {
2592 if (!fence_emitted) {
2593 radv_signal_fence(queue, fence);
2594 }
2595 fence->submitted = true;
2596 }
2597
2598 return VK_SUCCESS;
2599 }
2600
2601 VkResult radv_QueueWaitIdle(
2602 VkQueue _queue)
2603 {
2604 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2605
2606 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2607 radv_queue_family_to_ring(queue->queue_family_index),
2608 queue->queue_idx);
2609 return VK_SUCCESS;
2610 }
2611
2612 VkResult radv_DeviceWaitIdle(
2613 VkDevice _device)
2614 {
2615 RADV_FROM_HANDLE(radv_device, device, _device);
2616
2617 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2618 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2619 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2620 }
2621 }
2622 return VK_SUCCESS;
2623 }
2624
2625 VkResult radv_EnumerateInstanceExtensionProperties(
2626 const char* pLayerName,
2627 uint32_t* pPropertyCount,
2628 VkExtensionProperties* pProperties)
2629 {
2630 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2631
2632 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2633 if (radv_supported_instance_extensions.extensions[i]) {
2634 vk_outarray_append(&out, prop) {
2635 *prop = radv_instance_extensions[i];
2636 }
2637 }
2638 }
2639
2640 return vk_outarray_status(&out);
2641 }
2642
2643 VkResult radv_EnumerateDeviceExtensionProperties(
2644 VkPhysicalDevice physicalDevice,
2645 const char* pLayerName,
2646 uint32_t* pPropertyCount,
2647 VkExtensionProperties* pProperties)
2648 {
2649 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2650 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2651
2652 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2653 if (device->supported_extensions.extensions[i]) {
2654 vk_outarray_append(&out, prop) {
2655 *prop = radv_device_extensions[i];
2656 }
2657 }
2658 }
2659
2660 return vk_outarray_status(&out);
2661 }
2662
2663 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2664 VkInstance _instance,
2665 const char* pName)
2666 {
2667 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2668
2669 return radv_lookup_entrypoint_checked(pName,
2670 instance ? instance->apiVersion : 0,
2671 instance ? &instance->enabled_extensions : NULL,
2672 NULL);
2673 }
2674
2675 /* The loader wants us to expose a second GetInstanceProcAddr function
2676 * to work around certain LD_PRELOAD issues seen in apps.
2677 */
2678 PUBLIC
2679 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2680 VkInstance instance,
2681 const char* pName);
2682
2683 PUBLIC
2684 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2685 VkInstance instance,
2686 const char* pName)
2687 {
2688 return radv_GetInstanceProcAddr(instance, pName);
2689 }
2690
2691 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2692 VkDevice _device,
2693 const char* pName)
2694 {
2695 RADV_FROM_HANDLE(radv_device, device, _device);
2696
2697 return radv_lookup_entrypoint_checked(pName,
2698 device->instance->apiVersion,
2699 &device->instance->enabled_extensions,
2700 &device->enabled_extensions);
2701 }
2702
2703 bool radv_get_memory_fd(struct radv_device *device,
2704 struct radv_device_memory *memory,
2705 int *pFD)
2706 {
2707 struct radeon_bo_metadata metadata;
2708
2709 if (memory->image) {
2710 radv_init_metadata(device, memory->image, &metadata);
2711 device->ws->buffer_set_metadata(memory->bo, &metadata);
2712 }
2713
2714 return device->ws->buffer_get_fd(device->ws, memory->bo,
2715 pFD);
2716 }
2717
2718 static VkResult radv_alloc_memory(struct radv_device *device,
2719 const VkMemoryAllocateInfo* pAllocateInfo,
2720 const VkAllocationCallbacks* pAllocator,
2721 VkDeviceMemory* pMem)
2722 {
2723 struct radv_device_memory *mem;
2724 VkResult result;
2725 enum radeon_bo_domain domain;
2726 uint32_t flags = 0;
2727 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2728
2729 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2730
2731 if (pAllocateInfo->allocationSize == 0) {
2732 /* Apparently, this is allowed */
2733 *pMem = VK_NULL_HANDLE;
2734 return VK_SUCCESS;
2735 }
2736
2737 const VkImportMemoryFdInfoKHR *import_info =
2738 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2739 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2740 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2741 const VkExportMemoryAllocateInfoKHR *export_info =
2742 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2743 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2744 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2745
2746 const struct wsi_memory_allocate_info *wsi_info =
2747 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2748
2749 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2750 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2751 if (mem == NULL)
2752 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2753
2754 if (wsi_info && wsi_info->implicit_sync)
2755 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2756
2757 if (dedicate_info) {
2758 mem->image = radv_image_from_handle(dedicate_info->image);
2759 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2760 } else {
2761 mem->image = NULL;
2762 mem->buffer = NULL;
2763 }
2764
2765 mem->user_ptr = NULL;
2766
2767 if (import_info) {
2768 assert(import_info->handleType ==
2769 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2770 import_info->handleType ==
2771 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2772 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2773 NULL, NULL);
2774 if (!mem->bo) {
2775 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2776 goto fail;
2777 } else {
2778 close(import_info->fd);
2779 }
2780 } else if (host_ptr_info) {
2781 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2782 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2783 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2784 pAllocateInfo->allocationSize);
2785 if (!mem->bo) {
2786 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2787 goto fail;
2788 } else {
2789 mem->user_ptr = host_ptr_info->pHostPointer;
2790 }
2791 } else {
2792 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2793 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2794 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2795 domain = RADEON_DOMAIN_GTT;
2796 else
2797 domain = RADEON_DOMAIN_VRAM;
2798
2799 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2800 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2801 else
2802 flags |= RADEON_FLAG_CPU_ACCESS;
2803
2804 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2805 flags |= RADEON_FLAG_GTT_WC;
2806
2807 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2808 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2809
2810 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2811 domain, flags);
2812
2813 if (!mem->bo) {
2814 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2815 goto fail;
2816 }
2817 mem->type_index = mem_type_index;
2818 }
2819
2820 result = radv_bo_list_add(device, mem->bo);
2821 if (result != VK_SUCCESS)
2822 goto fail_bo;
2823
2824 *pMem = radv_device_memory_to_handle(mem);
2825
2826 return VK_SUCCESS;
2827
2828 fail_bo:
2829 device->ws->buffer_destroy(mem->bo);
2830 fail:
2831 vk_free2(&device->alloc, pAllocator, mem);
2832
2833 return result;
2834 }
2835
2836 VkResult radv_AllocateMemory(
2837 VkDevice _device,
2838 const VkMemoryAllocateInfo* pAllocateInfo,
2839 const VkAllocationCallbacks* pAllocator,
2840 VkDeviceMemory* pMem)
2841 {
2842 RADV_FROM_HANDLE(radv_device, device, _device);
2843 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2844 }
2845
2846 void radv_FreeMemory(
2847 VkDevice _device,
2848 VkDeviceMemory _mem,
2849 const VkAllocationCallbacks* pAllocator)
2850 {
2851 RADV_FROM_HANDLE(radv_device, device, _device);
2852 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2853
2854 if (mem == NULL)
2855 return;
2856
2857 radv_bo_list_remove(device, mem->bo);
2858 device->ws->buffer_destroy(mem->bo);
2859 mem->bo = NULL;
2860
2861 vk_free2(&device->alloc, pAllocator, mem);
2862 }
2863
2864 VkResult radv_MapMemory(
2865 VkDevice _device,
2866 VkDeviceMemory _memory,
2867 VkDeviceSize offset,
2868 VkDeviceSize size,
2869 VkMemoryMapFlags flags,
2870 void** ppData)
2871 {
2872 RADV_FROM_HANDLE(radv_device, device, _device);
2873 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2874
2875 if (mem == NULL) {
2876 *ppData = NULL;
2877 return VK_SUCCESS;
2878 }
2879
2880 if (mem->user_ptr)
2881 *ppData = mem->user_ptr;
2882 else
2883 *ppData = device->ws->buffer_map(mem->bo);
2884
2885 if (*ppData) {
2886 *ppData += offset;
2887 return VK_SUCCESS;
2888 }
2889
2890 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2891 }
2892
2893 void radv_UnmapMemory(
2894 VkDevice _device,
2895 VkDeviceMemory _memory)
2896 {
2897 RADV_FROM_HANDLE(radv_device, device, _device);
2898 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2899
2900 if (mem == NULL)
2901 return;
2902
2903 if (mem->user_ptr == NULL)
2904 device->ws->buffer_unmap(mem->bo);
2905 }
2906
2907 VkResult radv_FlushMappedMemoryRanges(
2908 VkDevice _device,
2909 uint32_t memoryRangeCount,
2910 const VkMappedMemoryRange* pMemoryRanges)
2911 {
2912 return VK_SUCCESS;
2913 }
2914
2915 VkResult radv_InvalidateMappedMemoryRanges(
2916 VkDevice _device,
2917 uint32_t memoryRangeCount,
2918 const VkMappedMemoryRange* pMemoryRanges)
2919 {
2920 return VK_SUCCESS;
2921 }
2922
2923 void radv_GetBufferMemoryRequirements(
2924 VkDevice _device,
2925 VkBuffer _buffer,
2926 VkMemoryRequirements* pMemoryRequirements)
2927 {
2928 RADV_FROM_HANDLE(radv_device, device, _device);
2929 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2930
2931 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2932
2933 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2934 pMemoryRequirements->alignment = 4096;
2935 else
2936 pMemoryRequirements->alignment = 16;
2937
2938 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2939 }
2940
2941 void radv_GetBufferMemoryRequirements2(
2942 VkDevice device,
2943 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2944 VkMemoryRequirements2KHR* pMemoryRequirements)
2945 {
2946 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2947 &pMemoryRequirements->memoryRequirements);
2948 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2949 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2950 switch (ext->sType) {
2951 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2952 VkMemoryDedicatedRequirementsKHR *req =
2953 (VkMemoryDedicatedRequirementsKHR *) ext;
2954 req->requiresDedicatedAllocation = buffer->shareable;
2955 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2956 break;
2957 }
2958 default:
2959 break;
2960 }
2961 }
2962 }
2963
2964 void radv_GetImageMemoryRequirements(
2965 VkDevice _device,
2966 VkImage _image,
2967 VkMemoryRequirements* pMemoryRequirements)
2968 {
2969 RADV_FROM_HANDLE(radv_device, device, _device);
2970 RADV_FROM_HANDLE(radv_image, image, _image);
2971
2972 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2973
2974 pMemoryRequirements->size = image->size;
2975 pMemoryRequirements->alignment = image->alignment;
2976 }
2977
2978 void radv_GetImageMemoryRequirements2(
2979 VkDevice device,
2980 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2981 VkMemoryRequirements2KHR* pMemoryRequirements)
2982 {
2983 radv_GetImageMemoryRequirements(device, pInfo->image,
2984 &pMemoryRequirements->memoryRequirements);
2985
2986 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2987
2988 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2989 switch (ext->sType) {
2990 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2991 VkMemoryDedicatedRequirementsKHR *req =
2992 (VkMemoryDedicatedRequirementsKHR *) ext;
2993 req->requiresDedicatedAllocation = image->shareable;
2994 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2995 break;
2996 }
2997 default:
2998 break;
2999 }
3000 }
3001 }
3002
3003 void radv_GetImageSparseMemoryRequirements(
3004 VkDevice device,
3005 VkImage image,
3006 uint32_t* pSparseMemoryRequirementCount,
3007 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3008 {
3009 stub();
3010 }
3011
3012 void radv_GetImageSparseMemoryRequirements2(
3013 VkDevice device,
3014 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3015 uint32_t* pSparseMemoryRequirementCount,
3016 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3017 {
3018 stub();
3019 }
3020
3021 void radv_GetDeviceMemoryCommitment(
3022 VkDevice device,
3023 VkDeviceMemory memory,
3024 VkDeviceSize* pCommittedMemoryInBytes)
3025 {
3026 *pCommittedMemoryInBytes = 0;
3027 }
3028
3029 VkResult radv_BindBufferMemory2(VkDevice device,
3030 uint32_t bindInfoCount,
3031 const VkBindBufferMemoryInfoKHR *pBindInfos)
3032 {
3033 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3034 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3035 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3036
3037 if (mem) {
3038 buffer->bo = mem->bo;
3039 buffer->offset = pBindInfos[i].memoryOffset;
3040 } else {
3041 buffer->bo = NULL;
3042 }
3043 }
3044 return VK_SUCCESS;
3045 }
3046
3047 VkResult radv_BindBufferMemory(
3048 VkDevice device,
3049 VkBuffer buffer,
3050 VkDeviceMemory memory,
3051 VkDeviceSize memoryOffset)
3052 {
3053 const VkBindBufferMemoryInfoKHR info = {
3054 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3055 .buffer = buffer,
3056 .memory = memory,
3057 .memoryOffset = memoryOffset
3058 };
3059
3060 return radv_BindBufferMemory2(device, 1, &info);
3061 }
3062
3063 VkResult radv_BindImageMemory2(VkDevice device,
3064 uint32_t bindInfoCount,
3065 const VkBindImageMemoryInfoKHR *pBindInfos)
3066 {
3067 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3068 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3069 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3070
3071 if (mem) {
3072 image->bo = mem->bo;
3073 image->offset = pBindInfos[i].memoryOffset;
3074 } else {
3075 image->bo = NULL;
3076 image->offset = 0;
3077 }
3078 }
3079 return VK_SUCCESS;
3080 }
3081
3082
3083 VkResult radv_BindImageMemory(
3084 VkDevice device,
3085 VkImage image,
3086 VkDeviceMemory memory,
3087 VkDeviceSize memoryOffset)
3088 {
3089 const VkBindImageMemoryInfoKHR info = {
3090 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3091 .image = image,
3092 .memory = memory,
3093 .memoryOffset = memoryOffset
3094 };
3095
3096 return radv_BindImageMemory2(device, 1, &info);
3097 }
3098
3099
3100 static void
3101 radv_sparse_buffer_bind_memory(struct radv_device *device,
3102 const VkSparseBufferMemoryBindInfo *bind)
3103 {
3104 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3105
3106 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3107 struct radv_device_memory *mem = NULL;
3108
3109 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3110 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3111
3112 device->ws->buffer_virtual_bind(buffer->bo,
3113 bind->pBinds[i].resourceOffset,
3114 bind->pBinds[i].size,
3115 mem ? mem->bo : NULL,
3116 bind->pBinds[i].memoryOffset);
3117 }
3118 }
3119
3120 static void
3121 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3122 const VkSparseImageOpaqueMemoryBindInfo *bind)
3123 {
3124 RADV_FROM_HANDLE(radv_image, image, bind->image);
3125
3126 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3127 struct radv_device_memory *mem = NULL;
3128
3129 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3130 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3131
3132 device->ws->buffer_virtual_bind(image->bo,
3133 bind->pBinds[i].resourceOffset,
3134 bind->pBinds[i].size,
3135 mem ? mem->bo : NULL,
3136 bind->pBinds[i].memoryOffset);
3137 }
3138 }
3139
3140 VkResult radv_QueueBindSparse(
3141 VkQueue _queue,
3142 uint32_t bindInfoCount,
3143 const VkBindSparseInfo* pBindInfo,
3144 VkFence _fence)
3145 {
3146 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3147 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3148 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3149 bool fence_emitted = false;
3150
3151 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3152 struct radv_winsys_sem_info sem_info;
3153 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3154 radv_sparse_buffer_bind_memory(queue->device,
3155 pBindInfo[i].pBufferBinds + j);
3156 }
3157
3158 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3159 radv_sparse_image_opaque_bind_memory(queue->device,
3160 pBindInfo[i].pImageOpaqueBinds + j);
3161 }
3162
3163 VkResult result;
3164 result = radv_alloc_sem_info(queue->device->instance,
3165 &sem_info,
3166 pBindInfo[i].waitSemaphoreCount,
3167 pBindInfo[i].pWaitSemaphores,
3168 pBindInfo[i].signalSemaphoreCount,
3169 pBindInfo[i].pSignalSemaphores,
3170 _fence);
3171 if (result != VK_SUCCESS)
3172 return result;
3173
3174 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3175 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3176 &queue->device->empty_cs[queue->queue_family_index],
3177 1, NULL, NULL,
3178 &sem_info, NULL,
3179 false, base_fence);
3180 fence_emitted = true;
3181 if (fence)
3182 fence->submitted = true;
3183 }
3184
3185 radv_free_sem_info(&sem_info);
3186
3187 }
3188
3189 if (fence) {
3190 if (!fence_emitted) {
3191 radv_signal_fence(queue, fence);
3192 }
3193 fence->submitted = true;
3194 }
3195
3196 return VK_SUCCESS;
3197 }
3198
3199 VkResult radv_CreateFence(
3200 VkDevice _device,
3201 const VkFenceCreateInfo* pCreateInfo,
3202 const VkAllocationCallbacks* pAllocator,
3203 VkFence* pFence)
3204 {
3205 RADV_FROM_HANDLE(radv_device, device, _device);
3206 const VkExportFenceCreateInfoKHR *export =
3207 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3208 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3209 export ? export->handleTypes : 0;
3210
3211 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3212 sizeof(*fence), 8,
3213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3214
3215 if (!fence)
3216 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3217
3218 fence->submitted = false;
3219 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3220 fence->temp_syncobj = 0;
3221 if (device->always_use_syncobj || handleTypes) {
3222 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3223 if (ret) {
3224 vk_free2(&device->alloc, pAllocator, fence);
3225 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3226 }
3227 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3228 device->ws->signal_syncobj(device->ws, fence->syncobj);
3229 }
3230 fence->fence = NULL;
3231 } else {
3232 fence->fence = device->ws->create_fence();
3233 if (!fence->fence) {
3234 vk_free2(&device->alloc, pAllocator, fence);
3235 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3236 }
3237 fence->syncobj = 0;
3238 }
3239
3240 *pFence = radv_fence_to_handle(fence);
3241
3242 return VK_SUCCESS;
3243 }
3244
3245 void radv_DestroyFence(
3246 VkDevice _device,
3247 VkFence _fence,
3248 const VkAllocationCallbacks* pAllocator)
3249 {
3250 RADV_FROM_HANDLE(radv_device, device, _device);
3251 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3252
3253 if (!fence)
3254 return;
3255
3256 if (fence->temp_syncobj)
3257 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3258 if (fence->syncobj)
3259 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3260 if (fence->fence)
3261 device->ws->destroy_fence(fence->fence);
3262 vk_free2(&device->alloc, pAllocator, fence);
3263 }
3264
3265
3266 static uint64_t radv_get_current_time()
3267 {
3268 struct timespec tv;
3269 clock_gettime(CLOCK_MONOTONIC, &tv);
3270 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3271 }
3272
3273 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3274 {
3275 uint64_t current_time = radv_get_current_time();
3276
3277 timeout = MIN2(UINT64_MAX - current_time, timeout);
3278
3279 return current_time + timeout;
3280 }
3281
3282
3283 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3284 {
3285 for (uint32_t i = 0; i < fenceCount; ++i) {
3286 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3287 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3288 return false;
3289 }
3290 return true;
3291 }
3292
3293 VkResult radv_WaitForFences(
3294 VkDevice _device,
3295 uint32_t fenceCount,
3296 const VkFence* pFences,
3297 VkBool32 waitAll,
3298 uint64_t timeout)
3299 {
3300 RADV_FROM_HANDLE(radv_device, device, _device);
3301 timeout = radv_get_absolute_timeout(timeout);
3302
3303 if (device->always_use_syncobj) {
3304 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3305 if (!handles)
3306 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3307
3308 for (uint32_t i = 0; i < fenceCount; ++i) {
3309 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3310 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3311 }
3312
3313 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3314
3315 free(handles);
3316 return success ? VK_SUCCESS : VK_TIMEOUT;
3317 }
3318
3319 if (!waitAll && fenceCount > 1) {
3320 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3321 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3322 uint32_t wait_count = 0;
3323 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3324 if (!fences)
3325 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3326
3327 for (uint32_t i = 0; i < fenceCount; ++i) {
3328 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3329
3330 if (fence->signalled) {
3331 free(fences);
3332 return VK_SUCCESS;
3333 }
3334
3335 fences[wait_count++] = fence->fence;
3336 }
3337
3338 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3339 waitAll, timeout - radv_get_current_time());
3340
3341 free(fences);
3342 return success ? VK_SUCCESS : VK_TIMEOUT;
3343 }
3344
3345 while(radv_get_current_time() <= timeout) {
3346 for (uint32_t i = 0; i < fenceCount; ++i) {
3347 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3348 return VK_SUCCESS;
3349 }
3350 }
3351 return VK_TIMEOUT;
3352 }
3353
3354 for (uint32_t i = 0; i < fenceCount; ++i) {
3355 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3356 bool expired = false;
3357
3358 if (fence->temp_syncobj) {
3359 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3360 return VK_TIMEOUT;
3361 continue;
3362 }
3363
3364 if (fence->syncobj) {
3365 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3366 return VK_TIMEOUT;
3367 continue;
3368 }
3369
3370 if (fence->signalled)
3371 continue;
3372
3373 if (!fence->submitted) {
3374 while(radv_get_current_time() <= timeout && !fence->submitted)
3375 /* Do nothing */;
3376
3377 if (!fence->submitted)
3378 return VK_TIMEOUT;
3379
3380 /* Recheck as it may have been set by submitting operations. */
3381 if (fence->signalled)
3382 continue;
3383 }
3384
3385 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3386 if (!expired)
3387 return VK_TIMEOUT;
3388
3389 fence->signalled = true;
3390 }
3391
3392 return VK_SUCCESS;
3393 }
3394
3395 VkResult radv_ResetFences(VkDevice _device,
3396 uint32_t fenceCount,
3397 const VkFence *pFences)
3398 {
3399 RADV_FROM_HANDLE(radv_device, device, _device);
3400
3401 for (unsigned i = 0; i < fenceCount; ++i) {
3402 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3403 fence->submitted = fence->signalled = false;
3404
3405 /* Per spec, we first restore the permanent payload, and then reset, so
3406 * having a temp syncobj should not skip resetting the permanent syncobj. */
3407 if (fence->temp_syncobj) {
3408 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3409 fence->temp_syncobj = 0;
3410 }
3411
3412 if (fence->syncobj) {
3413 device->ws->reset_syncobj(device->ws, fence->syncobj);
3414 }
3415 }
3416
3417 return VK_SUCCESS;
3418 }
3419
3420 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3421 {
3422 RADV_FROM_HANDLE(radv_device, device, _device);
3423 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3424
3425 if (fence->temp_syncobj) {
3426 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3427 return success ? VK_SUCCESS : VK_NOT_READY;
3428 }
3429
3430 if (fence->syncobj) {
3431 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3432 return success ? VK_SUCCESS : VK_NOT_READY;
3433 }
3434
3435 if (fence->signalled)
3436 return VK_SUCCESS;
3437 if (!fence->submitted)
3438 return VK_NOT_READY;
3439 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3440 return VK_NOT_READY;
3441
3442 return VK_SUCCESS;
3443 }
3444
3445
3446 // Queue semaphore functions
3447
3448 VkResult radv_CreateSemaphore(
3449 VkDevice _device,
3450 const VkSemaphoreCreateInfo* pCreateInfo,
3451 const VkAllocationCallbacks* pAllocator,
3452 VkSemaphore* pSemaphore)
3453 {
3454 RADV_FROM_HANDLE(radv_device, device, _device);
3455 const VkExportSemaphoreCreateInfoKHR *export =
3456 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3457 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3458 export ? export->handleTypes : 0;
3459
3460 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3461 sizeof(*sem), 8,
3462 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3463 if (!sem)
3464 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3465
3466 sem->temp_syncobj = 0;
3467 /* create a syncobject if we are going to export this semaphore */
3468 if (device->always_use_syncobj || handleTypes) {
3469 assert (device->physical_device->rad_info.has_syncobj);
3470 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3471 if (ret) {
3472 vk_free2(&device->alloc, pAllocator, sem);
3473 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3474 }
3475 sem->sem = NULL;
3476 } else {
3477 sem->sem = device->ws->create_sem(device->ws);
3478 if (!sem->sem) {
3479 vk_free2(&device->alloc, pAllocator, sem);
3480 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3481 }
3482 sem->syncobj = 0;
3483 }
3484
3485 *pSemaphore = radv_semaphore_to_handle(sem);
3486 return VK_SUCCESS;
3487 }
3488
3489 void radv_DestroySemaphore(
3490 VkDevice _device,
3491 VkSemaphore _semaphore,
3492 const VkAllocationCallbacks* pAllocator)
3493 {
3494 RADV_FROM_HANDLE(radv_device, device, _device);
3495 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3496 if (!_semaphore)
3497 return;
3498
3499 if (sem->syncobj)
3500 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3501 else
3502 device->ws->destroy_sem(sem->sem);
3503 vk_free2(&device->alloc, pAllocator, sem);
3504 }
3505
3506 VkResult radv_CreateEvent(
3507 VkDevice _device,
3508 const VkEventCreateInfo* pCreateInfo,
3509 const VkAllocationCallbacks* pAllocator,
3510 VkEvent* pEvent)
3511 {
3512 RADV_FROM_HANDLE(radv_device, device, _device);
3513 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3514 sizeof(*event), 8,
3515 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3516
3517 if (!event)
3518 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3519
3520 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3521 RADEON_DOMAIN_GTT,
3522 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3523 if (!event->bo) {
3524 vk_free2(&device->alloc, pAllocator, event);
3525 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3526 }
3527
3528 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3529
3530 *pEvent = radv_event_to_handle(event);
3531
3532 return VK_SUCCESS;
3533 }
3534
3535 void radv_DestroyEvent(
3536 VkDevice _device,
3537 VkEvent _event,
3538 const VkAllocationCallbacks* pAllocator)
3539 {
3540 RADV_FROM_HANDLE(radv_device, device, _device);
3541 RADV_FROM_HANDLE(radv_event, event, _event);
3542
3543 if (!event)
3544 return;
3545 device->ws->buffer_destroy(event->bo);
3546 vk_free2(&device->alloc, pAllocator, event);
3547 }
3548
3549 VkResult radv_GetEventStatus(
3550 VkDevice _device,
3551 VkEvent _event)
3552 {
3553 RADV_FROM_HANDLE(radv_event, event, _event);
3554
3555 if (*event->map == 1)
3556 return VK_EVENT_SET;
3557 return VK_EVENT_RESET;
3558 }
3559
3560 VkResult radv_SetEvent(
3561 VkDevice _device,
3562 VkEvent _event)
3563 {
3564 RADV_FROM_HANDLE(radv_event, event, _event);
3565 *event->map = 1;
3566
3567 return VK_SUCCESS;
3568 }
3569
3570 VkResult radv_ResetEvent(
3571 VkDevice _device,
3572 VkEvent _event)
3573 {
3574 RADV_FROM_HANDLE(radv_event, event, _event);
3575 *event->map = 0;
3576
3577 return VK_SUCCESS;
3578 }
3579
3580 VkResult radv_CreateBuffer(
3581 VkDevice _device,
3582 const VkBufferCreateInfo* pCreateInfo,
3583 const VkAllocationCallbacks* pAllocator,
3584 VkBuffer* pBuffer)
3585 {
3586 RADV_FROM_HANDLE(radv_device, device, _device);
3587 struct radv_buffer *buffer;
3588
3589 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3590
3591 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3592 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3593 if (buffer == NULL)
3594 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3595
3596 buffer->size = pCreateInfo->size;
3597 buffer->usage = pCreateInfo->usage;
3598 buffer->bo = NULL;
3599 buffer->offset = 0;
3600 buffer->flags = pCreateInfo->flags;
3601
3602 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3603 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3604
3605 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3606 buffer->bo = device->ws->buffer_create(device->ws,
3607 align64(buffer->size, 4096),
3608 4096, 0, RADEON_FLAG_VIRTUAL);
3609 if (!buffer->bo) {
3610 vk_free2(&device->alloc, pAllocator, buffer);
3611 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3612 }
3613 }
3614
3615 *pBuffer = radv_buffer_to_handle(buffer);
3616
3617 return VK_SUCCESS;
3618 }
3619
3620 void radv_DestroyBuffer(
3621 VkDevice _device,
3622 VkBuffer _buffer,
3623 const VkAllocationCallbacks* pAllocator)
3624 {
3625 RADV_FROM_HANDLE(radv_device, device, _device);
3626 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3627
3628 if (!buffer)
3629 return;
3630
3631 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3632 device->ws->buffer_destroy(buffer->bo);
3633
3634 vk_free2(&device->alloc, pAllocator, buffer);
3635 }
3636
3637 static inline unsigned
3638 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3639 {
3640 if (stencil)
3641 return image->surface.u.legacy.stencil_tiling_index[level];
3642 else
3643 return image->surface.u.legacy.tiling_index[level];
3644 }
3645
3646 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3647 {
3648 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3649 }
3650
3651 static uint32_t
3652 radv_init_dcc_control_reg(struct radv_device *device,
3653 struct radv_image_view *iview)
3654 {
3655 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3656 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3657 unsigned max_compressed_block_size;
3658 unsigned independent_64b_blocks;
3659
3660 if (device->physical_device->rad_info.chip_class < VI)
3661 return 0;
3662
3663 if (iview->image->info.samples > 1) {
3664 if (iview->image->surface.bpe == 1)
3665 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3666 else if (iview->image->surface.bpe == 2)
3667 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3668 }
3669
3670 if (!device->physical_device->rad_info.has_dedicated_vram) {
3671 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3672 * dGPU and 64 for APU because all of our APUs to date use
3673 * DIMMs which have a request granularity size of 64B while all
3674 * other chips have a 32B request size.
3675 */
3676 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3677 }
3678
3679 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3680 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3681 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3682 /* If this DCC image is potentially going to be used in texture
3683 * fetches, we need some special settings.
3684 */
3685 independent_64b_blocks = 1;
3686 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3687 } else {
3688 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3689 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3690 * big as possible for better compression state.
3691 */
3692 independent_64b_blocks = 0;
3693 max_compressed_block_size = max_uncompressed_block_size;
3694 }
3695
3696 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3697 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3698 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3699 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3700 }
3701
3702 static void
3703 radv_initialise_color_surface(struct radv_device *device,
3704 struct radv_color_buffer_info *cb,
3705 struct radv_image_view *iview)
3706 {
3707 const struct vk_format_description *desc;
3708 unsigned ntype, format, swap, endian;
3709 unsigned blend_clamp = 0, blend_bypass = 0;
3710 uint64_t va;
3711 const struct radeon_surf *surf = &iview->image->surface;
3712
3713 desc = vk_format_description(iview->vk_format);
3714
3715 memset(cb, 0, sizeof(*cb));
3716
3717 /* Intensity is implemented as Red, so treat it that way. */
3718 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3719
3720 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3721
3722 cb->cb_color_base = va >> 8;
3723
3724 if (device->physical_device->rad_info.chip_class >= GFX9) {
3725 struct gfx9_surf_meta_flags meta;
3726 if (iview->image->dcc_offset)
3727 meta = iview->image->surface.u.gfx9.dcc;
3728 else
3729 meta = iview->image->surface.u.gfx9.cmask;
3730
3731 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3732 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3733 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3734 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3735
3736 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3737 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3738 } else {
3739 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3740 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3741
3742 cb->cb_color_base += level_info->offset >> 8;
3743 if (level_info->mode == RADEON_SURF_MODE_2D)
3744 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3745
3746 pitch_tile_max = level_info->nblk_x / 8 - 1;
3747 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3748 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3749
3750 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3751 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3752 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3753
3754 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3755
3756 if (radv_image_has_fmask(iview->image)) {
3757 if (device->physical_device->rad_info.chip_class >= CIK)
3758 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3759 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3760 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3761 } else {
3762 /* This must be set for fast clear to work without FMASK. */
3763 if (device->physical_device->rad_info.chip_class >= CIK)
3764 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3765 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3766 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3767 }
3768 }
3769
3770 /* CMASK variables */
3771 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3772 va += iview->image->cmask.offset;
3773 cb->cb_color_cmask = va >> 8;
3774
3775 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3776 va += iview->image->dcc_offset;
3777 cb->cb_dcc_base = va >> 8;
3778 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3779
3780 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3781 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3782 S_028C6C_SLICE_MAX(max_slice);
3783
3784 if (iview->image->info.samples > 1) {
3785 unsigned log_samples = util_logbase2(iview->image->info.samples);
3786
3787 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3788 S_028C74_NUM_FRAGMENTS(log_samples);
3789 }
3790
3791 if (radv_image_has_fmask(iview->image)) {
3792 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3793 cb->cb_color_fmask = va >> 8;
3794 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3795 } else {
3796 cb->cb_color_fmask = cb->cb_color_base;
3797 }
3798
3799 ntype = radv_translate_color_numformat(iview->vk_format,
3800 desc,
3801 vk_format_get_first_non_void_channel(iview->vk_format));
3802 format = radv_translate_colorformat(iview->vk_format);
3803 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3804 radv_finishme("Illegal color\n");
3805 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3806 endian = radv_colorformat_endian_swap(format);
3807
3808 /* blend clamp should be set for all NORM/SRGB types */
3809 if (ntype == V_028C70_NUMBER_UNORM ||
3810 ntype == V_028C70_NUMBER_SNORM ||
3811 ntype == V_028C70_NUMBER_SRGB)
3812 blend_clamp = 1;
3813
3814 /* set blend bypass according to docs if SINT/UINT or
3815 8/24 COLOR variants */
3816 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3817 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3818 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3819 blend_clamp = 0;
3820 blend_bypass = 1;
3821 }
3822 #if 0
3823 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3824 (format == V_028C70_COLOR_8 ||
3825 format == V_028C70_COLOR_8_8 ||
3826 format == V_028C70_COLOR_8_8_8_8))
3827 ->color_is_int8 = true;
3828 #endif
3829 cb->cb_color_info = S_028C70_FORMAT(format) |
3830 S_028C70_COMP_SWAP(swap) |
3831 S_028C70_BLEND_CLAMP(blend_clamp) |
3832 S_028C70_BLEND_BYPASS(blend_bypass) |
3833 S_028C70_SIMPLE_FLOAT(1) |
3834 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3835 ntype != V_028C70_NUMBER_SNORM &&
3836 ntype != V_028C70_NUMBER_SRGB &&
3837 format != V_028C70_COLOR_8_24 &&
3838 format != V_028C70_COLOR_24_8) |
3839 S_028C70_NUMBER_TYPE(ntype) |
3840 S_028C70_ENDIAN(endian);
3841 if (radv_image_has_fmask(iview->image)) {
3842 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3843 if (device->physical_device->rad_info.chip_class == SI) {
3844 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3845 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3846 }
3847 }
3848
3849 if (radv_image_has_cmask(iview->image) &&
3850 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3851 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3852
3853 if (radv_dcc_enabled(iview->image, iview->base_mip))
3854 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3855
3856 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3857
3858 /* This must be set for fast clear to work without FMASK. */
3859 if (!radv_image_has_fmask(iview->image) &&
3860 device->physical_device->rad_info.chip_class == SI) {
3861 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3862 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3863 }
3864
3865 if (device->physical_device->rad_info.chip_class >= GFX9) {
3866 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3867 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3868
3869 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3870 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3871 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3872 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3873 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3874 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3875 }
3876 }
3877
3878 static unsigned
3879 radv_calc_decompress_on_z_planes(struct radv_device *device,
3880 struct radv_image_view *iview)
3881 {
3882 unsigned max_zplanes = 0;
3883
3884 assert(radv_image_is_tc_compat_htile(iview->image));
3885
3886 if (device->physical_device->rad_info.chip_class >= GFX9) {
3887 /* Default value for 32-bit depth surfaces. */
3888 max_zplanes = 4;
3889
3890 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3891 iview->image->info.samples > 1)
3892 max_zplanes = 2;
3893
3894 max_zplanes = max_zplanes + 1;
3895 } else {
3896 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3897 /* Do not enable Z plane compression for 16-bit depth
3898 * surfaces because isn't supported on GFX8. Only
3899 * 32-bit depth surfaces are supported by the hardware.
3900 * This allows to maintain shader compatibility and to
3901 * reduce the number of depth decompressions.
3902 */
3903 max_zplanes = 1;
3904 } else {
3905 if (iview->image->info.samples <= 1)
3906 max_zplanes = 5;
3907 else if (iview->image->info.samples <= 4)
3908 max_zplanes = 3;
3909 else
3910 max_zplanes = 2;
3911 }
3912 }
3913
3914 return max_zplanes;
3915 }
3916
3917 static void
3918 radv_initialise_ds_surface(struct radv_device *device,
3919 struct radv_ds_buffer_info *ds,
3920 struct radv_image_view *iview)
3921 {
3922 unsigned level = iview->base_mip;
3923 unsigned format, stencil_format;
3924 uint64_t va, s_offs, z_offs;
3925 bool stencil_only = false;
3926 memset(ds, 0, sizeof(*ds));
3927 switch (iview->image->vk_format) {
3928 case VK_FORMAT_D24_UNORM_S8_UINT:
3929 case VK_FORMAT_X8_D24_UNORM_PACK32:
3930 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3931 ds->offset_scale = 2.0f;
3932 break;
3933 case VK_FORMAT_D16_UNORM:
3934 case VK_FORMAT_D16_UNORM_S8_UINT:
3935 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3936 ds->offset_scale = 4.0f;
3937 break;
3938 case VK_FORMAT_D32_SFLOAT:
3939 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3940 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3941 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3942 ds->offset_scale = 1.0f;
3943 break;
3944 case VK_FORMAT_S8_UINT:
3945 stencil_only = true;
3946 break;
3947 default:
3948 break;
3949 }
3950
3951 format = radv_translate_dbformat(iview->image->vk_format);
3952 stencil_format = iview->image->surface.has_stencil ?
3953 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3954
3955 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3956 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3957 S_028008_SLICE_MAX(max_slice);
3958
3959 ds->db_htile_data_base = 0;
3960 ds->db_htile_surface = 0;
3961
3962 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3963 s_offs = z_offs = va;
3964
3965 if (device->physical_device->rad_info.chip_class >= GFX9) {
3966 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3967 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3968
3969 ds->db_z_info = S_028038_FORMAT(format) |
3970 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3971 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3972 S_028038_MAXMIP(iview->image->info.levels - 1);
3973 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3974 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3975
3976 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3977 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3978 ds->db_depth_view |= S_028008_MIPID(level);
3979
3980 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3981 S_02801C_Y_MAX(iview->image->info.height - 1);
3982
3983 if (radv_htile_enabled(iview->image, level)) {
3984 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3985
3986 if (radv_image_is_tc_compat_htile(iview->image)) {
3987 unsigned max_zplanes =
3988 radv_calc_decompress_on_z_planes(device, iview);
3989
3990 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3991 S_028038_ITERATE_FLUSH(1);
3992 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3993 }
3994
3995 if (!iview->image->surface.has_stencil)
3996 /* Use all of the htile_buffer for depth if there's no stencil. */
3997 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3998 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3999 iview->image->htile_offset;
4000 ds->db_htile_data_base = va >> 8;
4001 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4002 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4003 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4004 }
4005 } else {
4006 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4007
4008 if (stencil_only)
4009 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4010
4011 z_offs += iview->image->surface.u.legacy.level[level].offset;
4012 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4013
4014 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4015 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4016 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4017
4018 if (iview->image->info.samples > 1)
4019 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4020
4021 if (device->physical_device->rad_info.chip_class >= CIK) {
4022 struct radeon_info *info = &device->physical_device->rad_info;
4023 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4024 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4025 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4026 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4027 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4028 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4029
4030 if (stencil_only)
4031 tile_mode = stencil_tile_mode;
4032
4033 ds->db_depth_info |=
4034 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4035 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4036 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4037 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4038 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4039 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4040 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4041 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4042 } else {
4043 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4044 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4045 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4046 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4047 if (stencil_only)
4048 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4049 }
4050
4051 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4052 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4053 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4054
4055 if (radv_htile_enabled(iview->image, level)) {
4056 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4057
4058 if (!iview->image->surface.has_stencil &&
4059 !radv_image_is_tc_compat_htile(iview->image))
4060 /* Use all of the htile_buffer for depth if there's no stencil. */
4061 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4062
4063 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4064 iview->image->htile_offset;
4065 ds->db_htile_data_base = va >> 8;
4066 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4067
4068 if (radv_image_is_tc_compat_htile(iview->image)) {
4069 unsigned max_zplanes =
4070 radv_calc_decompress_on_z_planes(device, iview);
4071
4072 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4073 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4074 }
4075 }
4076 }
4077
4078 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4079 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4080 }
4081
4082 VkResult radv_CreateFramebuffer(
4083 VkDevice _device,
4084 const VkFramebufferCreateInfo* pCreateInfo,
4085 const VkAllocationCallbacks* pAllocator,
4086 VkFramebuffer* pFramebuffer)
4087 {
4088 RADV_FROM_HANDLE(radv_device, device, _device);
4089 struct radv_framebuffer *framebuffer;
4090
4091 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4092
4093 size_t size = sizeof(*framebuffer) +
4094 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4095 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4096 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4097 if (framebuffer == NULL)
4098 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4099
4100 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4101 framebuffer->width = pCreateInfo->width;
4102 framebuffer->height = pCreateInfo->height;
4103 framebuffer->layers = pCreateInfo->layers;
4104 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4105 VkImageView _iview = pCreateInfo->pAttachments[i];
4106 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4107 framebuffer->attachments[i].attachment = iview;
4108 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4109 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4110 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4111 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4112 }
4113 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4114 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4115 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4116 }
4117
4118 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4119 return VK_SUCCESS;
4120 }
4121
4122 void radv_DestroyFramebuffer(
4123 VkDevice _device,
4124 VkFramebuffer _fb,
4125 const VkAllocationCallbacks* pAllocator)
4126 {
4127 RADV_FROM_HANDLE(radv_device, device, _device);
4128 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4129
4130 if (!fb)
4131 return;
4132 vk_free2(&device->alloc, pAllocator, fb);
4133 }
4134
4135 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4136 {
4137 switch (address_mode) {
4138 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4139 return V_008F30_SQ_TEX_WRAP;
4140 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4141 return V_008F30_SQ_TEX_MIRROR;
4142 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4143 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4144 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4145 return V_008F30_SQ_TEX_CLAMP_BORDER;
4146 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4147 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4148 default:
4149 unreachable("illegal tex wrap mode");
4150 break;
4151 }
4152 }
4153
4154 static unsigned
4155 radv_tex_compare(VkCompareOp op)
4156 {
4157 switch (op) {
4158 case VK_COMPARE_OP_NEVER:
4159 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4160 case VK_COMPARE_OP_LESS:
4161 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4162 case VK_COMPARE_OP_EQUAL:
4163 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4164 case VK_COMPARE_OP_LESS_OR_EQUAL:
4165 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4166 case VK_COMPARE_OP_GREATER:
4167 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4168 case VK_COMPARE_OP_NOT_EQUAL:
4169 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4170 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4171 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4172 case VK_COMPARE_OP_ALWAYS:
4173 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4174 default:
4175 unreachable("illegal compare mode");
4176 break;
4177 }
4178 }
4179
4180 static unsigned
4181 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4182 {
4183 switch (filter) {
4184 case VK_FILTER_NEAREST:
4185 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4186 V_008F38_SQ_TEX_XY_FILTER_POINT);
4187 case VK_FILTER_LINEAR:
4188 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4189 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4190 case VK_FILTER_CUBIC_IMG:
4191 default:
4192 fprintf(stderr, "illegal texture filter");
4193 return 0;
4194 }
4195 }
4196
4197 static unsigned
4198 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4199 {
4200 switch (mode) {
4201 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4202 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4203 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4204 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4205 default:
4206 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4207 }
4208 }
4209
4210 static unsigned
4211 radv_tex_bordercolor(VkBorderColor bcolor)
4212 {
4213 switch (bcolor) {
4214 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4215 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4216 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4217 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4218 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4219 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4220 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4221 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4222 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4223 default:
4224 break;
4225 }
4226 return 0;
4227 }
4228
4229 static unsigned
4230 radv_tex_aniso_filter(unsigned filter)
4231 {
4232 if (filter < 2)
4233 return 0;
4234 if (filter < 4)
4235 return 1;
4236 if (filter < 8)
4237 return 2;
4238 if (filter < 16)
4239 return 3;
4240 return 4;
4241 }
4242
4243 static unsigned
4244 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4245 {
4246 switch (mode) {
4247 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4248 return SQ_IMG_FILTER_MODE_BLEND;
4249 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4250 return SQ_IMG_FILTER_MODE_MIN;
4251 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4252 return SQ_IMG_FILTER_MODE_MAX;
4253 default:
4254 break;
4255 }
4256 return 0;
4257 }
4258
4259 static void
4260 radv_init_sampler(struct radv_device *device,
4261 struct radv_sampler *sampler,
4262 const VkSamplerCreateInfo *pCreateInfo)
4263 {
4264 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4265 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4266 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4267 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4268 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4269
4270 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4271 vk_find_struct_const(pCreateInfo->pNext,
4272 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4273 if (sampler_reduction)
4274 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4275
4276 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4277 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4278 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4279 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4280 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4281 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4282 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4283 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4284 S_008F30_DISABLE_CUBE_WRAP(0) |
4285 S_008F30_COMPAT_MODE(is_vi) |
4286 S_008F30_FILTER_MODE(filter_mode));
4287 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4288 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4289 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4290 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4291 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4292 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4293 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4294 S_008F38_MIP_POINT_PRECLAMP(0) |
4295 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4296 S_008F38_FILTER_PREC_FIX(1) |
4297 S_008F38_ANISO_OVERRIDE(is_vi));
4298 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4299 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4300 }
4301
4302 VkResult radv_CreateSampler(
4303 VkDevice _device,
4304 const VkSamplerCreateInfo* pCreateInfo,
4305 const VkAllocationCallbacks* pAllocator,
4306 VkSampler* pSampler)
4307 {
4308 RADV_FROM_HANDLE(radv_device, device, _device);
4309 struct radv_sampler *sampler;
4310
4311 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4312
4313 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4314 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4315 if (!sampler)
4316 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4317
4318 radv_init_sampler(device, sampler, pCreateInfo);
4319 *pSampler = radv_sampler_to_handle(sampler);
4320
4321 return VK_SUCCESS;
4322 }
4323
4324 void radv_DestroySampler(
4325 VkDevice _device,
4326 VkSampler _sampler,
4327 const VkAllocationCallbacks* pAllocator)
4328 {
4329 RADV_FROM_HANDLE(radv_device, device, _device);
4330 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4331
4332 if (!sampler)
4333 return;
4334 vk_free2(&device->alloc, pAllocator, sampler);
4335 }
4336
4337 /* vk_icd.h does not declare this function, so we declare it here to
4338 * suppress Wmissing-prototypes.
4339 */
4340 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4341 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4342
4343 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4344 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4345 {
4346 /* For the full details on loader interface versioning, see
4347 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4348 * What follows is a condensed summary, to help you navigate the large and
4349 * confusing official doc.
4350 *
4351 * - Loader interface v0 is incompatible with later versions. We don't
4352 * support it.
4353 *
4354 * - In loader interface v1:
4355 * - The first ICD entrypoint called by the loader is
4356 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4357 * entrypoint.
4358 * - The ICD must statically expose no other Vulkan symbol unless it is
4359 * linked with -Bsymbolic.
4360 * - Each dispatchable Vulkan handle created by the ICD must be
4361 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4362 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4363 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4364 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4365 * such loader-managed surfaces.
4366 *
4367 * - Loader interface v2 differs from v1 in:
4368 * - The first ICD entrypoint called by the loader is
4369 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4370 * statically expose this entrypoint.
4371 *
4372 * - Loader interface v3 differs from v2 in:
4373 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4374 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4375 * because the loader no longer does so.
4376 */
4377 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4378 return VK_SUCCESS;
4379 }
4380
4381 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4382 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4383 int *pFD)
4384 {
4385 RADV_FROM_HANDLE(radv_device, device, _device);
4386 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4387
4388 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4389
4390 /* At the moment, we support only the below handle types. */
4391 assert(pGetFdInfo->handleType ==
4392 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4393 pGetFdInfo->handleType ==
4394 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4395
4396 bool ret = radv_get_memory_fd(device, memory, pFD);
4397 if (ret == false)
4398 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4399 return VK_SUCCESS;
4400 }
4401
4402 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4403 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4404 int fd,
4405 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4406 {
4407 RADV_FROM_HANDLE(radv_device, device, _device);
4408
4409 switch (handleType) {
4410 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4411 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4412 return VK_SUCCESS;
4413
4414 default:
4415 /* The valid usage section for this function says:
4416 *
4417 * "handleType must not be one of the handle types defined as
4418 * opaque."
4419 *
4420 * So opaque handle types fall into the default "unsupported" case.
4421 */
4422 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4423 }
4424 }
4425
4426 static VkResult radv_import_opaque_fd(struct radv_device *device,
4427 int fd,
4428 uint32_t *syncobj)
4429 {
4430 uint32_t syncobj_handle = 0;
4431 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4432 if (ret != 0)
4433 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4434
4435 if (*syncobj)
4436 device->ws->destroy_syncobj(device->ws, *syncobj);
4437
4438 *syncobj = syncobj_handle;
4439 close(fd);
4440
4441 return VK_SUCCESS;
4442 }
4443
4444 static VkResult radv_import_sync_fd(struct radv_device *device,
4445 int fd,
4446 uint32_t *syncobj)
4447 {
4448 /* If we create a syncobj we do it locally so that if we have an error, we don't
4449 * leave a syncobj in an undetermined state in the fence. */
4450 uint32_t syncobj_handle = *syncobj;
4451 if (!syncobj_handle) {
4452 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4453 if (ret) {
4454 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4455 }
4456 }
4457
4458 if (fd == -1) {
4459 device->ws->signal_syncobj(device->ws, syncobj_handle);
4460 } else {
4461 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4462 if (ret != 0)
4463 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4464 }
4465
4466 *syncobj = syncobj_handle;
4467 if (fd != -1)
4468 close(fd);
4469
4470 return VK_SUCCESS;
4471 }
4472
4473 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4474 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4475 {
4476 RADV_FROM_HANDLE(radv_device, device, _device);
4477 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4478 uint32_t *syncobj_dst = NULL;
4479
4480 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4481 syncobj_dst = &sem->temp_syncobj;
4482 } else {
4483 syncobj_dst = &sem->syncobj;
4484 }
4485
4486 switch(pImportSemaphoreFdInfo->handleType) {
4487 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4488 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4489 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4490 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4491 default:
4492 unreachable("Unhandled semaphore handle type");
4493 }
4494 }
4495
4496 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4497 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4498 int *pFd)
4499 {
4500 RADV_FROM_HANDLE(radv_device, device, _device);
4501 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4502 int ret;
4503 uint32_t syncobj_handle;
4504
4505 if (sem->temp_syncobj)
4506 syncobj_handle = sem->temp_syncobj;
4507 else
4508 syncobj_handle = sem->syncobj;
4509
4510 switch(pGetFdInfo->handleType) {
4511 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4512 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4513 break;
4514 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4515 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4516 if (!ret) {
4517 if (sem->temp_syncobj) {
4518 close (sem->temp_syncobj);
4519 sem->temp_syncobj = 0;
4520 } else {
4521 device->ws->reset_syncobj(device->ws, syncobj_handle);
4522 }
4523 }
4524 break;
4525 default:
4526 unreachable("Unhandled semaphore handle type");
4527 }
4528
4529 if (ret)
4530 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4531 return VK_SUCCESS;
4532 }
4533
4534 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4535 VkPhysicalDevice physicalDevice,
4536 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4537 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4538 {
4539 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4540
4541 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4542 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4543 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4544 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4545 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4546 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4547 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4548 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4549 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4550 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4551 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4552 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4553 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4554 } else {
4555 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4556 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4557 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4558 }
4559 }
4560
4561 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4562 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4563 {
4564 RADV_FROM_HANDLE(radv_device, device, _device);
4565 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4566 uint32_t *syncobj_dst = NULL;
4567
4568
4569 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4570 syncobj_dst = &fence->temp_syncobj;
4571 } else {
4572 syncobj_dst = &fence->syncobj;
4573 }
4574
4575 switch(pImportFenceFdInfo->handleType) {
4576 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4577 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4578 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4579 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4580 default:
4581 unreachable("Unhandled fence handle type");
4582 }
4583 }
4584
4585 VkResult radv_GetFenceFdKHR(VkDevice _device,
4586 const VkFenceGetFdInfoKHR *pGetFdInfo,
4587 int *pFd)
4588 {
4589 RADV_FROM_HANDLE(radv_device, device, _device);
4590 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4591 int ret;
4592 uint32_t syncobj_handle;
4593
4594 if (fence->temp_syncobj)
4595 syncobj_handle = fence->temp_syncobj;
4596 else
4597 syncobj_handle = fence->syncobj;
4598
4599 switch(pGetFdInfo->handleType) {
4600 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4601 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4602 break;
4603 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4604 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4605 if (!ret) {
4606 if (fence->temp_syncobj) {
4607 close (fence->temp_syncobj);
4608 fence->temp_syncobj = 0;
4609 } else {
4610 device->ws->reset_syncobj(device->ws, syncobj_handle);
4611 }
4612 }
4613 break;
4614 default:
4615 unreachable("Unhandled fence handle type");
4616 }
4617
4618 if (ret)
4619 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4620 return VK_SUCCESS;
4621 }
4622
4623 void radv_GetPhysicalDeviceExternalFenceProperties(
4624 VkPhysicalDevice physicalDevice,
4625 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4626 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4627 {
4628 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4629
4630 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4631 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4632 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4633 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4634 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4635 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4636 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4637 } else {
4638 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4639 pExternalFenceProperties->compatibleHandleTypes = 0;
4640 pExternalFenceProperties->externalFenceFeatures = 0;
4641 }
4642 }
4643
4644 VkResult
4645 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4646 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4647 const VkAllocationCallbacks* pAllocator,
4648 VkDebugReportCallbackEXT* pCallback)
4649 {
4650 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4651 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4652 pCreateInfo, pAllocator, &instance->alloc,
4653 pCallback);
4654 }
4655
4656 void
4657 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4658 VkDebugReportCallbackEXT _callback,
4659 const VkAllocationCallbacks* pAllocator)
4660 {
4661 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4662 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4663 _callback, pAllocator, &instance->alloc);
4664 }
4665
4666 void
4667 radv_DebugReportMessageEXT(VkInstance _instance,
4668 VkDebugReportFlagsEXT flags,
4669 VkDebugReportObjectTypeEXT objectType,
4670 uint64_t object,
4671 size_t location,
4672 int32_t messageCode,
4673 const char* pLayerPrefix,
4674 const char* pMessage)
4675 {
4676 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4677 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4678 object, location, messageCode, pLayerPrefix, pMessage);
4679 }
4680
4681 void
4682 radv_GetDeviceGroupPeerMemoryFeatures(
4683 VkDevice device,
4684 uint32_t heapIndex,
4685 uint32_t localDeviceIndex,
4686 uint32_t remoteDeviceIndex,
4687 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4688 {
4689 assert(localDeviceIndex == remoteDeviceIndex);
4690
4691 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4692 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4693 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4694 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4695 }