2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_private.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
46 #include "util/debug.h"
49 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
51 uint32_t mesa_timestamp
, llvm_timestamp
;
53 memset(uuid
, 0, VK_UUID_SIZE
);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
58 memcpy(uuid
, &mesa_timestamp
, 4);
59 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
60 memcpy((char*)uuid
+ 8, &f
, 2);
61 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
66 radv_get_device_uuid(drmDevicePtr device
, void *uuid
) {
67 memset(uuid
, 0, VK_UUID_SIZE
);
68 memcpy((char*)uuid
+ 0, &device
->businfo
.pci
->domain
, 2);
69 memcpy((char*)uuid
+ 2, &device
->businfo
.pci
->bus
, 1);
70 memcpy((char*)uuid
+ 3, &device
->businfo
.pci
->dev
, 1);
71 memcpy((char*)uuid
+ 4, &device
->businfo
.pci
->func
, 1);
74 static const VkExtensionProperties instance_extensions
[] = {
76 .extensionName
= VK_KHR_SURFACE_EXTENSION_NAME
,
79 #ifdef VK_USE_PLATFORM_XCB_KHR
81 .extensionName
= VK_KHR_XCB_SURFACE_EXTENSION_NAME
,
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
87 .extensionName
= VK_KHR_XLIB_SURFACE_EXTENSION_NAME
,
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
93 .extensionName
= VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME
,
98 .extensionName
= VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME
,
102 .extensionName
= VK_KHX_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME
,
107 static const VkExtensionProperties common_device_extensions
[] = {
109 .extensionName
= VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME
,
113 .extensionName
= VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME
,
117 .extensionName
= VK_KHR_MAINTENANCE1_EXTENSION_NAME
,
121 .extensionName
= VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME
,
125 .extensionName
= VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME
,
129 .extensionName
= VK_KHR_SWAPCHAIN_EXTENSION_NAME
,
133 .extensionName
= VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME
,
137 .extensionName
= VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME
,
141 .extensionName
= VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME
,
145 .extensionName
= VK_KHX_EXTERNAL_MEMORY_EXTENSION_NAME
,
149 .extensionName
= VK_KHX_EXTERNAL_MEMORY_FD_EXTENSION_NAME
,
155 radv_extensions_register(struct radv_instance
*instance
,
156 struct radv_extensions
*extensions
,
157 const VkExtensionProperties
*new_ext
,
161 VkExtensionProperties
*new_ptr
;
163 assert(new_ext
&& num_ext
> 0);
166 return VK_ERROR_INITIALIZATION_FAILED
;
168 new_size
= (extensions
->num_ext
+ num_ext
) * sizeof(VkExtensionProperties
);
169 new_ptr
= vk_realloc(&instance
->alloc
, extensions
->ext_array
,
170 new_size
, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
172 /* Old array continues to be valid, update nothing */
174 return VK_ERROR_OUT_OF_HOST_MEMORY
;
176 memcpy(&new_ptr
[extensions
->num_ext
], new_ext
,
177 num_ext
* sizeof(VkExtensionProperties
));
178 extensions
->ext_array
= new_ptr
;
179 extensions
->num_ext
+= num_ext
;
185 radv_extensions_finish(struct radv_instance
*instance
,
186 struct radv_extensions
*extensions
)
191 radv_loge("Attemted to free invalid extension struct\n");
193 if (extensions
->ext_array
)
194 vk_free(&instance
->alloc
, extensions
->ext_array
);
198 is_extension_enabled(const VkExtensionProperties
*extensions
,
202 assert(extensions
&& name
);
204 for (uint32_t i
= 0; i
< num_ext
; i
++) {
205 if (strcmp(name
, extensions
[i
].extensionName
) == 0)
213 get_chip_name(enum radeon_family family
)
216 case CHIP_TAHITI
: return "AMD RADV TAHITI";
217 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
218 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
219 case CHIP_OLAND
: return "AMD RADV OLAND";
220 case CHIP_HAINAN
: return "AMD RADV HAINAN";
221 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
222 case CHIP_KAVERI
: return "AMD RADV KAVERI";
223 case CHIP_KABINI
: return "AMD RADV KABINI";
224 case CHIP_HAWAII
: return "AMD RADV HAWAII";
225 case CHIP_MULLINS
: return "AMD RADV MULLINS";
226 case CHIP_TONGA
: return "AMD RADV TONGA";
227 case CHIP_ICELAND
: return "AMD RADV ICELAND";
228 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
229 case CHIP_FIJI
: return "AMD RADV FIJI";
230 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
231 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
232 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
233 case CHIP_STONEY
: return "AMD RADV STONEY";
234 case CHIP_VEGA10
: return "AMD RADV VEGA";
235 case CHIP_RAVEN
: return "AMD RADV RAVEN";
236 default: return "AMD RADV unknown";
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
250 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
252 return VK_ERROR_INCOMPATIBLE_DRIVER
;
254 version
= drmGetVersion(fd
);
257 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
258 "failed to get version %s: %m", path
);
261 if (strcmp(version
->name
, "amdgpu")) {
262 drmFreeVersion(version
);
264 return VK_ERROR_INCOMPATIBLE_DRIVER
;
266 drmFreeVersion(version
);
268 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
269 device
->instance
= instance
;
270 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
271 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
273 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
274 instance
->perftest_flags
);
276 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
280 device
->local_fd
= fd
;
281 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
282 result
= radv_init_wsi(device
);
283 if (result
!= VK_SUCCESS
) {
284 device
->ws
->destroy(device
->ws
);
288 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->uuid
)) {
289 radv_finish_wsi(device
);
290 device
->ws
->destroy(device
->ws
);
291 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
292 "cannot generate UUID");
296 result
= radv_extensions_register(instance
,
298 common_device_extensions
,
299 ARRAY_SIZE(common_device_extensions
));
300 if (result
!= VK_SUCCESS
)
303 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
304 device
->name
= get_chip_name(device
->rad_info
.family
);
306 radv_get_device_uuid(drm_device
, device
->device_uuid
);
308 if (device
->rad_info
.family
== CHIP_STONEY
||
309 device
->rad_info
.chip_class
>= GFX9
) {
310 device
->has_rbplus
= true;
311 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
322 radv_physical_device_finish(struct radv_physical_device
*device
)
324 radv_extensions_finish(device
->instance
, &device
->extensions
);
325 radv_finish_wsi(device
);
326 device
->ws
->destroy(device
->ws
);
327 close(device
->local_fd
);
331 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
332 VkSystemAllocationScope allocationScope
)
338 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
339 size_t align
, VkSystemAllocationScope allocationScope
)
341 return realloc(pOriginal
, size
);
345 default_free_func(void *pUserData
, void *pMemory
)
350 static const VkAllocationCallbacks default_alloc
= {
352 .pfnAllocation
= default_alloc_func
,
353 .pfnReallocation
= default_realloc_func
,
354 .pfnFree
= default_free_func
,
357 static const struct debug_control radv_debug_options
[] = {
358 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
359 {"nodcc", RADV_DEBUG_NO_DCC
},
360 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
361 {"nocache", RADV_DEBUG_NO_CACHE
},
362 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
363 {"nohiz", RADV_DEBUG_NO_HIZ
},
364 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
365 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
366 {"allbos", RADV_DEBUG_ALL_BOS
},
367 {"noibs", RADV_DEBUG_NO_IBS
},
371 static const struct debug_control radv_perftest_options
[] = {
372 {"batchchain", RADV_PERFTEST_BATCHCHAIN
},
376 VkResult
radv_CreateInstance(
377 const VkInstanceCreateInfo
* pCreateInfo
,
378 const VkAllocationCallbacks
* pAllocator
,
379 VkInstance
* pInstance
)
381 struct radv_instance
*instance
;
383 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
385 uint32_t client_version
;
386 if (pCreateInfo
->pApplicationInfo
&&
387 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
388 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
390 client_version
= VK_MAKE_VERSION(1, 0, 0);
393 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
394 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
395 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
396 "Client requested version %d.%d.%d",
397 VK_VERSION_MAJOR(client_version
),
398 VK_VERSION_MINOR(client_version
),
399 VK_VERSION_PATCH(client_version
));
402 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
403 if (!is_extension_enabled(instance_extensions
,
404 ARRAY_SIZE(instance_extensions
),
405 pCreateInfo
->ppEnabledExtensionNames
[i
]))
406 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
409 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
410 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
412 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
414 memset(instance
, 0, sizeof(*instance
));
416 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
419 instance
->alloc
= *pAllocator
;
421 instance
->alloc
= default_alloc
;
423 instance
->apiVersion
= client_version
;
424 instance
->physicalDeviceCount
= -1;
428 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
430 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
433 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
434 radv_perftest_options
);
436 *pInstance
= radv_instance_to_handle(instance
);
441 void radv_DestroyInstance(
442 VkInstance _instance
,
443 const VkAllocationCallbacks
* pAllocator
)
445 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
450 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
451 radv_physical_device_finish(instance
->physicalDevices
+ i
);
454 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
458 vk_free(&instance
->alloc
, instance
);
462 radv_enumerate_devices(struct radv_instance
*instance
)
464 /* TODO: Check for more devices ? */
465 drmDevicePtr devices
[8];
466 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
469 instance
->physicalDeviceCount
= 0;
471 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
473 return VK_ERROR_INCOMPATIBLE_DRIVER
;
475 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
476 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
477 devices
[i
]->bustype
== DRM_BUS_PCI
&&
478 devices
[i
]->deviceinfo
.pci
->vendor_id
== 0x1002) {
480 result
= radv_physical_device_init(instance
->physicalDevices
+
481 instance
->physicalDeviceCount
,
484 if (result
== VK_SUCCESS
)
485 ++instance
->physicalDeviceCount
;
486 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
490 drmFreeDevices(devices
, max_devices
);
495 VkResult
radv_EnumeratePhysicalDevices(
496 VkInstance _instance
,
497 uint32_t* pPhysicalDeviceCount
,
498 VkPhysicalDevice
* pPhysicalDevices
)
500 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
503 if (instance
->physicalDeviceCount
< 0) {
504 result
= radv_enumerate_devices(instance
);
505 if (result
!= VK_SUCCESS
&&
506 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
510 if (!pPhysicalDevices
) {
511 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
513 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
514 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
515 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
518 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
522 void radv_GetPhysicalDeviceFeatures(
523 VkPhysicalDevice physicalDevice
,
524 VkPhysicalDeviceFeatures
* pFeatures
)
526 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
527 bool is_gfx9
= pdevice
->rad_info
.chip_class
>= GFX9
;
528 memset(pFeatures
, 0, sizeof(*pFeatures
));
530 *pFeatures
= (VkPhysicalDeviceFeatures
) {
531 .robustBufferAccess
= true,
532 .fullDrawIndexUint32
= true,
533 .imageCubeArray
= true,
534 .independentBlend
= true,
535 .geometryShader
= !is_gfx9
,
536 .tessellationShader
= !is_gfx9
,
537 .sampleRateShading
= false,
538 .dualSrcBlend
= true,
540 .multiDrawIndirect
= true,
541 .drawIndirectFirstInstance
= true,
543 .depthBiasClamp
= true,
544 .fillModeNonSolid
= true,
549 .multiViewport
= true,
550 .samplerAnisotropy
= true,
551 .textureCompressionETC2
= false,
552 .textureCompressionASTC_LDR
= false,
553 .textureCompressionBC
= true,
554 .occlusionQueryPrecise
= true,
555 .pipelineStatisticsQuery
= true,
556 .vertexPipelineStoresAndAtomics
= true,
557 .fragmentStoresAndAtomics
= true,
558 .shaderTessellationAndGeometryPointSize
= true,
559 .shaderImageGatherExtended
= true,
560 .shaderStorageImageExtendedFormats
= true,
561 .shaderStorageImageMultisample
= false,
562 .shaderUniformBufferArrayDynamicIndexing
= true,
563 .shaderSampledImageArrayDynamicIndexing
= true,
564 .shaderStorageBufferArrayDynamicIndexing
= true,
565 .shaderStorageImageArrayDynamicIndexing
= true,
566 .shaderStorageImageReadWithoutFormat
= true,
567 .shaderStorageImageWriteWithoutFormat
= true,
568 .shaderClipDistance
= true,
569 .shaderCullDistance
= true,
570 .shaderFloat64
= true,
571 .shaderInt64
= false,
572 .shaderInt16
= false,
573 .sparseBinding
= true,
574 .variableMultisampleRate
= true,
575 .inheritedQueries
= true,
579 void radv_GetPhysicalDeviceFeatures2KHR(
580 VkPhysicalDevice physicalDevice
,
581 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
583 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
586 void radv_GetPhysicalDeviceProperties(
587 VkPhysicalDevice physicalDevice
,
588 VkPhysicalDeviceProperties
* pProperties
)
590 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
591 VkSampleCountFlags sample_counts
= 0xf;
593 /* make sure that the entire descriptor set is addressable with a signed
594 * 32-bit int. So the sum of all limits scaled by descriptor size has to
595 * be at most 2 GiB. the combined image & samples object count as one of
596 * both. This limit is for the pipeline layout, not for the set layout, but
597 * there is no set limit, so we just set a pipeline limit. I don't think
598 * any app is going to hit this soon. */
599 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
600 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
601 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
602 32 /* sampler, largest when combined with image */ +
603 64 /* sampled image */ +
604 64 /* storage image */);
606 VkPhysicalDeviceLimits limits
= {
607 .maxImageDimension1D
= (1 << 14),
608 .maxImageDimension2D
= (1 << 14),
609 .maxImageDimension3D
= (1 << 11),
610 .maxImageDimensionCube
= (1 << 14),
611 .maxImageArrayLayers
= (1 << 11),
612 .maxTexelBufferElements
= 128 * 1024 * 1024,
613 .maxUniformBufferRange
= UINT32_MAX
,
614 .maxStorageBufferRange
= UINT32_MAX
,
615 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
616 .maxMemoryAllocationCount
= UINT32_MAX
,
617 .maxSamplerAllocationCount
= 64 * 1024,
618 .bufferImageGranularity
= 64, /* A cache line */
619 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
620 .maxBoundDescriptorSets
= MAX_SETS
,
621 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
622 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
623 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
624 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
625 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
626 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
627 .maxPerStageResources
= max_descriptor_set_size
,
628 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
629 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
630 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
631 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
632 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
633 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
634 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
635 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
636 .maxVertexInputAttributes
= 32,
637 .maxVertexInputBindings
= 32,
638 .maxVertexInputAttributeOffset
= 2047,
639 .maxVertexInputBindingStride
= 2048,
640 .maxVertexOutputComponents
= 128,
641 .maxTessellationGenerationLevel
= 64,
642 .maxTessellationPatchSize
= 32,
643 .maxTessellationControlPerVertexInputComponents
= 128,
644 .maxTessellationControlPerVertexOutputComponents
= 128,
645 .maxTessellationControlPerPatchOutputComponents
= 120,
646 .maxTessellationControlTotalOutputComponents
= 4096,
647 .maxTessellationEvaluationInputComponents
= 128,
648 .maxTessellationEvaluationOutputComponents
= 128,
649 .maxGeometryShaderInvocations
= 127,
650 .maxGeometryInputComponents
= 64,
651 .maxGeometryOutputComponents
= 128,
652 .maxGeometryOutputVertices
= 256,
653 .maxGeometryTotalOutputComponents
= 1024,
654 .maxFragmentInputComponents
= 128,
655 .maxFragmentOutputAttachments
= 8,
656 .maxFragmentDualSrcAttachments
= 1,
657 .maxFragmentCombinedOutputResources
= 8,
658 .maxComputeSharedMemorySize
= 32768,
659 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
660 .maxComputeWorkGroupInvocations
= 2048,
661 .maxComputeWorkGroupSize
= {
666 .subPixelPrecisionBits
= 4 /* FIXME */,
667 .subTexelPrecisionBits
= 4 /* FIXME */,
668 .mipmapPrecisionBits
= 4 /* FIXME */,
669 .maxDrawIndexedIndexValue
= UINT32_MAX
,
670 .maxDrawIndirectCount
= UINT32_MAX
,
671 .maxSamplerLodBias
= 16,
672 .maxSamplerAnisotropy
= 16,
673 .maxViewports
= MAX_VIEWPORTS
,
674 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
675 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
676 .viewportSubPixelBits
= 13, /* We take a float? */
677 .minMemoryMapAlignment
= 4096, /* A page */
678 .minTexelBufferOffsetAlignment
= 1,
679 .minUniformBufferOffsetAlignment
= 4,
680 .minStorageBufferOffsetAlignment
= 4,
681 .minTexelOffset
= -32,
682 .maxTexelOffset
= 31,
683 .minTexelGatherOffset
= -32,
684 .maxTexelGatherOffset
= 31,
685 .minInterpolationOffset
= -2,
686 .maxInterpolationOffset
= 2,
687 .subPixelInterpolationOffsetBits
= 8,
688 .maxFramebufferWidth
= (1 << 14),
689 .maxFramebufferHeight
= (1 << 14),
690 .maxFramebufferLayers
= (1 << 10),
691 .framebufferColorSampleCounts
= sample_counts
,
692 .framebufferDepthSampleCounts
= sample_counts
,
693 .framebufferStencilSampleCounts
= sample_counts
,
694 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
695 .maxColorAttachments
= MAX_RTS
,
696 .sampledImageColorSampleCounts
= sample_counts
,
697 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
698 .sampledImageDepthSampleCounts
= sample_counts
,
699 .sampledImageStencilSampleCounts
= sample_counts
,
700 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
701 .maxSampleMaskWords
= 1,
702 .timestampComputeAndGraphics
= true,
703 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
704 .maxClipDistances
= 8,
705 .maxCullDistances
= 8,
706 .maxCombinedClipAndCullDistances
= 8,
707 .discreteQueuePriorities
= 1,
708 .pointSizeRange
= { 0.125, 255.875 },
709 .lineWidthRange
= { 0.0, 7.9921875 },
710 .pointSizeGranularity
= (1.0 / 8.0),
711 .lineWidthGranularity
= (1.0 / 128.0),
712 .strictLines
= false, /* FINISHME */
713 .standardSampleLocations
= true,
714 .optimalBufferCopyOffsetAlignment
= 128,
715 .optimalBufferCopyRowPitchAlignment
= 128,
716 .nonCoherentAtomSize
= 64,
719 *pProperties
= (VkPhysicalDeviceProperties
) {
720 .apiVersion
= VK_MAKE_VERSION(1, 0, 42),
721 .driverVersion
= vk_get_driver_version(),
723 .deviceID
= pdevice
->rad_info
.pci_id
,
724 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
726 .sparseProperties
= {0},
729 strcpy(pProperties
->deviceName
, pdevice
->name
);
730 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->uuid
, VK_UUID_SIZE
);
733 void radv_GetPhysicalDeviceProperties2KHR(
734 VkPhysicalDevice physicalDevice
,
735 VkPhysicalDeviceProperties2KHR
*pProperties
)
737 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
738 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
740 vk_foreach_struct(ext
, pProperties
->pNext
) {
741 switch (ext
->sType
) {
742 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
743 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
744 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
745 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHX
: {
749 VkPhysicalDeviceIDPropertiesKHX
*properties
= (VkPhysicalDeviceIDPropertiesKHX
*)ext
;
750 radv_device_get_cache_uuid(0, properties
->driverUUID
);
751 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
752 properties
->deviceLUIDValid
= false;
761 static void radv_get_physical_device_queue_family_properties(
762 struct radv_physical_device
* pdevice
,
764 VkQueueFamilyProperties
** pQueueFamilyProperties
)
766 int num_queue_families
= 1;
768 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
769 pdevice
->rad_info
.chip_class
>= CIK
&&
770 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
771 num_queue_families
++;
773 if (pQueueFamilyProperties
== NULL
) {
774 *pCount
= num_queue_families
;
783 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
784 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
785 VK_QUEUE_COMPUTE_BIT
|
786 VK_QUEUE_TRANSFER_BIT
|
787 VK_QUEUE_SPARSE_BINDING_BIT
,
789 .timestampValidBits
= 64,
790 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
795 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
796 pdevice
->rad_info
.chip_class
>= CIK
&&
797 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
799 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
800 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
801 VK_QUEUE_TRANSFER_BIT
|
802 VK_QUEUE_SPARSE_BINDING_BIT
,
803 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
804 .timestampValidBits
= 64,
805 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
813 void radv_GetPhysicalDeviceQueueFamilyProperties(
814 VkPhysicalDevice physicalDevice
,
816 VkQueueFamilyProperties
* pQueueFamilyProperties
)
818 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
819 if (!pQueueFamilyProperties
) {
820 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
823 VkQueueFamilyProperties
*properties
[] = {
824 pQueueFamilyProperties
+ 0,
825 pQueueFamilyProperties
+ 1,
826 pQueueFamilyProperties
+ 2,
828 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
829 assert(*pCount
<= 3);
832 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
833 VkPhysicalDevice physicalDevice
,
835 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
837 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
838 if (!pQueueFamilyProperties
) {
839 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
842 VkQueueFamilyProperties
*properties
[] = {
843 &pQueueFamilyProperties
[0].queueFamilyProperties
,
844 &pQueueFamilyProperties
[1].queueFamilyProperties
,
845 &pQueueFamilyProperties
[2].queueFamilyProperties
,
847 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
848 assert(*pCount
<= 3);
851 void radv_GetPhysicalDeviceMemoryProperties(
852 VkPhysicalDevice physicalDevice
,
853 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
855 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
857 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
859 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
860 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
861 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
862 .heapIndex
= RADV_MEM_HEAP_VRAM
,
864 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
865 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
866 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
867 .heapIndex
= RADV_MEM_HEAP_GTT
,
869 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
870 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
871 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
872 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
873 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
875 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
876 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
877 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
878 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
879 .heapIndex
= RADV_MEM_HEAP_GTT
,
882 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
884 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
885 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
886 .size
= physical_device
->rad_info
.vram_size
-
887 physical_device
->rad_info
.vram_vis_size
,
888 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
890 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
891 .size
= physical_device
->rad_info
.vram_vis_size
,
892 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
894 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
895 .size
= physical_device
->rad_info
.gart_size
,
900 void radv_GetPhysicalDeviceMemoryProperties2KHR(
901 VkPhysicalDevice physicalDevice
,
902 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
904 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
905 &pMemoryProperties
->memoryProperties
);
909 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
910 int queue_family_index
, int idx
)
912 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
913 queue
->device
= device
;
914 queue
->queue_family_index
= queue_family_index
;
915 queue
->queue_idx
= idx
;
917 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
);
919 return VK_ERROR_OUT_OF_HOST_MEMORY
;
925 radv_queue_finish(struct radv_queue
*queue
)
928 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
930 if (queue
->initial_preamble_cs
)
931 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
932 if (queue
->continue_preamble_cs
)
933 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
934 if (queue
->descriptor_bo
)
935 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
936 if (queue
->scratch_bo
)
937 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
938 if (queue
->esgs_ring_bo
)
939 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
940 if (queue
->gsvs_ring_bo
)
941 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
942 if (queue
->tess_factor_ring_bo
)
943 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
944 if (queue
->tess_offchip_ring_bo
)
945 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
946 if (queue
->compute_scratch_bo
)
947 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
951 radv_device_init_gs_info(struct radv_device
*device
)
953 switch (device
->physical_device
->rad_info
.family
) {
962 device
->gs_table_depth
= 16;
976 device
->gs_table_depth
= 32;
979 unreachable("unknown GPU");
983 VkResult
radv_CreateDevice(
984 VkPhysicalDevice physicalDevice
,
985 const VkDeviceCreateInfo
* pCreateInfo
,
986 const VkAllocationCallbacks
* pAllocator
,
989 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
991 struct radv_device
*device
;
993 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
994 if (!is_extension_enabled(physical_device
->extensions
.ext_array
,
995 physical_device
->extensions
.num_ext
,
996 pCreateInfo
->ppEnabledExtensionNames
[i
]))
997 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
1000 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
1002 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1004 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1006 memset(device
, 0, sizeof(*device
));
1008 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1009 device
->instance
= physical_device
->instance
;
1010 device
->physical_device
= physical_device
;
1012 device
->debug_flags
= device
->instance
->debug_flags
;
1014 device
->ws
= physical_device
->ws
;
1016 device
->alloc
= *pAllocator
;
1018 device
->alloc
= physical_device
->instance
->alloc
;
1020 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1021 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1022 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1024 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1025 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1026 if (!device
->queues
[qfi
]) {
1027 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1031 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1033 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1035 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1036 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
);
1037 if (result
!= VK_SUCCESS
)
1042 #if HAVE_LLVM < 0x0400
1043 device
->llvm_supports_spill
= false;
1045 device
->llvm_supports_spill
= true;
1048 /* The maximum number of scratch waves. Scratch space isn't divided
1049 * evenly between CUs. The number is only a function of the number of CUs.
1050 * We can decrease the constant to decrease the scratch buffer size.
1052 * sctx->scratch_waves must be >= the maximum posible size of
1053 * 1 threadgroup, so that the hw doesn't hang from being unable
1056 * The recommended value is 4 per CU at most. Higher numbers don't
1057 * bring much benefit, but they still occupy chip resources (think
1058 * async compute). I've seen ~2% performance difference between 4 and 32.
1060 uint32_t max_threads_per_block
= 2048;
1061 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1062 max_threads_per_block
/ 64);
1064 radv_device_init_gs_info(device
);
1066 device
->tess_offchip_block_dw_size
=
1067 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1068 device
->has_distributed_tess
=
1069 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1070 device
->physical_device
->rad_info
.max_se
>= 2;
1072 result
= radv_device_init_meta(device
);
1073 if (result
!= VK_SUCCESS
)
1076 radv_device_init_msaa(device
);
1078 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1079 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1081 case RADV_QUEUE_GENERAL
:
1082 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1083 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1084 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1086 case RADV_QUEUE_COMPUTE
:
1087 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1088 radeon_emit(device
->empty_cs
[family
], 0);
1091 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1093 device
->flush_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1095 case RADV_QUEUE_GENERAL
:
1096 case RADV_QUEUE_COMPUTE
:
1097 si_cs_emit_cache_flush(device
->flush_cs
[family
],
1098 device
->physical_device
->rad_info
.chip_class
,
1100 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1101 RADV_CMD_FLAG_INV_ICACHE
|
1102 RADV_CMD_FLAG_INV_SMEM_L1
|
1103 RADV_CMD_FLAG_INV_VMEM_L1
|
1104 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1107 device
->ws
->cs_finalize(device
->flush_cs
[family
]);
1109 device
->flush_shader_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1111 case RADV_QUEUE_GENERAL
:
1112 case RADV_QUEUE_COMPUTE
:
1113 si_cs_emit_cache_flush(device
->flush_shader_cs
[family
],
1114 device
->physical_device
->rad_info
.chip_class
,
1116 family
== RADV_QUEUE_COMPUTE
&& device
->physical_device
->rad_info
.chip_class
>= CIK
,
1117 family
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
) |
1118 RADV_CMD_FLAG_INV_ICACHE
|
1119 RADV_CMD_FLAG_INV_SMEM_L1
|
1120 RADV_CMD_FLAG_INV_VMEM_L1
|
1121 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1124 device
->ws
->cs_finalize(device
->flush_shader_cs
[family
]);
1127 if (getenv("RADV_TRACE_FILE")) {
1128 device
->trace_bo
= device
->ws
->buffer_create(device
->ws
, 4096, 8,
1129 RADEON_DOMAIN_VRAM
, RADEON_FLAG_CPU_ACCESS
);
1130 if (!device
->trace_bo
)
1133 device
->trace_id_ptr
= device
->ws
->buffer_map(device
->trace_bo
);
1134 if (!device
->trace_id_ptr
)
1138 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1139 cik_create_gfx_config(device
);
1141 VkPipelineCacheCreateInfo ci
;
1142 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1145 ci
.pInitialData
= NULL
;
1146 ci
.initialDataSize
= 0;
1148 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1150 if (result
!= VK_SUCCESS
)
1153 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1155 *pDevice
= radv_device_to_handle(device
);
1159 if (device
->trace_bo
)
1160 device
->ws
->buffer_destroy(device
->trace_bo
);
1162 if (device
->gfx_init
)
1163 device
->ws
->buffer_destroy(device
->gfx_init
);
1165 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1166 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1167 radv_queue_finish(&device
->queues
[i
][q
]);
1168 if (device
->queue_count
[i
])
1169 vk_free(&device
->alloc
, device
->queues
[i
]);
1172 vk_free(&device
->alloc
, device
);
1176 void radv_DestroyDevice(
1178 const VkAllocationCallbacks
* pAllocator
)
1180 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1185 if (device
->trace_bo
)
1186 device
->ws
->buffer_destroy(device
->trace_bo
);
1188 if (device
->gfx_init
)
1189 device
->ws
->buffer_destroy(device
->gfx_init
);
1191 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1192 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1193 radv_queue_finish(&device
->queues
[i
][q
]);
1194 if (device
->queue_count
[i
])
1195 vk_free(&device
->alloc
, device
->queues
[i
]);
1196 if (device
->empty_cs
[i
])
1197 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1198 if (device
->flush_cs
[i
])
1199 device
->ws
->cs_destroy(device
->flush_cs
[i
]);
1200 if (device
->flush_shader_cs
[i
])
1201 device
->ws
->cs_destroy(device
->flush_shader_cs
[i
]);
1203 radv_device_finish_meta(device
);
1205 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1206 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1208 vk_free(&device
->alloc
, device
);
1211 VkResult
radv_EnumerateInstanceExtensionProperties(
1212 const char* pLayerName
,
1213 uint32_t* pPropertyCount
,
1214 VkExtensionProperties
* pProperties
)
1216 if (pProperties
== NULL
) {
1217 *pPropertyCount
= ARRAY_SIZE(instance_extensions
);
1221 *pPropertyCount
= MIN2(*pPropertyCount
, ARRAY_SIZE(instance_extensions
));
1222 typed_memcpy(pProperties
, instance_extensions
, *pPropertyCount
);
1224 if (*pPropertyCount
< ARRAY_SIZE(instance_extensions
))
1225 return VK_INCOMPLETE
;
1230 VkResult
radv_EnumerateDeviceExtensionProperties(
1231 VkPhysicalDevice physicalDevice
,
1232 const char* pLayerName
,
1233 uint32_t* pPropertyCount
,
1234 VkExtensionProperties
* pProperties
)
1236 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1238 if (pProperties
== NULL
) {
1239 *pPropertyCount
= pdevice
->extensions
.num_ext
;
1243 *pPropertyCount
= MIN2(*pPropertyCount
, pdevice
->extensions
.num_ext
);
1244 typed_memcpy(pProperties
, pdevice
->extensions
.ext_array
, *pPropertyCount
);
1246 if (*pPropertyCount
< pdevice
->extensions
.num_ext
)
1247 return VK_INCOMPLETE
;
1252 VkResult
radv_EnumerateInstanceLayerProperties(
1253 uint32_t* pPropertyCount
,
1254 VkLayerProperties
* pProperties
)
1256 if (pProperties
== NULL
) {
1257 *pPropertyCount
= 0;
1261 /* None supported at this time */
1262 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1265 VkResult
radv_EnumerateDeviceLayerProperties(
1266 VkPhysicalDevice physicalDevice
,
1267 uint32_t* pPropertyCount
,
1268 VkLayerProperties
* pProperties
)
1270 if (pProperties
== NULL
) {
1271 *pPropertyCount
= 0;
1275 /* None supported at this time */
1276 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1279 void radv_GetDeviceQueue(
1281 uint32_t queueFamilyIndex
,
1282 uint32_t queueIndex
,
1285 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1287 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1290 static void radv_dump_trace(struct radv_device
*device
,
1291 struct radeon_winsys_cs
*cs
)
1293 const char *filename
= getenv("RADV_TRACE_FILE");
1294 FILE *f
= fopen(filename
, "w");
1296 fprintf(stderr
, "Failed to write trace dump to %s\n", filename
);
1300 fprintf(f
, "Trace ID: %x\n", *device
->trace_id_ptr
);
1301 device
->ws
->cs_dump(cs
, f
, *device
->trace_id_ptr
);
1306 fill_geom_tess_rings(struct radv_queue
*queue
,
1308 bool add_sample_positions
,
1309 uint32_t esgs_ring_size
,
1310 struct radeon_winsys_bo
*esgs_ring_bo
,
1311 uint32_t gsvs_ring_size
,
1312 struct radeon_winsys_bo
*gsvs_ring_bo
,
1313 uint32_t tess_factor_ring_size
,
1314 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1315 uint32_t tess_offchip_ring_size
,
1316 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1318 uint64_t esgs_va
= 0, gsvs_va
= 0;
1319 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1320 uint32_t *desc
= &map
[4];
1323 esgs_va
= queue
->device
->ws
->buffer_get_va(esgs_ring_bo
);
1325 gsvs_va
= queue
->device
->ws
->buffer_get_va(gsvs_ring_bo
);
1326 if (tess_factor_ring_bo
)
1327 tess_factor_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1328 if (tess_offchip_ring_bo
)
1329 tess_offchip_va
= queue
->device
->ws
->buffer_get_va(tess_offchip_ring_bo
);
1331 /* stride 0, num records - size, add tid, swizzle, elsize4,
1334 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1335 S_008F04_STRIDE(0) |
1336 S_008F04_SWIZZLE_ENABLE(true);
1337 desc
[2] = esgs_ring_size
;
1338 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1342 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1344 S_008F0C_ELEMENT_SIZE(1) |
1345 S_008F0C_INDEX_STRIDE(3) |
1346 S_008F0C_ADD_TID_ENABLE(true);
1349 /* GS entry for ES->GS ring */
1350 /* stride 0, num records - size, elsize0,
1353 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1354 S_008F04_STRIDE(0) |
1355 S_008F04_SWIZZLE_ENABLE(false);
1356 desc
[2] = esgs_ring_size
;
1357 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1358 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1359 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1360 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1361 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1362 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1363 S_008F0C_ELEMENT_SIZE(0) |
1364 S_008F0C_INDEX_STRIDE(0) |
1365 S_008F0C_ADD_TID_ENABLE(false);
1368 /* VS entry for GS->VS ring */
1369 /* stride 0, num records - size, elsize0,
1372 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1373 S_008F04_STRIDE(0) |
1374 S_008F04_SWIZZLE_ENABLE(false);
1375 desc
[2] = gsvs_ring_size
;
1376 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1377 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1378 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1379 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1380 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1381 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1382 S_008F0C_ELEMENT_SIZE(0) |
1383 S_008F0C_INDEX_STRIDE(0) |
1384 S_008F0C_ADD_TID_ENABLE(false);
1387 /* stride gsvs_itemsize, num records 64
1388 elsize 4, index stride 16 */
1389 /* shader will patch stride and desc[2] */
1391 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1392 S_008F04_STRIDE(0) |
1393 S_008F04_SWIZZLE_ENABLE(true);
1395 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1396 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1397 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1398 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1399 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1400 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1401 S_008F0C_ELEMENT_SIZE(1) |
1402 S_008F0C_INDEX_STRIDE(1) |
1403 S_008F0C_ADD_TID_ENABLE(true);
1406 desc
[0] = tess_factor_va
;
1407 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1408 S_008F04_STRIDE(0) |
1409 S_008F04_SWIZZLE_ENABLE(false);
1410 desc
[2] = tess_factor_ring_size
;
1411 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1412 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1413 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1414 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1415 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1416 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1417 S_008F0C_ELEMENT_SIZE(0) |
1418 S_008F0C_INDEX_STRIDE(0) |
1419 S_008F0C_ADD_TID_ENABLE(false);
1422 desc
[0] = tess_offchip_va
;
1423 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1424 S_008F04_STRIDE(0) |
1425 S_008F04_SWIZZLE_ENABLE(false);
1426 desc
[2] = tess_offchip_ring_size
;
1427 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1428 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1429 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1430 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1431 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1432 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1433 S_008F0C_ELEMENT_SIZE(0) |
1434 S_008F0C_INDEX_STRIDE(0) |
1435 S_008F0C_ADD_TID_ENABLE(false);
1438 /* add sample positions after all rings */
1439 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1441 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1443 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1445 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1447 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1451 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1453 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1454 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1455 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1456 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1457 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1458 device
->physical_device
->rad_info
.max_se
;
1459 unsigned offchip_granularity
;
1460 unsigned hs_offchip_param
;
1461 switch (device
->tess_offchip_block_dw_size
) {
1466 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1469 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1473 switch (device
->physical_device
->rad_info
.chip_class
) {
1475 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1481 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1485 *max_offchip_buffers_p
= max_offchip_buffers
;
1486 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1487 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1488 --max_offchip_buffers
;
1490 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1491 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1494 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1496 return hs_offchip_param
;
1500 radv_get_preamble_cs(struct radv_queue
*queue
,
1501 uint32_t scratch_size
,
1502 uint32_t compute_scratch_size
,
1503 uint32_t esgs_ring_size
,
1504 uint32_t gsvs_ring_size
,
1505 bool needs_tess_rings
,
1506 bool needs_sample_positions
,
1507 struct radeon_winsys_cs
**initial_preamble_cs
,
1508 struct radeon_winsys_cs
**continue_preamble_cs
)
1510 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1511 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1512 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1513 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1514 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1515 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1516 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1517 struct radeon_winsys_cs
*dest_cs
[2] = {0};
1518 bool add_tess_rings
= false, add_sample_positions
= false;
1519 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1520 unsigned max_offchip_buffers
;
1521 unsigned hs_offchip_param
= 0;
1522 if (!queue
->has_tess_rings
) {
1523 if (needs_tess_rings
)
1524 add_tess_rings
= true;
1526 if (!queue
->has_sample_positions
) {
1527 if (needs_sample_positions
)
1528 add_sample_positions
= true;
1530 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1531 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1532 &max_offchip_buffers
);
1533 tess_offchip_ring_size
= max_offchip_buffers
*
1534 queue
->device
->tess_offchip_block_dw_size
* 4;
1536 if (scratch_size
<= queue
->scratch_size
&&
1537 compute_scratch_size
<= queue
->compute_scratch_size
&&
1538 esgs_ring_size
<= queue
->esgs_ring_size
&&
1539 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1540 !add_tess_rings
&& !add_sample_positions
&&
1541 queue
->initial_preamble_cs
) {
1542 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1543 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1544 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1545 *continue_preamble_cs
= NULL
;
1549 if (scratch_size
> queue
->scratch_size
) {
1550 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1554 RADEON_FLAG_NO_CPU_ACCESS
);
1558 scratch_bo
= queue
->scratch_bo
;
1560 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1561 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1562 compute_scratch_size
,
1565 RADEON_FLAG_NO_CPU_ACCESS
);
1566 if (!compute_scratch_bo
)
1570 compute_scratch_bo
= queue
->compute_scratch_bo
;
1572 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1573 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1577 RADEON_FLAG_NO_CPU_ACCESS
);
1581 esgs_ring_bo
= queue
->esgs_ring_bo
;
1582 esgs_ring_size
= queue
->esgs_ring_size
;
1585 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1586 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1590 RADEON_FLAG_NO_CPU_ACCESS
);
1594 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1595 gsvs_ring_size
= queue
->gsvs_ring_size
;
1598 if (add_tess_rings
) {
1599 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1600 tess_factor_ring_size
,
1603 RADEON_FLAG_NO_CPU_ACCESS
);
1604 if (!tess_factor_ring_bo
)
1606 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1607 tess_offchip_ring_size
,
1610 RADEON_FLAG_NO_CPU_ACCESS
);
1611 if (!tess_offchip_ring_bo
)
1614 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1615 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1618 if (scratch_bo
!= queue
->scratch_bo
||
1619 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1620 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1621 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1622 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1624 if (gsvs_ring_bo
|| esgs_ring_bo
||
1625 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1626 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1627 if (add_sample_positions
)
1628 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1630 else if (scratch_bo
)
1631 size
= 8; /* 2 dword */
1633 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1637 RADEON_FLAG_CPU_ACCESS
);
1641 descriptor_bo
= queue
->descriptor_bo
;
1643 for(int i
= 0; i
< 2; ++i
) {
1644 struct radeon_winsys_cs
*cs
= NULL
;
1645 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1646 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1653 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1656 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1659 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1661 if (tess_factor_ring_bo
)
1662 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1664 if (tess_offchip_ring_bo
)
1665 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1668 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1670 if (descriptor_bo
!= queue
->descriptor_bo
) {
1671 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1674 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(scratch_bo
);
1675 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1676 S_008F04_SWIZZLE_ENABLE(1);
1677 map
[0] = scratch_va
;
1681 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1682 add_sample_positions
)
1683 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1684 esgs_ring_size
, esgs_ring_bo
,
1685 gsvs_ring_size
, gsvs_ring_bo
,
1686 tess_factor_ring_size
, tess_factor_ring_bo
,
1687 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1689 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1692 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1693 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1694 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1695 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1696 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1699 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1700 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1701 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1702 radeon_emit(cs
, esgs_ring_size
>> 8);
1703 radeon_emit(cs
, gsvs_ring_size
>> 8);
1705 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1706 radeon_emit(cs
, esgs_ring_size
>> 8);
1707 radeon_emit(cs
, gsvs_ring_size
>> 8);
1711 if (tess_factor_ring_bo
) {
1712 uint64_t tf_va
= queue
->device
->ws
->buffer_get_va(tess_factor_ring_bo
);
1713 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1714 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1715 S_030938_SIZE(tess_factor_ring_size
/ 4));
1716 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1718 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1719 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1722 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1724 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1725 S_008988_SIZE(tess_factor_ring_size
/ 4));
1726 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1728 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1733 if (descriptor_bo
) {
1734 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1735 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1736 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1737 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1738 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1739 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1741 uint64_t va
= queue
->device
->ws
->buffer_get_va(descriptor_bo
);
1743 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1744 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1745 radeon_emit(cs
, va
);
1746 radeon_emit(cs
, va
>> 32);
1750 if (compute_scratch_bo
) {
1751 uint64_t scratch_va
= queue
->device
->ws
->buffer_get_va(compute_scratch_bo
);
1752 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1753 S_008F04_SWIZZLE_ENABLE(1);
1755 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1757 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1758 radeon_emit(cs
, scratch_va
);
1759 radeon_emit(cs
, rsrc1
);
1763 si_cs_emit_cache_flush(cs
,
1764 queue
->device
->physical_device
->rad_info
.chip_class
,
1766 queue
->queue_family_index
== RING_COMPUTE
&&
1767 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1768 RADV_CMD_FLAG_INV_ICACHE
|
1769 RADV_CMD_FLAG_INV_SMEM_L1
|
1770 RADV_CMD_FLAG_INV_VMEM_L1
|
1771 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1774 if (!queue
->device
->ws
->cs_finalize(cs
))
1778 if (queue
->initial_preamble_cs
)
1779 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1781 if (queue
->continue_preamble_cs
)
1782 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1784 queue
->initial_preamble_cs
= dest_cs
[0];
1785 queue
->continue_preamble_cs
= dest_cs
[1];
1787 if (scratch_bo
!= queue
->scratch_bo
) {
1788 if (queue
->scratch_bo
)
1789 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1790 queue
->scratch_bo
= scratch_bo
;
1791 queue
->scratch_size
= scratch_size
;
1794 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1795 if (queue
->compute_scratch_bo
)
1796 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1797 queue
->compute_scratch_bo
= compute_scratch_bo
;
1798 queue
->compute_scratch_size
= compute_scratch_size
;
1801 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1802 if (queue
->esgs_ring_bo
)
1803 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1804 queue
->esgs_ring_bo
= esgs_ring_bo
;
1805 queue
->esgs_ring_size
= esgs_ring_size
;
1808 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1809 if (queue
->gsvs_ring_bo
)
1810 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1811 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1812 queue
->gsvs_ring_size
= gsvs_ring_size
;
1815 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1816 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1819 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1820 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1821 queue
->has_tess_rings
= true;
1824 if (descriptor_bo
!= queue
->descriptor_bo
) {
1825 if (queue
->descriptor_bo
)
1826 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1828 queue
->descriptor_bo
= descriptor_bo
;
1831 if (add_sample_positions
)
1832 queue
->has_sample_positions
= true;
1834 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1835 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1836 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1837 *continue_preamble_cs
= NULL
;
1840 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1842 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1843 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1844 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1845 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1846 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1847 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1848 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1849 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1850 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1851 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1852 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1853 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1854 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1855 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1856 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1857 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1860 VkResult
radv_QueueSubmit(
1862 uint32_t submitCount
,
1863 const VkSubmitInfo
* pSubmits
,
1866 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1867 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1868 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1869 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1871 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1872 uint32_t scratch_size
= 0;
1873 uint32_t compute_scratch_size
= 0;
1874 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1875 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1877 bool fence_emitted
= false;
1878 bool tess_rings_needed
= false;
1879 bool sample_positions_needed
= false;
1881 /* Do this first so failing to allocate scratch buffers can't result in
1882 * partially executed submissions. */
1883 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1884 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1885 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1886 pSubmits
[i
].pCommandBuffers
[j
]);
1888 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1889 compute_scratch_size
= MAX2(compute_scratch_size
,
1890 cmd_buffer
->compute_scratch_size_needed
);
1891 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1892 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1893 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1894 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1898 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1899 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1900 sample_positions_needed
,
1901 &initial_preamble_cs
, &continue_preamble_cs
);
1902 if (result
!= VK_SUCCESS
)
1905 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1906 struct radeon_winsys_cs
**cs_array
;
1907 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1908 bool can_patch
= !do_flush
;
1911 if (!pSubmits
[i
].commandBufferCount
) {
1912 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1913 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1914 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1916 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1917 pSubmits
[i
].waitSemaphoreCount
,
1918 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1919 pSubmits
[i
].signalSemaphoreCount
,
1922 radv_loge("failed to submit CS %d\n", i
);
1925 fence_emitted
= true;
1930 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1931 (pSubmits
[i
].commandBufferCount
+ do_flush
));
1934 cs_array
[0] = pSubmits
[i
].waitSemaphoreCount
?
1935 queue
->device
->flush_shader_cs
[queue
->queue_family_index
] :
1936 queue
->device
->flush_cs
[queue
->queue_family_index
];
1938 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1939 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1940 pSubmits
[i
].pCommandBuffers
[j
]);
1941 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1943 cs_array
[j
+ do_flush
] = cmd_buffer
->cs
;
1944 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1948 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
+ do_flush
; j
+= advance
) {
1949 advance
= MIN2(max_cs_submission
,
1950 pSubmits
[i
].commandBufferCount
+ do_flush
- j
);
1952 bool e
= j
+ advance
== pSubmits
[i
].commandBufferCount
+ do_flush
;
1954 if (queue
->device
->trace_bo
)
1955 *queue
->device
->trace_id_ptr
= 0;
1957 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1958 advance
, initial_preamble_cs
, continue_preamble_cs
,
1959 (struct radeon_winsys_sem
**)pSubmits
[i
].pWaitSemaphores
,
1960 b
? pSubmits
[i
].waitSemaphoreCount
: 0,
1961 (struct radeon_winsys_sem
**)pSubmits
[i
].pSignalSemaphores
,
1962 e
? pSubmits
[i
].signalSemaphoreCount
: 0,
1963 can_patch
, base_fence
);
1966 radv_loge("failed to submit CS %d\n", i
);
1969 fence_emitted
= true;
1970 if (queue
->device
->trace_bo
) {
1971 bool success
= queue
->device
->ws
->ctx_wait_idle(
1973 radv_queue_family_to_ring(
1974 queue
->queue_family_index
),
1977 if (!success
) { /* Hang */
1978 radv_dump_trace(queue
->device
, cs_array
[j
]);
1988 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1989 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1990 1, NULL
, NULL
, NULL
, 0, NULL
, 0,
1993 fence
->submitted
= true;
1999 VkResult
radv_QueueWaitIdle(
2002 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2004 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2005 radv_queue_family_to_ring(queue
->queue_family_index
),
2010 VkResult
radv_DeviceWaitIdle(
2013 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2015 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2016 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2017 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2023 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2024 VkInstance instance
,
2027 return radv_lookup_entrypoint(pName
);
2030 /* The loader wants us to expose a second GetInstanceProcAddr function
2031 * to work around certain LD_PRELOAD issues seen in apps.
2034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2035 VkInstance instance
,
2039 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2040 VkInstance instance
,
2043 return radv_GetInstanceProcAddr(instance
, pName
);
2046 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2050 return radv_lookup_entrypoint(pName
);
2053 bool radv_get_memory_fd(struct radv_device
*device
,
2054 struct radv_device_memory
*memory
,
2057 struct radeon_bo_metadata metadata
;
2059 if (memory
->image
) {
2060 radv_init_metadata(device
, memory
->image
, &metadata
);
2061 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2064 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2068 VkResult
radv_AllocateMemory(
2070 const VkMemoryAllocateInfo
* pAllocateInfo
,
2071 const VkAllocationCallbacks
* pAllocator
,
2072 VkDeviceMemory
* pMem
)
2074 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2075 struct radv_device_memory
*mem
;
2077 enum radeon_bo_domain domain
;
2080 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2082 if (pAllocateInfo
->allocationSize
== 0) {
2083 /* Apparently, this is allowed */
2084 *pMem
= VK_NULL_HANDLE
;
2088 const VkImportMemoryFdInfoKHX
*import_info
=
2089 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHX
);
2090 const VkDedicatedAllocationMemoryAllocateInfoNV
*dedicate_info
=
2091 vk_find_struct_const(pAllocateInfo
->pNext
, DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV
);
2093 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2094 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2096 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2098 if (dedicate_info
) {
2099 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2100 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2107 assert(import_info
->handleType
==
2108 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
2109 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2117 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2118 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2119 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2120 domain
= RADEON_DOMAIN_GTT
;
2122 domain
= RADEON_DOMAIN_VRAM
;
2124 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2125 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2127 flags
|= RADEON_FLAG_CPU_ACCESS
;
2129 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2130 flags
|= RADEON_FLAG_GTT_WC
;
2132 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, 65536,
2136 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2139 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2141 *pMem
= radv_device_memory_to_handle(mem
);
2146 vk_free2(&device
->alloc
, pAllocator
, mem
);
2151 void radv_FreeMemory(
2153 VkDeviceMemory _mem
,
2154 const VkAllocationCallbacks
* pAllocator
)
2156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2157 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2162 device
->ws
->buffer_destroy(mem
->bo
);
2165 vk_free2(&device
->alloc
, pAllocator
, mem
);
2168 VkResult
radv_MapMemory(
2170 VkDeviceMemory _memory
,
2171 VkDeviceSize offset
,
2173 VkMemoryMapFlags flags
,
2176 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2177 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2184 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2190 return VK_ERROR_MEMORY_MAP_FAILED
;
2193 void radv_UnmapMemory(
2195 VkDeviceMemory _memory
)
2197 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2198 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2203 device
->ws
->buffer_unmap(mem
->bo
);
2206 VkResult
radv_FlushMappedMemoryRanges(
2208 uint32_t memoryRangeCount
,
2209 const VkMappedMemoryRange
* pMemoryRanges
)
2214 VkResult
radv_InvalidateMappedMemoryRanges(
2216 uint32_t memoryRangeCount
,
2217 const VkMappedMemoryRange
* pMemoryRanges
)
2222 void radv_GetBufferMemoryRequirements(
2225 VkMemoryRequirements
* pMemoryRequirements
)
2227 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2229 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2231 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2232 pMemoryRequirements
->alignment
= 4096;
2234 pMemoryRequirements
->alignment
= 16;
2236 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2239 void radv_GetImageMemoryRequirements(
2242 VkMemoryRequirements
* pMemoryRequirements
)
2244 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2246 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2248 pMemoryRequirements
->size
= image
->size
;
2249 pMemoryRequirements
->alignment
= image
->alignment
;
2252 void radv_GetImageSparseMemoryRequirements(
2255 uint32_t* pSparseMemoryRequirementCount
,
2256 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2261 void radv_GetDeviceMemoryCommitment(
2263 VkDeviceMemory memory
,
2264 VkDeviceSize
* pCommittedMemoryInBytes
)
2266 *pCommittedMemoryInBytes
= 0;
2269 VkResult
radv_BindBufferMemory(
2272 VkDeviceMemory _memory
,
2273 VkDeviceSize memoryOffset
)
2275 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2276 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2279 buffer
->bo
= mem
->bo
;
2280 buffer
->offset
= memoryOffset
;
2289 VkResult
radv_BindImageMemory(
2292 VkDeviceMemory _memory
,
2293 VkDeviceSize memoryOffset
)
2295 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2296 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2299 image
->bo
= mem
->bo
;
2300 image
->offset
= memoryOffset
;
2311 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2312 const VkSparseBufferMemoryBindInfo
*bind
)
2314 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2316 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2317 struct radv_device_memory
*mem
= NULL
;
2319 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2320 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2322 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2323 bind
->pBinds
[i
].resourceOffset
,
2324 bind
->pBinds
[i
].size
,
2325 mem
? mem
->bo
: NULL
,
2326 bind
->pBinds
[i
].memoryOffset
);
2331 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2332 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2334 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2336 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2337 struct radv_device_memory
*mem
= NULL
;
2339 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2340 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2342 device
->ws
->buffer_virtual_bind(image
->bo
,
2343 bind
->pBinds
[i
].resourceOffset
,
2344 bind
->pBinds
[i
].size
,
2345 mem
? mem
->bo
: NULL
,
2346 bind
->pBinds
[i
].memoryOffset
);
2350 VkResult
radv_QueueBindSparse(
2352 uint32_t bindInfoCount
,
2353 const VkBindSparseInfo
* pBindInfo
,
2356 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2357 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2358 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2359 bool fence_emitted
= false;
2361 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2362 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2363 radv_sparse_buffer_bind_memory(queue
->device
,
2364 pBindInfo
[i
].pBufferBinds
+ j
);
2367 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2368 radv_sparse_image_opaque_bind_memory(queue
->device
,
2369 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2372 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2373 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2374 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2376 (struct radeon_winsys_sem
**)pBindInfo
[i
].pWaitSemaphores
,
2377 pBindInfo
[i
].waitSemaphoreCount
,
2378 (struct radeon_winsys_sem
**)pBindInfo
[i
].pSignalSemaphores
,
2379 pBindInfo
[i
].signalSemaphoreCount
,
2381 fence_emitted
= true;
2383 fence
->submitted
= true;
2387 if (fence
&& !fence_emitted
) {
2388 fence
->signalled
= true;
2394 VkResult
radv_CreateFence(
2396 const VkFenceCreateInfo
* pCreateInfo
,
2397 const VkAllocationCallbacks
* pAllocator
,
2400 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2401 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2403 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2406 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2408 memset(fence
, 0, sizeof(*fence
));
2409 fence
->submitted
= false;
2410 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2411 fence
->fence
= device
->ws
->create_fence();
2412 if (!fence
->fence
) {
2413 vk_free2(&device
->alloc
, pAllocator
, fence
);
2414 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2417 *pFence
= radv_fence_to_handle(fence
);
2422 void radv_DestroyFence(
2425 const VkAllocationCallbacks
* pAllocator
)
2427 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2428 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2432 device
->ws
->destroy_fence(fence
->fence
);
2433 vk_free2(&device
->alloc
, pAllocator
, fence
);
2436 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2438 uint64_t current_time
;
2441 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2442 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2444 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2446 return current_time
+ timeout
;
2449 VkResult
radv_WaitForFences(
2451 uint32_t fenceCount
,
2452 const VkFence
* pFences
,
2456 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2457 timeout
= radv_get_absolute_timeout(timeout
);
2459 if (!waitAll
&& fenceCount
> 1) {
2460 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2463 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2464 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2465 bool expired
= false;
2467 if (fence
->signalled
)
2470 if (!fence
->submitted
)
2473 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2477 fence
->signalled
= true;
2483 VkResult
radv_ResetFences(VkDevice device
,
2484 uint32_t fenceCount
,
2485 const VkFence
*pFences
)
2487 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2488 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2489 fence
->submitted
= fence
->signalled
= false;
2495 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2497 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2498 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2500 if (fence
->signalled
)
2502 if (!fence
->submitted
)
2503 return VK_NOT_READY
;
2505 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2506 return VK_NOT_READY
;
2512 // Queue semaphore functions
2514 VkResult
radv_CreateSemaphore(
2516 const VkSemaphoreCreateInfo
* pCreateInfo
,
2517 const VkAllocationCallbacks
* pAllocator
,
2518 VkSemaphore
* pSemaphore
)
2520 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2521 struct radeon_winsys_sem
*sem
;
2523 sem
= device
->ws
->create_sem(device
->ws
);
2525 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2527 *pSemaphore
= radeon_winsys_sem_to_handle(sem
);
2531 void radv_DestroySemaphore(
2533 VkSemaphore _semaphore
,
2534 const VkAllocationCallbacks
* pAllocator
)
2536 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2537 RADV_FROM_HANDLE(radeon_winsys_sem
, sem
, _semaphore
);
2541 device
->ws
->destroy_sem(sem
);
2544 VkResult
radv_CreateEvent(
2546 const VkEventCreateInfo
* pCreateInfo
,
2547 const VkAllocationCallbacks
* pAllocator
,
2550 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2551 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2553 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2556 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2558 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2560 RADEON_FLAG_CPU_ACCESS
);
2562 vk_free2(&device
->alloc
, pAllocator
, event
);
2563 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2566 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2568 *pEvent
= radv_event_to_handle(event
);
2573 void radv_DestroyEvent(
2576 const VkAllocationCallbacks
* pAllocator
)
2578 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2579 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2583 device
->ws
->buffer_destroy(event
->bo
);
2584 vk_free2(&device
->alloc
, pAllocator
, event
);
2587 VkResult
radv_GetEventStatus(
2591 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2593 if (*event
->map
== 1)
2594 return VK_EVENT_SET
;
2595 return VK_EVENT_RESET
;
2598 VkResult
radv_SetEvent(
2602 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2608 VkResult
radv_ResetEvent(
2612 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2618 VkResult
radv_CreateBuffer(
2620 const VkBufferCreateInfo
* pCreateInfo
,
2621 const VkAllocationCallbacks
* pAllocator
,
2624 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2625 struct radv_buffer
*buffer
;
2627 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2629 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2630 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2632 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2634 buffer
->size
= pCreateInfo
->size
;
2635 buffer
->usage
= pCreateInfo
->usage
;
2638 buffer
->flags
= pCreateInfo
->flags
;
2640 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2641 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2642 align64(buffer
->size
, 4096),
2643 4096, 0, RADEON_FLAG_VIRTUAL
);
2645 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2646 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2650 *pBuffer
= radv_buffer_to_handle(buffer
);
2655 void radv_DestroyBuffer(
2658 const VkAllocationCallbacks
* pAllocator
)
2660 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2661 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2666 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2667 device
->ws
->buffer_destroy(buffer
->bo
);
2669 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2672 static inline unsigned
2673 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2676 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2678 return image
->surface
.u
.legacy
.tiling_index
[level
];
2681 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2683 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2687 radv_initialise_color_surface(struct radv_device
*device
,
2688 struct radv_color_buffer_info
*cb
,
2689 struct radv_image_view
*iview
)
2691 const struct vk_format_description
*desc
;
2692 unsigned ntype
, format
, swap
, endian
;
2693 unsigned blend_clamp
= 0, blend_bypass
= 0;
2695 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2697 desc
= vk_format_description(iview
->vk_format
);
2699 memset(cb
, 0, sizeof(*cb
));
2701 /* Intensity is implemented as Red, so treat it that way. */
2702 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2704 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2706 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2707 struct gfx9_surf_meta_flags meta
;
2708 if (iview
->image
->dcc_offset
)
2709 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
2711 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
2713 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2714 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2715 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2716 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2718 va
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
2720 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2721 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2723 va
+= level_info
->offset
;
2725 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2726 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2727 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2729 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2730 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2731 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2733 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2734 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2736 if (iview
->image
->fmask
.size
) {
2737 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2738 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2739 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2740 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2742 /* This must be set for fast clear to work without FMASK. */
2743 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2744 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2745 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2746 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2750 cb
->cb_color_base
= va
>> 8;
2752 /* CMASK variables */
2753 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2754 va
+= iview
->image
->cmask
.offset
;
2755 cb
->cb_color_cmask
= va
>> 8;
2757 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2758 va
+= iview
->image
->dcc_offset
;
2759 cb
->cb_dcc_base
= va
>> 8;
2761 uint32_t max_slice
= radv_surface_layer_count(iview
);
2762 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2763 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2765 if (iview
->image
->info
.samples
> 1) {
2766 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2768 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2769 S_028C74_NUM_FRAGMENTS(log_samples
);
2772 if (iview
->image
->fmask
.size
) {
2773 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2774 cb
->cb_color_fmask
= va
>> 8;
2776 cb
->cb_color_fmask
= cb
->cb_color_base
;
2779 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2781 vk_format_get_first_non_void_channel(iview
->vk_format
));
2782 format
= radv_translate_colorformat(iview
->vk_format
);
2783 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2784 radv_finishme("Illegal color\n");
2785 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2786 endian
= radv_colorformat_endian_swap(format
);
2788 /* blend clamp should be set for all NORM/SRGB types */
2789 if (ntype
== V_028C70_NUMBER_UNORM
||
2790 ntype
== V_028C70_NUMBER_SNORM
||
2791 ntype
== V_028C70_NUMBER_SRGB
)
2794 /* set blend bypass according to docs if SINT/UINT or
2795 8/24 COLOR variants */
2796 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2797 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2798 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2803 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2804 (format
== V_028C70_COLOR_8
||
2805 format
== V_028C70_COLOR_8_8
||
2806 format
== V_028C70_COLOR_8_8_8_8
))
2807 ->color_is_int8
= true;
2809 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2810 S_028C70_COMP_SWAP(swap
) |
2811 S_028C70_BLEND_CLAMP(blend_clamp
) |
2812 S_028C70_BLEND_BYPASS(blend_bypass
) |
2813 S_028C70_SIMPLE_FLOAT(1) |
2814 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2815 ntype
!= V_028C70_NUMBER_SNORM
&&
2816 ntype
!= V_028C70_NUMBER_SRGB
&&
2817 format
!= V_028C70_COLOR_8_24
&&
2818 format
!= V_028C70_COLOR_24_8
) |
2819 S_028C70_NUMBER_TYPE(ntype
) |
2820 S_028C70_ENDIAN(endian
);
2821 if (iview
->image
->info
.samples
> 1)
2822 if (iview
->image
->fmask
.size
)
2823 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2825 if (iview
->image
->cmask
.size
&&
2826 !(device
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2827 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2829 if (iview
->image
->surface
.dcc_size
&& iview
->base_mip
< surf
->num_dcc_levels
)
2830 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2832 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2833 unsigned max_uncompressed_block_size
= 2;
2834 if (iview
->image
->info
.samples
> 1) {
2835 if (iview
->image
->surface
.bpe
== 1)
2836 max_uncompressed_block_size
= 0;
2837 else if (iview
->image
->surface
.bpe
== 2)
2838 max_uncompressed_block_size
= 1;
2841 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2842 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2845 /* This must be set for fast clear to work without FMASK. */
2846 if (!iview
->image
->fmask
.size
&&
2847 device
->physical_device
->rad_info
.chip_class
== SI
) {
2848 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
2849 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2852 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2853 uint32_t max_slice
= radv_surface_layer_count(iview
);
2854 unsigned mip0_depth
= iview
->base_layer
+ max_slice
- 1;
2856 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
2857 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2858 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
2859 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->image
->info
.width
- 1) |
2860 S_028C68_MIP0_HEIGHT(iview
->image
->info
.height
- 1) |
2861 S_028C68_MAX_MIP(iview
->image
->info
.levels
);
2863 cb
->gfx9_epitch
= S_0287A0_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
2869 radv_initialise_ds_surface(struct radv_device
*device
,
2870 struct radv_ds_buffer_info
*ds
,
2871 struct radv_image_view
*iview
)
2873 unsigned level
= iview
->base_mip
;
2874 unsigned format
, stencil_format
;
2875 uint64_t va
, s_offs
, z_offs
;
2876 bool stencil_only
= false;
2877 memset(ds
, 0, sizeof(*ds
));
2878 switch (iview
->vk_format
) {
2879 case VK_FORMAT_D24_UNORM_S8_UINT
:
2880 case VK_FORMAT_X8_D24_UNORM_PACK32
:
2881 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2882 ds
->offset_scale
= 2.0f
;
2884 case VK_FORMAT_D16_UNORM
:
2885 case VK_FORMAT_D16_UNORM_S8_UINT
:
2886 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2887 ds
->offset_scale
= 4.0f
;
2889 case VK_FORMAT_D32_SFLOAT
:
2890 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
2891 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2892 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2893 ds
->offset_scale
= 1.0f
;
2895 case VK_FORMAT_S8_UINT
:
2896 stencil_only
= true;
2902 format
= radv_translate_dbformat(iview
->vk_format
);
2903 stencil_format
= iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
?
2904 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2906 uint32_t max_slice
= radv_surface_layer_count(iview
);
2907 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
2908 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2910 ds
->db_htile_data_base
= 0;
2911 ds
->db_htile_surface
= 0;
2913 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2914 s_offs
= z_offs
= va
;
2916 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2917 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
2918 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
2920 ds
->db_z_info
= S_028038_FORMAT(format
) |
2921 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
2922 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2923 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
2924 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
2925 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2927 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
2928 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
2929 ds
->db_depth_view
|= S_028008_MIPID(level
);
2931 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
2932 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
2934 /* Only use HTILE for the first level. */
2935 if (iview
->image
->surface
.htile_size
&& !level
) {
2936 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
2938 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
2939 /* Use all of the htile_buffer for depth if there's no stencil. */
2940 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2941 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
2942 iview
->image
->htile_offset
;
2943 ds
->db_htile_data_base
= va
>> 8;
2944 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2945 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2946 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
2949 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
2952 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
2954 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
2955 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
2957 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2958 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
2959 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
2961 if (iview
->image
->info
.samples
> 1)
2962 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
2964 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2965 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
2966 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
2967 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2968 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
2969 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
2970 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2971 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2974 tile_mode
= stencil_tile_mode
;
2976 ds
->db_depth_info
|=
2977 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2978 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2979 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2980 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2981 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2982 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2983 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2984 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2986 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
2987 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2988 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
2989 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2992 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
2993 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
2994 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
2996 if (iview
->image
->surface
.htile_size
&& !level
) {
2997 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
2999 if (!(iview
->image
->surface
.flags
& RADEON_SURF_SBUFFER
))
3000 /* Use all of the htile_buffer for depth if there's no stencil. */
3001 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3003 va
= device
->ws
->buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3004 iview
->image
->htile_offset
;
3005 ds
->db_htile_data_base
= va
>> 8;
3006 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3010 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3011 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3014 VkResult
radv_CreateFramebuffer(
3016 const VkFramebufferCreateInfo
* pCreateInfo
,
3017 const VkAllocationCallbacks
* pAllocator
,
3018 VkFramebuffer
* pFramebuffer
)
3020 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3021 struct radv_framebuffer
*framebuffer
;
3023 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3025 size_t size
= sizeof(*framebuffer
) +
3026 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3027 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3028 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3029 if (framebuffer
== NULL
)
3030 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3032 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3033 framebuffer
->width
= pCreateInfo
->width
;
3034 framebuffer
->height
= pCreateInfo
->height
;
3035 framebuffer
->layers
= pCreateInfo
->layers
;
3036 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3037 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3038 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3039 framebuffer
->attachments
[i
].attachment
= iview
;
3040 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3041 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3042 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3043 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3045 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3046 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3047 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3050 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3054 void radv_DestroyFramebuffer(
3057 const VkAllocationCallbacks
* pAllocator
)
3059 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3060 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3064 vk_free2(&device
->alloc
, pAllocator
, fb
);
3067 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3069 switch (address_mode
) {
3070 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3071 return V_008F30_SQ_TEX_WRAP
;
3072 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3073 return V_008F30_SQ_TEX_MIRROR
;
3074 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3075 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3076 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3077 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3078 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3079 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3081 unreachable("illegal tex wrap mode");
3087 radv_tex_compare(VkCompareOp op
)
3090 case VK_COMPARE_OP_NEVER
:
3091 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3092 case VK_COMPARE_OP_LESS
:
3093 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3094 case VK_COMPARE_OP_EQUAL
:
3095 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3096 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3097 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3098 case VK_COMPARE_OP_GREATER
:
3099 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3100 case VK_COMPARE_OP_NOT_EQUAL
:
3101 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3102 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3103 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3104 case VK_COMPARE_OP_ALWAYS
:
3105 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3107 unreachable("illegal compare mode");
3113 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3116 case VK_FILTER_NEAREST
:
3117 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3118 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3119 case VK_FILTER_LINEAR
:
3120 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3121 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3122 case VK_FILTER_CUBIC_IMG
:
3124 fprintf(stderr
, "illegal texture filter");
3130 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3133 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3134 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3135 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3136 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3138 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3143 radv_tex_bordercolor(VkBorderColor bcolor
)
3146 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3147 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3148 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3149 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3150 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3151 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3152 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3153 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3154 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3162 radv_tex_aniso_filter(unsigned filter
)
3176 radv_init_sampler(struct radv_device
*device
,
3177 struct radv_sampler
*sampler
,
3178 const VkSamplerCreateInfo
*pCreateInfo
)
3180 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3181 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3182 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3183 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3185 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3186 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3187 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3188 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3189 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3190 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3191 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3192 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3193 S_008F30_DISABLE_CUBE_WRAP(0) |
3194 S_008F30_COMPAT_MODE(is_vi
));
3195 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3196 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3197 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3198 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3199 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3200 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3201 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3202 S_008F38_MIP_POINT_PRECLAMP(0) |
3203 S_008F38_DISABLE_LSB_CEIL(1) |
3204 S_008F38_FILTER_PREC_FIX(1) |
3205 S_008F38_ANISO_OVERRIDE(is_vi
));
3206 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3207 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3210 VkResult
radv_CreateSampler(
3212 const VkSamplerCreateInfo
* pCreateInfo
,
3213 const VkAllocationCallbacks
* pAllocator
,
3214 VkSampler
* pSampler
)
3216 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3217 struct radv_sampler
*sampler
;
3219 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3221 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3224 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3226 radv_init_sampler(device
, sampler
, pCreateInfo
);
3227 *pSampler
= radv_sampler_to_handle(sampler
);
3232 void radv_DestroySampler(
3235 const VkAllocationCallbacks
* pAllocator
)
3237 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3238 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3242 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3245 /* vk_icd.h does not declare this function, so we declare it here to
3246 * suppress Wmissing-prototypes.
3248 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3249 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3251 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3252 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3254 /* For the full details on loader interface versioning, see
3255 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3256 * What follows is a condensed summary, to help you navigate the large and
3257 * confusing official doc.
3259 * - Loader interface v0 is incompatible with later versions. We don't
3262 * - In loader interface v1:
3263 * - The first ICD entrypoint called by the loader is
3264 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3266 * - The ICD must statically expose no other Vulkan symbol unless it is
3267 * linked with -Bsymbolic.
3268 * - Each dispatchable Vulkan handle created by the ICD must be
3269 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3270 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3271 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3272 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3273 * such loader-managed surfaces.
3275 * - Loader interface v2 differs from v1 in:
3276 * - The first ICD entrypoint called by the loader is
3277 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3278 * statically expose this entrypoint.
3280 * - Loader interface v3 differs from v2 in:
3281 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3282 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3283 * because the loader no longer does so.
3285 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3289 VkResult
radv_GetMemoryFdKHX(VkDevice _device
,
3290 VkDeviceMemory _memory
,
3291 VkExternalMemoryHandleTypeFlagsKHX handleType
,
3294 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3295 RADV_FROM_HANDLE(radv_device_memory
, memory
, _memory
);
3297 /* We support only one handle type. */
3298 assert(handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX
);
3300 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3302 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3306 VkResult
radv_GetMemoryFdPropertiesKHX(VkDevice _device
,
3307 VkExternalMemoryHandleTypeFlagBitsKHX handleType
,
3309 VkMemoryFdPropertiesKHX
*pMemoryFdProperties
)
3311 /* The valid usage section for this function says:
3313 * "handleType must not be one of the handle types defined as opaque."
3315 * Since we only handle opaque handles for now, there are no FD properties.
3317 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX
;