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radv: Fix freeing meta state if the device pipeline cache fails to allocate.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
267
268 /* Vega10/Raven need a special workaround for a hardware bug. */
269 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
270 device->rad_info.family == CHIP_RAVEN;
271
272 radv_physical_device_init_mem_types(device);
273
274 result = radv_init_wsi(device);
275 if (result != VK_SUCCESS) {
276 device->ws->destroy(device->ws);
277 goto fail;
278 }
279
280 return VK_SUCCESS;
281
282 fail:
283 close(fd);
284 return result;
285 }
286
287 static void
288 radv_physical_device_finish(struct radv_physical_device *device)
289 {
290 radv_finish_wsi(device);
291 device->ws->destroy(device->ws);
292 disk_cache_destroy(device->disk_cache);
293 close(device->local_fd);
294 }
295
296 static void *
297 default_alloc_func(void *pUserData, size_t size, size_t align,
298 VkSystemAllocationScope allocationScope)
299 {
300 return malloc(size);
301 }
302
303 static void *
304 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
305 size_t align, VkSystemAllocationScope allocationScope)
306 {
307 return realloc(pOriginal, size);
308 }
309
310 static void
311 default_free_func(void *pUserData, void *pMemory)
312 {
313 free(pMemory);
314 }
315
316 static const VkAllocationCallbacks default_alloc = {
317 .pUserData = NULL,
318 .pfnAllocation = default_alloc_func,
319 .pfnReallocation = default_realloc_func,
320 .pfnFree = default_free_func,
321 };
322
323 static const struct debug_control radv_debug_options[] = {
324 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
325 {"nodcc", RADV_DEBUG_NO_DCC},
326 {"shaders", RADV_DEBUG_DUMP_SHADERS},
327 {"nocache", RADV_DEBUG_NO_CACHE},
328 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
329 {"nohiz", RADV_DEBUG_NO_HIZ},
330 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
331 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
332 {"allbos", RADV_DEBUG_ALL_BOS},
333 {"noibs", RADV_DEBUG_NO_IBS},
334 {"spirv", RADV_DEBUG_DUMP_SPIRV},
335 {"vmfaults", RADV_DEBUG_VM_FAULTS},
336 {"zerovram", RADV_DEBUG_ZERO_VRAM},
337 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
338 {"nosisched", RADV_DEBUG_NO_SISCHED},
339 {NULL, 0}
340 };
341
342 const char *
343 radv_get_debug_option_name(int id)
344 {
345 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
346 return radv_debug_options[id].string;
347 }
348
349 static const struct debug_control radv_perftest_options[] = {
350 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
351 {"sisched", RADV_PERFTEST_SISCHED},
352 {"localbos", RADV_PERFTEST_LOCAL_BOS},
353 {"binning", RADV_PERFTEST_BINNING},
354 {NULL, 0}
355 };
356
357 const char *
358 radv_get_perftest_option_name(int id)
359 {
360 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
361 return radv_perftest_options[id].string;
362 }
363
364 static void
365 radv_handle_per_app_options(struct radv_instance *instance,
366 const VkApplicationInfo *info)
367 {
368 const char *name = info ? info->pApplicationName : NULL;
369
370 if (!name)
371 return;
372
373 if (!strcmp(name, "Talos - Linux - 32bit") ||
374 !strcmp(name, "Talos - Linux - 64bit")) {
375 /* Force enable LLVM sisched for Talos because it looks safe
376 * and it gives few more FPS.
377 */
378 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
379 }
380 }
381
382 VkResult radv_CreateInstance(
383 const VkInstanceCreateInfo* pCreateInfo,
384 const VkAllocationCallbacks* pAllocator,
385 VkInstance* pInstance)
386 {
387 struct radv_instance *instance;
388 VkResult result;
389
390 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
391
392 uint32_t client_version;
393 if (pCreateInfo->pApplicationInfo &&
394 pCreateInfo->pApplicationInfo->apiVersion != 0) {
395 client_version = pCreateInfo->pApplicationInfo->apiVersion;
396 } else {
397 client_version = VK_MAKE_VERSION(1, 0, 0);
398 }
399
400 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
401 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
402 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
403 "Client requested version %d.%d.%d",
404 VK_VERSION_MAJOR(client_version),
405 VK_VERSION_MINOR(client_version),
406 VK_VERSION_PATCH(client_version));
407 }
408
409 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
410 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
411 if (!radv_instance_extension_supported(ext_name))
412 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
413 }
414
415 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
416 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
417 if (!instance)
418 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
419
420 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
421
422 if (pAllocator)
423 instance->alloc = *pAllocator;
424 else
425 instance->alloc = default_alloc;
426
427 instance->apiVersion = client_version;
428 instance->physicalDeviceCount = -1;
429
430 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
431 if (result != VK_SUCCESS) {
432 vk_free2(&default_alloc, pAllocator, instance);
433 return vk_error(result);
434 }
435
436 _mesa_locale_init();
437
438 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
439
440 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
441 radv_debug_options);
442
443 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
444 radv_perftest_options);
445
446 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
447
448 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
449 /* Disable sisched when the user requests it, this is mostly
450 * useful when the driver force-enable sisched for the given
451 * application.
452 */
453 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
454 }
455
456 *pInstance = radv_instance_to_handle(instance);
457
458 return VK_SUCCESS;
459 }
460
461 void radv_DestroyInstance(
462 VkInstance _instance,
463 const VkAllocationCallbacks* pAllocator)
464 {
465 RADV_FROM_HANDLE(radv_instance, instance, _instance);
466
467 if (!instance)
468 return;
469
470 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
471 radv_physical_device_finish(instance->physicalDevices + i);
472 }
473
474 VG(VALGRIND_DESTROY_MEMPOOL(instance));
475
476 _mesa_locale_fini();
477
478 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
479
480 vk_free(&instance->alloc, instance);
481 }
482
483 static VkResult
484 radv_enumerate_devices(struct radv_instance *instance)
485 {
486 /* TODO: Check for more devices ? */
487 drmDevicePtr devices[8];
488 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
489 int max_devices;
490
491 instance->physicalDeviceCount = 0;
492
493 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
494 if (max_devices < 1)
495 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
496
497 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
498 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
499 devices[i]->bustype == DRM_BUS_PCI &&
500 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
501
502 result = radv_physical_device_init(instance->physicalDevices +
503 instance->physicalDeviceCount,
504 instance,
505 devices[i]);
506 if (result == VK_SUCCESS)
507 ++instance->physicalDeviceCount;
508 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
509 break;
510 }
511 }
512 drmFreeDevices(devices, max_devices);
513
514 return result;
515 }
516
517 VkResult radv_EnumeratePhysicalDevices(
518 VkInstance _instance,
519 uint32_t* pPhysicalDeviceCount,
520 VkPhysicalDevice* pPhysicalDevices)
521 {
522 RADV_FROM_HANDLE(radv_instance, instance, _instance);
523 VkResult result;
524
525 if (instance->physicalDeviceCount < 0) {
526 result = radv_enumerate_devices(instance);
527 if (result != VK_SUCCESS &&
528 result != VK_ERROR_INCOMPATIBLE_DRIVER)
529 return result;
530 }
531
532 if (!pPhysicalDevices) {
533 *pPhysicalDeviceCount = instance->physicalDeviceCount;
534 } else {
535 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
536 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
537 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
538 }
539
540 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
541 : VK_SUCCESS;
542 }
543
544 void radv_GetPhysicalDeviceFeatures(
545 VkPhysicalDevice physicalDevice,
546 VkPhysicalDeviceFeatures* pFeatures)
547 {
548 memset(pFeatures, 0, sizeof(*pFeatures));
549
550 *pFeatures = (VkPhysicalDeviceFeatures) {
551 .robustBufferAccess = true,
552 .fullDrawIndexUint32 = true,
553 .imageCubeArray = true,
554 .independentBlend = true,
555 .geometryShader = true,
556 .tessellationShader = true,
557 .sampleRateShading = true,
558 .dualSrcBlend = true,
559 .logicOp = true,
560 .multiDrawIndirect = true,
561 .drawIndirectFirstInstance = true,
562 .depthClamp = true,
563 .depthBiasClamp = true,
564 .fillModeNonSolid = true,
565 .depthBounds = true,
566 .wideLines = true,
567 .largePoints = true,
568 .alphaToOne = true,
569 .multiViewport = true,
570 .samplerAnisotropy = true,
571 .textureCompressionETC2 = false,
572 .textureCompressionASTC_LDR = false,
573 .textureCompressionBC = true,
574 .occlusionQueryPrecise = true,
575 .pipelineStatisticsQuery = true,
576 .vertexPipelineStoresAndAtomics = true,
577 .fragmentStoresAndAtomics = true,
578 .shaderTessellationAndGeometryPointSize = true,
579 .shaderImageGatherExtended = true,
580 .shaderStorageImageExtendedFormats = true,
581 .shaderStorageImageMultisample = false,
582 .shaderUniformBufferArrayDynamicIndexing = true,
583 .shaderSampledImageArrayDynamicIndexing = true,
584 .shaderStorageBufferArrayDynamicIndexing = true,
585 .shaderStorageImageArrayDynamicIndexing = true,
586 .shaderStorageImageReadWithoutFormat = true,
587 .shaderStorageImageWriteWithoutFormat = true,
588 .shaderClipDistance = true,
589 .shaderCullDistance = true,
590 .shaderFloat64 = true,
591 .shaderInt64 = true,
592 .shaderInt16 = false,
593 .sparseBinding = true,
594 .variableMultisampleRate = true,
595 .inheritedQueries = true,
596 };
597 }
598
599 void radv_GetPhysicalDeviceFeatures2KHR(
600 VkPhysicalDevice physicalDevice,
601 VkPhysicalDeviceFeatures2KHR *pFeatures)
602 {
603 vk_foreach_struct(ext, pFeatures->pNext) {
604 switch (ext->sType) {
605 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
606 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
607 features->variablePointersStorageBuffer = true;
608 features->variablePointers = false;
609 break;
610 }
611 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
612 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
613 features->multiview = true;
614 features->multiviewGeometryShader = true;
615 features->multiviewTessellationShader = true;
616 break;
617 }
618 default:
619 break;
620 }
621 }
622 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
623 }
624
625 void radv_GetPhysicalDeviceProperties(
626 VkPhysicalDevice physicalDevice,
627 VkPhysicalDeviceProperties* pProperties)
628 {
629 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
630 VkSampleCountFlags sample_counts = 0xf;
631
632 /* make sure that the entire descriptor set is addressable with a signed
633 * 32-bit int. So the sum of all limits scaled by descriptor size has to
634 * be at most 2 GiB. the combined image & samples object count as one of
635 * both. This limit is for the pipeline layout, not for the set layout, but
636 * there is no set limit, so we just set a pipeline limit. I don't think
637 * any app is going to hit this soon. */
638 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
639 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
640 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
641 32 /* sampler, largest when combined with image */ +
642 64 /* sampled image */ +
643 64 /* storage image */);
644
645 VkPhysicalDeviceLimits limits = {
646 .maxImageDimension1D = (1 << 14),
647 .maxImageDimension2D = (1 << 14),
648 .maxImageDimension3D = (1 << 11),
649 .maxImageDimensionCube = (1 << 14),
650 .maxImageArrayLayers = (1 << 11),
651 .maxTexelBufferElements = 128 * 1024 * 1024,
652 .maxUniformBufferRange = UINT32_MAX,
653 .maxStorageBufferRange = UINT32_MAX,
654 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
655 .maxMemoryAllocationCount = UINT32_MAX,
656 .maxSamplerAllocationCount = 64 * 1024,
657 .bufferImageGranularity = 64, /* A cache line */
658 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
659 .maxBoundDescriptorSets = MAX_SETS,
660 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
661 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
662 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
663 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
664 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
665 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
666 .maxPerStageResources = max_descriptor_set_size,
667 .maxDescriptorSetSamplers = max_descriptor_set_size,
668 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
669 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
670 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
671 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
672 .maxDescriptorSetSampledImages = max_descriptor_set_size,
673 .maxDescriptorSetStorageImages = max_descriptor_set_size,
674 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
675 .maxVertexInputAttributes = 32,
676 .maxVertexInputBindings = 32,
677 .maxVertexInputAttributeOffset = 2047,
678 .maxVertexInputBindingStride = 2048,
679 .maxVertexOutputComponents = 128,
680 .maxTessellationGenerationLevel = 64,
681 .maxTessellationPatchSize = 32,
682 .maxTessellationControlPerVertexInputComponents = 128,
683 .maxTessellationControlPerVertexOutputComponents = 128,
684 .maxTessellationControlPerPatchOutputComponents = 120,
685 .maxTessellationControlTotalOutputComponents = 4096,
686 .maxTessellationEvaluationInputComponents = 128,
687 .maxTessellationEvaluationOutputComponents = 128,
688 .maxGeometryShaderInvocations = 127,
689 .maxGeometryInputComponents = 64,
690 .maxGeometryOutputComponents = 128,
691 .maxGeometryOutputVertices = 256,
692 .maxGeometryTotalOutputComponents = 1024,
693 .maxFragmentInputComponents = 128,
694 .maxFragmentOutputAttachments = 8,
695 .maxFragmentDualSrcAttachments = 1,
696 .maxFragmentCombinedOutputResources = 8,
697 .maxComputeSharedMemorySize = 32768,
698 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
699 .maxComputeWorkGroupInvocations = 2048,
700 .maxComputeWorkGroupSize = {
701 2048,
702 2048,
703 2048
704 },
705 .subPixelPrecisionBits = 4 /* FIXME */,
706 .subTexelPrecisionBits = 4 /* FIXME */,
707 .mipmapPrecisionBits = 4 /* FIXME */,
708 .maxDrawIndexedIndexValue = UINT32_MAX,
709 .maxDrawIndirectCount = UINT32_MAX,
710 .maxSamplerLodBias = 16,
711 .maxSamplerAnisotropy = 16,
712 .maxViewports = MAX_VIEWPORTS,
713 .maxViewportDimensions = { (1 << 14), (1 << 14) },
714 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
715 .viewportSubPixelBits = 13, /* We take a float? */
716 .minMemoryMapAlignment = 4096, /* A page */
717 .minTexelBufferOffsetAlignment = 1,
718 .minUniformBufferOffsetAlignment = 4,
719 .minStorageBufferOffsetAlignment = 4,
720 .minTexelOffset = -32,
721 .maxTexelOffset = 31,
722 .minTexelGatherOffset = -32,
723 .maxTexelGatherOffset = 31,
724 .minInterpolationOffset = -2,
725 .maxInterpolationOffset = 2,
726 .subPixelInterpolationOffsetBits = 8,
727 .maxFramebufferWidth = (1 << 14),
728 .maxFramebufferHeight = (1 << 14),
729 .maxFramebufferLayers = (1 << 10),
730 .framebufferColorSampleCounts = sample_counts,
731 .framebufferDepthSampleCounts = sample_counts,
732 .framebufferStencilSampleCounts = sample_counts,
733 .framebufferNoAttachmentsSampleCounts = sample_counts,
734 .maxColorAttachments = MAX_RTS,
735 .sampledImageColorSampleCounts = sample_counts,
736 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
737 .sampledImageDepthSampleCounts = sample_counts,
738 .sampledImageStencilSampleCounts = sample_counts,
739 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
740 .maxSampleMaskWords = 1,
741 .timestampComputeAndGraphics = true,
742 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
743 .maxClipDistances = 8,
744 .maxCullDistances = 8,
745 .maxCombinedClipAndCullDistances = 8,
746 .discreteQueuePriorities = 1,
747 .pointSizeRange = { 0.125, 255.875 },
748 .lineWidthRange = { 0.0, 7.9921875 },
749 .pointSizeGranularity = (1.0 / 8.0),
750 .lineWidthGranularity = (1.0 / 128.0),
751 .strictLines = false, /* FINISHME */
752 .standardSampleLocations = true,
753 .optimalBufferCopyOffsetAlignment = 128,
754 .optimalBufferCopyRowPitchAlignment = 128,
755 .nonCoherentAtomSize = 64,
756 };
757
758 *pProperties = (VkPhysicalDeviceProperties) {
759 .apiVersion = radv_physical_device_api_version(pdevice),
760 .driverVersion = vk_get_driver_version(),
761 .vendorID = ATI_VENDOR_ID,
762 .deviceID = pdevice->rad_info.pci_id,
763 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
764 .limits = limits,
765 .sparseProperties = {0},
766 };
767
768 strcpy(pProperties->deviceName, pdevice->name);
769 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
770 }
771
772 void radv_GetPhysicalDeviceProperties2KHR(
773 VkPhysicalDevice physicalDevice,
774 VkPhysicalDeviceProperties2KHR *pProperties)
775 {
776 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
777 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
778
779 vk_foreach_struct(ext, pProperties->pNext) {
780 switch (ext->sType) {
781 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
782 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
783 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
784 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
785 break;
786 }
787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
788 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
789 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
790 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
791 properties->deviceLUIDValid = false;
792 break;
793 }
794 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
795 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
796 properties->maxMultiviewViewCount = MAX_VIEWS;
797 properties->maxMultiviewInstanceIndex = INT_MAX;
798 break;
799 }
800 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
801 VkPhysicalDevicePointClippingPropertiesKHR *properties =
802 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
803 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
804 break;
805 }
806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
807 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
808 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
809 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
810 break;
811 }
812 default:
813 break;
814 }
815 }
816 }
817
818 static void radv_get_physical_device_queue_family_properties(
819 struct radv_physical_device* pdevice,
820 uint32_t* pCount,
821 VkQueueFamilyProperties** pQueueFamilyProperties)
822 {
823 int num_queue_families = 1;
824 int idx;
825 if (pdevice->rad_info.num_compute_rings > 0 &&
826 pdevice->rad_info.chip_class >= CIK &&
827 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
828 num_queue_families++;
829
830 if (pQueueFamilyProperties == NULL) {
831 *pCount = num_queue_families;
832 return;
833 }
834
835 if (!*pCount)
836 return;
837
838 idx = 0;
839 if (*pCount >= 1) {
840 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
841 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
842 VK_QUEUE_COMPUTE_BIT |
843 VK_QUEUE_TRANSFER_BIT |
844 VK_QUEUE_SPARSE_BINDING_BIT,
845 .queueCount = 1,
846 .timestampValidBits = 64,
847 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
848 };
849 idx++;
850 }
851
852 if (pdevice->rad_info.num_compute_rings > 0 &&
853 pdevice->rad_info.chip_class >= CIK &&
854 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
855 if (*pCount > idx) {
856 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
857 .queueFlags = VK_QUEUE_COMPUTE_BIT |
858 VK_QUEUE_TRANSFER_BIT |
859 VK_QUEUE_SPARSE_BINDING_BIT,
860 .queueCount = pdevice->rad_info.num_compute_rings,
861 .timestampValidBits = 64,
862 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
863 };
864 idx++;
865 }
866 }
867 *pCount = idx;
868 }
869
870 void radv_GetPhysicalDeviceQueueFamilyProperties(
871 VkPhysicalDevice physicalDevice,
872 uint32_t* pCount,
873 VkQueueFamilyProperties* pQueueFamilyProperties)
874 {
875 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
876 if (!pQueueFamilyProperties) {
877 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
878 return;
879 }
880 VkQueueFamilyProperties *properties[] = {
881 pQueueFamilyProperties + 0,
882 pQueueFamilyProperties + 1,
883 pQueueFamilyProperties + 2,
884 };
885 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
886 assert(*pCount <= 3);
887 }
888
889 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
890 VkPhysicalDevice physicalDevice,
891 uint32_t* pCount,
892 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
893 {
894 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
895 if (!pQueueFamilyProperties) {
896 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
897 return;
898 }
899 VkQueueFamilyProperties *properties[] = {
900 &pQueueFamilyProperties[0].queueFamilyProperties,
901 &pQueueFamilyProperties[1].queueFamilyProperties,
902 &pQueueFamilyProperties[2].queueFamilyProperties,
903 };
904 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
905 assert(*pCount <= 3);
906 }
907
908 void radv_GetPhysicalDeviceMemoryProperties(
909 VkPhysicalDevice physicalDevice,
910 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
911 {
912 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
913
914 *pMemoryProperties = physical_device->memory_properties;
915 }
916
917 void radv_GetPhysicalDeviceMemoryProperties2KHR(
918 VkPhysicalDevice physicalDevice,
919 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
920 {
921 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
922 &pMemoryProperties->memoryProperties);
923 }
924
925 static enum radeon_ctx_priority
926 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
927 {
928 /* Default to MEDIUM when a specific global priority isn't requested */
929 if (!pObj)
930 return RADEON_CTX_PRIORITY_MEDIUM;
931
932 switch(pObj->globalPriority) {
933 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
934 return RADEON_CTX_PRIORITY_REALTIME;
935 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
936 return RADEON_CTX_PRIORITY_HIGH;
937 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
938 return RADEON_CTX_PRIORITY_MEDIUM;
939 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
940 return RADEON_CTX_PRIORITY_LOW;
941 default:
942 unreachable("Illegal global priority value");
943 return RADEON_CTX_PRIORITY_INVALID;
944 }
945 }
946
947 static int
948 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
949 uint32_t queue_family_index, int idx,
950 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
951 {
952 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
953 queue->device = device;
954 queue->queue_family_index = queue_family_index;
955 queue->queue_idx = idx;
956 queue->priority = radv_get_queue_global_priority(global_priority);
957
958 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
959 if (!queue->hw_ctx)
960 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
961
962 return VK_SUCCESS;
963 }
964
965 static void
966 radv_queue_finish(struct radv_queue *queue)
967 {
968 if (queue->hw_ctx)
969 queue->device->ws->ctx_destroy(queue->hw_ctx);
970
971 if (queue->initial_full_flush_preamble_cs)
972 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
973 if (queue->initial_preamble_cs)
974 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
975 if (queue->continue_preamble_cs)
976 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
977 if (queue->descriptor_bo)
978 queue->device->ws->buffer_destroy(queue->descriptor_bo);
979 if (queue->scratch_bo)
980 queue->device->ws->buffer_destroy(queue->scratch_bo);
981 if (queue->esgs_ring_bo)
982 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
983 if (queue->gsvs_ring_bo)
984 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
985 if (queue->tess_factor_ring_bo)
986 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
987 if (queue->tess_offchip_ring_bo)
988 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
989 if (queue->compute_scratch_bo)
990 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
991 }
992
993 static void
994 radv_device_init_gs_info(struct radv_device *device)
995 {
996 switch (device->physical_device->rad_info.family) {
997 case CHIP_OLAND:
998 case CHIP_HAINAN:
999 case CHIP_KAVERI:
1000 case CHIP_KABINI:
1001 case CHIP_MULLINS:
1002 case CHIP_ICELAND:
1003 case CHIP_CARRIZO:
1004 case CHIP_STONEY:
1005 device->gs_table_depth = 16;
1006 return;
1007 case CHIP_TAHITI:
1008 case CHIP_PITCAIRN:
1009 case CHIP_VERDE:
1010 case CHIP_BONAIRE:
1011 case CHIP_HAWAII:
1012 case CHIP_TONGA:
1013 case CHIP_FIJI:
1014 case CHIP_POLARIS10:
1015 case CHIP_POLARIS11:
1016 case CHIP_POLARIS12:
1017 case CHIP_VEGA10:
1018 case CHIP_RAVEN:
1019 device->gs_table_depth = 32;
1020 return;
1021 default:
1022 unreachable("unknown GPU");
1023 }
1024 }
1025
1026 VkResult radv_CreateDevice(
1027 VkPhysicalDevice physicalDevice,
1028 const VkDeviceCreateInfo* pCreateInfo,
1029 const VkAllocationCallbacks* pAllocator,
1030 VkDevice* pDevice)
1031 {
1032 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1033 VkResult result;
1034 struct radv_device *device;
1035
1036 bool keep_shader_info = false;
1037
1038 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1039 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1040 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1041 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1042
1043 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1044 keep_shader_info = true;
1045 }
1046
1047 /* Check enabled features */
1048 if (pCreateInfo->pEnabledFeatures) {
1049 VkPhysicalDeviceFeatures supported_features;
1050 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1051 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1052 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1053 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1054 for (uint32_t i = 0; i < num_features; i++) {
1055 if (enabled_feature[i] && !supported_feature[i])
1056 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1057 }
1058 }
1059
1060 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1061 sizeof(*device), 8,
1062 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1063 if (!device)
1064 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1065
1066 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1067 device->instance = physical_device->instance;
1068 device->physical_device = physical_device;
1069
1070 device->ws = physical_device->ws;
1071 if (pAllocator)
1072 device->alloc = *pAllocator;
1073 else
1074 device->alloc = physical_device->instance->alloc;
1075
1076 mtx_init(&device->shader_slab_mutex, mtx_plain);
1077 list_inithead(&device->shader_slabs);
1078
1079 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1080 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1081 uint32_t qfi = queue_create->queueFamilyIndex;
1082 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1083 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1084
1085 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1086
1087 device->queues[qfi] = vk_alloc(&device->alloc,
1088 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1089 if (!device->queues[qfi]) {
1090 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1091 goto fail;
1092 }
1093
1094 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1095
1096 device->queue_count[qfi] = queue_create->queueCount;
1097
1098 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1099 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1100 if (result != VK_SUCCESS)
1101 goto fail;
1102 }
1103 }
1104
1105 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1106 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1107
1108 /* Disabled and not implemented for now. */
1109 device->dfsm_allowed = device->pbb_allowed && false;
1110
1111 #ifdef ANDROID
1112 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1113 #endif
1114
1115 #if HAVE_LLVM < 0x0400
1116 device->llvm_supports_spill = false;
1117 #else
1118 device->llvm_supports_spill = true;
1119 #endif
1120
1121 /* The maximum number of scratch waves. Scratch space isn't divided
1122 * evenly between CUs. The number is only a function of the number of CUs.
1123 * We can decrease the constant to decrease the scratch buffer size.
1124 *
1125 * sctx->scratch_waves must be >= the maximum posible size of
1126 * 1 threadgroup, so that the hw doesn't hang from being unable
1127 * to start any.
1128 *
1129 * The recommended value is 4 per CU at most. Higher numbers don't
1130 * bring much benefit, but they still occupy chip resources (think
1131 * async compute). I've seen ~2% performance difference between 4 and 32.
1132 */
1133 uint32_t max_threads_per_block = 2048;
1134 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1135 max_threads_per_block / 64);
1136
1137 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1138 S_00B800_FORCE_START_AT_000(1);
1139
1140 if (device->physical_device->rad_info.chip_class >= CIK) {
1141 /* If the KMD allows it (there is a KMD hw register for it),
1142 * allow launching waves out-of-order.
1143 */
1144 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1145 }
1146
1147 radv_device_init_gs_info(device);
1148
1149 device->tess_offchip_block_dw_size =
1150 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1151 device->has_distributed_tess =
1152 device->physical_device->rad_info.chip_class >= VI &&
1153 device->physical_device->rad_info.max_se >= 2;
1154
1155 if (getenv("RADV_TRACE_FILE")) {
1156 keep_shader_info = true;
1157
1158 if (!radv_init_trace(device))
1159 goto fail;
1160 }
1161
1162 device->keep_shader_info = keep_shader_info;
1163
1164 result = radv_device_init_meta(device);
1165 if (result != VK_SUCCESS)
1166 goto fail;
1167
1168 radv_device_init_msaa(device);
1169
1170 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1171 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1172 switch (family) {
1173 case RADV_QUEUE_GENERAL:
1174 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1175 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1176 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1177 break;
1178 case RADV_QUEUE_COMPUTE:
1179 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1180 radeon_emit(device->empty_cs[family], 0);
1181 break;
1182 }
1183 device->ws->cs_finalize(device->empty_cs[family]);
1184 }
1185
1186 if (device->physical_device->rad_info.chip_class >= CIK)
1187 cik_create_gfx_config(device);
1188
1189 VkPipelineCacheCreateInfo ci;
1190 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1191 ci.pNext = NULL;
1192 ci.flags = 0;
1193 ci.pInitialData = NULL;
1194 ci.initialDataSize = 0;
1195 VkPipelineCache pc;
1196 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1197 &ci, NULL, &pc);
1198 if (result != VK_SUCCESS)
1199 goto fail_meta;
1200
1201 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1202
1203 *pDevice = radv_device_to_handle(device);
1204 return VK_SUCCESS;
1205
1206 fail_meta:
1207 radv_device_finish_meta(device);
1208 fail:
1209 if (device->trace_bo)
1210 device->ws->buffer_destroy(device->trace_bo);
1211
1212 if (device->gfx_init)
1213 device->ws->buffer_destroy(device->gfx_init);
1214
1215 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1216 for (unsigned q = 0; q < device->queue_count[i]; q++)
1217 radv_queue_finish(&device->queues[i][q]);
1218 if (device->queue_count[i])
1219 vk_free(&device->alloc, device->queues[i]);
1220 }
1221
1222 vk_free(&device->alloc, device);
1223 return result;
1224 }
1225
1226 void radv_DestroyDevice(
1227 VkDevice _device,
1228 const VkAllocationCallbacks* pAllocator)
1229 {
1230 RADV_FROM_HANDLE(radv_device, device, _device);
1231
1232 if (!device)
1233 return;
1234
1235 if (device->trace_bo)
1236 device->ws->buffer_destroy(device->trace_bo);
1237
1238 if (device->gfx_init)
1239 device->ws->buffer_destroy(device->gfx_init);
1240
1241 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1242 for (unsigned q = 0; q < device->queue_count[i]; q++)
1243 radv_queue_finish(&device->queues[i][q]);
1244 if (device->queue_count[i])
1245 vk_free(&device->alloc, device->queues[i]);
1246 if (device->empty_cs[i])
1247 device->ws->cs_destroy(device->empty_cs[i]);
1248 }
1249 radv_device_finish_meta(device);
1250
1251 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1252 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1253
1254 radv_destroy_shader_slabs(device);
1255
1256 vk_free(&device->alloc, device);
1257 }
1258
1259 VkResult radv_EnumerateInstanceLayerProperties(
1260 uint32_t* pPropertyCount,
1261 VkLayerProperties* pProperties)
1262 {
1263 if (pProperties == NULL) {
1264 *pPropertyCount = 0;
1265 return VK_SUCCESS;
1266 }
1267
1268 /* None supported at this time */
1269 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1270 }
1271
1272 VkResult radv_EnumerateDeviceLayerProperties(
1273 VkPhysicalDevice physicalDevice,
1274 uint32_t* pPropertyCount,
1275 VkLayerProperties* pProperties)
1276 {
1277 if (pProperties == NULL) {
1278 *pPropertyCount = 0;
1279 return VK_SUCCESS;
1280 }
1281
1282 /* None supported at this time */
1283 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1284 }
1285
1286 void radv_GetDeviceQueue(
1287 VkDevice _device,
1288 uint32_t queueFamilyIndex,
1289 uint32_t queueIndex,
1290 VkQueue* pQueue)
1291 {
1292 RADV_FROM_HANDLE(radv_device, device, _device);
1293
1294 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1295 }
1296
1297 static void
1298 fill_geom_tess_rings(struct radv_queue *queue,
1299 uint32_t *map,
1300 bool add_sample_positions,
1301 uint32_t esgs_ring_size,
1302 struct radeon_winsys_bo *esgs_ring_bo,
1303 uint32_t gsvs_ring_size,
1304 struct radeon_winsys_bo *gsvs_ring_bo,
1305 uint32_t tess_factor_ring_size,
1306 struct radeon_winsys_bo *tess_factor_ring_bo,
1307 uint32_t tess_offchip_ring_size,
1308 struct radeon_winsys_bo *tess_offchip_ring_bo)
1309 {
1310 uint64_t esgs_va = 0, gsvs_va = 0;
1311 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1312 uint32_t *desc = &map[4];
1313
1314 if (esgs_ring_bo)
1315 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1316 if (gsvs_ring_bo)
1317 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1318 if (tess_factor_ring_bo)
1319 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1320 if (tess_offchip_ring_bo)
1321 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1322
1323 /* stride 0, num records - size, add tid, swizzle, elsize4,
1324 index stride 64 */
1325 desc[0] = esgs_va;
1326 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1327 S_008F04_STRIDE(0) |
1328 S_008F04_SWIZZLE_ENABLE(true);
1329 desc[2] = esgs_ring_size;
1330 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1331 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1332 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1333 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1334 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1335 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1336 S_008F0C_ELEMENT_SIZE(1) |
1337 S_008F0C_INDEX_STRIDE(3) |
1338 S_008F0C_ADD_TID_ENABLE(true);
1339
1340 desc += 4;
1341 /* GS entry for ES->GS ring */
1342 /* stride 0, num records - size, elsize0,
1343 index stride 0 */
1344 desc[0] = esgs_va;
1345 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1346 S_008F04_STRIDE(0) |
1347 S_008F04_SWIZZLE_ENABLE(false);
1348 desc[2] = esgs_ring_size;
1349 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1350 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1351 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1352 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1353 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1354 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1355 S_008F0C_ELEMENT_SIZE(0) |
1356 S_008F0C_INDEX_STRIDE(0) |
1357 S_008F0C_ADD_TID_ENABLE(false);
1358
1359 desc += 4;
1360 /* VS entry for GS->VS ring */
1361 /* stride 0, num records - size, elsize0,
1362 index stride 0 */
1363 desc[0] = gsvs_va;
1364 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1365 S_008F04_STRIDE(0) |
1366 S_008F04_SWIZZLE_ENABLE(false);
1367 desc[2] = gsvs_ring_size;
1368 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1369 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1370 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1371 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1372 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1373 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1374 S_008F0C_ELEMENT_SIZE(0) |
1375 S_008F0C_INDEX_STRIDE(0) |
1376 S_008F0C_ADD_TID_ENABLE(false);
1377 desc += 4;
1378
1379 /* stride gsvs_itemsize, num records 64
1380 elsize 4, index stride 16 */
1381 /* shader will patch stride and desc[2] */
1382 desc[0] = gsvs_va;
1383 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1384 S_008F04_STRIDE(0) |
1385 S_008F04_SWIZZLE_ENABLE(true);
1386 desc[2] = 0;
1387 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1388 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1389 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1390 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1391 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1392 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1393 S_008F0C_ELEMENT_SIZE(1) |
1394 S_008F0C_INDEX_STRIDE(1) |
1395 S_008F0C_ADD_TID_ENABLE(true);
1396 desc += 4;
1397
1398 desc[0] = tess_factor_va;
1399 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1400 S_008F04_STRIDE(0) |
1401 S_008F04_SWIZZLE_ENABLE(false);
1402 desc[2] = tess_factor_ring_size;
1403 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1404 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1405 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1406 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1407 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1408 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1409 S_008F0C_ELEMENT_SIZE(0) |
1410 S_008F0C_INDEX_STRIDE(0) |
1411 S_008F0C_ADD_TID_ENABLE(false);
1412 desc += 4;
1413
1414 desc[0] = tess_offchip_va;
1415 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1416 S_008F04_STRIDE(0) |
1417 S_008F04_SWIZZLE_ENABLE(false);
1418 desc[2] = tess_offchip_ring_size;
1419 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1420 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1421 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1422 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1423 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1424 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1425 S_008F0C_ELEMENT_SIZE(0) |
1426 S_008F0C_INDEX_STRIDE(0) |
1427 S_008F0C_ADD_TID_ENABLE(false);
1428 desc += 4;
1429
1430 /* add sample positions after all rings */
1431 memcpy(desc, queue->device->sample_locations_1x, 8);
1432 desc += 2;
1433 memcpy(desc, queue->device->sample_locations_2x, 16);
1434 desc += 4;
1435 memcpy(desc, queue->device->sample_locations_4x, 32);
1436 desc += 8;
1437 memcpy(desc, queue->device->sample_locations_8x, 64);
1438 desc += 16;
1439 memcpy(desc, queue->device->sample_locations_16x, 128);
1440 }
1441
1442 static unsigned
1443 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1444 {
1445 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1446 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1447 device->physical_device->rad_info.family != CHIP_STONEY;
1448 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1449 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1450 device->physical_device->rad_info.max_se;
1451 unsigned offchip_granularity;
1452 unsigned hs_offchip_param;
1453 switch (device->tess_offchip_block_dw_size) {
1454 default:
1455 assert(0);
1456 /* fall through */
1457 case 8192:
1458 offchip_granularity = V_03093C_X_8K_DWORDS;
1459 break;
1460 case 4096:
1461 offchip_granularity = V_03093C_X_4K_DWORDS;
1462 break;
1463 }
1464
1465 switch (device->physical_device->rad_info.chip_class) {
1466 case SI:
1467 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1468 break;
1469 case CIK:
1470 case VI:
1471 case GFX9:
1472 default:
1473 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1474 break;
1475 }
1476
1477 *max_offchip_buffers_p = max_offchip_buffers;
1478 if (device->physical_device->rad_info.chip_class >= CIK) {
1479 if (device->physical_device->rad_info.chip_class >= VI)
1480 --max_offchip_buffers;
1481 hs_offchip_param =
1482 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1483 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1484 } else {
1485 hs_offchip_param =
1486 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1487 }
1488 return hs_offchip_param;
1489 }
1490
1491 static VkResult
1492 radv_get_preamble_cs(struct radv_queue *queue,
1493 uint32_t scratch_size,
1494 uint32_t compute_scratch_size,
1495 uint32_t esgs_ring_size,
1496 uint32_t gsvs_ring_size,
1497 bool needs_tess_rings,
1498 bool needs_sample_positions,
1499 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1500 struct radeon_winsys_cs **initial_preamble_cs,
1501 struct radeon_winsys_cs **continue_preamble_cs)
1502 {
1503 struct radeon_winsys_bo *scratch_bo = NULL;
1504 struct radeon_winsys_bo *descriptor_bo = NULL;
1505 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1506 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1507 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1508 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1509 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1510 struct radeon_winsys_cs *dest_cs[3] = {0};
1511 bool add_tess_rings = false, add_sample_positions = false;
1512 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1513 unsigned max_offchip_buffers;
1514 unsigned hs_offchip_param = 0;
1515 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1516 if (!queue->has_tess_rings) {
1517 if (needs_tess_rings)
1518 add_tess_rings = true;
1519 }
1520 if (!queue->has_sample_positions) {
1521 if (needs_sample_positions)
1522 add_sample_positions = true;
1523 }
1524 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1525 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1526 &max_offchip_buffers);
1527 tess_offchip_ring_size = max_offchip_buffers *
1528 queue->device->tess_offchip_block_dw_size * 4;
1529
1530 if (scratch_size <= queue->scratch_size &&
1531 compute_scratch_size <= queue->compute_scratch_size &&
1532 esgs_ring_size <= queue->esgs_ring_size &&
1533 gsvs_ring_size <= queue->gsvs_ring_size &&
1534 !add_tess_rings && !add_sample_positions &&
1535 queue->initial_preamble_cs) {
1536 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1537 *initial_preamble_cs = queue->initial_preamble_cs;
1538 *continue_preamble_cs = queue->continue_preamble_cs;
1539 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1540 *continue_preamble_cs = NULL;
1541 return VK_SUCCESS;
1542 }
1543
1544 if (scratch_size > queue->scratch_size) {
1545 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1546 scratch_size,
1547 4096,
1548 RADEON_DOMAIN_VRAM,
1549 ring_bo_flags);
1550 if (!scratch_bo)
1551 goto fail;
1552 } else
1553 scratch_bo = queue->scratch_bo;
1554
1555 if (compute_scratch_size > queue->compute_scratch_size) {
1556 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1557 compute_scratch_size,
1558 4096,
1559 RADEON_DOMAIN_VRAM,
1560 ring_bo_flags);
1561 if (!compute_scratch_bo)
1562 goto fail;
1563
1564 } else
1565 compute_scratch_bo = queue->compute_scratch_bo;
1566
1567 if (esgs_ring_size > queue->esgs_ring_size) {
1568 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1569 esgs_ring_size,
1570 4096,
1571 RADEON_DOMAIN_VRAM,
1572 ring_bo_flags);
1573 if (!esgs_ring_bo)
1574 goto fail;
1575 } else {
1576 esgs_ring_bo = queue->esgs_ring_bo;
1577 esgs_ring_size = queue->esgs_ring_size;
1578 }
1579
1580 if (gsvs_ring_size > queue->gsvs_ring_size) {
1581 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1582 gsvs_ring_size,
1583 4096,
1584 RADEON_DOMAIN_VRAM,
1585 ring_bo_flags);
1586 if (!gsvs_ring_bo)
1587 goto fail;
1588 } else {
1589 gsvs_ring_bo = queue->gsvs_ring_bo;
1590 gsvs_ring_size = queue->gsvs_ring_size;
1591 }
1592
1593 if (add_tess_rings) {
1594 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1595 tess_factor_ring_size,
1596 256,
1597 RADEON_DOMAIN_VRAM,
1598 ring_bo_flags);
1599 if (!tess_factor_ring_bo)
1600 goto fail;
1601 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1602 tess_offchip_ring_size,
1603 256,
1604 RADEON_DOMAIN_VRAM,
1605 ring_bo_flags);
1606 if (!tess_offchip_ring_bo)
1607 goto fail;
1608 } else {
1609 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1610 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1611 }
1612
1613 if (scratch_bo != queue->scratch_bo ||
1614 esgs_ring_bo != queue->esgs_ring_bo ||
1615 gsvs_ring_bo != queue->gsvs_ring_bo ||
1616 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1617 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1618 uint32_t size = 0;
1619 if (gsvs_ring_bo || esgs_ring_bo ||
1620 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1621 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1622 if (add_sample_positions)
1623 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1624 }
1625 else if (scratch_bo)
1626 size = 8; /* 2 dword */
1627
1628 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1629 size,
1630 4096,
1631 RADEON_DOMAIN_VRAM,
1632 RADEON_FLAG_CPU_ACCESS |
1633 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1634 RADEON_FLAG_READ_ONLY);
1635 if (!descriptor_bo)
1636 goto fail;
1637 } else
1638 descriptor_bo = queue->descriptor_bo;
1639
1640 for(int i = 0; i < 3; ++i) {
1641 struct radeon_winsys_cs *cs = NULL;
1642 cs = queue->device->ws->cs_create(queue->device->ws,
1643 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1644 if (!cs)
1645 goto fail;
1646
1647 dest_cs[i] = cs;
1648
1649 if (scratch_bo)
1650 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1651
1652 if (esgs_ring_bo)
1653 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1654
1655 if (gsvs_ring_bo)
1656 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1657
1658 if (tess_factor_ring_bo)
1659 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1660
1661 if (tess_offchip_ring_bo)
1662 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1663
1664 if (descriptor_bo)
1665 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1666
1667 if (descriptor_bo != queue->descriptor_bo) {
1668 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1669
1670 if (scratch_bo) {
1671 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1672 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1673 S_008F04_SWIZZLE_ENABLE(1);
1674 map[0] = scratch_va;
1675 map[1] = rsrc1;
1676 }
1677
1678 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1679 add_sample_positions)
1680 fill_geom_tess_rings(queue, map, add_sample_positions,
1681 esgs_ring_size, esgs_ring_bo,
1682 gsvs_ring_size, gsvs_ring_bo,
1683 tess_factor_ring_size, tess_factor_ring_bo,
1684 tess_offchip_ring_size, tess_offchip_ring_bo);
1685
1686 queue->device->ws->buffer_unmap(descriptor_bo);
1687 }
1688
1689 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1690 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1691 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1692 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1693 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1694 }
1695
1696 if (esgs_ring_bo || gsvs_ring_bo) {
1697 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1698 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1699 radeon_emit(cs, esgs_ring_size >> 8);
1700 radeon_emit(cs, gsvs_ring_size >> 8);
1701 } else {
1702 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1703 radeon_emit(cs, esgs_ring_size >> 8);
1704 radeon_emit(cs, gsvs_ring_size >> 8);
1705 }
1706 }
1707
1708 if (tess_factor_ring_bo) {
1709 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1710 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1711 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1712 S_030938_SIZE(tess_factor_ring_size / 4));
1713 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1714 tf_va >> 8);
1715 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1716 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1717 tf_va >> 40);
1718 }
1719 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1720 } else {
1721 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1722 S_008988_SIZE(tess_factor_ring_size / 4));
1723 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1724 tf_va >> 8);
1725 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1726 hs_offchip_param);
1727 }
1728 }
1729
1730 if (descriptor_bo) {
1731 uint64_t va = radv_buffer_get_va(descriptor_bo);
1732 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1733 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1734 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1735 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1736 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1737
1738 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1739 radeon_set_sh_reg_seq(cs, regs[i], 2);
1740 radeon_emit(cs, va);
1741 radeon_emit(cs, va >> 32);
1742 }
1743 } else {
1744 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1745 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1746 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1747 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1748 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1749 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1750
1751 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1752 radeon_set_sh_reg_seq(cs, regs[i], 2);
1753 radeon_emit(cs, va);
1754 radeon_emit(cs, va >> 32);
1755 }
1756 }
1757 }
1758
1759 if (compute_scratch_bo) {
1760 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1761 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1762 S_008F04_SWIZZLE_ENABLE(1);
1763
1764 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1765
1766 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1767 radeon_emit(cs, scratch_va);
1768 radeon_emit(cs, rsrc1);
1769 }
1770
1771 if (i == 0) {
1772 si_cs_emit_cache_flush(cs,
1773 false,
1774 queue->device->physical_device->rad_info.chip_class,
1775 NULL, 0,
1776 queue->queue_family_index == RING_COMPUTE &&
1777 queue->device->physical_device->rad_info.chip_class >= CIK,
1778 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1779 RADV_CMD_FLAG_INV_ICACHE |
1780 RADV_CMD_FLAG_INV_SMEM_L1 |
1781 RADV_CMD_FLAG_INV_VMEM_L1 |
1782 RADV_CMD_FLAG_INV_GLOBAL_L2);
1783 } else if (i == 1) {
1784 si_cs_emit_cache_flush(cs,
1785 false,
1786 queue->device->physical_device->rad_info.chip_class,
1787 NULL, 0,
1788 queue->queue_family_index == RING_COMPUTE &&
1789 queue->device->physical_device->rad_info.chip_class >= CIK,
1790 RADV_CMD_FLAG_INV_ICACHE |
1791 RADV_CMD_FLAG_INV_SMEM_L1 |
1792 RADV_CMD_FLAG_INV_VMEM_L1 |
1793 RADV_CMD_FLAG_INV_GLOBAL_L2);
1794 }
1795
1796 if (!queue->device->ws->cs_finalize(cs))
1797 goto fail;
1798 }
1799
1800 if (queue->initial_full_flush_preamble_cs)
1801 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1802
1803 if (queue->initial_preamble_cs)
1804 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1805
1806 if (queue->continue_preamble_cs)
1807 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1808
1809 queue->initial_full_flush_preamble_cs = dest_cs[0];
1810 queue->initial_preamble_cs = dest_cs[1];
1811 queue->continue_preamble_cs = dest_cs[2];
1812
1813 if (scratch_bo != queue->scratch_bo) {
1814 if (queue->scratch_bo)
1815 queue->device->ws->buffer_destroy(queue->scratch_bo);
1816 queue->scratch_bo = scratch_bo;
1817 queue->scratch_size = scratch_size;
1818 }
1819
1820 if (compute_scratch_bo != queue->compute_scratch_bo) {
1821 if (queue->compute_scratch_bo)
1822 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1823 queue->compute_scratch_bo = compute_scratch_bo;
1824 queue->compute_scratch_size = compute_scratch_size;
1825 }
1826
1827 if (esgs_ring_bo != queue->esgs_ring_bo) {
1828 if (queue->esgs_ring_bo)
1829 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1830 queue->esgs_ring_bo = esgs_ring_bo;
1831 queue->esgs_ring_size = esgs_ring_size;
1832 }
1833
1834 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1835 if (queue->gsvs_ring_bo)
1836 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1837 queue->gsvs_ring_bo = gsvs_ring_bo;
1838 queue->gsvs_ring_size = gsvs_ring_size;
1839 }
1840
1841 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1842 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1843 }
1844
1845 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1846 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1847 queue->has_tess_rings = true;
1848 }
1849
1850 if (descriptor_bo != queue->descriptor_bo) {
1851 if (queue->descriptor_bo)
1852 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1853
1854 queue->descriptor_bo = descriptor_bo;
1855 }
1856
1857 if (add_sample_positions)
1858 queue->has_sample_positions = true;
1859
1860 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1861 *initial_preamble_cs = queue->initial_preamble_cs;
1862 *continue_preamble_cs = queue->continue_preamble_cs;
1863 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1864 *continue_preamble_cs = NULL;
1865 return VK_SUCCESS;
1866 fail:
1867 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1868 if (dest_cs[i])
1869 queue->device->ws->cs_destroy(dest_cs[i]);
1870 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1871 queue->device->ws->buffer_destroy(descriptor_bo);
1872 if (scratch_bo && scratch_bo != queue->scratch_bo)
1873 queue->device->ws->buffer_destroy(scratch_bo);
1874 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1875 queue->device->ws->buffer_destroy(compute_scratch_bo);
1876 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1877 queue->device->ws->buffer_destroy(esgs_ring_bo);
1878 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1879 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1880 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1881 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1882 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1883 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1884 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1885 }
1886
1887 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1888 int num_sems,
1889 const VkSemaphore *sems,
1890 VkFence _fence,
1891 bool reset_temp)
1892 {
1893 int syncobj_idx = 0, sem_idx = 0;
1894
1895 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1896 return VK_SUCCESS;
1897
1898 for (uint32_t i = 0; i < num_sems; i++) {
1899 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1900
1901 if (sem->temp_syncobj || sem->syncobj)
1902 counts->syncobj_count++;
1903 else
1904 counts->sem_count++;
1905 }
1906
1907 if (_fence != VK_NULL_HANDLE) {
1908 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1909 if (fence->temp_syncobj || fence->syncobj)
1910 counts->syncobj_count++;
1911 }
1912
1913 if (counts->syncobj_count) {
1914 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1915 if (!counts->syncobj)
1916 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1917 }
1918
1919 if (counts->sem_count) {
1920 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1921 if (!counts->sem) {
1922 free(counts->syncobj);
1923 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1924 }
1925 }
1926
1927 for (uint32_t i = 0; i < num_sems; i++) {
1928 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1929
1930 if (sem->temp_syncobj) {
1931 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1932 }
1933 else if (sem->syncobj)
1934 counts->syncobj[syncobj_idx++] = sem->syncobj;
1935 else {
1936 assert(sem->sem);
1937 counts->sem[sem_idx++] = sem->sem;
1938 }
1939 }
1940
1941 if (_fence != VK_NULL_HANDLE) {
1942 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1943 if (fence->temp_syncobj)
1944 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1945 else if (fence->syncobj)
1946 counts->syncobj[syncobj_idx++] = fence->syncobj;
1947 }
1948
1949 return VK_SUCCESS;
1950 }
1951
1952 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1953 {
1954 free(sem_info->wait.syncobj);
1955 free(sem_info->wait.sem);
1956 free(sem_info->signal.syncobj);
1957 free(sem_info->signal.sem);
1958 }
1959
1960
1961 static void radv_free_temp_syncobjs(struct radv_device *device,
1962 int num_sems,
1963 const VkSemaphore *sems)
1964 {
1965 for (uint32_t i = 0; i < num_sems; i++) {
1966 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1967
1968 if (sem->temp_syncobj) {
1969 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1970 sem->temp_syncobj = 0;
1971 }
1972 }
1973 }
1974
1975 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1976 int num_wait_sems,
1977 const VkSemaphore *wait_sems,
1978 int num_signal_sems,
1979 const VkSemaphore *signal_sems,
1980 VkFence fence)
1981 {
1982 VkResult ret;
1983 memset(sem_info, 0, sizeof(*sem_info));
1984
1985 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
1986 if (ret)
1987 return ret;
1988 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
1989 if (ret)
1990 radv_free_sem_info(sem_info);
1991
1992 /* caller can override these */
1993 sem_info->cs_emit_wait = true;
1994 sem_info->cs_emit_signal = true;
1995 return ret;
1996 }
1997
1998 VkResult radv_QueueSubmit(
1999 VkQueue _queue,
2000 uint32_t submitCount,
2001 const VkSubmitInfo* pSubmits,
2002 VkFence _fence)
2003 {
2004 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2005 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2006 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2007 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2008 int ret;
2009 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2010 uint32_t scratch_size = 0;
2011 uint32_t compute_scratch_size = 0;
2012 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2013 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2014 VkResult result;
2015 bool fence_emitted = false;
2016 bool tess_rings_needed = false;
2017 bool sample_positions_needed = false;
2018
2019 /* Do this first so failing to allocate scratch buffers can't result in
2020 * partially executed submissions. */
2021 for (uint32_t i = 0; i < submitCount; i++) {
2022 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2023 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2024 pSubmits[i].pCommandBuffers[j]);
2025
2026 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2027 compute_scratch_size = MAX2(compute_scratch_size,
2028 cmd_buffer->compute_scratch_size_needed);
2029 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2030 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2031 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2032 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2033 }
2034 }
2035
2036 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2037 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2038 sample_positions_needed, &initial_flush_preamble_cs,
2039 &initial_preamble_cs, &continue_preamble_cs);
2040 if (result != VK_SUCCESS)
2041 return result;
2042
2043 for (uint32_t i = 0; i < submitCount; i++) {
2044 struct radeon_winsys_cs **cs_array;
2045 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2046 bool can_patch = true;
2047 uint32_t advance;
2048 struct radv_winsys_sem_info sem_info;
2049
2050 result = radv_alloc_sem_info(&sem_info,
2051 pSubmits[i].waitSemaphoreCount,
2052 pSubmits[i].pWaitSemaphores,
2053 pSubmits[i].signalSemaphoreCount,
2054 pSubmits[i].pSignalSemaphores,
2055 _fence);
2056 if (result != VK_SUCCESS)
2057 return result;
2058
2059 if (!pSubmits[i].commandBufferCount) {
2060 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2061 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2062 &queue->device->empty_cs[queue->queue_family_index],
2063 1, NULL, NULL,
2064 &sem_info,
2065 false, base_fence);
2066 if (ret) {
2067 radv_loge("failed to submit CS %d\n", i);
2068 abort();
2069 }
2070 fence_emitted = true;
2071 }
2072 radv_free_sem_info(&sem_info);
2073 continue;
2074 }
2075
2076 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2077 (pSubmits[i].commandBufferCount));
2078
2079 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2081 pSubmits[i].pCommandBuffers[j]);
2082 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2083
2084 cs_array[j] = cmd_buffer->cs;
2085 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2086 can_patch = false;
2087
2088 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2089 }
2090
2091 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2092 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2093 advance = MIN2(max_cs_submission,
2094 pSubmits[i].commandBufferCount - j);
2095
2096 if (queue->device->trace_bo)
2097 *queue->device->trace_id_ptr = 0;
2098
2099 sem_info.cs_emit_wait = j == 0;
2100 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2101
2102 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2103 advance, initial_preamble, continue_preamble_cs,
2104 &sem_info,
2105 can_patch, base_fence);
2106
2107 if (ret) {
2108 radv_loge("failed to submit CS %d\n", i);
2109 abort();
2110 }
2111 fence_emitted = true;
2112 if (queue->device->trace_bo) {
2113 radv_check_gpu_hangs(queue, cs_array[j]);
2114 }
2115 }
2116
2117 radv_free_temp_syncobjs(queue->device,
2118 pSubmits[i].waitSemaphoreCount,
2119 pSubmits[i].pWaitSemaphores);
2120 radv_free_sem_info(&sem_info);
2121 free(cs_array);
2122 }
2123
2124 if (fence) {
2125 if (!fence_emitted) {
2126 struct radv_winsys_sem_info sem_info;
2127
2128 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2129 _fence);
2130 if (result != VK_SUCCESS)
2131 return result;
2132
2133 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2134 &queue->device->empty_cs[queue->queue_family_index],
2135 1, NULL, NULL, &sem_info,
2136 false, base_fence);
2137 radv_free_sem_info(&sem_info);
2138 }
2139 fence->submitted = true;
2140 }
2141
2142 return VK_SUCCESS;
2143 }
2144
2145 VkResult radv_QueueWaitIdle(
2146 VkQueue _queue)
2147 {
2148 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2149
2150 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2151 radv_queue_family_to_ring(queue->queue_family_index),
2152 queue->queue_idx);
2153 return VK_SUCCESS;
2154 }
2155
2156 VkResult radv_DeviceWaitIdle(
2157 VkDevice _device)
2158 {
2159 RADV_FROM_HANDLE(radv_device, device, _device);
2160
2161 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2162 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2163 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2164 }
2165 }
2166 return VK_SUCCESS;
2167 }
2168
2169 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2170 VkInstance instance,
2171 const char* pName)
2172 {
2173 return radv_lookup_entrypoint(pName);
2174 }
2175
2176 /* The loader wants us to expose a second GetInstanceProcAddr function
2177 * to work around certain LD_PRELOAD issues seen in apps.
2178 */
2179 PUBLIC
2180 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2181 VkInstance instance,
2182 const char* pName);
2183
2184 PUBLIC
2185 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2186 VkInstance instance,
2187 const char* pName)
2188 {
2189 return radv_GetInstanceProcAddr(instance, pName);
2190 }
2191
2192 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2193 VkDevice device,
2194 const char* pName)
2195 {
2196 return radv_lookup_entrypoint(pName);
2197 }
2198
2199 bool radv_get_memory_fd(struct radv_device *device,
2200 struct radv_device_memory *memory,
2201 int *pFD)
2202 {
2203 struct radeon_bo_metadata metadata;
2204
2205 if (memory->image) {
2206 radv_init_metadata(device, memory->image, &metadata);
2207 device->ws->buffer_set_metadata(memory->bo, &metadata);
2208 }
2209
2210 return device->ws->buffer_get_fd(device->ws, memory->bo,
2211 pFD);
2212 }
2213
2214 static VkResult radv_alloc_memory(struct radv_device *device,
2215 const VkMemoryAllocateInfo* pAllocateInfo,
2216 const VkAllocationCallbacks* pAllocator,
2217 VkDeviceMemory* pMem)
2218 {
2219 struct radv_device_memory *mem;
2220 VkResult result;
2221 enum radeon_bo_domain domain;
2222 uint32_t flags = 0;
2223 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2224
2225 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2226
2227 if (pAllocateInfo->allocationSize == 0) {
2228 /* Apparently, this is allowed */
2229 *pMem = VK_NULL_HANDLE;
2230 return VK_SUCCESS;
2231 }
2232
2233 const VkImportMemoryFdInfoKHR *import_info =
2234 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2235 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2236 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2237 const VkExportMemoryAllocateInfoKHR *export_info =
2238 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2239
2240 const struct wsi_memory_allocate_info *wsi_info =
2241 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2242
2243 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2244 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2245 if (mem == NULL)
2246 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2247
2248 if (wsi_info && wsi_info->implicit_sync)
2249 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2250
2251 if (dedicate_info) {
2252 mem->image = radv_image_from_handle(dedicate_info->image);
2253 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2254 } else {
2255 mem->image = NULL;
2256 mem->buffer = NULL;
2257 }
2258
2259 if (import_info) {
2260 assert(import_info->handleType ==
2261 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2262 import_info->handleType ==
2263 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2264 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2265 NULL, NULL);
2266 if (!mem->bo) {
2267 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2268 goto fail;
2269 } else {
2270 close(import_info->fd);
2271 goto out_success;
2272 }
2273 }
2274
2275 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2276 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2277 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2278 domain = RADEON_DOMAIN_GTT;
2279 else
2280 domain = RADEON_DOMAIN_VRAM;
2281
2282 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2283 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2284 else
2285 flags |= RADEON_FLAG_CPU_ACCESS;
2286
2287 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2288 flags |= RADEON_FLAG_GTT_WC;
2289
2290 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2291 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2292
2293 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2294 domain, flags);
2295
2296 if (!mem->bo) {
2297 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2298 goto fail;
2299 }
2300 mem->type_index = mem_type_index;
2301 out_success:
2302 *pMem = radv_device_memory_to_handle(mem);
2303
2304 return VK_SUCCESS;
2305
2306 fail:
2307 vk_free2(&device->alloc, pAllocator, mem);
2308
2309 return result;
2310 }
2311
2312 VkResult radv_AllocateMemory(
2313 VkDevice _device,
2314 const VkMemoryAllocateInfo* pAllocateInfo,
2315 const VkAllocationCallbacks* pAllocator,
2316 VkDeviceMemory* pMem)
2317 {
2318 RADV_FROM_HANDLE(radv_device, device, _device);
2319 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2320 }
2321
2322 void radv_FreeMemory(
2323 VkDevice _device,
2324 VkDeviceMemory _mem,
2325 const VkAllocationCallbacks* pAllocator)
2326 {
2327 RADV_FROM_HANDLE(radv_device, device, _device);
2328 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2329
2330 if (mem == NULL)
2331 return;
2332
2333 device->ws->buffer_destroy(mem->bo);
2334 mem->bo = NULL;
2335
2336 vk_free2(&device->alloc, pAllocator, mem);
2337 }
2338
2339 VkResult radv_MapMemory(
2340 VkDevice _device,
2341 VkDeviceMemory _memory,
2342 VkDeviceSize offset,
2343 VkDeviceSize size,
2344 VkMemoryMapFlags flags,
2345 void** ppData)
2346 {
2347 RADV_FROM_HANDLE(radv_device, device, _device);
2348 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2349
2350 if (mem == NULL) {
2351 *ppData = NULL;
2352 return VK_SUCCESS;
2353 }
2354
2355 *ppData = device->ws->buffer_map(mem->bo);
2356 if (*ppData) {
2357 *ppData += offset;
2358 return VK_SUCCESS;
2359 }
2360
2361 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2362 }
2363
2364 void radv_UnmapMemory(
2365 VkDevice _device,
2366 VkDeviceMemory _memory)
2367 {
2368 RADV_FROM_HANDLE(radv_device, device, _device);
2369 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2370
2371 if (mem == NULL)
2372 return;
2373
2374 device->ws->buffer_unmap(mem->bo);
2375 }
2376
2377 VkResult radv_FlushMappedMemoryRanges(
2378 VkDevice _device,
2379 uint32_t memoryRangeCount,
2380 const VkMappedMemoryRange* pMemoryRanges)
2381 {
2382 return VK_SUCCESS;
2383 }
2384
2385 VkResult radv_InvalidateMappedMemoryRanges(
2386 VkDevice _device,
2387 uint32_t memoryRangeCount,
2388 const VkMappedMemoryRange* pMemoryRanges)
2389 {
2390 return VK_SUCCESS;
2391 }
2392
2393 void radv_GetBufferMemoryRequirements(
2394 VkDevice _device,
2395 VkBuffer _buffer,
2396 VkMemoryRequirements* pMemoryRequirements)
2397 {
2398 RADV_FROM_HANDLE(radv_device, device, _device);
2399 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2400
2401 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2402
2403 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2404 pMemoryRequirements->alignment = 4096;
2405 else
2406 pMemoryRequirements->alignment = 16;
2407
2408 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2409 }
2410
2411 void radv_GetBufferMemoryRequirements2KHR(
2412 VkDevice device,
2413 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2414 VkMemoryRequirements2KHR* pMemoryRequirements)
2415 {
2416 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2417 &pMemoryRequirements->memoryRequirements);
2418 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2419 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2420 switch (ext->sType) {
2421 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2422 VkMemoryDedicatedRequirementsKHR *req =
2423 (VkMemoryDedicatedRequirementsKHR *) ext;
2424 req->requiresDedicatedAllocation = buffer->shareable;
2425 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2426 break;
2427 }
2428 default:
2429 break;
2430 }
2431 }
2432 }
2433
2434 void radv_GetImageMemoryRequirements(
2435 VkDevice _device,
2436 VkImage _image,
2437 VkMemoryRequirements* pMemoryRequirements)
2438 {
2439 RADV_FROM_HANDLE(radv_device, device, _device);
2440 RADV_FROM_HANDLE(radv_image, image, _image);
2441
2442 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2443
2444 pMemoryRequirements->size = image->size;
2445 pMemoryRequirements->alignment = image->alignment;
2446 }
2447
2448 void radv_GetImageMemoryRequirements2KHR(
2449 VkDevice device,
2450 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2451 VkMemoryRequirements2KHR* pMemoryRequirements)
2452 {
2453 radv_GetImageMemoryRequirements(device, pInfo->image,
2454 &pMemoryRequirements->memoryRequirements);
2455
2456 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2457
2458 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2459 switch (ext->sType) {
2460 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2461 VkMemoryDedicatedRequirementsKHR *req =
2462 (VkMemoryDedicatedRequirementsKHR *) ext;
2463 req->requiresDedicatedAllocation = image->shareable;
2464 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2465 break;
2466 }
2467 default:
2468 break;
2469 }
2470 }
2471 }
2472
2473 void radv_GetImageSparseMemoryRequirements(
2474 VkDevice device,
2475 VkImage image,
2476 uint32_t* pSparseMemoryRequirementCount,
2477 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2478 {
2479 stub();
2480 }
2481
2482 void radv_GetImageSparseMemoryRequirements2KHR(
2483 VkDevice device,
2484 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2485 uint32_t* pSparseMemoryRequirementCount,
2486 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2487 {
2488 stub();
2489 }
2490
2491 void radv_GetDeviceMemoryCommitment(
2492 VkDevice device,
2493 VkDeviceMemory memory,
2494 VkDeviceSize* pCommittedMemoryInBytes)
2495 {
2496 *pCommittedMemoryInBytes = 0;
2497 }
2498
2499 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2500 uint32_t bindInfoCount,
2501 const VkBindBufferMemoryInfoKHR *pBindInfos)
2502 {
2503 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2504 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2505 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2506
2507 if (mem) {
2508 buffer->bo = mem->bo;
2509 buffer->offset = pBindInfos[i].memoryOffset;
2510 } else {
2511 buffer->bo = NULL;
2512 }
2513 }
2514 return VK_SUCCESS;
2515 }
2516
2517 VkResult radv_BindBufferMemory(
2518 VkDevice device,
2519 VkBuffer buffer,
2520 VkDeviceMemory memory,
2521 VkDeviceSize memoryOffset)
2522 {
2523 const VkBindBufferMemoryInfoKHR info = {
2524 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2525 .buffer = buffer,
2526 .memory = memory,
2527 .memoryOffset = memoryOffset
2528 };
2529
2530 return radv_BindBufferMemory2KHR(device, 1, &info);
2531 }
2532
2533 VkResult radv_BindImageMemory2KHR(VkDevice device,
2534 uint32_t bindInfoCount,
2535 const VkBindImageMemoryInfoKHR *pBindInfos)
2536 {
2537 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2538 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2539 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2540
2541 if (mem) {
2542 image->bo = mem->bo;
2543 image->offset = pBindInfos[i].memoryOffset;
2544 } else {
2545 image->bo = NULL;
2546 image->offset = 0;
2547 }
2548 }
2549 return VK_SUCCESS;
2550 }
2551
2552
2553 VkResult radv_BindImageMemory(
2554 VkDevice device,
2555 VkImage image,
2556 VkDeviceMemory memory,
2557 VkDeviceSize memoryOffset)
2558 {
2559 const VkBindImageMemoryInfoKHR info = {
2560 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2561 .image = image,
2562 .memory = memory,
2563 .memoryOffset = memoryOffset
2564 };
2565
2566 return radv_BindImageMemory2KHR(device, 1, &info);
2567 }
2568
2569
2570 static void
2571 radv_sparse_buffer_bind_memory(struct radv_device *device,
2572 const VkSparseBufferMemoryBindInfo *bind)
2573 {
2574 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2575
2576 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2577 struct radv_device_memory *mem = NULL;
2578
2579 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2580 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2581
2582 device->ws->buffer_virtual_bind(buffer->bo,
2583 bind->pBinds[i].resourceOffset,
2584 bind->pBinds[i].size,
2585 mem ? mem->bo : NULL,
2586 bind->pBinds[i].memoryOffset);
2587 }
2588 }
2589
2590 static void
2591 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2592 const VkSparseImageOpaqueMemoryBindInfo *bind)
2593 {
2594 RADV_FROM_HANDLE(radv_image, image, bind->image);
2595
2596 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2597 struct radv_device_memory *mem = NULL;
2598
2599 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2600 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2601
2602 device->ws->buffer_virtual_bind(image->bo,
2603 bind->pBinds[i].resourceOffset,
2604 bind->pBinds[i].size,
2605 mem ? mem->bo : NULL,
2606 bind->pBinds[i].memoryOffset);
2607 }
2608 }
2609
2610 VkResult radv_QueueBindSparse(
2611 VkQueue _queue,
2612 uint32_t bindInfoCount,
2613 const VkBindSparseInfo* pBindInfo,
2614 VkFence _fence)
2615 {
2616 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2617 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2618 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2619 bool fence_emitted = false;
2620
2621 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2622 struct radv_winsys_sem_info sem_info;
2623 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2624 radv_sparse_buffer_bind_memory(queue->device,
2625 pBindInfo[i].pBufferBinds + j);
2626 }
2627
2628 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2629 radv_sparse_image_opaque_bind_memory(queue->device,
2630 pBindInfo[i].pImageOpaqueBinds + j);
2631 }
2632
2633 VkResult result;
2634 result = radv_alloc_sem_info(&sem_info,
2635 pBindInfo[i].waitSemaphoreCount,
2636 pBindInfo[i].pWaitSemaphores,
2637 pBindInfo[i].signalSemaphoreCount,
2638 pBindInfo[i].pSignalSemaphores,
2639 _fence);
2640 if (result != VK_SUCCESS)
2641 return result;
2642
2643 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2644 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2645 &queue->device->empty_cs[queue->queue_family_index],
2646 1, NULL, NULL,
2647 &sem_info,
2648 false, base_fence);
2649 fence_emitted = true;
2650 if (fence)
2651 fence->submitted = true;
2652 }
2653
2654 radv_free_sem_info(&sem_info);
2655
2656 }
2657
2658 if (fence && !fence_emitted) {
2659 fence->signalled = true;
2660 }
2661
2662 return VK_SUCCESS;
2663 }
2664
2665 VkResult radv_CreateFence(
2666 VkDevice _device,
2667 const VkFenceCreateInfo* pCreateInfo,
2668 const VkAllocationCallbacks* pAllocator,
2669 VkFence* pFence)
2670 {
2671 RADV_FROM_HANDLE(radv_device, device, _device);
2672 const VkExportFenceCreateInfoKHR *export =
2673 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2674 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2675 export ? export->handleTypes : 0;
2676
2677 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2678 sizeof(*fence), 8,
2679 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2680
2681 if (!fence)
2682 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2683
2684 fence->submitted = false;
2685 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2686 fence->temp_syncobj = 0;
2687 if (device->always_use_syncobj || handleTypes) {
2688 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2689 if (ret) {
2690 vk_free2(&device->alloc, pAllocator, fence);
2691 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2692 }
2693 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2694 device->ws->signal_syncobj(device->ws, fence->syncobj);
2695 }
2696 fence->fence = NULL;
2697 } else {
2698 fence->fence = device->ws->create_fence();
2699 if (!fence->fence) {
2700 vk_free2(&device->alloc, pAllocator, fence);
2701 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2702 }
2703 fence->syncobj = 0;
2704 }
2705
2706 *pFence = radv_fence_to_handle(fence);
2707
2708 return VK_SUCCESS;
2709 }
2710
2711 void radv_DestroyFence(
2712 VkDevice _device,
2713 VkFence _fence,
2714 const VkAllocationCallbacks* pAllocator)
2715 {
2716 RADV_FROM_HANDLE(radv_device, device, _device);
2717 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2718
2719 if (!fence)
2720 return;
2721
2722 if (fence->temp_syncobj)
2723 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2724 if (fence->syncobj)
2725 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2726 if (fence->fence)
2727 device->ws->destroy_fence(fence->fence);
2728 vk_free2(&device->alloc, pAllocator, fence);
2729 }
2730
2731 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2732 {
2733 uint64_t current_time;
2734 struct timespec tv;
2735
2736 clock_gettime(CLOCK_MONOTONIC, &tv);
2737 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2738
2739 timeout = MIN2(UINT64_MAX - current_time, timeout);
2740
2741 return current_time + timeout;
2742 }
2743
2744 VkResult radv_WaitForFences(
2745 VkDevice _device,
2746 uint32_t fenceCount,
2747 const VkFence* pFences,
2748 VkBool32 waitAll,
2749 uint64_t timeout)
2750 {
2751 RADV_FROM_HANDLE(radv_device, device, _device);
2752 timeout = radv_get_absolute_timeout(timeout);
2753
2754 if (!waitAll && fenceCount > 1) {
2755 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2756 }
2757
2758 for (uint32_t i = 0; i < fenceCount; ++i) {
2759 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2760 bool expired = false;
2761
2762 if (fence->temp_syncobj) {
2763 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2764 return VK_TIMEOUT;
2765 continue;
2766 }
2767
2768 if (fence->syncobj) {
2769 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2770 return VK_TIMEOUT;
2771 continue;
2772 }
2773
2774 if (fence->signalled)
2775 continue;
2776
2777 if (!fence->submitted)
2778 return VK_TIMEOUT;
2779
2780 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2781 if (!expired)
2782 return VK_TIMEOUT;
2783
2784 fence->signalled = true;
2785 }
2786
2787 return VK_SUCCESS;
2788 }
2789
2790 VkResult radv_ResetFences(VkDevice _device,
2791 uint32_t fenceCount,
2792 const VkFence *pFences)
2793 {
2794 RADV_FROM_HANDLE(radv_device, device, _device);
2795
2796 for (unsigned i = 0; i < fenceCount; ++i) {
2797 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2798 fence->submitted = fence->signalled = false;
2799
2800 /* Per spec, we first restore the permanent payload, and then reset, so
2801 * having a temp syncobj should not skip resetting the permanent syncobj. */
2802 if (fence->temp_syncobj) {
2803 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2804 fence->temp_syncobj = 0;
2805 }
2806
2807 if (fence->syncobj) {
2808 device->ws->reset_syncobj(device->ws, fence->syncobj);
2809 }
2810 }
2811
2812 return VK_SUCCESS;
2813 }
2814
2815 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2816 {
2817 RADV_FROM_HANDLE(radv_device, device, _device);
2818 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2819
2820 if (fence->temp_syncobj) {
2821 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2822 return success ? VK_SUCCESS : VK_NOT_READY;
2823 }
2824
2825 if (fence->syncobj) {
2826 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2827 return success ? VK_SUCCESS : VK_NOT_READY;
2828 }
2829
2830 if (fence->signalled)
2831 return VK_SUCCESS;
2832 if (!fence->submitted)
2833 return VK_NOT_READY;
2834 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2835 return VK_NOT_READY;
2836
2837 return VK_SUCCESS;
2838 }
2839
2840
2841 // Queue semaphore functions
2842
2843 VkResult radv_CreateSemaphore(
2844 VkDevice _device,
2845 const VkSemaphoreCreateInfo* pCreateInfo,
2846 const VkAllocationCallbacks* pAllocator,
2847 VkSemaphore* pSemaphore)
2848 {
2849 RADV_FROM_HANDLE(radv_device, device, _device);
2850 const VkExportSemaphoreCreateInfoKHR *export =
2851 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2852 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2853 export ? export->handleTypes : 0;
2854
2855 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2856 sizeof(*sem), 8,
2857 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2858 if (!sem)
2859 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2860
2861 sem->temp_syncobj = 0;
2862 /* create a syncobject if we are going to export this semaphore */
2863 if (device->always_use_syncobj || handleTypes) {
2864 assert (device->physical_device->rad_info.has_syncobj);
2865 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2866 if (ret) {
2867 vk_free2(&device->alloc, pAllocator, sem);
2868 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2869 }
2870 sem->sem = NULL;
2871 } else {
2872 sem->sem = device->ws->create_sem(device->ws);
2873 if (!sem->sem) {
2874 vk_free2(&device->alloc, pAllocator, sem);
2875 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2876 }
2877 sem->syncobj = 0;
2878 }
2879
2880 *pSemaphore = radv_semaphore_to_handle(sem);
2881 return VK_SUCCESS;
2882 }
2883
2884 void radv_DestroySemaphore(
2885 VkDevice _device,
2886 VkSemaphore _semaphore,
2887 const VkAllocationCallbacks* pAllocator)
2888 {
2889 RADV_FROM_HANDLE(radv_device, device, _device);
2890 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2891 if (!_semaphore)
2892 return;
2893
2894 if (sem->syncobj)
2895 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2896 else
2897 device->ws->destroy_sem(sem->sem);
2898 vk_free2(&device->alloc, pAllocator, sem);
2899 }
2900
2901 VkResult radv_CreateEvent(
2902 VkDevice _device,
2903 const VkEventCreateInfo* pCreateInfo,
2904 const VkAllocationCallbacks* pAllocator,
2905 VkEvent* pEvent)
2906 {
2907 RADV_FROM_HANDLE(radv_device, device, _device);
2908 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2909 sizeof(*event), 8,
2910 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2911
2912 if (!event)
2913 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2914
2915 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2916 RADEON_DOMAIN_GTT,
2917 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2918 if (!event->bo) {
2919 vk_free2(&device->alloc, pAllocator, event);
2920 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2921 }
2922
2923 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2924
2925 *pEvent = radv_event_to_handle(event);
2926
2927 return VK_SUCCESS;
2928 }
2929
2930 void radv_DestroyEvent(
2931 VkDevice _device,
2932 VkEvent _event,
2933 const VkAllocationCallbacks* pAllocator)
2934 {
2935 RADV_FROM_HANDLE(radv_device, device, _device);
2936 RADV_FROM_HANDLE(radv_event, event, _event);
2937
2938 if (!event)
2939 return;
2940 device->ws->buffer_destroy(event->bo);
2941 vk_free2(&device->alloc, pAllocator, event);
2942 }
2943
2944 VkResult radv_GetEventStatus(
2945 VkDevice _device,
2946 VkEvent _event)
2947 {
2948 RADV_FROM_HANDLE(radv_event, event, _event);
2949
2950 if (*event->map == 1)
2951 return VK_EVENT_SET;
2952 return VK_EVENT_RESET;
2953 }
2954
2955 VkResult radv_SetEvent(
2956 VkDevice _device,
2957 VkEvent _event)
2958 {
2959 RADV_FROM_HANDLE(radv_event, event, _event);
2960 *event->map = 1;
2961
2962 return VK_SUCCESS;
2963 }
2964
2965 VkResult radv_ResetEvent(
2966 VkDevice _device,
2967 VkEvent _event)
2968 {
2969 RADV_FROM_HANDLE(radv_event, event, _event);
2970 *event->map = 0;
2971
2972 return VK_SUCCESS;
2973 }
2974
2975 VkResult radv_CreateBuffer(
2976 VkDevice _device,
2977 const VkBufferCreateInfo* pCreateInfo,
2978 const VkAllocationCallbacks* pAllocator,
2979 VkBuffer* pBuffer)
2980 {
2981 RADV_FROM_HANDLE(radv_device, device, _device);
2982 struct radv_buffer *buffer;
2983
2984 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2985
2986 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2987 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2988 if (buffer == NULL)
2989 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2990
2991 buffer->size = pCreateInfo->size;
2992 buffer->usage = pCreateInfo->usage;
2993 buffer->bo = NULL;
2994 buffer->offset = 0;
2995 buffer->flags = pCreateInfo->flags;
2996
2997 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2998 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2999
3000 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3001 buffer->bo = device->ws->buffer_create(device->ws,
3002 align64(buffer->size, 4096),
3003 4096, 0, RADEON_FLAG_VIRTUAL);
3004 if (!buffer->bo) {
3005 vk_free2(&device->alloc, pAllocator, buffer);
3006 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3007 }
3008 }
3009
3010 *pBuffer = radv_buffer_to_handle(buffer);
3011
3012 return VK_SUCCESS;
3013 }
3014
3015 void radv_DestroyBuffer(
3016 VkDevice _device,
3017 VkBuffer _buffer,
3018 const VkAllocationCallbacks* pAllocator)
3019 {
3020 RADV_FROM_HANDLE(radv_device, device, _device);
3021 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3022
3023 if (!buffer)
3024 return;
3025
3026 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3027 device->ws->buffer_destroy(buffer->bo);
3028
3029 vk_free2(&device->alloc, pAllocator, buffer);
3030 }
3031
3032 static inline unsigned
3033 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3034 {
3035 if (stencil)
3036 return image->surface.u.legacy.stencil_tiling_index[level];
3037 else
3038 return image->surface.u.legacy.tiling_index[level];
3039 }
3040
3041 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3042 {
3043 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3044 }
3045
3046 static void
3047 radv_initialise_color_surface(struct radv_device *device,
3048 struct radv_color_buffer_info *cb,
3049 struct radv_image_view *iview)
3050 {
3051 const struct vk_format_description *desc;
3052 unsigned ntype, format, swap, endian;
3053 unsigned blend_clamp = 0, blend_bypass = 0;
3054 uint64_t va;
3055 const struct radeon_surf *surf = &iview->image->surface;
3056
3057 desc = vk_format_description(iview->vk_format);
3058
3059 memset(cb, 0, sizeof(*cb));
3060
3061 /* Intensity is implemented as Red, so treat it that way. */
3062 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3063
3064 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3065
3066 cb->cb_color_base = va >> 8;
3067
3068 if (device->physical_device->rad_info.chip_class >= GFX9) {
3069 struct gfx9_surf_meta_flags meta;
3070 if (iview->image->dcc_offset)
3071 meta = iview->image->surface.u.gfx9.dcc;
3072 else
3073 meta = iview->image->surface.u.gfx9.cmask;
3074
3075 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3076 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3077 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3078 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3079
3080 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3081 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3082 } else {
3083 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3084 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3085
3086 cb->cb_color_base += level_info->offset >> 8;
3087 if (level_info->mode == RADEON_SURF_MODE_2D)
3088 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3089
3090 pitch_tile_max = level_info->nblk_x / 8 - 1;
3091 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3092 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3093
3094 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3095 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3096 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3097
3098 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3099
3100 if (iview->image->fmask.size) {
3101 if (device->physical_device->rad_info.chip_class >= CIK)
3102 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3103 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3104 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3105 } else {
3106 /* This must be set for fast clear to work without FMASK. */
3107 if (device->physical_device->rad_info.chip_class >= CIK)
3108 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3109 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3110 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3111 }
3112 }
3113
3114 /* CMASK variables */
3115 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3116 va += iview->image->cmask.offset;
3117 cb->cb_color_cmask = va >> 8;
3118
3119 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3120 va += iview->image->dcc_offset;
3121 cb->cb_dcc_base = va >> 8;
3122 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3123
3124 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3125 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3126 S_028C6C_SLICE_MAX(max_slice);
3127
3128 if (iview->image->info.samples > 1) {
3129 unsigned log_samples = util_logbase2(iview->image->info.samples);
3130
3131 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3132 S_028C74_NUM_FRAGMENTS(log_samples);
3133 }
3134
3135 if (iview->image->fmask.size) {
3136 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3137 cb->cb_color_fmask = va >> 8;
3138 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3139 } else {
3140 cb->cb_color_fmask = cb->cb_color_base;
3141 }
3142
3143 ntype = radv_translate_color_numformat(iview->vk_format,
3144 desc,
3145 vk_format_get_first_non_void_channel(iview->vk_format));
3146 format = radv_translate_colorformat(iview->vk_format);
3147 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3148 radv_finishme("Illegal color\n");
3149 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3150 endian = radv_colorformat_endian_swap(format);
3151
3152 /* blend clamp should be set for all NORM/SRGB types */
3153 if (ntype == V_028C70_NUMBER_UNORM ||
3154 ntype == V_028C70_NUMBER_SNORM ||
3155 ntype == V_028C70_NUMBER_SRGB)
3156 blend_clamp = 1;
3157
3158 /* set blend bypass according to docs if SINT/UINT or
3159 8/24 COLOR variants */
3160 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3161 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3162 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3163 blend_clamp = 0;
3164 blend_bypass = 1;
3165 }
3166 #if 0
3167 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3168 (format == V_028C70_COLOR_8 ||
3169 format == V_028C70_COLOR_8_8 ||
3170 format == V_028C70_COLOR_8_8_8_8))
3171 ->color_is_int8 = true;
3172 #endif
3173 cb->cb_color_info = S_028C70_FORMAT(format) |
3174 S_028C70_COMP_SWAP(swap) |
3175 S_028C70_BLEND_CLAMP(blend_clamp) |
3176 S_028C70_BLEND_BYPASS(blend_bypass) |
3177 S_028C70_SIMPLE_FLOAT(1) |
3178 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3179 ntype != V_028C70_NUMBER_SNORM &&
3180 ntype != V_028C70_NUMBER_SRGB &&
3181 format != V_028C70_COLOR_8_24 &&
3182 format != V_028C70_COLOR_24_8) |
3183 S_028C70_NUMBER_TYPE(ntype) |
3184 S_028C70_ENDIAN(endian);
3185 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3186 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3187 if (device->physical_device->rad_info.chip_class == SI) {
3188 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3189 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3190 }
3191 }
3192
3193 if (iview->image->cmask.size &&
3194 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3195 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3196
3197 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3198 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3199
3200 if (device->physical_device->rad_info.chip_class >= VI) {
3201 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3202 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3203 unsigned independent_64b_blocks = 0;
3204 unsigned max_compressed_block_size;
3205
3206 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3207 64 for APU because all of our APUs to date use DIMMs which have
3208 a request granularity size of 64B while all other chips have a
3209 32B request size */
3210 if (!device->physical_device->rad_info.has_dedicated_vram)
3211 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3212
3213 if (iview->image->info.samples > 1) {
3214 if (iview->image->surface.bpe == 1)
3215 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3216 else if (iview->image->surface.bpe == 2)
3217 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3218 }
3219
3220 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3221 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3222 independent_64b_blocks = 1;
3223 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3224 } else
3225 max_compressed_block_size = max_uncompressed_block_size;
3226
3227 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3228 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3229 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3230 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3231 }
3232
3233 /* This must be set for fast clear to work without FMASK. */
3234 if (!iview->image->fmask.size &&
3235 device->physical_device->rad_info.chip_class == SI) {
3236 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3237 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3238 }
3239
3240 if (device->physical_device->rad_info.chip_class >= GFX9) {
3241 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3242 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3243
3244 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3245 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3246 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3247 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3248 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3249 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3250 }
3251 }
3252
3253 static void
3254 radv_initialise_ds_surface(struct radv_device *device,
3255 struct radv_ds_buffer_info *ds,
3256 struct radv_image_view *iview)
3257 {
3258 unsigned level = iview->base_mip;
3259 unsigned format, stencil_format;
3260 uint64_t va, s_offs, z_offs;
3261 bool stencil_only = false;
3262 memset(ds, 0, sizeof(*ds));
3263 switch (iview->image->vk_format) {
3264 case VK_FORMAT_D24_UNORM_S8_UINT:
3265 case VK_FORMAT_X8_D24_UNORM_PACK32:
3266 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3267 ds->offset_scale = 2.0f;
3268 break;
3269 case VK_FORMAT_D16_UNORM:
3270 case VK_FORMAT_D16_UNORM_S8_UINT:
3271 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3272 ds->offset_scale = 4.0f;
3273 break;
3274 case VK_FORMAT_D32_SFLOAT:
3275 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3276 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3277 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3278 ds->offset_scale = 1.0f;
3279 break;
3280 case VK_FORMAT_S8_UINT:
3281 stencil_only = true;
3282 break;
3283 default:
3284 break;
3285 }
3286
3287 format = radv_translate_dbformat(iview->image->vk_format);
3288 stencil_format = iview->image->surface.has_stencil ?
3289 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3290
3291 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3292 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3293 S_028008_SLICE_MAX(max_slice);
3294
3295 ds->db_htile_data_base = 0;
3296 ds->db_htile_surface = 0;
3297
3298 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3299 s_offs = z_offs = va;
3300
3301 if (device->physical_device->rad_info.chip_class >= GFX9) {
3302 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3303 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3304
3305 ds->db_z_info = S_028038_FORMAT(format) |
3306 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3307 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3308 S_028038_MAXMIP(iview->image->info.levels - 1);
3309 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3310 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3311
3312 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3313 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3314 ds->db_depth_view |= S_028008_MIPID(level);
3315
3316 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3317 S_02801C_Y_MAX(iview->image->info.height - 1);
3318
3319 if (radv_htile_enabled(iview->image, level)) {
3320 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3321
3322 if (iview->image->tc_compatible_htile) {
3323 unsigned max_zplanes = 4;
3324
3325 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3326 iview->image->info.samples > 1)
3327 max_zplanes = 2;
3328
3329 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3330 S_028038_ITERATE_FLUSH(1);
3331 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3332 }
3333
3334 if (!iview->image->surface.has_stencil)
3335 /* Use all of the htile_buffer for depth if there's no stencil. */
3336 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3337 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3338 iview->image->htile_offset;
3339 ds->db_htile_data_base = va >> 8;
3340 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3341 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3342 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3343 }
3344 } else {
3345 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3346
3347 if (stencil_only)
3348 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3349
3350 z_offs += iview->image->surface.u.legacy.level[level].offset;
3351 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3352
3353 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3354 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3355 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3356
3357 if (iview->image->info.samples > 1)
3358 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3359
3360 if (device->physical_device->rad_info.chip_class >= CIK) {
3361 struct radeon_info *info = &device->physical_device->rad_info;
3362 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3363 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3364 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3365 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3366 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3367 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3368
3369 if (stencil_only)
3370 tile_mode = stencil_tile_mode;
3371
3372 ds->db_depth_info |=
3373 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3374 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3375 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3376 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3377 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3378 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3379 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3380 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3381 } else {
3382 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3383 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3384 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3385 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3386 if (stencil_only)
3387 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3388 }
3389
3390 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3391 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3392 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3393
3394 if (radv_htile_enabled(iview->image, level)) {
3395 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3396
3397 if (!iview->image->surface.has_stencil &&
3398 !iview->image->tc_compatible_htile)
3399 /* Use all of the htile_buffer for depth if there's no stencil. */
3400 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3401
3402 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3403 iview->image->htile_offset;
3404 ds->db_htile_data_base = va >> 8;
3405 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3406
3407 if (iview->image->tc_compatible_htile) {
3408 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3409
3410 if (iview->image->info.samples <= 1)
3411 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3412 else if (iview->image->info.samples <= 4)
3413 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3414 else
3415 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3416 }
3417 }
3418 }
3419
3420 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3421 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3422 }
3423
3424 VkResult radv_CreateFramebuffer(
3425 VkDevice _device,
3426 const VkFramebufferCreateInfo* pCreateInfo,
3427 const VkAllocationCallbacks* pAllocator,
3428 VkFramebuffer* pFramebuffer)
3429 {
3430 RADV_FROM_HANDLE(radv_device, device, _device);
3431 struct radv_framebuffer *framebuffer;
3432
3433 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3434
3435 size_t size = sizeof(*framebuffer) +
3436 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3437 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3438 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3439 if (framebuffer == NULL)
3440 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3441
3442 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3443 framebuffer->width = pCreateInfo->width;
3444 framebuffer->height = pCreateInfo->height;
3445 framebuffer->layers = pCreateInfo->layers;
3446 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3447 VkImageView _iview = pCreateInfo->pAttachments[i];
3448 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3449 framebuffer->attachments[i].attachment = iview;
3450 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3451 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3452 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3453 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3454 }
3455 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3456 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3457 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3458 }
3459
3460 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3461 return VK_SUCCESS;
3462 }
3463
3464 void radv_DestroyFramebuffer(
3465 VkDevice _device,
3466 VkFramebuffer _fb,
3467 const VkAllocationCallbacks* pAllocator)
3468 {
3469 RADV_FROM_HANDLE(radv_device, device, _device);
3470 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3471
3472 if (!fb)
3473 return;
3474 vk_free2(&device->alloc, pAllocator, fb);
3475 }
3476
3477 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3478 {
3479 switch (address_mode) {
3480 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3481 return V_008F30_SQ_TEX_WRAP;
3482 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3483 return V_008F30_SQ_TEX_MIRROR;
3484 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3485 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3486 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3487 return V_008F30_SQ_TEX_CLAMP_BORDER;
3488 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3489 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3490 default:
3491 unreachable("illegal tex wrap mode");
3492 break;
3493 }
3494 }
3495
3496 static unsigned
3497 radv_tex_compare(VkCompareOp op)
3498 {
3499 switch (op) {
3500 case VK_COMPARE_OP_NEVER:
3501 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3502 case VK_COMPARE_OP_LESS:
3503 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3504 case VK_COMPARE_OP_EQUAL:
3505 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3506 case VK_COMPARE_OP_LESS_OR_EQUAL:
3507 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3508 case VK_COMPARE_OP_GREATER:
3509 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3510 case VK_COMPARE_OP_NOT_EQUAL:
3511 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3512 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3513 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3514 case VK_COMPARE_OP_ALWAYS:
3515 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3516 default:
3517 unreachable("illegal compare mode");
3518 break;
3519 }
3520 }
3521
3522 static unsigned
3523 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3524 {
3525 switch (filter) {
3526 case VK_FILTER_NEAREST:
3527 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3528 V_008F38_SQ_TEX_XY_FILTER_POINT);
3529 case VK_FILTER_LINEAR:
3530 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3531 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3532 case VK_FILTER_CUBIC_IMG:
3533 default:
3534 fprintf(stderr, "illegal texture filter");
3535 return 0;
3536 }
3537 }
3538
3539 static unsigned
3540 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3541 {
3542 switch (mode) {
3543 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3544 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3545 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3546 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3547 default:
3548 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3549 }
3550 }
3551
3552 static unsigned
3553 radv_tex_bordercolor(VkBorderColor bcolor)
3554 {
3555 switch (bcolor) {
3556 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3557 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3558 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3559 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3560 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3561 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3562 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3563 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3564 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3565 default:
3566 break;
3567 }
3568 return 0;
3569 }
3570
3571 static unsigned
3572 radv_tex_aniso_filter(unsigned filter)
3573 {
3574 if (filter < 2)
3575 return 0;
3576 if (filter < 4)
3577 return 1;
3578 if (filter < 8)
3579 return 2;
3580 if (filter < 16)
3581 return 3;
3582 return 4;
3583 }
3584
3585 static void
3586 radv_init_sampler(struct radv_device *device,
3587 struct radv_sampler *sampler,
3588 const VkSamplerCreateInfo *pCreateInfo)
3589 {
3590 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3591 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3592 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3593 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3594
3595 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3596 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3597 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3598 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3599 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3600 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3601 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3602 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3603 S_008F30_DISABLE_CUBE_WRAP(0) |
3604 S_008F30_COMPAT_MODE(is_vi));
3605 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3606 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3607 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3608 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3609 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3610 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3611 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3612 S_008F38_MIP_POINT_PRECLAMP(0) |
3613 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3614 S_008F38_FILTER_PREC_FIX(1) |
3615 S_008F38_ANISO_OVERRIDE(is_vi));
3616 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3617 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3618 }
3619
3620 VkResult radv_CreateSampler(
3621 VkDevice _device,
3622 const VkSamplerCreateInfo* pCreateInfo,
3623 const VkAllocationCallbacks* pAllocator,
3624 VkSampler* pSampler)
3625 {
3626 RADV_FROM_HANDLE(radv_device, device, _device);
3627 struct radv_sampler *sampler;
3628
3629 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3630
3631 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3632 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3633 if (!sampler)
3634 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3635
3636 radv_init_sampler(device, sampler, pCreateInfo);
3637 *pSampler = radv_sampler_to_handle(sampler);
3638
3639 return VK_SUCCESS;
3640 }
3641
3642 void radv_DestroySampler(
3643 VkDevice _device,
3644 VkSampler _sampler,
3645 const VkAllocationCallbacks* pAllocator)
3646 {
3647 RADV_FROM_HANDLE(radv_device, device, _device);
3648 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3649
3650 if (!sampler)
3651 return;
3652 vk_free2(&device->alloc, pAllocator, sampler);
3653 }
3654
3655 /* vk_icd.h does not declare this function, so we declare it here to
3656 * suppress Wmissing-prototypes.
3657 */
3658 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3659 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3660
3661 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3662 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3663 {
3664 /* For the full details on loader interface versioning, see
3665 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3666 * What follows is a condensed summary, to help you navigate the large and
3667 * confusing official doc.
3668 *
3669 * - Loader interface v0 is incompatible with later versions. We don't
3670 * support it.
3671 *
3672 * - In loader interface v1:
3673 * - The first ICD entrypoint called by the loader is
3674 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3675 * entrypoint.
3676 * - The ICD must statically expose no other Vulkan symbol unless it is
3677 * linked with -Bsymbolic.
3678 * - Each dispatchable Vulkan handle created by the ICD must be
3679 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3680 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3681 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3682 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3683 * such loader-managed surfaces.
3684 *
3685 * - Loader interface v2 differs from v1 in:
3686 * - The first ICD entrypoint called by the loader is
3687 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3688 * statically expose this entrypoint.
3689 *
3690 * - Loader interface v3 differs from v2 in:
3691 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3692 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3693 * because the loader no longer does so.
3694 */
3695 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3696 return VK_SUCCESS;
3697 }
3698
3699 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3700 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3701 int *pFD)
3702 {
3703 RADV_FROM_HANDLE(radv_device, device, _device);
3704 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3705
3706 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3707
3708 /* At the moment, we support only the below handle types. */
3709 assert(pGetFdInfo->handleType ==
3710 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3711 pGetFdInfo->handleType ==
3712 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3713
3714 bool ret = radv_get_memory_fd(device, memory, pFD);
3715 if (ret == false)
3716 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3717 return VK_SUCCESS;
3718 }
3719
3720 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3721 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3722 int fd,
3723 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3724 {
3725 switch (handleType) {
3726 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3727 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3728 return VK_SUCCESS;
3729
3730 default:
3731 /* The valid usage section for this function says:
3732 *
3733 * "handleType must not be one of the handle types defined as
3734 * opaque."
3735 *
3736 * So opaque handle types fall into the default "unsupported" case.
3737 */
3738 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3739 }
3740 }
3741
3742 static VkResult radv_import_opaque_fd(struct radv_device *device,
3743 int fd,
3744 uint32_t *syncobj)
3745 {
3746 uint32_t syncobj_handle = 0;
3747 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3748 if (ret != 0)
3749 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3750
3751 if (*syncobj)
3752 device->ws->destroy_syncobj(device->ws, *syncobj);
3753
3754 *syncobj = syncobj_handle;
3755 close(fd);
3756
3757 return VK_SUCCESS;
3758 }
3759
3760 static VkResult radv_import_sync_fd(struct radv_device *device,
3761 int fd,
3762 uint32_t *syncobj)
3763 {
3764 /* If we create a syncobj we do it locally so that if we have an error, we don't
3765 * leave a syncobj in an undetermined state in the fence. */
3766 uint32_t syncobj_handle = *syncobj;
3767 if (!syncobj_handle) {
3768 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3769 if (ret) {
3770 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3771 }
3772 }
3773
3774 if (fd == -1) {
3775 device->ws->signal_syncobj(device->ws, syncobj_handle);
3776 } else {
3777 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3778 if (ret != 0)
3779 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3780 }
3781
3782 *syncobj = syncobj_handle;
3783 if (fd != -1)
3784 close(fd);
3785
3786 return VK_SUCCESS;
3787 }
3788
3789 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3790 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3791 {
3792 RADV_FROM_HANDLE(radv_device, device, _device);
3793 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3794 uint32_t *syncobj_dst = NULL;
3795
3796 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3797 syncobj_dst = &sem->temp_syncobj;
3798 } else {
3799 syncobj_dst = &sem->syncobj;
3800 }
3801
3802 switch(pImportSemaphoreFdInfo->handleType) {
3803 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3804 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3805 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3806 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3807 default:
3808 unreachable("Unhandled semaphore handle type");
3809 }
3810 }
3811
3812 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3813 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3814 int *pFd)
3815 {
3816 RADV_FROM_HANDLE(radv_device, device, _device);
3817 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3818 int ret;
3819 uint32_t syncobj_handle;
3820
3821 if (sem->temp_syncobj)
3822 syncobj_handle = sem->temp_syncobj;
3823 else
3824 syncobj_handle = sem->syncobj;
3825
3826 switch(pGetFdInfo->handleType) {
3827 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3828 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3829 break;
3830 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3831 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3832 if (!ret) {
3833 if (sem->temp_syncobj) {
3834 close (sem->temp_syncobj);
3835 sem->temp_syncobj = 0;
3836 } else {
3837 device->ws->reset_syncobj(device->ws, syncobj_handle);
3838 }
3839 }
3840 break;
3841 default:
3842 unreachable("Unhandled semaphore handle type");
3843 }
3844
3845 if (ret)
3846 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3847 return VK_SUCCESS;
3848 }
3849
3850 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3851 VkPhysicalDevice physicalDevice,
3852 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3853 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3854 {
3855 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3856
3857 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3858 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3859 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3860 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3861 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3862 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3863 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3864 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3865 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3866 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3867 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3868 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3869 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3870 } else {
3871 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3872 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3873 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3874 }
3875 }
3876
3877 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3878 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3879 {
3880 RADV_FROM_HANDLE(radv_device, device, _device);
3881 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3882 uint32_t *syncobj_dst = NULL;
3883
3884
3885 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3886 syncobj_dst = &fence->temp_syncobj;
3887 } else {
3888 syncobj_dst = &fence->syncobj;
3889 }
3890
3891 switch(pImportFenceFdInfo->handleType) {
3892 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3893 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3894 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3895 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3896 default:
3897 unreachable("Unhandled fence handle type");
3898 }
3899 }
3900
3901 VkResult radv_GetFenceFdKHR(VkDevice _device,
3902 const VkFenceGetFdInfoKHR *pGetFdInfo,
3903 int *pFd)
3904 {
3905 RADV_FROM_HANDLE(radv_device, device, _device);
3906 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3907 int ret;
3908 uint32_t syncobj_handle;
3909
3910 if (fence->temp_syncobj)
3911 syncobj_handle = fence->temp_syncobj;
3912 else
3913 syncobj_handle = fence->syncobj;
3914
3915 switch(pGetFdInfo->handleType) {
3916 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3917 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3918 break;
3919 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3920 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3921 if (!ret) {
3922 if (fence->temp_syncobj) {
3923 close (fence->temp_syncobj);
3924 fence->temp_syncobj = 0;
3925 } else {
3926 device->ws->reset_syncobj(device->ws, syncobj_handle);
3927 }
3928 }
3929 break;
3930 default:
3931 unreachable("Unhandled fence handle type");
3932 }
3933
3934 if (ret)
3935 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3936 return VK_SUCCESS;
3937 }
3938
3939 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3940 VkPhysicalDevice physicalDevice,
3941 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
3942 VkExternalFencePropertiesKHR* pExternalFenceProperties)
3943 {
3944 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3945
3946 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3947 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3948 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3949 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3950 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3951 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
3952 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3953 } else {
3954 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
3955 pExternalFenceProperties->compatibleHandleTypes = 0;
3956 pExternalFenceProperties->externalFenceFeatures = 0;
3957 }
3958 }
3959
3960 VkResult
3961 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
3962 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
3963 const VkAllocationCallbacks* pAllocator,
3964 VkDebugReportCallbackEXT* pCallback)
3965 {
3966 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3967 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
3968 pCreateInfo, pAllocator, &instance->alloc,
3969 pCallback);
3970 }
3971
3972 void
3973 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
3974 VkDebugReportCallbackEXT _callback,
3975 const VkAllocationCallbacks* pAllocator)
3976 {
3977 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3978 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
3979 _callback, pAllocator, &instance->alloc);
3980 }
3981
3982 void
3983 radv_DebugReportMessageEXT(VkInstance _instance,
3984 VkDebugReportFlagsEXT flags,
3985 VkDebugReportObjectTypeEXT objectType,
3986 uint64_t object,
3987 size_t location,
3988 int32_t messageCode,
3989 const char* pLayerPrefix,
3990 const char* pMessage)
3991 {
3992 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3993 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
3994 object, location, messageCode, pLayerPrefix, pMessage);
3995 }