projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: implement VK_EXT_conservative_rasterization
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static bool
53 radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
54 {
55 uint32_t timestamp;
56
57 #ifdef HAVE_DL_ITERATE_PHDR
58 const struct build_id_note *note = NULL;
59 if ((note = build_id_find_nhdr_for_addr(ptr))) {
60 _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
61 } else
62 #endif
63 if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
64 if (!timestamp) {
65 fprintf(stderr, "radv: The provided filesystem timestamp for the cache is bogus!\n");
66 }
67
68 _mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
69 } else
70 return false;
71 return true;
72 }
73
74 static int
75 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
76 {
77 struct mesa_sha1 ctx;
78 unsigned char sha1[20];
79 unsigned ptr_size = sizeof(void*);
80 memset(uuid, 0, VK_UUID_SIZE);
81
82 if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
83 !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
84 return -1;
85
86 _mesa_sha1_update(&ctx, &family, sizeof(family));
87 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
88 _mesa_sha1_final(&ctx, sha1);
89
90 memcpy(uuid, sha1, VK_UUID_SIZE);
91 return 0;
92 }
93
94 static void
95 radv_get_driver_uuid(void *uuid)
96 {
97 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
98 }
99
100 static void
101 radv_get_device_uuid(struct radeon_info *info, void *uuid)
102 {
103 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
104 }
105
106 static void
107 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
108 {
109 const char *chip_string;
110 char llvm_string[32] = {};
111
112 switch (family) {
113 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
114 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
115 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
116 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
117 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
118 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
119 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
120 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
121 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
122 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
123 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
124 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
125 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
126 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
127 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
128 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
129 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
130 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
131 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
132 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
133 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
134 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
135 default: chip_string = "AMD RADV unknown"; break;
136 }
137
138 snprintf(llvm_string, sizeof(llvm_string),
139 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
140 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
141 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
142 }
143
144 static void
145 radv_physical_device_init_mem_types(struct radv_physical_device *device)
146 {
147 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
148 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
149 device->rad_info.vram_vis_size);
150
151 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
152 device->memory_properties.memoryHeapCount = 0;
153 if (device->rad_info.vram_size - visible_vram_size > 0) {
154 vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
156 .size = device->rad_info.vram_size - visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (visible_vram_size) {
161 visible_vram_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
163 .size = visible_vram_size,
164 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
172 };
173 }
174
175 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
176 unsigned type_count = 0;
177 if (vram_index >= 0) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
181 .heapIndex = vram_index,
182 };
183 }
184 if (gart_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
189 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
190 .heapIndex = gart_index,
191 };
192 }
193 if (visible_vram_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
197 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
199 .heapIndex = visible_vram_index,
200 };
201 }
202 if (gart_index >= 0) {
203 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
204 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
205 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
206 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
207 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
208 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
209 .heapIndex = gart_index,
210 };
211 }
212 device->memory_properties.memoryTypeCount = type_count;
213 }
214
215 static void
216 radv_handle_env_var_force_family(struct radv_physical_device *device)
217 {
218 const char *family = getenv("RADV_FORCE_FAMILY");
219 unsigned i;
220
221 if (!family)
222 return;
223
224 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
225 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
226 /* Override family and chip_class. */
227 device->rad_info.family = i;
228
229 if (i >= CHIP_VEGA10)
230 device->rad_info.chip_class = GFX9;
231 else if (i >= CHIP_TONGA)
232 device->rad_info.chip_class = VI;
233 else if (i >= CHIP_BONAIRE)
234 device->rad_info.chip_class = CIK;
235 else
236 device->rad_info.chip_class = SI;
237
238 return;
239 }
240 }
241
242 fprintf(stderr, "radv: Unknown family: %s\n", family);
243 exit(1);
244 }
245
246 static VkResult
247 radv_physical_device_init(struct radv_physical_device *device,
248 struct radv_instance *instance,
249 drmDevicePtr drm_device)
250 {
251 const char *path = drm_device->nodes[DRM_NODE_RENDER];
252 VkResult result;
253 drmVersionPtr version;
254 int fd;
255 int master_fd = -1;
256
257 fd = open(path, O_RDWR | O_CLOEXEC);
258 if (fd < 0) {
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not open device '%s'", path);
261
262 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
263 }
264
265 version = drmGetVersion(fd);
266 if (!version) {
267 close(fd);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Could not get the kernel driver version for device '%s'", path);
271
272 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
273 "failed to get version %s: %m", path);
274 }
275
276 if (strcmp(version->name, "amdgpu")) {
277 drmFreeVersion(version);
278 if (master_fd != -1)
279 close(master_fd);
280 close(fd);
281
282 if (instance->debug_flags & RADV_DEBUG_STARTUP)
283 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
284
285 return VK_ERROR_INCOMPATIBLE_DRIVER;
286 }
287 drmFreeVersion(version);
288
289 if (instance->debug_flags & RADV_DEBUG_STARTUP)
290 radv_logi("Found compatible device '%s'.", path);
291
292 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
293 device->instance = instance;
294 assert(strlen(path) < ARRAY_SIZE(device->path));
295 strncpy(device->path, path, ARRAY_SIZE(device->path));
296
297 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
298 instance->perftest_flags);
299 if (!device->ws) {
300 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
301 goto fail;
302 }
303
304 if (instance->enabled_extensions.KHR_display) {
305 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
306 if (master_fd >= 0) {
307 uint32_t accel_working = 0;
308 struct drm_amdgpu_info request = {
309 .return_pointer = (uintptr_t)&accel_working,
310 .return_size = sizeof(accel_working),
311 .query = AMDGPU_INFO_ACCEL_WORKING
312 };
313
314 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
315 close(master_fd);
316 master_fd = -1;
317 }
318 }
319 }
320
321 device->master_fd = master_fd;
322 device->local_fd = fd;
323 device->ws->query_info(device->ws, &device->rad_info);
324
325 radv_handle_env_var_force_family(device);
326
327 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
328
329 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
330 device->ws->destroy(device->ws);
331 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
332 "cannot generate UUID");
333 goto fail;
334 }
335
336 /* These flags affect shader compilation. */
337 uint64_t shader_env_flags =
338 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
339 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
340
341 /* The gpu id is already embedded in the uuid so we just pass "radv"
342 * when creating the cache.
343 */
344 char buf[VK_UUID_SIZE * 2 + 1];
345 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
346 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
347
348 if (device->rad_info.chip_class < VI ||
349 device->rad_info.chip_class > GFX9)
350 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
351
352 radv_get_driver_uuid(&device->device_uuid);
353 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
354
355 if (device->rad_info.family == CHIP_STONEY ||
356 device->rad_info.chip_class >= GFX9) {
357 device->has_rbplus = true;
358 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
359 device->rad_info.family == CHIP_VEGA12 ||
360 device->rad_info.family == CHIP_RAVEN;
361 }
362
363 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
364 * on SI.
365 */
366 device->has_clear_state = device->rad_info.chip_class >= CIK;
367
368 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
369
370 /* Vega10/Raven need a special workaround for a hardware bug. */
371 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
372 device->rad_info.family == CHIP_RAVEN;
373
374 /* Out-of-order primitive rasterization. */
375 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
376 device->rad_info.max_se >= 2;
377 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
378 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
379
380 device->dcc_msaa_allowed =
381 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
382
383 radv_physical_device_init_mem_types(device);
384 radv_fill_device_extension_table(device, &device->supported_extensions);
385
386 result = radv_init_wsi(device);
387 if (result != VK_SUCCESS) {
388 device->ws->destroy(device->ws);
389 vk_error(instance, result);
390 goto fail;
391 }
392
393 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
394 ac_print_gpu_info(&device->rad_info);
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"binning", RADV_PERFTEST_BINNING},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 radv_EnumerateInstanceVersion(&client_version);
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
743 pdevice->rad_info.family == CHIP_STONEY,
744 .textureCompressionASTC_LDR = false,
745 .textureCompressionBC = true,
746 .occlusionQueryPrecise = true,
747 .pipelineStatisticsQuery = true,
748 .vertexPipelineStoresAndAtomics = true,
749 .fragmentStoresAndAtomics = true,
750 .shaderTessellationAndGeometryPointSize = true,
751 .shaderImageGatherExtended = true,
752 .shaderStorageImageExtendedFormats = true,
753 .shaderStorageImageMultisample = false,
754 .shaderUniformBufferArrayDynamicIndexing = true,
755 .shaderSampledImageArrayDynamicIndexing = true,
756 .shaderStorageBufferArrayDynamicIndexing = true,
757 .shaderStorageImageArrayDynamicIndexing = true,
758 .shaderStorageImageReadWithoutFormat = true,
759 .shaderStorageImageWriteWithoutFormat = true,
760 .shaderClipDistance = true,
761 .shaderCullDistance = true,
762 .shaderFloat64 = true,
763 .shaderInt64 = true,
764 .shaderInt16 = true,
765 .sparseBinding = true,
766 .variableMultisampleRate = true,
767 .inheritedQueries = true,
768 };
769 }
770
771 void radv_GetPhysicalDeviceFeatures2(
772 VkPhysicalDevice physicalDevice,
773 VkPhysicalDeviceFeatures2KHR *pFeatures)
774 {
775 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
776 vk_foreach_struct(ext, pFeatures->pNext) {
777 switch (ext->sType) {
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
779 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
780 features->variablePointersStorageBuffer = true;
781 features->variablePointers = false;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
785 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
786 features->multiview = true;
787 features->multiviewGeometryShader = true;
788 features->multiviewTessellationShader = true;
789 break;
790 }
791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
792 VkPhysicalDeviceShaderDrawParameterFeatures *features =
793 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
794 features->shaderDrawParameters = true;
795 break;
796 }
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
798 VkPhysicalDeviceProtectedMemoryFeatures *features =
799 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
800 features->protectedMemory = false;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
804 VkPhysicalDevice16BitStorageFeatures *features =
805 (VkPhysicalDevice16BitStorageFeatures*)ext;
806 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
807 features->storageBuffer16BitAccess = enabled;
808 features->uniformAndStorageBuffer16BitAccess = enabled;
809 features->storagePushConstant16 = enabled;
810 features->storageInputOutput16 = enabled;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
814 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
815 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
816 features->samplerYcbcrConversion = false;
817 break;
818 }
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
820 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
821 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
822 features->shaderInputAttachmentArrayDynamicIndexing = true;
823 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
824 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
825 features->shaderUniformBufferArrayNonUniformIndexing = false;
826 features->shaderSampledImageArrayNonUniformIndexing = false;
827 features->shaderStorageBufferArrayNonUniformIndexing = false;
828 features->shaderStorageImageArrayNonUniformIndexing = false;
829 features->shaderInputAttachmentArrayNonUniformIndexing = false;
830 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
831 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
832 features->descriptorBindingUniformBufferUpdateAfterBind = true;
833 features->descriptorBindingSampledImageUpdateAfterBind = true;
834 features->descriptorBindingStorageImageUpdateAfterBind = true;
835 features->descriptorBindingStorageBufferUpdateAfterBind = true;
836 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
838 features->descriptorBindingUpdateUnusedWhilePending = true;
839 features->descriptorBindingPartiallyBound = true;
840 features->descriptorBindingVariableDescriptorCount = true;
841 features->runtimeDescriptorArray = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
845 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
846 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
847 features->conditionalRendering = true;
848 features->inheritedConditionalRendering = false;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
852 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
853 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
854 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
855 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
856 break;
857 }
858 default:
859 break;
860 }
861 }
862 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
863 }
864
865 void radv_GetPhysicalDeviceProperties(
866 VkPhysicalDevice physicalDevice,
867 VkPhysicalDeviceProperties* pProperties)
868 {
869 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
870 VkSampleCountFlags sample_counts = 0xf;
871
872 /* make sure that the entire descriptor set is addressable with a signed
873 * 32-bit int. So the sum of all limits scaled by descriptor size has to
874 * be at most 2 GiB. the combined image & samples object count as one of
875 * both. This limit is for the pipeline layout, not for the set layout, but
876 * there is no set limit, so we just set a pipeline limit. I don't think
877 * any app is going to hit this soon. */
878 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
879 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
880 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
881 32 /* sampler, largest when combined with image */ +
882 64 /* sampled image */ +
883 64 /* storage image */);
884
885 VkPhysicalDeviceLimits limits = {
886 .maxImageDimension1D = (1 << 14),
887 .maxImageDimension2D = (1 << 14),
888 .maxImageDimension3D = (1 << 11),
889 .maxImageDimensionCube = (1 << 14),
890 .maxImageArrayLayers = (1 << 11),
891 .maxTexelBufferElements = 128 * 1024 * 1024,
892 .maxUniformBufferRange = UINT32_MAX,
893 .maxStorageBufferRange = UINT32_MAX,
894 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
895 .maxMemoryAllocationCount = UINT32_MAX,
896 .maxSamplerAllocationCount = 64 * 1024,
897 .bufferImageGranularity = 64, /* A cache line */
898 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
899 .maxBoundDescriptorSets = MAX_SETS,
900 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
901 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
902 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
903 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
904 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
905 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
906 .maxPerStageResources = max_descriptor_set_size,
907 .maxDescriptorSetSamplers = max_descriptor_set_size,
908 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
909 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
910 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
911 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
912 .maxDescriptorSetSampledImages = max_descriptor_set_size,
913 .maxDescriptorSetStorageImages = max_descriptor_set_size,
914 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
915 .maxVertexInputAttributes = 32,
916 .maxVertexInputBindings = 32,
917 .maxVertexInputAttributeOffset = 2047,
918 .maxVertexInputBindingStride = 2048,
919 .maxVertexOutputComponents = 128,
920 .maxTessellationGenerationLevel = 64,
921 .maxTessellationPatchSize = 32,
922 .maxTessellationControlPerVertexInputComponents = 128,
923 .maxTessellationControlPerVertexOutputComponents = 128,
924 .maxTessellationControlPerPatchOutputComponents = 120,
925 .maxTessellationControlTotalOutputComponents = 4096,
926 .maxTessellationEvaluationInputComponents = 128,
927 .maxTessellationEvaluationOutputComponents = 128,
928 .maxGeometryShaderInvocations = 127,
929 .maxGeometryInputComponents = 64,
930 .maxGeometryOutputComponents = 128,
931 .maxGeometryOutputVertices = 256,
932 .maxGeometryTotalOutputComponents = 1024,
933 .maxFragmentInputComponents = 128,
934 .maxFragmentOutputAttachments = 8,
935 .maxFragmentDualSrcAttachments = 1,
936 .maxFragmentCombinedOutputResources = 8,
937 .maxComputeSharedMemorySize = 32768,
938 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
939 .maxComputeWorkGroupInvocations = 2048,
940 .maxComputeWorkGroupSize = {
941 2048,
942 2048,
943 2048
944 },
945 .subPixelPrecisionBits = 4 /* FIXME */,
946 .subTexelPrecisionBits = 4 /* FIXME */,
947 .mipmapPrecisionBits = 4 /* FIXME */,
948 .maxDrawIndexedIndexValue = UINT32_MAX,
949 .maxDrawIndirectCount = UINT32_MAX,
950 .maxSamplerLodBias = 16,
951 .maxSamplerAnisotropy = 16,
952 .maxViewports = MAX_VIEWPORTS,
953 .maxViewportDimensions = { (1 << 14), (1 << 14) },
954 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
955 .viewportSubPixelBits = 8,
956 .minMemoryMapAlignment = 4096, /* A page */
957 .minTexelBufferOffsetAlignment = 1,
958 .minUniformBufferOffsetAlignment = 4,
959 .minStorageBufferOffsetAlignment = 4,
960 .minTexelOffset = -32,
961 .maxTexelOffset = 31,
962 .minTexelGatherOffset = -32,
963 .maxTexelGatherOffset = 31,
964 .minInterpolationOffset = -2,
965 .maxInterpolationOffset = 2,
966 .subPixelInterpolationOffsetBits = 8,
967 .maxFramebufferWidth = (1 << 14),
968 .maxFramebufferHeight = (1 << 14),
969 .maxFramebufferLayers = (1 << 10),
970 .framebufferColorSampleCounts = sample_counts,
971 .framebufferDepthSampleCounts = sample_counts,
972 .framebufferStencilSampleCounts = sample_counts,
973 .framebufferNoAttachmentsSampleCounts = sample_counts,
974 .maxColorAttachments = MAX_RTS,
975 .sampledImageColorSampleCounts = sample_counts,
976 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
977 .sampledImageDepthSampleCounts = sample_counts,
978 .sampledImageStencilSampleCounts = sample_counts,
979 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
980 .maxSampleMaskWords = 1,
981 .timestampComputeAndGraphics = true,
982 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
983 .maxClipDistances = 8,
984 .maxCullDistances = 8,
985 .maxCombinedClipAndCullDistances = 8,
986 .discreteQueuePriorities = 1,
987 .pointSizeRange = { 0.125, 255.875 },
988 .lineWidthRange = { 0.0, 7.9921875 },
989 .pointSizeGranularity = (1.0 / 8.0),
990 .lineWidthGranularity = (1.0 / 128.0),
991 .strictLines = false, /* FINISHME */
992 .standardSampleLocations = true,
993 .optimalBufferCopyOffsetAlignment = 128,
994 .optimalBufferCopyRowPitchAlignment = 128,
995 .nonCoherentAtomSize = 64,
996 };
997
998 *pProperties = (VkPhysicalDeviceProperties) {
999 .apiVersion = radv_physical_device_api_version(pdevice),
1000 .driverVersion = vk_get_driver_version(),
1001 .vendorID = ATI_VENDOR_ID,
1002 .deviceID = pdevice->rad_info.pci_id,
1003 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1004 .limits = limits,
1005 .sparseProperties = {0},
1006 };
1007
1008 strcpy(pProperties->deviceName, pdevice->name);
1009 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1010 }
1011
1012 void radv_GetPhysicalDeviceProperties2(
1013 VkPhysicalDevice physicalDevice,
1014 VkPhysicalDeviceProperties2KHR *pProperties)
1015 {
1016 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1017 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1018
1019 vk_foreach_struct(ext, pProperties->pNext) {
1020 switch (ext->sType) {
1021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1022 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1023 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1024 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1028 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1029 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1030 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1031 properties->deviceLUIDValid = false;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1035 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1036 properties->maxMultiviewViewCount = MAX_VIEWS;
1037 properties->maxMultiviewInstanceIndex = INT_MAX;
1038 break;
1039 }
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1041 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1042 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1043 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1044 break;
1045 }
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1047 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1048 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1049 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1050 break;
1051 }
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1053 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1054 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1055 properties->minImportedHostPointerAlignment = 4096;
1056 break;
1057 }
1058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1059 VkPhysicalDeviceSubgroupProperties *properties =
1060 (VkPhysicalDeviceSubgroupProperties*)ext;
1061 properties->subgroupSize = 64;
1062 properties->supportedStages = VK_SHADER_STAGE_ALL;
1063 properties->supportedOperations =
1064 VK_SUBGROUP_FEATURE_BASIC_BIT |
1065 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1066 VK_SUBGROUP_FEATURE_QUAD_BIT |
1067 VK_SUBGROUP_FEATURE_VOTE_BIT;
1068 if (pdevice->rad_info.chip_class >= VI) {
1069 properties->supportedOperations |=
1070 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1071 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1072 }
1073 properties->quadOperationsInAllStages = true;
1074 break;
1075 }
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1077 VkPhysicalDeviceMaintenance3Properties *properties =
1078 (VkPhysicalDeviceMaintenance3Properties*)ext;
1079 /* Make sure everything is addressable by a signed 32-bit int, and
1080 * our largest descriptors are 96 bytes. */
1081 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1082 /* Our buffer size fields allow only this much */
1083 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1084 break;
1085 }
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1087 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1088 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1089 /* GFX6-8 only support single channel min/max filter. */
1090 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1091 properties->filterMinmaxSingleComponentFormats = true;
1092 break;
1093 }
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1095 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1096 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1097
1098 /* Shader engines. */
1099 properties->shaderEngineCount =
1100 pdevice->rad_info.max_se;
1101 properties->shaderArraysPerEngineCount =
1102 pdevice->rad_info.max_sh_per_se;
1103 properties->computeUnitsPerShaderArray =
1104 pdevice->rad_info.num_good_compute_units /
1105 (pdevice->rad_info.max_se *
1106 pdevice->rad_info.max_sh_per_se);
1107 properties->simdPerComputeUnit = 4;
1108 properties->wavefrontsPerSimd =
1109 pdevice->rad_info.family == CHIP_TONGA ||
1110 pdevice->rad_info.family == CHIP_ICELAND ||
1111 pdevice->rad_info.family == CHIP_POLARIS10 ||
1112 pdevice->rad_info.family == CHIP_POLARIS11 ||
1113 pdevice->rad_info.family == CHIP_POLARIS12 ||
1114 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1115 properties->wavefrontSize = 64;
1116
1117 /* SGPR. */
1118 properties->sgprsPerSimd =
1119 radv_get_num_physical_sgprs(pdevice);
1120 properties->minSgprAllocation =
1121 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1122 properties->maxSgprAllocation =
1123 pdevice->rad_info.family == CHIP_TONGA ||
1124 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1125 properties->sgprAllocationGranularity =
1126 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1127
1128 /* VGPR. */
1129 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1130 properties->minVgprAllocation = 4;
1131 properties->maxVgprAllocation = 256;
1132 properties->vgprAllocationGranularity = 4;
1133 break;
1134 }
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1136 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1137 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1138 properties->maxVertexAttribDivisor = UINT32_MAX;
1139 break;
1140 }
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1142 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1143 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1144 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1145 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1146 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1147 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1148 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1149 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1150 properties->robustBufferAccessUpdateAfterBind = false;
1151 properties->quadDivergentImplicitLod = false;
1152
1153 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1154 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1155 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1156 32 /* sampler, largest when combined with image */ +
1157 64 /* sampled image */ +
1158 64 /* storage image */);
1159 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1160 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1162 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1163 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1164 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1165 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1166 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1167 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1168 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1169 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1170 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1171 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1172 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1173 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1177 VkPhysicalDeviceProtectedMemoryProperties *properties =
1178 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1179 properties->protectedNoFault = false;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1183 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1184 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1185 properties->primitiveOverestimationSize = 0;
1186 properties->maxExtraPrimitiveOverestimationSize = 0;
1187 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1188 properties->primitiveUnderestimation = VK_FALSE;
1189 properties->conservativePointAndLineRasterization = VK_FALSE;
1190 properties->degenerateTrianglesRasterized = VK_FALSE;
1191 properties->degenerateLinesRasterized = VK_FALSE;
1192 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1193 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1194 break;
1195 }
1196 default:
1197 break;
1198 }
1199 }
1200 }
1201
1202 static void radv_get_physical_device_queue_family_properties(
1203 struct radv_physical_device* pdevice,
1204 uint32_t* pCount,
1205 VkQueueFamilyProperties** pQueueFamilyProperties)
1206 {
1207 int num_queue_families = 1;
1208 int idx;
1209 if (pdevice->rad_info.num_compute_rings > 0 &&
1210 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1211 num_queue_families++;
1212
1213 if (pQueueFamilyProperties == NULL) {
1214 *pCount = num_queue_families;
1215 return;
1216 }
1217
1218 if (!*pCount)
1219 return;
1220
1221 idx = 0;
1222 if (*pCount >= 1) {
1223 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1224 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1225 VK_QUEUE_COMPUTE_BIT |
1226 VK_QUEUE_TRANSFER_BIT |
1227 VK_QUEUE_SPARSE_BINDING_BIT,
1228 .queueCount = 1,
1229 .timestampValidBits = 64,
1230 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1231 };
1232 idx++;
1233 }
1234
1235 if (pdevice->rad_info.num_compute_rings > 0 &&
1236 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1237 if (*pCount > idx) {
1238 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1239 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1240 VK_QUEUE_TRANSFER_BIT |
1241 VK_QUEUE_SPARSE_BINDING_BIT,
1242 .queueCount = pdevice->rad_info.num_compute_rings,
1243 .timestampValidBits = 64,
1244 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1245 };
1246 idx++;
1247 }
1248 }
1249 *pCount = idx;
1250 }
1251
1252 void radv_GetPhysicalDeviceQueueFamilyProperties(
1253 VkPhysicalDevice physicalDevice,
1254 uint32_t* pCount,
1255 VkQueueFamilyProperties* pQueueFamilyProperties)
1256 {
1257 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1258 if (!pQueueFamilyProperties) {
1259 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1260 return;
1261 }
1262 VkQueueFamilyProperties *properties[] = {
1263 pQueueFamilyProperties + 0,
1264 pQueueFamilyProperties + 1,
1265 pQueueFamilyProperties + 2,
1266 };
1267 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1268 assert(*pCount <= 3);
1269 }
1270
1271 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1272 VkPhysicalDevice physicalDevice,
1273 uint32_t* pCount,
1274 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1275 {
1276 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1277 if (!pQueueFamilyProperties) {
1278 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1279 return;
1280 }
1281 VkQueueFamilyProperties *properties[] = {
1282 &pQueueFamilyProperties[0].queueFamilyProperties,
1283 &pQueueFamilyProperties[1].queueFamilyProperties,
1284 &pQueueFamilyProperties[2].queueFamilyProperties,
1285 };
1286 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1287 assert(*pCount <= 3);
1288 }
1289
1290 void radv_GetPhysicalDeviceMemoryProperties(
1291 VkPhysicalDevice physicalDevice,
1292 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1293 {
1294 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1295
1296 *pMemoryProperties = physical_device->memory_properties;
1297 }
1298
1299 void radv_GetPhysicalDeviceMemoryProperties2(
1300 VkPhysicalDevice physicalDevice,
1301 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1302 {
1303 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1304 &pMemoryProperties->memoryProperties);
1305 }
1306
1307 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1308 VkDevice _device,
1309 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1310 const void *pHostPointer,
1311 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1312 {
1313 RADV_FROM_HANDLE(radv_device, device, _device);
1314
1315 switch (handleType)
1316 {
1317 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1318 const struct radv_physical_device *physical_device = device->physical_device;
1319 uint32_t memoryTypeBits = 0;
1320 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1321 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1322 memoryTypeBits = (1 << i);
1323 break;
1324 }
1325 }
1326 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1327 return VK_SUCCESS;
1328 }
1329 default:
1330 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1331 }
1332 }
1333
1334 static enum radeon_ctx_priority
1335 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1336 {
1337 /* Default to MEDIUM when a specific global priority isn't requested */
1338 if (!pObj)
1339 return RADEON_CTX_PRIORITY_MEDIUM;
1340
1341 switch(pObj->globalPriority) {
1342 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1343 return RADEON_CTX_PRIORITY_REALTIME;
1344 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1345 return RADEON_CTX_PRIORITY_HIGH;
1346 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1347 return RADEON_CTX_PRIORITY_MEDIUM;
1348 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1349 return RADEON_CTX_PRIORITY_LOW;
1350 default:
1351 unreachable("Illegal global priority value");
1352 return RADEON_CTX_PRIORITY_INVALID;
1353 }
1354 }
1355
1356 static int
1357 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1358 uint32_t queue_family_index, int idx,
1359 VkDeviceQueueCreateFlags flags,
1360 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1361 {
1362 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1363 queue->device = device;
1364 queue->queue_family_index = queue_family_index;
1365 queue->queue_idx = idx;
1366 queue->priority = radv_get_queue_global_priority(global_priority);
1367 queue->flags = flags;
1368
1369 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1370 if (!queue->hw_ctx)
1371 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1372
1373 return VK_SUCCESS;
1374 }
1375
1376 static void
1377 radv_queue_finish(struct radv_queue *queue)
1378 {
1379 if (queue->hw_ctx)
1380 queue->device->ws->ctx_destroy(queue->hw_ctx);
1381
1382 if (queue->initial_full_flush_preamble_cs)
1383 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1384 if (queue->initial_preamble_cs)
1385 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1386 if (queue->continue_preamble_cs)
1387 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1388 if (queue->descriptor_bo)
1389 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1390 if (queue->scratch_bo)
1391 queue->device->ws->buffer_destroy(queue->scratch_bo);
1392 if (queue->esgs_ring_bo)
1393 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1394 if (queue->gsvs_ring_bo)
1395 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1396 if (queue->tess_rings_bo)
1397 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1398 if (queue->compute_scratch_bo)
1399 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1400 }
1401
1402 static void
1403 radv_bo_list_init(struct radv_bo_list *bo_list)
1404 {
1405 pthread_mutex_init(&bo_list->mutex, NULL);
1406 bo_list->list.count = bo_list->capacity = 0;
1407 bo_list->list.bos = NULL;
1408 }
1409
1410 static void
1411 radv_bo_list_finish(struct radv_bo_list *bo_list)
1412 {
1413 free(bo_list->list.bos);
1414 pthread_mutex_destroy(&bo_list->mutex);
1415 }
1416
1417 static VkResult radv_bo_list_add(struct radv_device *device,
1418 struct radeon_winsys_bo *bo)
1419 {
1420 struct radv_bo_list *bo_list = &device->bo_list;
1421
1422 if (unlikely(!device->use_global_bo_list))
1423 return VK_SUCCESS;
1424
1425 pthread_mutex_lock(&bo_list->mutex);
1426 if (bo_list->list.count == bo_list->capacity) {
1427 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1428 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1429
1430 if (!data) {
1431 pthread_mutex_unlock(&bo_list->mutex);
1432 return VK_ERROR_OUT_OF_HOST_MEMORY;
1433 }
1434
1435 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1436 bo_list->capacity = capacity;
1437 }
1438
1439 bo_list->list.bos[bo_list->list.count++] = bo;
1440 pthread_mutex_unlock(&bo_list->mutex);
1441 return VK_SUCCESS;
1442 }
1443
1444 static void radv_bo_list_remove(struct radv_device *device,
1445 struct radeon_winsys_bo *bo)
1446 {
1447 struct radv_bo_list *bo_list = &device->bo_list;
1448
1449 if (unlikely(!device->use_global_bo_list))
1450 return;
1451
1452 pthread_mutex_lock(&bo_list->mutex);
1453 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1454 if (bo_list->list.bos[i] == bo) {
1455 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1456 --bo_list->list.count;
1457 break;
1458 }
1459 }
1460 pthread_mutex_unlock(&bo_list->mutex);
1461 }
1462
1463 static void
1464 radv_device_init_gs_info(struct radv_device *device)
1465 {
1466 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1467 device->physical_device->rad_info.family);
1468 }
1469
1470 static int radv_get_device_extension_index(const char *name)
1471 {
1472 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1473 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1474 return i;
1475 }
1476 return -1;
1477 }
1478
1479 static int
1480 radv_get_int_debug_option(const char *name, int default_value)
1481 {
1482 const char *str;
1483 int result;
1484
1485 str = getenv(name);
1486 if (!str) {
1487 result = default_value;
1488 } else {
1489 char *endptr;
1490
1491 result = strtol(str, &endptr, 0);
1492 if (str == endptr) {
1493 /* No digits founs. */
1494 result = default_value;
1495 }
1496 }
1497
1498 return result;
1499 }
1500
1501 VkResult radv_CreateDevice(
1502 VkPhysicalDevice physicalDevice,
1503 const VkDeviceCreateInfo* pCreateInfo,
1504 const VkAllocationCallbacks* pAllocator,
1505 VkDevice* pDevice)
1506 {
1507 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1508 VkResult result;
1509 struct radv_device *device;
1510
1511 bool keep_shader_info = false;
1512
1513 /* Check enabled features */
1514 if (pCreateInfo->pEnabledFeatures) {
1515 VkPhysicalDeviceFeatures supported_features;
1516 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1517 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1518 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1519 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1520 for (uint32_t i = 0; i < num_features; i++) {
1521 if (enabled_feature[i] && !supported_feature[i])
1522 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1523 }
1524 }
1525
1526 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1527 sizeof(*device), 8,
1528 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1529 if (!device)
1530 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1531
1532 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1533 device->instance = physical_device->instance;
1534 device->physical_device = physical_device;
1535
1536 device->ws = physical_device->ws;
1537 if (pAllocator)
1538 device->alloc = *pAllocator;
1539 else
1540 device->alloc = physical_device->instance->alloc;
1541
1542 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1543 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1544 int index = radv_get_device_extension_index(ext_name);
1545 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1546 vk_free(&device->alloc, device);
1547 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1548 }
1549
1550 device->enabled_extensions.extensions[index] = true;
1551 }
1552
1553 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1554
1555 /* With update after bind we can't attach bo's to the command buffer
1556 * from the descriptor set anymore, so we have to use a global BO list.
1557 */
1558 device->use_global_bo_list =
1559 device->enabled_extensions.EXT_descriptor_indexing;
1560
1561 mtx_init(&device->shader_slab_mutex, mtx_plain);
1562 list_inithead(&device->shader_slabs);
1563
1564 radv_bo_list_init(&device->bo_list);
1565
1566 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1567 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1568 uint32_t qfi = queue_create->queueFamilyIndex;
1569 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1570 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1571
1572 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1573
1574 device->queues[qfi] = vk_alloc(&device->alloc,
1575 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1576 if (!device->queues[qfi]) {
1577 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1578 goto fail;
1579 }
1580
1581 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1582
1583 device->queue_count[qfi] = queue_create->queueCount;
1584
1585 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1586 result = radv_queue_init(device, &device->queues[qfi][q],
1587 qfi, q, queue_create->flags,
1588 global_priority);
1589 if (result != VK_SUCCESS)
1590 goto fail;
1591 }
1592 }
1593
1594 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1595 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1596 device->physical_device->rad_info.family == CHIP_RAVEN);
1597
1598 /* Disabled and not implemented for now. */
1599 device->dfsm_allowed = device->pbb_allowed &&
1600 device->physical_device->rad_info.family == CHIP_RAVEN;
1601
1602 #ifdef ANDROID
1603 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1604 #endif
1605
1606 /* The maximum number of scratch waves. Scratch space isn't divided
1607 * evenly between CUs. The number is only a function of the number of CUs.
1608 * We can decrease the constant to decrease the scratch buffer size.
1609 *
1610 * sctx->scratch_waves must be >= the maximum possible size of
1611 * 1 threadgroup, so that the hw doesn't hang from being unable
1612 * to start any.
1613 *
1614 * The recommended value is 4 per CU at most. Higher numbers don't
1615 * bring much benefit, but they still occupy chip resources (think
1616 * async compute). I've seen ~2% performance difference between 4 and 32.
1617 */
1618 uint32_t max_threads_per_block = 2048;
1619 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1620 max_threads_per_block / 64);
1621
1622 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1623
1624 if (device->physical_device->rad_info.chip_class >= CIK) {
1625 /* If the KMD allows it (there is a KMD hw register for it),
1626 * allow launching waves out-of-order.
1627 */
1628 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1629 }
1630
1631 radv_device_init_gs_info(device);
1632
1633 device->tess_offchip_block_dw_size =
1634 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1635 device->has_distributed_tess =
1636 device->physical_device->rad_info.chip_class >= VI &&
1637 device->physical_device->rad_info.max_se >= 2;
1638
1639 if (getenv("RADV_TRACE_FILE")) {
1640 const char *filename = getenv("RADV_TRACE_FILE");
1641
1642 keep_shader_info = true;
1643
1644 if (!radv_init_trace(device))
1645 goto fail;
1646
1647 fprintf(stderr, "*****************************************************************************\n");
1648 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1649 fprintf(stderr, "*****************************************************************************\n");
1650
1651 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1652 radv_dump_enabled_options(device, stderr);
1653 }
1654
1655 device->keep_shader_info = keep_shader_info;
1656
1657 result = radv_device_init_meta(device);
1658 if (result != VK_SUCCESS)
1659 goto fail;
1660
1661 radv_device_init_msaa(device);
1662
1663 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1664 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1665 switch (family) {
1666 case RADV_QUEUE_GENERAL:
1667 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1668 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1669 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1670 break;
1671 case RADV_QUEUE_COMPUTE:
1672 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1673 radeon_emit(device->empty_cs[family], 0);
1674 break;
1675 }
1676 device->ws->cs_finalize(device->empty_cs[family]);
1677 }
1678
1679 if (device->physical_device->rad_info.chip_class >= CIK)
1680 cik_create_gfx_config(device);
1681
1682 VkPipelineCacheCreateInfo ci;
1683 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1684 ci.pNext = NULL;
1685 ci.flags = 0;
1686 ci.pInitialData = NULL;
1687 ci.initialDataSize = 0;
1688 VkPipelineCache pc;
1689 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1690 &ci, NULL, &pc);
1691 if (result != VK_SUCCESS)
1692 goto fail_meta;
1693
1694 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1695
1696 device->force_aniso =
1697 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1698 if (device->force_aniso >= 0) {
1699 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1700 1 << util_logbase2(device->force_aniso));
1701 }
1702
1703 *pDevice = radv_device_to_handle(device);
1704 return VK_SUCCESS;
1705
1706 fail_meta:
1707 radv_device_finish_meta(device);
1708 fail:
1709 radv_bo_list_finish(&device->bo_list);
1710
1711 if (device->trace_bo)
1712 device->ws->buffer_destroy(device->trace_bo);
1713
1714 if (device->gfx_init)
1715 device->ws->buffer_destroy(device->gfx_init);
1716
1717 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1718 for (unsigned q = 0; q < device->queue_count[i]; q++)
1719 radv_queue_finish(&device->queues[i][q]);
1720 if (device->queue_count[i])
1721 vk_free(&device->alloc, device->queues[i]);
1722 }
1723
1724 vk_free(&device->alloc, device);
1725 return result;
1726 }
1727
1728 void radv_DestroyDevice(
1729 VkDevice _device,
1730 const VkAllocationCallbacks* pAllocator)
1731 {
1732 RADV_FROM_HANDLE(radv_device, device, _device);
1733
1734 if (!device)
1735 return;
1736
1737 if (device->trace_bo)
1738 device->ws->buffer_destroy(device->trace_bo);
1739
1740 if (device->gfx_init)
1741 device->ws->buffer_destroy(device->gfx_init);
1742
1743 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1744 for (unsigned q = 0; q < device->queue_count[i]; q++)
1745 radv_queue_finish(&device->queues[i][q]);
1746 if (device->queue_count[i])
1747 vk_free(&device->alloc, device->queues[i]);
1748 if (device->empty_cs[i])
1749 device->ws->cs_destroy(device->empty_cs[i]);
1750 }
1751 radv_device_finish_meta(device);
1752
1753 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1754 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1755
1756 radv_destroy_shader_slabs(device);
1757
1758 radv_bo_list_finish(&device->bo_list);
1759 vk_free(&device->alloc, device);
1760 }
1761
1762 VkResult radv_EnumerateInstanceLayerProperties(
1763 uint32_t* pPropertyCount,
1764 VkLayerProperties* pProperties)
1765 {
1766 if (pProperties == NULL) {
1767 *pPropertyCount = 0;
1768 return VK_SUCCESS;
1769 }
1770
1771 /* None supported at this time */
1772 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1773 }
1774
1775 VkResult radv_EnumerateDeviceLayerProperties(
1776 VkPhysicalDevice physicalDevice,
1777 uint32_t* pPropertyCount,
1778 VkLayerProperties* pProperties)
1779 {
1780 if (pProperties == NULL) {
1781 *pPropertyCount = 0;
1782 return VK_SUCCESS;
1783 }
1784
1785 /* None supported at this time */
1786 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1787 }
1788
1789 void radv_GetDeviceQueue2(
1790 VkDevice _device,
1791 const VkDeviceQueueInfo2* pQueueInfo,
1792 VkQueue* pQueue)
1793 {
1794 RADV_FROM_HANDLE(radv_device, device, _device);
1795 struct radv_queue *queue;
1796
1797 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1798 if (pQueueInfo->flags != queue->flags) {
1799 /* From the Vulkan 1.1.70 spec:
1800 *
1801 * "The queue returned by vkGetDeviceQueue2 must have the same
1802 * flags value from this structure as that used at device
1803 * creation time in a VkDeviceQueueCreateInfo instance. If no
1804 * matching flags were specified at device creation time then
1805 * pQueue will return VK_NULL_HANDLE."
1806 */
1807 *pQueue = VK_NULL_HANDLE;
1808 return;
1809 }
1810
1811 *pQueue = radv_queue_to_handle(queue);
1812 }
1813
1814 void radv_GetDeviceQueue(
1815 VkDevice _device,
1816 uint32_t queueFamilyIndex,
1817 uint32_t queueIndex,
1818 VkQueue* pQueue)
1819 {
1820 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1821 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1822 .queueFamilyIndex = queueFamilyIndex,
1823 .queueIndex = queueIndex
1824 };
1825
1826 radv_GetDeviceQueue2(_device, &info, pQueue);
1827 }
1828
1829 static void
1830 fill_geom_tess_rings(struct radv_queue *queue,
1831 uint32_t *map,
1832 bool add_sample_positions,
1833 uint32_t esgs_ring_size,
1834 struct radeon_winsys_bo *esgs_ring_bo,
1835 uint32_t gsvs_ring_size,
1836 struct radeon_winsys_bo *gsvs_ring_bo,
1837 uint32_t tess_factor_ring_size,
1838 uint32_t tess_offchip_ring_offset,
1839 uint32_t tess_offchip_ring_size,
1840 struct radeon_winsys_bo *tess_rings_bo)
1841 {
1842 uint64_t esgs_va = 0, gsvs_va = 0;
1843 uint64_t tess_va = 0, tess_offchip_va = 0;
1844 uint32_t *desc = &map[4];
1845
1846 if (esgs_ring_bo)
1847 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1848 if (gsvs_ring_bo)
1849 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1850 if (tess_rings_bo) {
1851 tess_va = radv_buffer_get_va(tess_rings_bo);
1852 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1853 }
1854
1855 /* stride 0, num records - size, add tid, swizzle, elsize4,
1856 index stride 64 */
1857 desc[0] = esgs_va;
1858 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1859 S_008F04_STRIDE(0) |
1860 S_008F04_SWIZZLE_ENABLE(true);
1861 desc[2] = esgs_ring_size;
1862 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1863 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1864 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1865 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1866 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1867 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1868 S_008F0C_ELEMENT_SIZE(1) |
1869 S_008F0C_INDEX_STRIDE(3) |
1870 S_008F0C_ADD_TID_ENABLE(true);
1871
1872 desc += 4;
1873 /* GS entry for ES->GS ring */
1874 /* stride 0, num records - size, elsize0,
1875 index stride 0 */
1876 desc[0] = esgs_va;
1877 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1878 S_008F04_STRIDE(0) |
1879 S_008F04_SWIZZLE_ENABLE(false);
1880 desc[2] = esgs_ring_size;
1881 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1882 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1883 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1884 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1885 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1886 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1887 S_008F0C_ELEMENT_SIZE(0) |
1888 S_008F0C_INDEX_STRIDE(0) |
1889 S_008F0C_ADD_TID_ENABLE(false);
1890
1891 desc += 4;
1892 /* VS entry for GS->VS ring */
1893 /* stride 0, num records - size, elsize0,
1894 index stride 0 */
1895 desc[0] = gsvs_va;
1896 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1897 S_008F04_STRIDE(0) |
1898 S_008F04_SWIZZLE_ENABLE(false);
1899 desc[2] = gsvs_ring_size;
1900 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1901 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1902 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1903 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1904 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1905 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1906 S_008F0C_ELEMENT_SIZE(0) |
1907 S_008F0C_INDEX_STRIDE(0) |
1908 S_008F0C_ADD_TID_ENABLE(false);
1909 desc += 4;
1910
1911 /* stride gsvs_itemsize, num records 64
1912 elsize 4, index stride 16 */
1913 /* shader will patch stride and desc[2] */
1914 desc[0] = gsvs_va;
1915 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1916 S_008F04_STRIDE(0) |
1917 S_008F04_SWIZZLE_ENABLE(true);
1918 desc[2] = 0;
1919 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1920 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1921 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1922 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1923 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1924 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1925 S_008F0C_ELEMENT_SIZE(1) |
1926 S_008F0C_INDEX_STRIDE(1) |
1927 S_008F0C_ADD_TID_ENABLE(true);
1928 desc += 4;
1929
1930 desc[0] = tess_va;
1931 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1932 S_008F04_STRIDE(0) |
1933 S_008F04_SWIZZLE_ENABLE(false);
1934 desc[2] = tess_factor_ring_size;
1935 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1939 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1940 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1941 S_008F0C_ELEMENT_SIZE(0) |
1942 S_008F0C_INDEX_STRIDE(0) |
1943 S_008F0C_ADD_TID_ENABLE(false);
1944 desc += 4;
1945
1946 desc[0] = tess_offchip_va;
1947 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1948 S_008F04_STRIDE(0) |
1949 S_008F04_SWIZZLE_ENABLE(false);
1950 desc[2] = tess_offchip_ring_size;
1951 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1952 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1953 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1954 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1955 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1956 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1957 S_008F0C_ELEMENT_SIZE(0) |
1958 S_008F0C_INDEX_STRIDE(0) |
1959 S_008F0C_ADD_TID_ENABLE(false);
1960 desc += 4;
1961
1962 /* add sample positions after all rings */
1963 memcpy(desc, queue->device->sample_locations_1x, 8);
1964 desc += 2;
1965 memcpy(desc, queue->device->sample_locations_2x, 16);
1966 desc += 4;
1967 memcpy(desc, queue->device->sample_locations_4x, 32);
1968 desc += 8;
1969 memcpy(desc, queue->device->sample_locations_8x, 64);
1970 desc += 16;
1971 memcpy(desc, queue->device->sample_locations_16x, 128);
1972 }
1973
1974 static unsigned
1975 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1976 {
1977 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1978 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1979 device->physical_device->rad_info.family != CHIP_STONEY;
1980 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1981 unsigned max_offchip_buffers;
1982 unsigned offchip_granularity;
1983 unsigned hs_offchip_param;
1984
1985 /*
1986 * Per RadeonSI:
1987 * This must be one less than the maximum number due to a hw limitation.
1988 * Various hardware bugs in SI, CIK, and GFX9 need this.
1989 *
1990 * Per AMDVLK:
1991 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1992 * Gfx7 should limit max_offchip_buffers to 508
1993 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1994 *
1995 * Follow AMDVLK here.
1996 */
1997 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1998 device->physical_device->rad_info.chip_class == CIK ||
1999 device->physical_device->rad_info.chip_class == SI)
2000 --max_offchip_buffers_per_se;
2001
2002 max_offchip_buffers = max_offchip_buffers_per_se *
2003 device->physical_device->rad_info.max_se;
2004
2005 switch (device->tess_offchip_block_dw_size) {
2006 default:
2007 assert(0);
2008 /* fall through */
2009 case 8192:
2010 offchip_granularity = V_03093C_X_8K_DWORDS;
2011 break;
2012 case 4096:
2013 offchip_granularity = V_03093C_X_4K_DWORDS;
2014 break;
2015 }
2016
2017 switch (device->physical_device->rad_info.chip_class) {
2018 case SI:
2019 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2020 break;
2021 case CIK:
2022 case VI:
2023 case GFX9:
2024 default:
2025 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2026 break;
2027 }
2028
2029 *max_offchip_buffers_p = max_offchip_buffers;
2030 if (device->physical_device->rad_info.chip_class >= CIK) {
2031 if (device->physical_device->rad_info.chip_class >= VI)
2032 --max_offchip_buffers;
2033 hs_offchip_param =
2034 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2035 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2036 } else {
2037 hs_offchip_param =
2038 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2039 }
2040 return hs_offchip_param;
2041 }
2042
2043 static void
2044 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2045 struct radeon_winsys_bo *esgs_ring_bo,
2046 uint32_t esgs_ring_size,
2047 struct radeon_winsys_bo *gsvs_ring_bo,
2048 uint32_t gsvs_ring_size)
2049 {
2050 if (!esgs_ring_bo && !gsvs_ring_bo)
2051 return;
2052
2053 if (esgs_ring_bo)
2054 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2055
2056 if (gsvs_ring_bo)
2057 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2058
2059 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2060 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2061 radeon_emit(cs, esgs_ring_size >> 8);
2062 radeon_emit(cs, gsvs_ring_size >> 8);
2063 } else {
2064 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2065 radeon_emit(cs, esgs_ring_size >> 8);
2066 radeon_emit(cs, gsvs_ring_size >> 8);
2067 }
2068 }
2069
2070 static void
2071 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2072 unsigned hs_offchip_param, unsigned tf_ring_size,
2073 struct radeon_winsys_bo *tess_rings_bo)
2074 {
2075 uint64_t tf_va;
2076
2077 if (!tess_rings_bo)
2078 return;
2079
2080 tf_va = radv_buffer_get_va(tess_rings_bo);
2081
2082 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2083
2084 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2085 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2086 S_030938_SIZE(tf_ring_size / 4));
2087 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2088 tf_va >> 8);
2089 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2090 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2091 S_030944_BASE_HI(tf_va >> 40));
2092 }
2093 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2094 hs_offchip_param);
2095 } else {
2096 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2097 S_008988_SIZE(tf_ring_size / 4));
2098 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2099 tf_va >> 8);
2100 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2101 hs_offchip_param);
2102 }
2103 }
2104
2105 static void
2106 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2107 struct radeon_winsys_bo *compute_scratch_bo)
2108 {
2109 uint64_t scratch_va;
2110
2111 if (!compute_scratch_bo)
2112 return;
2113
2114 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2115
2116 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2117
2118 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2119 radeon_emit(cs, scratch_va);
2120 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2121 S_008F04_SWIZZLE_ENABLE(1));
2122 }
2123
2124 static void
2125 radv_emit_global_shader_pointers(struct radv_queue *queue,
2126 struct radeon_cmdbuf *cs,
2127 struct radeon_winsys_bo *descriptor_bo)
2128 {
2129 uint64_t va;
2130
2131 if (!descriptor_bo)
2132 return;
2133
2134 va = radv_buffer_get_va(descriptor_bo);
2135
2136 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2137
2138 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2139 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2140 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2141 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2142 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2143
2144 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2145 radv_emit_shader_pointer(queue->device, cs, regs[i],
2146 va, true);
2147 }
2148 } else {
2149 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2150 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2151 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2152 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2153 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2154 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2155
2156 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2157 radv_emit_shader_pointer(queue->device, cs, regs[i],
2158 va, true);
2159 }
2160 }
2161 }
2162
2163 static void
2164 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2165 {
2166 struct radv_device *device = queue->device;
2167
2168 if (device->gfx_init) {
2169 uint64_t va = radv_buffer_get_va(device->gfx_init);
2170
2171 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2172 radeon_emit(cs, va);
2173 radeon_emit(cs, va >> 32);
2174 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2175
2176 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2177 } else {
2178 struct radv_physical_device *physical_device = device->physical_device;
2179 si_emit_graphics(physical_device, cs);
2180 }
2181 }
2182
2183 static void
2184 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2185 {
2186 struct radv_physical_device *physical_device = queue->device->physical_device;
2187 si_emit_compute(physical_device, cs);
2188 }
2189
2190 static VkResult
2191 radv_get_preamble_cs(struct radv_queue *queue,
2192 uint32_t scratch_size,
2193 uint32_t compute_scratch_size,
2194 uint32_t esgs_ring_size,
2195 uint32_t gsvs_ring_size,
2196 bool needs_tess_rings,
2197 bool needs_sample_positions,
2198 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2199 struct radeon_cmdbuf **initial_preamble_cs,
2200 struct radeon_cmdbuf **continue_preamble_cs)
2201 {
2202 struct radeon_winsys_bo *scratch_bo = NULL;
2203 struct radeon_winsys_bo *descriptor_bo = NULL;
2204 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2205 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2206 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2207 struct radeon_winsys_bo *tess_rings_bo = NULL;
2208 struct radeon_cmdbuf *dest_cs[3] = {0};
2209 bool add_tess_rings = false, add_sample_positions = false;
2210 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2211 unsigned max_offchip_buffers;
2212 unsigned hs_offchip_param = 0;
2213 unsigned tess_offchip_ring_offset;
2214 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2215 if (!queue->has_tess_rings) {
2216 if (needs_tess_rings)
2217 add_tess_rings = true;
2218 }
2219 if (!queue->has_sample_positions) {
2220 if (needs_sample_positions)
2221 add_sample_positions = true;
2222 }
2223 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2224 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2225 &max_offchip_buffers);
2226 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2227 tess_offchip_ring_size = max_offchip_buffers *
2228 queue->device->tess_offchip_block_dw_size * 4;
2229
2230 if (scratch_size <= queue->scratch_size &&
2231 compute_scratch_size <= queue->compute_scratch_size &&
2232 esgs_ring_size <= queue->esgs_ring_size &&
2233 gsvs_ring_size <= queue->gsvs_ring_size &&
2234 !add_tess_rings && !add_sample_positions &&
2235 queue->initial_preamble_cs) {
2236 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2237 *initial_preamble_cs = queue->initial_preamble_cs;
2238 *continue_preamble_cs = queue->continue_preamble_cs;
2239 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2240 *continue_preamble_cs = NULL;
2241 return VK_SUCCESS;
2242 }
2243
2244 if (scratch_size > queue->scratch_size) {
2245 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2246 scratch_size,
2247 4096,
2248 RADEON_DOMAIN_VRAM,
2249 ring_bo_flags);
2250 if (!scratch_bo)
2251 goto fail;
2252 } else
2253 scratch_bo = queue->scratch_bo;
2254
2255 if (compute_scratch_size > queue->compute_scratch_size) {
2256 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2257 compute_scratch_size,
2258 4096,
2259 RADEON_DOMAIN_VRAM,
2260 ring_bo_flags);
2261 if (!compute_scratch_bo)
2262 goto fail;
2263
2264 } else
2265 compute_scratch_bo = queue->compute_scratch_bo;
2266
2267 if (esgs_ring_size > queue->esgs_ring_size) {
2268 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2269 esgs_ring_size,
2270 4096,
2271 RADEON_DOMAIN_VRAM,
2272 ring_bo_flags);
2273 if (!esgs_ring_bo)
2274 goto fail;
2275 } else {
2276 esgs_ring_bo = queue->esgs_ring_bo;
2277 esgs_ring_size = queue->esgs_ring_size;
2278 }
2279
2280 if (gsvs_ring_size > queue->gsvs_ring_size) {
2281 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2282 gsvs_ring_size,
2283 4096,
2284 RADEON_DOMAIN_VRAM,
2285 ring_bo_flags);
2286 if (!gsvs_ring_bo)
2287 goto fail;
2288 } else {
2289 gsvs_ring_bo = queue->gsvs_ring_bo;
2290 gsvs_ring_size = queue->gsvs_ring_size;
2291 }
2292
2293 if (add_tess_rings) {
2294 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2295 tess_offchip_ring_offset + tess_offchip_ring_size,
2296 256,
2297 RADEON_DOMAIN_VRAM,
2298 ring_bo_flags);
2299 if (!tess_rings_bo)
2300 goto fail;
2301 } else {
2302 tess_rings_bo = queue->tess_rings_bo;
2303 }
2304
2305 if (scratch_bo != queue->scratch_bo ||
2306 esgs_ring_bo != queue->esgs_ring_bo ||
2307 gsvs_ring_bo != queue->gsvs_ring_bo ||
2308 tess_rings_bo != queue->tess_rings_bo ||
2309 add_sample_positions) {
2310 uint32_t size = 0;
2311 if (gsvs_ring_bo || esgs_ring_bo ||
2312 tess_rings_bo || add_sample_positions) {
2313 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2314 if (add_sample_positions)
2315 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2316 }
2317 else if (scratch_bo)
2318 size = 8; /* 2 dword */
2319
2320 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2321 size,
2322 4096,
2323 RADEON_DOMAIN_VRAM,
2324 RADEON_FLAG_CPU_ACCESS |
2325 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2326 RADEON_FLAG_READ_ONLY);
2327 if (!descriptor_bo)
2328 goto fail;
2329 } else
2330 descriptor_bo = queue->descriptor_bo;
2331
2332 for(int i = 0; i < 3; ++i) {
2333 struct radeon_cmdbuf *cs = NULL;
2334 cs = queue->device->ws->cs_create(queue->device->ws,
2335 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2336 if (!cs)
2337 goto fail;
2338
2339 dest_cs[i] = cs;
2340
2341 if (scratch_bo)
2342 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2343
2344 /* Emit initial configuration. */
2345 switch (queue->queue_family_index) {
2346 case RADV_QUEUE_GENERAL:
2347 radv_init_graphics_state(cs, queue);
2348 break;
2349 case RADV_QUEUE_COMPUTE:
2350 radv_init_compute_state(cs, queue);
2351 break;
2352 case RADV_QUEUE_TRANSFER:
2353 break;
2354 }
2355
2356 if (descriptor_bo != queue->descriptor_bo) {
2357 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2358
2359 if (scratch_bo) {
2360 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2361 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2362 S_008F04_SWIZZLE_ENABLE(1);
2363 map[0] = scratch_va;
2364 map[1] = rsrc1;
2365 }
2366
2367 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2368 add_sample_positions)
2369 fill_geom_tess_rings(queue, map, add_sample_positions,
2370 esgs_ring_size, esgs_ring_bo,
2371 gsvs_ring_size, gsvs_ring_bo,
2372 tess_factor_ring_size,
2373 tess_offchip_ring_offset,
2374 tess_offchip_ring_size,
2375 tess_rings_bo);
2376
2377 queue->device->ws->buffer_unmap(descriptor_bo);
2378 }
2379
2380 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2381 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2382 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2383 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2384 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2385 }
2386
2387 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2388 gsvs_ring_bo, gsvs_ring_size);
2389 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2390 tess_factor_ring_size, tess_rings_bo);
2391 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2392 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2393
2394 if (i == 0) {
2395 si_cs_emit_cache_flush(cs,
2396 queue->device->physical_device->rad_info.chip_class,
2397 NULL, 0,
2398 queue->queue_family_index == RING_COMPUTE &&
2399 queue->device->physical_device->rad_info.chip_class >= CIK,
2400 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2401 RADV_CMD_FLAG_INV_ICACHE |
2402 RADV_CMD_FLAG_INV_SMEM_L1 |
2403 RADV_CMD_FLAG_INV_VMEM_L1 |
2404 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2405 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2406 } else if (i == 1) {
2407 si_cs_emit_cache_flush(cs,
2408 queue->device->physical_device->rad_info.chip_class,
2409 NULL, 0,
2410 queue->queue_family_index == RING_COMPUTE &&
2411 queue->device->physical_device->rad_info.chip_class >= CIK,
2412 RADV_CMD_FLAG_INV_ICACHE |
2413 RADV_CMD_FLAG_INV_SMEM_L1 |
2414 RADV_CMD_FLAG_INV_VMEM_L1 |
2415 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2416 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2417 }
2418
2419 if (!queue->device->ws->cs_finalize(cs))
2420 goto fail;
2421 }
2422
2423 if (queue->initial_full_flush_preamble_cs)
2424 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2425
2426 if (queue->initial_preamble_cs)
2427 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2428
2429 if (queue->continue_preamble_cs)
2430 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2431
2432 queue->initial_full_flush_preamble_cs = dest_cs[0];
2433 queue->initial_preamble_cs = dest_cs[1];
2434 queue->continue_preamble_cs = dest_cs[2];
2435
2436 if (scratch_bo != queue->scratch_bo) {
2437 if (queue->scratch_bo)
2438 queue->device->ws->buffer_destroy(queue->scratch_bo);
2439 queue->scratch_bo = scratch_bo;
2440 queue->scratch_size = scratch_size;
2441 }
2442
2443 if (compute_scratch_bo != queue->compute_scratch_bo) {
2444 if (queue->compute_scratch_bo)
2445 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2446 queue->compute_scratch_bo = compute_scratch_bo;
2447 queue->compute_scratch_size = compute_scratch_size;
2448 }
2449
2450 if (esgs_ring_bo != queue->esgs_ring_bo) {
2451 if (queue->esgs_ring_bo)
2452 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2453 queue->esgs_ring_bo = esgs_ring_bo;
2454 queue->esgs_ring_size = esgs_ring_size;
2455 }
2456
2457 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2458 if (queue->gsvs_ring_bo)
2459 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2460 queue->gsvs_ring_bo = gsvs_ring_bo;
2461 queue->gsvs_ring_size = gsvs_ring_size;
2462 }
2463
2464 if (tess_rings_bo != queue->tess_rings_bo) {
2465 queue->tess_rings_bo = tess_rings_bo;
2466 queue->has_tess_rings = true;
2467 }
2468
2469 if (descriptor_bo != queue->descriptor_bo) {
2470 if (queue->descriptor_bo)
2471 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2472
2473 queue->descriptor_bo = descriptor_bo;
2474 }
2475
2476 if (add_sample_positions)
2477 queue->has_sample_positions = true;
2478
2479 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2480 *initial_preamble_cs = queue->initial_preamble_cs;
2481 *continue_preamble_cs = queue->continue_preamble_cs;
2482 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2483 *continue_preamble_cs = NULL;
2484 return VK_SUCCESS;
2485 fail:
2486 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2487 if (dest_cs[i])
2488 queue->device->ws->cs_destroy(dest_cs[i]);
2489 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2490 queue->device->ws->buffer_destroy(descriptor_bo);
2491 if (scratch_bo && scratch_bo != queue->scratch_bo)
2492 queue->device->ws->buffer_destroy(scratch_bo);
2493 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2494 queue->device->ws->buffer_destroy(compute_scratch_bo);
2495 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2496 queue->device->ws->buffer_destroy(esgs_ring_bo);
2497 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2498 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2499 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2500 queue->device->ws->buffer_destroy(tess_rings_bo);
2501 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2502 }
2503
2504 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2505 struct radv_winsys_sem_counts *counts,
2506 int num_sems,
2507 const VkSemaphore *sems,
2508 VkFence _fence,
2509 bool reset_temp)
2510 {
2511 int syncobj_idx = 0, sem_idx = 0;
2512
2513 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2514 return VK_SUCCESS;
2515
2516 for (uint32_t i = 0; i < num_sems; i++) {
2517 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2518
2519 if (sem->temp_syncobj || sem->syncobj)
2520 counts->syncobj_count++;
2521 else
2522 counts->sem_count++;
2523 }
2524
2525 if (_fence != VK_NULL_HANDLE) {
2526 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2527 if (fence->temp_syncobj || fence->syncobj)
2528 counts->syncobj_count++;
2529 }
2530
2531 if (counts->syncobj_count) {
2532 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2533 if (!counts->syncobj)
2534 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2535 }
2536
2537 if (counts->sem_count) {
2538 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2539 if (!counts->sem) {
2540 free(counts->syncobj);
2541 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2542 }
2543 }
2544
2545 for (uint32_t i = 0; i < num_sems; i++) {
2546 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2547
2548 if (sem->temp_syncobj) {
2549 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2550 }
2551 else if (sem->syncobj)
2552 counts->syncobj[syncobj_idx++] = sem->syncobj;
2553 else {
2554 assert(sem->sem);
2555 counts->sem[sem_idx++] = sem->sem;
2556 }
2557 }
2558
2559 if (_fence != VK_NULL_HANDLE) {
2560 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2561 if (fence->temp_syncobj)
2562 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2563 else if (fence->syncobj)
2564 counts->syncobj[syncobj_idx++] = fence->syncobj;
2565 }
2566
2567 return VK_SUCCESS;
2568 }
2569
2570 static void
2571 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2572 {
2573 free(sem_info->wait.syncobj);
2574 free(sem_info->wait.sem);
2575 free(sem_info->signal.syncobj);
2576 free(sem_info->signal.sem);
2577 }
2578
2579
2580 static void radv_free_temp_syncobjs(struct radv_device *device,
2581 int num_sems,
2582 const VkSemaphore *sems)
2583 {
2584 for (uint32_t i = 0; i < num_sems; i++) {
2585 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2586
2587 if (sem->temp_syncobj) {
2588 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2589 sem->temp_syncobj = 0;
2590 }
2591 }
2592 }
2593
2594 static VkResult
2595 radv_alloc_sem_info(struct radv_instance *instance,
2596 struct radv_winsys_sem_info *sem_info,
2597 int num_wait_sems,
2598 const VkSemaphore *wait_sems,
2599 int num_signal_sems,
2600 const VkSemaphore *signal_sems,
2601 VkFence fence)
2602 {
2603 VkResult ret;
2604 memset(sem_info, 0, sizeof(*sem_info));
2605
2606 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2607 if (ret)
2608 return ret;
2609 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2610 if (ret)
2611 radv_free_sem_info(sem_info);
2612
2613 /* caller can override these */
2614 sem_info->cs_emit_wait = true;
2615 sem_info->cs_emit_signal = true;
2616 return ret;
2617 }
2618
2619 /* Signals fence as soon as all the work currently put on queue is done. */
2620 static VkResult radv_signal_fence(struct radv_queue *queue,
2621 struct radv_fence *fence)
2622 {
2623 int ret;
2624 VkResult result;
2625 struct radv_winsys_sem_info sem_info;
2626
2627 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2628 radv_fence_to_handle(fence));
2629 if (result != VK_SUCCESS)
2630 return result;
2631
2632 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2633 &queue->device->empty_cs[queue->queue_family_index],
2634 1, NULL, NULL, &sem_info, NULL,
2635 false, fence->fence);
2636 radv_free_sem_info(&sem_info);
2637
2638 if (ret)
2639 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2640
2641 return VK_SUCCESS;
2642 }
2643
2644 VkResult radv_QueueSubmit(
2645 VkQueue _queue,
2646 uint32_t submitCount,
2647 const VkSubmitInfo* pSubmits,
2648 VkFence _fence)
2649 {
2650 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2651 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2652 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2653 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2654 int ret;
2655 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2656 uint32_t scratch_size = 0;
2657 uint32_t compute_scratch_size = 0;
2658 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2659 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2660 VkResult result;
2661 bool fence_emitted = false;
2662 bool tess_rings_needed = false;
2663 bool sample_positions_needed = false;
2664
2665 /* Do this first so failing to allocate scratch buffers can't result in
2666 * partially executed submissions. */
2667 for (uint32_t i = 0; i < submitCount; i++) {
2668 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2669 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2670 pSubmits[i].pCommandBuffers[j]);
2671
2672 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2673 compute_scratch_size = MAX2(compute_scratch_size,
2674 cmd_buffer->compute_scratch_size_needed);
2675 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2676 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2677 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2678 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2679 }
2680 }
2681
2682 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2683 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2684 sample_positions_needed, &initial_flush_preamble_cs,
2685 &initial_preamble_cs, &continue_preamble_cs);
2686 if (result != VK_SUCCESS)
2687 return result;
2688
2689 for (uint32_t i = 0; i < submitCount; i++) {
2690 struct radeon_cmdbuf **cs_array;
2691 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2692 bool can_patch = true;
2693 uint32_t advance;
2694 struct radv_winsys_sem_info sem_info;
2695
2696 result = radv_alloc_sem_info(queue->device->instance,
2697 &sem_info,
2698 pSubmits[i].waitSemaphoreCount,
2699 pSubmits[i].pWaitSemaphores,
2700 pSubmits[i].signalSemaphoreCount,
2701 pSubmits[i].pSignalSemaphores,
2702 _fence);
2703 if (result != VK_SUCCESS)
2704 return result;
2705
2706 if (!pSubmits[i].commandBufferCount) {
2707 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2708 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2709 &queue->device->empty_cs[queue->queue_family_index],
2710 1, NULL, NULL,
2711 &sem_info, NULL,
2712 false, base_fence);
2713 if (ret) {
2714 radv_loge("failed to submit CS %d\n", i);
2715 abort();
2716 }
2717 fence_emitted = true;
2718 }
2719 radv_free_sem_info(&sem_info);
2720 continue;
2721 }
2722
2723 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2724 (pSubmits[i].commandBufferCount));
2725
2726 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2727 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2728 pSubmits[i].pCommandBuffers[j]);
2729 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2730
2731 cs_array[j] = cmd_buffer->cs;
2732 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2733 can_patch = false;
2734
2735 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2736 }
2737
2738 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2739 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2740 const struct radv_winsys_bo_list *bo_list = NULL;
2741
2742 advance = MIN2(max_cs_submission,
2743 pSubmits[i].commandBufferCount - j);
2744
2745 if (queue->device->trace_bo)
2746 *queue->device->trace_id_ptr = 0;
2747
2748 sem_info.cs_emit_wait = j == 0;
2749 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2750
2751 if (unlikely(queue->device->use_global_bo_list)) {
2752 pthread_mutex_lock(&queue->device->bo_list.mutex);
2753 bo_list = &queue->device->bo_list.list;
2754 }
2755
2756 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2757 advance, initial_preamble, continue_preamble_cs,
2758 &sem_info, bo_list,
2759 can_patch, base_fence);
2760
2761 if (unlikely(queue->device->use_global_bo_list))
2762 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2763
2764 if (ret) {
2765 radv_loge("failed to submit CS %d\n", i);
2766 abort();
2767 }
2768 fence_emitted = true;
2769 if (queue->device->trace_bo) {
2770 radv_check_gpu_hangs(queue, cs_array[j]);
2771 }
2772 }
2773
2774 radv_free_temp_syncobjs(queue->device,
2775 pSubmits[i].waitSemaphoreCount,
2776 pSubmits[i].pWaitSemaphores);
2777 radv_free_sem_info(&sem_info);
2778 free(cs_array);
2779 }
2780
2781 if (fence) {
2782 if (!fence_emitted) {
2783 result = radv_signal_fence(queue, fence);
2784 if (result != VK_SUCCESS)
2785 return result;
2786 }
2787 fence->submitted = true;
2788 }
2789
2790 return VK_SUCCESS;
2791 }
2792
2793 VkResult radv_QueueWaitIdle(
2794 VkQueue _queue)
2795 {
2796 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2797
2798 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2799 radv_queue_family_to_ring(queue->queue_family_index),
2800 queue->queue_idx);
2801 return VK_SUCCESS;
2802 }
2803
2804 VkResult radv_DeviceWaitIdle(
2805 VkDevice _device)
2806 {
2807 RADV_FROM_HANDLE(radv_device, device, _device);
2808
2809 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2810 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2811 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2812 }
2813 }
2814 return VK_SUCCESS;
2815 }
2816
2817 VkResult radv_EnumerateInstanceExtensionProperties(
2818 const char* pLayerName,
2819 uint32_t* pPropertyCount,
2820 VkExtensionProperties* pProperties)
2821 {
2822 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2823
2824 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2825 if (radv_supported_instance_extensions.extensions[i]) {
2826 vk_outarray_append(&out, prop) {
2827 *prop = radv_instance_extensions[i];
2828 }
2829 }
2830 }
2831
2832 return vk_outarray_status(&out);
2833 }
2834
2835 VkResult radv_EnumerateDeviceExtensionProperties(
2836 VkPhysicalDevice physicalDevice,
2837 const char* pLayerName,
2838 uint32_t* pPropertyCount,
2839 VkExtensionProperties* pProperties)
2840 {
2841 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2842 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2843
2844 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2845 if (device->supported_extensions.extensions[i]) {
2846 vk_outarray_append(&out, prop) {
2847 *prop = radv_device_extensions[i];
2848 }
2849 }
2850 }
2851
2852 return vk_outarray_status(&out);
2853 }
2854
2855 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2856 VkInstance _instance,
2857 const char* pName)
2858 {
2859 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2860
2861 return radv_lookup_entrypoint_checked(pName,
2862 instance ? instance->apiVersion : 0,
2863 instance ? &instance->enabled_extensions : NULL,
2864 NULL);
2865 }
2866
2867 /* The loader wants us to expose a second GetInstanceProcAddr function
2868 * to work around certain LD_PRELOAD issues seen in apps.
2869 */
2870 PUBLIC
2871 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2872 VkInstance instance,
2873 const char* pName);
2874
2875 PUBLIC
2876 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2877 VkInstance instance,
2878 const char* pName)
2879 {
2880 return radv_GetInstanceProcAddr(instance, pName);
2881 }
2882
2883 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2884 VkDevice _device,
2885 const char* pName)
2886 {
2887 RADV_FROM_HANDLE(radv_device, device, _device);
2888
2889 return radv_lookup_entrypoint_checked(pName,
2890 device->instance->apiVersion,
2891 &device->instance->enabled_extensions,
2892 &device->enabled_extensions);
2893 }
2894
2895 bool radv_get_memory_fd(struct radv_device *device,
2896 struct radv_device_memory *memory,
2897 int *pFD)
2898 {
2899 struct radeon_bo_metadata metadata;
2900
2901 if (memory->image) {
2902 radv_init_metadata(device, memory->image, &metadata);
2903 device->ws->buffer_set_metadata(memory->bo, &metadata);
2904 }
2905
2906 return device->ws->buffer_get_fd(device->ws, memory->bo,
2907 pFD);
2908 }
2909
2910 static VkResult radv_alloc_memory(struct radv_device *device,
2911 const VkMemoryAllocateInfo* pAllocateInfo,
2912 const VkAllocationCallbacks* pAllocator,
2913 VkDeviceMemory* pMem)
2914 {
2915 struct radv_device_memory *mem;
2916 VkResult result;
2917 enum radeon_bo_domain domain;
2918 uint32_t flags = 0;
2919 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2920
2921 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2922
2923 if (pAllocateInfo->allocationSize == 0) {
2924 /* Apparently, this is allowed */
2925 *pMem = VK_NULL_HANDLE;
2926 return VK_SUCCESS;
2927 }
2928
2929 const VkImportMemoryFdInfoKHR *import_info =
2930 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2931 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2932 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2933 const VkExportMemoryAllocateInfoKHR *export_info =
2934 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2935 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2936 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2937
2938 const struct wsi_memory_allocate_info *wsi_info =
2939 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2940
2941 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2942 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2943 if (mem == NULL)
2944 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2945
2946 if (wsi_info && wsi_info->implicit_sync)
2947 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2948
2949 if (dedicate_info) {
2950 mem->image = radv_image_from_handle(dedicate_info->image);
2951 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2952 } else {
2953 mem->image = NULL;
2954 mem->buffer = NULL;
2955 }
2956
2957 mem->user_ptr = NULL;
2958
2959 if (import_info) {
2960 assert(import_info->handleType ==
2961 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2962 import_info->handleType ==
2963 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2964 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2965 NULL, NULL);
2966 if (!mem->bo) {
2967 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2968 goto fail;
2969 } else {
2970 close(import_info->fd);
2971 }
2972 } else if (host_ptr_info) {
2973 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2974 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2975 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2976 pAllocateInfo->allocationSize);
2977 if (!mem->bo) {
2978 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2979 goto fail;
2980 } else {
2981 mem->user_ptr = host_ptr_info->pHostPointer;
2982 }
2983 } else {
2984 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2985 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2986 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2987 domain = RADEON_DOMAIN_GTT;
2988 else
2989 domain = RADEON_DOMAIN_VRAM;
2990
2991 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2992 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2993 else
2994 flags |= RADEON_FLAG_CPU_ACCESS;
2995
2996 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2997 flags |= RADEON_FLAG_GTT_WC;
2998
2999 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3000 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3001
3002 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3003 domain, flags);
3004
3005 if (!mem->bo) {
3006 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3007 goto fail;
3008 }
3009 mem->type_index = mem_type_index;
3010 }
3011
3012 result = radv_bo_list_add(device, mem->bo);
3013 if (result != VK_SUCCESS)
3014 goto fail_bo;
3015
3016 *pMem = radv_device_memory_to_handle(mem);
3017
3018 return VK_SUCCESS;
3019
3020 fail_bo:
3021 device->ws->buffer_destroy(mem->bo);
3022 fail:
3023 vk_free2(&device->alloc, pAllocator, mem);
3024
3025 return result;
3026 }
3027
3028 VkResult radv_AllocateMemory(
3029 VkDevice _device,
3030 const VkMemoryAllocateInfo* pAllocateInfo,
3031 const VkAllocationCallbacks* pAllocator,
3032 VkDeviceMemory* pMem)
3033 {
3034 RADV_FROM_HANDLE(radv_device, device, _device);
3035 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3036 }
3037
3038 void radv_FreeMemory(
3039 VkDevice _device,
3040 VkDeviceMemory _mem,
3041 const VkAllocationCallbacks* pAllocator)
3042 {
3043 RADV_FROM_HANDLE(radv_device, device, _device);
3044 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3045
3046 if (mem == NULL)
3047 return;
3048
3049 radv_bo_list_remove(device, mem->bo);
3050 device->ws->buffer_destroy(mem->bo);
3051 mem->bo = NULL;
3052
3053 vk_free2(&device->alloc, pAllocator, mem);
3054 }
3055
3056 VkResult radv_MapMemory(
3057 VkDevice _device,
3058 VkDeviceMemory _memory,
3059 VkDeviceSize offset,
3060 VkDeviceSize size,
3061 VkMemoryMapFlags flags,
3062 void** ppData)
3063 {
3064 RADV_FROM_HANDLE(radv_device, device, _device);
3065 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3066
3067 if (mem == NULL) {
3068 *ppData = NULL;
3069 return VK_SUCCESS;
3070 }
3071
3072 if (mem->user_ptr)
3073 *ppData = mem->user_ptr;
3074 else
3075 *ppData = device->ws->buffer_map(mem->bo);
3076
3077 if (*ppData) {
3078 *ppData += offset;
3079 return VK_SUCCESS;
3080 }
3081
3082 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3083 }
3084
3085 void radv_UnmapMemory(
3086 VkDevice _device,
3087 VkDeviceMemory _memory)
3088 {
3089 RADV_FROM_HANDLE(radv_device, device, _device);
3090 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3091
3092 if (mem == NULL)
3093 return;
3094
3095 if (mem->user_ptr == NULL)
3096 device->ws->buffer_unmap(mem->bo);
3097 }
3098
3099 VkResult radv_FlushMappedMemoryRanges(
3100 VkDevice _device,
3101 uint32_t memoryRangeCount,
3102 const VkMappedMemoryRange* pMemoryRanges)
3103 {
3104 return VK_SUCCESS;
3105 }
3106
3107 VkResult radv_InvalidateMappedMemoryRanges(
3108 VkDevice _device,
3109 uint32_t memoryRangeCount,
3110 const VkMappedMemoryRange* pMemoryRanges)
3111 {
3112 return VK_SUCCESS;
3113 }
3114
3115 void radv_GetBufferMemoryRequirements(
3116 VkDevice _device,
3117 VkBuffer _buffer,
3118 VkMemoryRequirements* pMemoryRequirements)
3119 {
3120 RADV_FROM_HANDLE(radv_device, device, _device);
3121 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3122
3123 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3124
3125 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3126 pMemoryRequirements->alignment = 4096;
3127 else
3128 pMemoryRequirements->alignment = 16;
3129
3130 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3131 }
3132
3133 void radv_GetBufferMemoryRequirements2(
3134 VkDevice device,
3135 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3136 VkMemoryRequirements2KHR* pMemoryRequirements)
3137 {
3138 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3139 &pMemoryRequirements->memoryRequirements);
3140 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3141 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3142 switch (ext->sType) {
3143 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3144 VkMemoryDedicatedRequirementsKHR *req =
3145 (VkMemoryDedicatedRequirementsKHR *) ext;
3146 req->requiresDedicatedAllocation = buffer->shareable;
3147 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3148 break;
3149 }
3150 default:
3151 break;
3152 }
3153 }
3154 }
3155
3156 void radv_GetImageMemoryRequirements(
3157 VkDevice _device,
3158 VkImage _image,
3159 VkMemoryRequirements* pMemoryRequirements)
3160 {
3161 RADV_FROM_HANDLE(radv_device, device, _device);
3162 RADV_FROM_HANDLE(radv_image, image, _image);
3163
3164 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3165
3166 pMemoryRequirements->size = image->size;
3167 pMemoryRequirements->alignment = image->alignment;
3168 }
3169
3170 void radv_GetImageMemoryRequirements2(
3171 VkDevice device,
3172 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3173 VkMemoryRequirements2KHR* pMemoryRequirements)
3174 {
3175 radv_GetImageMemoryRequirements(device, pInfo->image,
3176 &pMemoryRequirements->memoryRequirements);
3177
3178 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3179
3180 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3181 switch (ext->sType) {
3182 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3183 VkMemoryDedicatedRequirementsKHR *req =
3184 (VkMemoryDedicatedRequirementsKHR *) ext;
3185 req->requiresDedicatedAllocation = image->shareable;
3186 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3187 break;
3188 }
3189 default:
3190 break;
3191 }
3192 }
3193 }
3194
3195 void radv_GetImageSparseMemoryRequirements(
3196 VkDevice device,
3197 VkImage image,
3198 uint32_t* pSparseMemoryRequirementCount,
3199 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3200 {
3201 stub();
3202 }
3203
3204 void radv_GetImageSparseMemoryRequirements2(
3205 VkDevice device,
3206 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3207 uint32_t* pSparseMemoryRequirementCount,
3208 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3209 {
3210 stub();
3211 }
3212
3213 void radv_GetDeviceMemoryCommitment(
3214 VkDevice device,
3215 VkDeviceMemory memory,
3216 VkDeviceSize* pCommittedMemoryInBytes)
3217 {
3218 *pCommittedMemoryInBytes = 0;
3219 }
3220
3221 VkResult radv_BindBufferMemory2(VkDevice device,
3222 uint32_t bindInfoCount,
3223 const VkBindBufferMemoryInfoKHR *pBindInfos)
3224 {
3225 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3226 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3227 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3228
3229 if (mem) {
3230 buffer->bo = mem->bo;
3231 buffer->offset = pBindInfos[i].memoryOffset;
3232 } else {
3233 buffer->bo = NULL;
3234 }
3235 }
3236 return VK_SUCCESS;
3237 }
3238
3239 VkResult radv_BindBufferMemory(
3240 VkDevice device,
3241 VkBuffer buffer,
3242 VkDeviceMemory memory,
3243 VkDeviceSize memoryOffset)
3244 {
3245 const VkBindBufferMemoryInfoKHR info = {
3246 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3247 .buffer = buffer,
3248 .memory = memory,
3249 .memoryOffset = memoryOffset
3250 };
3251
3252 return radv_BindBufferMemory2(device, 1, &info);
3253 }
3254
3255 VkResult radv_BindImageMemory2(VkDevice device,
3256 uint32_t bindInfoCount,
3257 const VkBindImageMemoryInfoKHR *pBindInfos)
3258 {
3259 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3260 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3261 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3262
3263 if (mem) {
3264 image->bo = mem->bo;
3265 image->offset = pBindInfos[i].memoryOffset;
3266 } else {
3267 image->bo = NULL;
3268 image->offset = 0;
3269 }
3270 }
3271 return VK_SUCCESS;
3272 }
3273
3274
3275 VkResult radv_BindImageMemory(
3276 VkDevice device,
3277 VkImage image,
3278 VkDeviceMemory memory,
3279 VkDeviceSize memoryOffset)
3280 {
3281 const VkBindImageMemoryInfoKHR info = {
3282 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3283 .image = image,
3284 .memory = memory,
3285 .memoryOffset = memoryOffset
3286 };
3287
3288 return radv_BindImageMemory2(device, 1, &info);
3289 }
3290
3291
3292 static void
3293 radv_sparse_buffer_bind_memory(struct radv_device *device,
3294 const VkSparseBufferMemoryBindInfo *bind)
3295 {
3296 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3297
3298 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3299 struct radv_device_memory *mem = NULL;
3300
3301 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3302 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3303
3304 device->ws->buffer_virtual_bind(buffer->bo,
3305 bind->pBinds[i].resourceOffset,
3306 bind->pBinds[i].size,
3307 mem ? mem->bo : NULL,
3308 bind->pBinds[i].memoryOffset);
3309 }
3310 }
3311
3312 static void
3313 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3314 const VkSparseImageOpaqueMemoryBindInfo *bind)
3315 {
3316 RADV_FROM_HANDLE(radv_image, image, bind->image);
3317
3318 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3319 struct radv_device_memory *mem = NULL;
3320
3321 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3322 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3323
3324 device->ws->buffer_virtual_bind(image->bo,
3325 bind->pBinds[i].resourceOffset,
3326 bind->pBinds[i].size,
3327 mem ? mem->bo : NULL,
3328 bind->pBinds[i].memoryOffset);
3329 }
3330 }
3331
3332 VkResult radv_QueueBindSparse(
3333 VkQueue _queue,
3334 uint32_t bindInfoCount,
3335 const VkBindSparseInfo* pBindInfo,
3336 VkFence _fence)
3337 {
3338 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3339 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3340 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3341 bool fence_emitted = false;
3342 VkResult result;
3343 int ret;
3344
3345 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3346 struct radv_winsys_sem_info sem_info;
3347 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3348 radv_sparse_buffer_bind_memory(queue->device,
3349 pBindInfo[i].pBufferBinds + j);
3350 }
3351
3352 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3353 radv_sparse_image_opaque_bind_memory(queue->device,
3354 pBindInfo[i].pImageOpaqueBinds + j);
3355 }
3356
3357 VkResult result;
3358 result = radv_alloc_sem_info(queue->device->instance,
3359 &sem_info,
3360 pBindInfo[i].waitSemaphoreCount,
3361 pBindInfo[i].pWaitSemaphores,
3362 pBindInfo[i].signalSemaphoreCount,
3363 pBindInfo[i].pSignalSemaphores,
3364 _fence);
3365 if (result != VK_SUCCESS)
3366 return result;
3367
3368 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3369 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3370 &queue->device->empty_cs[queue->queue_family_index],
3371 1, NULL, NULL,
3372 &sem_info, NULL,
3373 false, base_fence);
3374 if (ret) {
3375 radv_loge("failed to submit CS %d\n", i);
3376 abort();
3377 }
3378
3379 fence_emitted = true;
3380 if (fence)
3381 fence->submitted = true;
3382 }
3383
3384 radv_free_sem_info(&sem_info);
3385
3386 }
3387
3388 if (fence) {
3389 if (!fence_emitted) {
3390 result = radv_signal_fence(queue, fence);
3391 if (result != VK_SUCCESS)
3392 return result;
3393 }
3394 fence->submitted = true;
3395 }
3396
3397 return VK_SUCCESS;
3398 }
3399
3400 VkResult radv_CreateFence(
3401 VkDevice _device,
3402 const VkFenceCreateInfo* pCreateInfo,
3403 const VkAllocationCallbacks* pAllocator,
3404 VkFence* pFence)
3405 {
3406 RADV_FROM_HANDLE(radv_device, device, _device);
3407 const VkExportFenceCreateInfoKHR *export =
3408 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3409 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3410 export ? export->handleTypes : 0;
3411
3412 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3413 sizeof(*fence), 8,
3414 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3415
3416 if (!fence)
3417 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3418
3419 fence->fence_wsi = NULL;
3420 fence->submitted = false;
3421 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3422 fence->temp_syncobj = 0;
3423 if (device->always_use_syncobj || handleTypes) {
3424 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3425 if (ret) {
3426 vk_free2(&device->alloc, pAllocator, fence);
3427 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3428 }
3429 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3430 device->ws->signal_syncobj(device->ws, fence->syncobj);
3431 }
3432 fence->fence = NULL;
3433 } else {
3434 fence->fence = device->ws->create_fence();
3435 if (!fence->fence) {
3436 vk_free2(&device->alloc, pAllocator, fence);
3437 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3438 }
3439 fence->syncobj = 0;
3440 }
3441
3442 *pFence = radv_fence_to_handle(fence);
3443
3444 return VK_SUCCESS;
3445 }
3446
3447 void radv_DestroyFence(
3448 VkDevice _device,
3449 VkFence _fence,
3450 const VkAllocationCallbacks* pAllocator)
3451 {
3452 RADV_FROM_HANDLE(radv_device, device, _device);
3453 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3454
3455 if (!fence)
3456 return;
3457
3458 if (fence->temp_syncobj)
3459 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3460 if (fence->syncobj)
3461 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3462 if (fence->fence)
3463 device->ws->destroy_fence(fence->fence);
3464 if (fence->fence_wsi)
3465 fence->fence_wsi->destroy(fence->fence_wsi);
3466 vk_free2(&device->alloc, pAllocator, fence);
3467 }
3468
3469
3470 static uint64_t radv_get_current_time()
3471 {
3472 struct timespec tv;
3473 clock_gettime(CLOCK_MONOTONIC, &tv);
3474 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3475 }
3476
3477 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3478 {
3479 uint64_t current_time = radv_get_current_time();
3480
3481 timeout = MIN2(UINT64_MAX - current_time, timeout);
3482
3483 return current_time + timeout;
3484 }
3485
3486
3487 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3488 {
3489 for (uint32_t i = 0; i < fenceCount; ++i) {
3490 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3491 if (fence->fence == NULL || fence->syncobj ||
3492 fence->temp_syncobj ||
3493 (!fence->signalled && !fence->submitted))
3494 return false;
3495 }
3496 return true;
3497 }
3498
3499 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3500 {
3501 for (uint32_t i = 0; i < fenceCount; ++i) {
3502 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3503 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3504 return false;
3505 }
3506 return true;
3507 }
3508
3509 VkResult radv_WaitForFences(
3510 VkDevice _device,
3511 uint32_t fenceCount,
3512 const VkFence* pFences,
3513 VkBool32 waitAll,
3514 uint64_t timeout)
3515 {
3516 RADV_FROM_HANDLE(radv_device, device, _device);
3517 timeout = radv_get_absolute_timeout(timeout);
3518
3519 if (device->always_use_syncobj &&
3520 radv_all_fences_syncobj(fenceCount, pFences))
3521 {
3522 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3523 if (!handles)
3524 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3525
3526 for (uint32_t i = 0; i < fenceCount; ++i) {
3527 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3528 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3529 }
3530
3531 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3532
3533 free(handles);
3534 return success ? VK_SUCCESS : VK_TIMEOUT;
3535 }
3536
3537 if (!waitAll && fenceCount > 1) {
3538 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3539 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3540 uint32_t wait_count = 0;
3541 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3542 if (!fences)
3543 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3544
3545 for (uint32_t i = 0; i < fenceCount; ++i) {
3546 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3547
3548 if (fence->signalled) {
3549 free(fences);
3550 return VK_SUCCESS;
3551 }
3552
3553 fences[wait_count++] = fence->fence;
3554 }
3555
3556 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3557 waitAll, timeout - radv_get_current_time());
3558
3559 free(fences);
3560 return success ? VK_SUCCESS : VK_TIMEOUT;
3561 }
3562
3563 while(radv_get_current_time() <= timeout) {
3564 for (uint32_t i = 0; i < fenceCount; ++i) {
3565 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3566 return VK_SUCCESS;
3567 }
3568 }
3569 return VK_TIMEOUT;
3570 }
3571
3572 for (uint32_t i = 0; i < fenceCount; ++i) {
3573 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3574 bool expired = false;
3575
3576 if (fence->temp_syncobj) {
3577 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3578 return VK_TIMEOUT;
3579 continue;
3580 }
3581
3582 if (fence->syncobj) {
3583 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3584 return VK_TIMEOUT;
3585 continue;
3586 }
3587
3588 if (fence->signalled)
3589 continue;
3590
3591 if (fence->fence) {
3592 if (!fence->submitted) {
3593 while(radv_get_current_time() <= timeout &&
3594 !fence->submitted)
3595 /* Do nothing */;
3596
3597 if (!fence->submitted)
3598 return VK_TIMEOUT;
3599
3600 /* Recheck as it may have been set by
3601 * submitting operations. */
3602
3603 if (fence->signalled)
3604 continue;
3605 }
3606
3607 expired = device->ws->fence_wait(device->ws,
3608 fence->fence,
3609 true, timeout);
3610 if (!expired)
3611 return VK_TIMEOUT;
3612 }
3613
3614 if (fence->fence_wsi) {
3615 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3616 if (result != VK_SUCCESS)
3617 return result;
3618 }
3619
3620 fence->signalled = true;
3621 }
3622
3623 return VK_SUCCESS;
3624 }
3625
3626 VkResult radv_ResetFences(VkDevice _device,
3627 uint32_t fenceCount,
3628 const VkFence *pFences)
3629 {
3630 RADV_FROM_HANDLE(radv_device, device, _device);
3631
3632 for (unsigned i = 0; i < fenceCount; ++i) {
3633 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3634 fence->submitted = fence->signalled = false;
3635
3636 /* Per spec, we first restore the permanent payload, and then reset, so
3637 * having a temp syncobj should not skip resetting the permanent syncobj. */
3638 if (fence->temp_syncobj) {
3639 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3640 fence->temp_syncobj = 0;
3641 }
3642
3643 if (fence->syncobj) {
3644 device->ws->reset_syncobj(device->ws, fence->syncobj);
3645 }
3646 }
3647
3648 return VK_SUCCESS;
3649 }
3650
3651 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3652 {
3653 RADV_FROM_HANDLE(radv_device, device, _device);
3654 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3655
3656 if (fence->temp_syncobj) {
3657 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3658 return success ? VK_SUCCESS : VK_NOT_READY;
3659 }
3660
3661 if (fence->syncobj) {
3662 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3663 return success ? VK_SUCCESS : VK_NOT_READY;
3664 }
3665
3666 if (fence->signalled)
3667 return VK_SUCCESS;
3668 if (!fence->submitted)
3669 return VK_NOT_READY;
3670 if (fence->fence) {
3671 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3672 return VK_NOT_READY;
3673 }
3674 if (fence->fence_wsi) {
3675 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3676
3677 if (result != VK_SUCCESS) {
3678 if (result == VK_TIMEOUT)
3679 return VK_NOT_READY;
3680 return result;
3681 }
3682 }
3683 return VK_SUCCESS;
3684 }
3685
3686
3687 // Queue semaphore functions
3688
3689 VkResult radv_CreateSemaphore(
3690 VkDevice _device,
3691 const VkSemaphoreCreateInfo* pCreateInfo,
3692 const VkAllocationCallbacks* pAllocator,
3693 VkSemaphore* pSemaphore)
3694 {
3695 RADV_FROM_HANDLE(radv_device, device, _device);
3696 const VkExportSemaphoreCreateInfoKHR *export =
3697 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3698 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3699 export ? export->handleTypes : 0;
3700
3701 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3702 sizeof(*sem), 8,
3703 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3704 if (!sem)
3705 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3706
3707 sem->temp_syncobj = 0;
3708 /* create a syncobject if we are going to export this semaphore */
3709 if (device->always_use_syncobj || handleTypes) {
3710 assert (device->physical_device->rad_info.has_syncobj);
3711 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3712 if (ret) {
3713 vk_free2(&device->alloc, pAllocator, sem);
3714 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3715 }
3716 sem->sem = NULL;
3717 } else {
3718 sem->sem = device->ws->create_sem(device->ws);
3719 if (!sem->sem) {
3720 vk_free2(&device->alloc, pAllocator, sem);
3721 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3722 }
3723 sem->syncobj = 0;
3724 }
3725
3726 *pSemaphore = radv_semaphore_to_handle(sem);
3727 return VK_SUCCESS;
3728 }
3729
3730 void radv_DestroySemaphore(
3731 VkDevice _device,
3732 VkSemaphore _semaphore,
3733 const VkAllocationCallbacks* pAllocator)
3734 {
3735 RADV_FROM_HANDLE(radv_device, device, _device);
3736 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3737 if (!_semaphore)
3738 return;
3739
3740 if (sem->syncobj)
3741 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3742 else
3743 device->ws->destroy_sem(sem->sem);
3744 vk_free2(&device->alloc, pAllocator, sem);
3745 }
3746
3747 VkResult radv_CreateEvent(
3748 VkDevice _device,
3749 const VkEventCreateInfo* pCreateInfo,
3750 const VkAllocationCallbacks* pAllocator,
3751 VkEvent* pEvent)
3752 {
3753 RADV_FROM_HANDLE(radv_device, device, _device);
3754 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3755 sizeof(*event), 8,
3756 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3757
3758 if (!event)
3759 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3760
3761 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3762 RADEON_DOMAIN_GTT,
3763 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3764 if (!event->bo) {
3765 vk_free2(&device->alloc, pAllocator, event);
3766 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3767 }
3768
3769 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3770
3771 *pEvent = radv_event_to_handle(event);
3772
3773 return VK_SUCCESS;
3774 }
3775
3776 void radv_DestroyEvent(
3777 VkDevice _device,
3778 VkEvent _event,
3779 const VkAllocationCallbacks* pAllocator)
3780 {
3781 RADV_FROM_HANDLE(radv_device, device, _device);
3782 RADV_FROM_HANDLE(radv_event, event, _event);
3783
3784 if (!event)
3785 return;
3786 device->ws->buffer_destroy(event->bo);
3787 vk_free2(&device->alloc, pAllocator, event);
3788 }
3789
3790 VkResult radv_GetEventStatus(
3791 VkDevice _device,
3792 VkEvent _event)
3793 {
3794 RADV_FROM_HANDLE(radv_event, event, _event);
3795
3796 if (*event->map == 1)
3797 return VK_EVENT_SET;
3798 return VK_EVENT_RESET;
3799 }
3800
3801 VkResult radv_SetEvent(
3802 VkDevice _device,
3803 VkEvent _event)
3804 {
3805 RADV_FROM_HANDLE(radv_event, event, _event);
3806 *event->map = 1;
3807
3808 return VK_SUCCESS;
3809 }
3810
3811 VkResult radv_ResetEvent(
3812 VkDevice _device,
3813 VkEvent _event)
3814 {
3815 RADV_FROM_HANDLE(radv_event, event, _event);
3816 *event->map = 0;
3817
3818 return VK_SUCCESS;
3819 }
3820
3821 VkResult radv_CreateBuffer(
3822 VkDevice _device,
3823 const VkBufferCreateInfo* pCreateInfo,
3824 const VkAllocationCallbacks* pAllocator,
3825 VkBuffer* pBuffer)
3826 {
3827 RADV_FROM_HANDLE(radv_device, device, _device);
3828 struct radv_buffer *buffer;
3829
3830 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3831
3832 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3833 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3834 if (buffer == NULL)
3835 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3836
3837 buffer->size = pCreateInfo->size;
3838 buffer->usage = pCreateInfo->usage;
3839 buffer->bo = NULL;
3840 buffer->offset = 0;
3841 buffer->flags = pCreateInfo->flags;
3842
3843 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3844 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3845
3846 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3847 buffer->bo = device->ws->buffer_create(device->ws,
3848 align64(buffer->size, 4096),
3849 4096, 0, RADEON_FLAG_VIRTUAL);
3850 if (!buffer->bo) {
3851 vk_free2(&device->alloc, pAllocator, buffer);
3852 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3853 }
3854 }
3855
3856 *pBuffer = radv_buffer_to_handle(buffer);
3857
3858 return VK_SUCCESS;
3859 }
3860
3861 void radv_DestroyBuffer(
3862 VkDevice _device,
3863 VkBuffer _buffer,
3864 const VkAllocationCallbacks* pAllocator)
3865 {
3866 RADV_FROM_HANDLE(radv_device, device, _device);
3867 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3868
3869 if (!buffer)
3870 return;
3871
3872 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3873 device->ws->buffer_destroy(buffer->bo);
3874
3875 vk_free2(&device->alloc, pAllocator, buffer);
3876 }
3877
3878 static inline unsigned
3879 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3880 {
3881 if (stencil)
3882 return image->surface.u.legacy.stencil_tiling_index[level];
3883 else
3884 return image->surface.u.legacy.tiling_index[level];
3885 }
3886
3887 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3888 {
3889 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3890 }
3891
3892 static uint32_t
3893 radv_init_dcc_control_reg(struct radv_device *device,
3894 struct radv_image_view *iview)
3895 {
3896 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3897 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3898 unsigned max_compressed_block_size;
3899 unsigned independent_64b_blocks;
3900
3901 if (device->physical_device->rad_info.chip_class < VI)
3902 return 0;
3903
3904 if (iview->image->info.samples > 1) {
3905 if (iview->image->surface.bpe == 1)
3906 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3907 else if (iview->image->surface.bpe == 2)
3908 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3909 }
3910
3911 if (!device->physical_device->rad_info.has_dedicated_vram) {
3912 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3913 * dGPU and 64 for APU because all of our APUs to date use
3914 * DIMMs which have a request granularity size of 64B while all
3915 * other chips have a 32B request size.
3916 */
3917 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3918 }
3919
3920 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3921 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3922 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3923 /* If this DCC image is potentially going to be used in texture
3924 * fetches, we need some special settings.
3925 */
3926 independent_64b_blocks = 1;
3927 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3928 } else {
3929 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3930 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3931 * big as possible for better compression state.
3932 */
3933 independent_64b_blocks = 0;
3934 max_compressed_block_size = max_uncompressed_block_size;
3935 }
3936
3937 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3938 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3939 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3940 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3941 }
3942
3943 static void
3944 radv_initialise_color_surface(struct radv_device *device,
3945 struct radv_color_buffer_info *cb,
3946 struct radv_image_view *iview)
3947 {
3948 const struct vk_format_description *desc;
3949 unsigned ntype, format, swap, endian;
3950 unsigned blend_clamp = 0, blend_bypass = 0;
3951 uint64_t va;
3952 const struct radeon_surf *surf = &iview->image->surface;
3953
3954 desc = vk_format_description(iview->vk_format);
3955
3956 memset(cb, 0, sizeof(*cb));
3957
3958 /* Intensity is implemented as Red, so treat it that way. */
3959 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3960
3961 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3962
3963 cb->cb_color_base = va >> 8;
3964
3965 if (device->physical_device->rad_info.chip_class >= GFX9) {
3966 struct gfx9_surf_meta_flags meta;
3967 if (iview->image->dcc_offset)
3968 meta = iview->image->surface.u.gfx9.dcc;
3969 else
3970 meta = iview->image->surface.u.gfx9.cmask;
3971
3972 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3973 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3974 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3975 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3976
3977 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3978 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3979 } else {
3980 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3981 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3982
3983 cb->cb_color_base += level_info->offset >> 8;
3984 if (level_info->mode == RADEON_SURF_MODE_2D)
3985 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3986
3987 pitch_tile_max = level_info->nblk_x / 8 - 1;
3988 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3989 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3990
3991 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3992 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3993 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3994
3995 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3996
3997 if (radv_image_has_fmask(iview->image)) {
3998 if (device->physical_device->rad_info.chip_class >= CIK)
3999 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4000 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4001 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4002 } else {
4003 /* This must be set for fast clear to work without FMASK. */
4004 if (device->physical_device->rad_info.chip_class >= CIK)
4005 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4006 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4007 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4008 }
4009 }
4010
4011 /* CMASK variables */
4012 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4013 va += iview->image->cmask.offset;
4014 cb->cb_color_cmask = va >> 8;
4015
4016 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4017 va += iview->image->dcc_offset;
4018 cb->cb_dcc_base = va >> 8;
4019 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4020
4021 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4022 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4023 S_028C6C_SLICE_MAX(max_slice);
4024
4025 if (iview->image->info.samples > 1) {
4026 unsigned log_samples = util_logbase2(iview->image->info.samples);
4027
4028 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4029 S_028C74_NUM_FRAGMENTS(log_samples);
4030 }
4031
4032 if (radv_image_has_fmask(iview->image)) {
4033 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4034 cb->cb_color_fmask = va >> 8;
4035 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4036 } else {
4037 cb->cb_color_fmask = cb->cb_color_base;
4038 }
4039
4040 ntype = radv_translate_color_numformat(iview->vk_format,
4041 desc,
4042 vk_format_get_first_non_void_channel(iview->vk_format));
4043 format = radv_translate_colorformat(iview->vk_format);
4044 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4045 radv_finishme("Illegal color\n");
4046 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4047 endian = radv_colorformat_endian_swap(format);
4048
4049 /* blend clamp should be set for all NORM/SRGB types */
4050 if (ntype == V_028C70_NUMBER_UNORM ||
4051 ntype == V_028C70_NUMBER_SNORM ||
4052 ntype == V_028C70_NUMBER_SRGB)
4053 blend_clamp = 1;
4054
4055 /* set blend bypass according to docs if SINT/UINT or
4056 8/24 COLOR variants */
4057 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4058 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4059 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4060 blend_clamp = 0;
4061 blend_bypass = 1;
4062 }
4063 #if 0
4064 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4065 (format == V_028C70_COLOR_8 ||
4066 format == V_028C70_COLOR_8_8 ||
4067 format == V_028C70_COLOR_8_8_8_8))
4068 ->color_is_int8 = true;
4069 #endif
4070 cb->cb_color_info = S_028C70_FORMAT(format) |
4071 S_028C70_COMP_SWAP(swap) |
4072 S_028C70_BLEND_CLAMP(blend_clamp) |
4073 S_028C70_BLEND_BYPASS(blend_bypass) |
4074 S_028C70_SIMPLE_FLOAT(1) |
4075 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4076 ntype != V_028C70_NUMBER_SNORM &&
4077 ntype != V_028C70_NUMBER_SRGB &&
4078 format != V_028C70_COLOR_8_24 &&
4079 format != V_028C70_COLOR_24_8) |
4080 S_028C70_NUMBER_TYPE(ntype) |
4081 S_028C70_ENDIAN(endian);
4082 if (radv_image_has_fmask(iview->image)) {
4083 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4084 if (device->physical_device->rad_info.chip_class == SI) {
4085 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4086 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4087 }
4088 }
4089
4090 if (radv_image_has_cmask(iview->image) &&
4091 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4092 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4093
4094 if (radv_dcc_enabled(iview->image, iview->base_mip))
4095 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4096
4097 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4098
4099 /* This must be set for fast clear to work without FMASK. */
4100 if (!radv_image_has_fmask(iview->image) &&
4101 device->physical_device->rad_info.chip_class == SI) {
4102 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4103 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4104 }
4105
4106 if (device->physical_device->rad_info.chip_class >= GFX9) {
4107 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4108 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4109
4110 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4111 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4112 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4113 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4114 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4115 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4116 }
4117 }
4118
4119 static unsigned
4120 radv_calc_decompress_on_z_planes(struct radv_device *device,
4121 struct radv_image_view *iview)
4122 {
4123 unsigned max_zplanes = 0;
4124
4125 assert(radv_image_is_tc_compat_htile(iview->image));
4126
4127 if (device->physical_device->rad_info.chip_class >= GFX9) {
4128 /* Default value for 32-bit depth surfaces. */
4129 max_zplanes = 4;
4130
4131 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4132 iview->image->info.samples > 1)
4133 max_zplanes = 2;
4134
4135 max_zplanes = max_zplanes + 1;
4136 } else {
4137 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4138 /* Do not enable Z plane compression for 16-bit depth
4139 * surfaces because isn't supported on GFX8. Only
4140 * 32-bit depth surfaces are supported by the hardware.
4141 * This allows to maintain shader compatibility and to
4142 * reduce the number of depth decompressions.
4143 */
4144 max_zplanes = 1;
4145 } else {
4146 if (iview->image->info.samples <= 1)
4147 max_zplanes = 5;
4148 else if (iview->image->info.samples <= 4)
4149 max_zplanes = 3;
4150 else
4151 max_zplanes = 2;
4152 }
4153 }
4154
4155 return max_zplanes;
4156 }
4157
4158 static void
4159 radv_initialise_ds_surface(struct radv_device *device,
4160 struct radv_ds_buffer_info *ds,
4161 struct radv_image_view *iview)
4162 {
4163 unsigned level = iview->base_mip;
4164 unsigned format, stencil_format;
4165 uint64_t va, s_offs, z_offs;
4166 bool stencil_only = false;
4167 memset(ds, 0, sizeof(*ds));
4168 switch (iview->image->vk_format) {
4169 case VK_FORMAT_D24_UNORM_S8_UINT:
4170 case VK_FORMAT_X8_D24_UNORM_PACK32:
4171 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4172 ds->offset_scale = 2.0f;
4173 break;
4174 case VK_FORMAT_D16_UNORM:
4175 case VK_FORMAT_D16_UNORM_S8_UINT:
4176 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4177 ds->offset_scale = 4.0f;
4178 break;
4179 case VK_FORMAT_D32_SFLOAT:
4180 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4181 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4182 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4183 ds->offset_scale = 1.0f;
4184 break;
4185 case VK_FORMAT_S8_UINT:
4186 stencil_only = true;
4187 break;
4188 default:
4189 break;
4190 }
4191
4192 format = radv_translate_dbformat(iview->image->vk_format);
4193 stencil_format = iview->image->surface.has_stencil ?
4194 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4195
4196 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4197 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4198 S_028008_SLICE_MAX(max_slice);
4199
4200 ds->db_htile_data_base = 0;
4201 ds->db_htile_surface = 0;
4202
4203 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4204 s_offs = z_offs = va;
4205
4206 if (device->physical_device->rad_info.chip_class >= GFX9) {
4207 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4208 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4209
4210 ds->db_z_info = S_028038_FORMAT(format) |
4211 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4212 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4213 S_028038_MAXMIP(iview->image->info.levels - 1) |
4214 S_028038_ZRANGE_PRECISION(1);
4215 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4216 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4217
4218 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4219 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4220 ds->db_depth_view |= S_028008_MIPID(level);
4221
4222 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4223 S_02801C_Y_MAX(iview->image->info.height - 1);
4224
4225 if (radv_htile_enabled(iview->image, level)) {
4226 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4227
4228 if (radv_image_is_tc_compat_htile(iview->image)) {
4229 unsigned max_zplanes =
4230 radv_calc_decompress_on_z_planes(device, iview);
4231
4232 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4233 S_028038_ITERATE_FLUSH(1);
4234 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4235 }
4236
4237 if (!iview->image->surface.has_stencil)
4238 /* Use all of the htile_buffer for depth if there's no stencil. */
4239 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4240 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4241 iview->image->htile_offset;
4242 ds->db_htile_data_base = va >> 8;
4243 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4244 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4245 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4246 }
4247 } else {
4248 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4249
4250 if (stencil_only)
4251 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4252
4253 z_offs += iview->image->surface.u.legacy.level[level].offset;
4254 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4255
4256 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4257 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4258 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4259
4260 if (iview->image->info.samples > 1)
4261 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4262
4263 if (device->physical_device->rad_info.chip_class >= CIK) {
4264 struct radeon_info *info = &device->physical_device->rad_info;
4265 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4266 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4267 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4268 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4269 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4270 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4271
4272 if (stencil_only)
4273 tile_mode = stencil_tile_mode;
4274
4275 ds->db_depth_info |=
4276 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4277 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4278 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4279 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4280 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4281 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4282 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4283 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4284 } else {
4285 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4286 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4287 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4288 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4289 if (stencil_only)
4290 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4291 }
4292
4293 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4294 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4295 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4296
4297 if (radv_htile_enabled(iview->image, level)) {
4298 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4299
4300 if (!iview->image->surface.has_stencil &&
4301 !radv_image_is_tc_compat_htile(iview->image))
4302 /* Use all of the htile_buffer for depth if there's no stencil. */
4303 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4304
4305 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4306 iview->image->htile_offset;
4307 ds->db_htile_data_base = va >> 8;
4308 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4309
4310 if (radv_image_is_tc_compat_htile(iview->image)) {
4311 unsigned max_zplanes =
4312 radv_calc_decompress_on_z_planes(device, iview);
4313
4314 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4315 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4316 }
4317 }
4318 }
4319
4320 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4321 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4322 }
4323
4324 VkResult radv_CreateFramebuffer(
4325 VkDevice _device,
4326 const VkFramebufferCreateInfo* pCreateInfo,
4327 const VkAllocationCallbacks* pAllocator,
4328 VkFramebuffer* pFramebuffer)
4329 {
4330 RADV_FROM_HANDLE(radv_device, device, _device);
4331 struct radv_framebuffer *framebuffer;
4332
4333 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4334
4335 size_t size = sizeof(*framebuffer) +
4336 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4337 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4338 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4339 if (framebuffer == NULL)
4340 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4341
4342 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4343 framebuffer->width = pCreateInfo->width;
4344 framebuffer->height = pCreateInfo->height;
4345 framebuffer->layers = pCreateInfo->layers;
4346 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4347 VkImageView _iview = pCreateInfo->pAttachments[i];
4348 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4349 framebuffer->attachments[i].attachment = iview;
4350 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4351 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4352 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4353 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4354 }
4355 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4356 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4357 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4358 }
4359
4360 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4361 return VK_SUCCESS;
4362 }
4363
4364 void radv_DestroyFramebuffer(
4365 VkDevice _device,
4366 VkFramebuffer _fb,
4367 const VkAllocationCallbacks* pAllocator)
4368 {
4369 RADV_FROM_HANDLE(radv_device, device, _device);
4370 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4371
4372 if (!fb)
4373 return;
4374 vk_free2(&device->alloc, pAllocator, fb);
4375 }
4376
4377 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4378 {
4379 switch (address_mode) {
4380 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4381 return V_008F30_SQ_TEX_WRAP;
4382 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4383 return V_008F30_SQ_TEX_MIRROR;
4384 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4385 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4386 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4387 return V_008F30_SQ_TEX_CLAMP_BORDER;
4388 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4389 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4390 default:
4391 unreachable("illegal tex wrap mode");
4392 break;
4393 }
4394 }
4395
4396 static unsigned
4397 radv_tex_compare(VkCompareOp op)
4398 {
4399 switch (op) {
4400 case VK_COMPARE_OP_NEVER:
4401 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4402 case VK_COMPARE_OP_LESS:
4403 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4404 case VK_COMPARE_OP_EQUAL:
4405 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4406 case VK_COMPARE_OP_LESS_OR_EQUAL:
4407 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4408 case VK_COMPARE_OP_GREATER:
4409 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4410 case VK_COMPARE_OP_NOT_EQUAL:
4411 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4412 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4413 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4414 case VK_COMPARE_OP_ALWAYS:
4415 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4416 default:
4417 unreachable("illegal compare mode");
4418 break;
4419 }
4420 }
4421
4422 static unsigned
4423 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4424 {
4425 switch (filter) {
4426 case VK_FILTER_NEAREST:
4427 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4428 V_008F38_SQ_TEX_XY_FILTER_POINT);
4429 case VK_FILTER_LINEAR:
4430 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4431 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4432 case VK_FILTER_CUBIC_IMG:
4433 default:
4434 fprintf(stderr, "illegal texture filter");
4435 return 0;
4436 }
4437 }
4438
4439 static unsigned
4440 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4441 {
4442 switch (mode) {
4443 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4444 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4445 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4446 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4447 default:
4448 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4449 }
4450 }
4451
4452 static unsigned
4453 radv_tex_bordercolor(VkBorderColor bcolor)
4454 {
4455 switch (bcolor) {
4456 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4457 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4458 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4459 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4460 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4461 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4462 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4463 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4464 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4465 default:
4466 break;
4467 }
4468 return 0;
4469 }
4470
4471 static unsigned
4472 radv_tex_aniso_filter(unsigned filter)
4473 {
4474 if (filter < 2)
4475 return 0;
4476 if (filter < 4)
4477 return 1;
4478 if (filter < 8)
4479 return 2;
4480 if (filter < 16)
4481 return 3;
4482 return 4;
4483 }
4484
4485 static unsigned
4486 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4487 {
4488 switch (mode) {
4489 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4490 return SQ_IMG_FILTER_MODE_BLEND;
4491 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4492 return SQ_IMG_FILTER_MODE_MIN;
4493 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4494 return SQ_IMG_FILTER_MODE_MAX;
4495 default:
4496 break;
4497 }
4498 return 0;
4499 }
4500
4501 static uint32_t
4502 radv_get_max_anisotropy(struct radv_device *device,
4503 const VkSamplerCreateInfo *pCreateInfo)
4504 {
4505 if (device->force_aniso >= 0)
4506 return device->force_aniso;
4507
4508 if (pCreateInfo->anisotropyEnable &&
4509 pCreateInfo->maxAnisotropy > 1.0f)
4510 return (uint32_t)pCreateInfo->maxAnisotropy;
4511
4512 return 0;
4513 }
4514
4515 static void
4516 radv_init_sampler(struct radv_device *device,
4517 struct radv_sampler *sampler,
4518 const VkSamplerCreateInfo *pCreateInfo)
4519 {
4520 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4521 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4522 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4523 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4524
4525 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4526 vk_find_struct_const(pCreateInfo->pNext,
4527 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4528 if (sampler_reduction)
4529 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4530
4531 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4532 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4533 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4534 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4535 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4536 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4537 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4538 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4539 S_008F30_DISABLE_CUBE_WRAP(0) |
4540 S_008F30_COMPAT_MODE(is_vi) |
4541 S_008F30_FILTER_MODE(filter_mode));
4542 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4543 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4544 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4545 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4546 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4547 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4548 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4549 S_008F38_MIP_POINT_PRECLAMP(0) |
4550 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4551 S_008F38_FILTER_PREC_FIX(1) |
4552 S_008F38_ANISO_OVERRIDE(is_vi));
4553 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4554 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4555 }
4556
4557 VkResult radv_CreateSampler(
4558 VkDevice _device,
4559 const VkSamplerCreateInfo* pCreateInfo,
4560 const VkAllocationCallbacks* pAllocator,
4561 VkSampler* pSampler)
4562 {
4563 RADV_FROM_HANDLE(radv_device, device, _device);
4564 struct radv_sampler *sampler;
4565
4566 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4567
4568 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4569 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4570 if (!sampler)
4571 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4572
4573 radv_init_sampler(device, sampler, pCreateInfo);
4574 *pSampler = radv_sampler_to_handle(sampler);
4575
4576 return VK_SUCCESS;
4577 }
4578
4579 void radv_DestroySampler(
4580 VkDevice _device,
4581 VkSampler _sampler,
4582 const VkAllocationCallbacks* pAllocator)
4583 {
4584 RADV_FROM_HANDLE(radv_device, device, _device);
4585 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4586
4587 if (!sampler)
4588 return;
4589 vk_free2(&device->alloc, pAllocator, sampler);
4590 }
4591
4592 /* vk_icd.h does not declare this function, so we declare it here to
4593 * suppress Wmissing-prototypes.
4594 */
4595 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4596 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4597
4598 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4599 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4600 {
4601 /* For the full details on loader interface versioning, see
4602 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4603 * What follows is a condensed summary, to help you navigate the large and
4604 * confusing official doc.
4605 *
4606 * - Loader interface v0 is incompatible with later versions. We don't
4607 * support it.
4608 *
4609 * - In loader interface v1:
4610 * - The first ICD entrypoint called by the loader is
4611 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4612 * entrypoint.
4613 * - The ICD must statically expose no other Vulkan symbol unless it is
4614 * linked with -Bsymbolic.
4615 * - Each dispatchable Vulkan handle created by the ICD must be
4616 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4617 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4618 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4619 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4620 * such loader-managed surfaces.
4621 *
4622 * - Loader interface v2 differs from v1 in:
4623 * - The first ICD entrypoint called by the loader is
4624 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4625 * statically expose this entrypoint.
4626 *
4627 * - Loader interface v3 differs from v2 in:
4628 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4629 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4630 * because the loader no longer does so.
4631 */
4632 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4633 return VK_SUCCESS;
4634 }
4635
4636 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4637 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4638 int *pFD)
4639 {
4640 RADV_FROM_HANDLE(radv_device, device, _device);
4641 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4642
4643 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4644
4645 /* At the moment, we support only the below handle types. */
4646 assert(pGetFdInfo->handleType ==
4647 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4648 pGetFdInfo->handleType ==
4649 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4650
4651 bool ret = radv_get_memory_fd(device, memory, pFD);
4652 if (ret == false)
4653 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4654 return VK_SUCCESS;
4655 }
4656
4657 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4658 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4659 int fd,
4660 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4661 {
4662 RADV_FROM_HANDLE(radv_device, device, _device);
4663
4664 switch (handleType) {
4665 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4666 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4667 return VK_SUCCESS;
4668
4669 default:
4670 /* The valid usage section for this function says:
4671 *
4672 * "handleType must not be one of the handle types defined as
4673 * opaque."
4674 *
4675 * So opaque handle types fall into the default "unsupported" case.
4676 */
4677 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4678 }
4679 }
4680
4681 static VkResult radv_import_opaque_fd(struct radv_device *device,
4682 int fd,
4683 uint32_t *syncobj)
4684 {
4685 uint32_t syncobj_handle = 0;
4686 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4687 if (ret != 0)
4688 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4689
4690 if (*syncobj)
4691 device->ws->destroy_syncobj(device->ws, *syncobj);
4692
4693 *syncobj = syncobj_handle;
4694 close(fd);
4695
4696 return VK_SUCCESS;
4697 }
4698
4699 static VkResult radv_import_sync_fd(struct radv_device *device,
4700 int fd,
4701 uint32_t *syncobj)
4702 {
4703 /* If we create a syncobj we do it locally so that if we have an error, we don't
4704 * leave a syncobj in an undetermined state in the fence. */
4705 uint32_t syncobj_handle = *syncobj;
4706 if (!syncobj_handle) {
4707 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4708 if (ret) {
4709 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4710 }
4711 }
4712
4713 if (fd == -1) {
4714 device->ws->signal_syncobj(device->ws, syncobj_handle);
4715 } else {
4716 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4717 if (ret != 0)
4718 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4719 }
4720
4721 *syncobj = syncobj_handle;
4722 if (fd != -1)
4723 close(fd);
4724
4725 return VK_SUCCESS;
4726 }
4727
4728 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4729 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4730 {
4731 RADV_FROM_HANDLE(radv_device, device, _device);
4732 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4733 uint32_t *syncobj_dst = NULL;
4734
4735 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4736 syncobj_dst = &sem->temp_syncobj;
4737 } else {
4738 syncobj_dst = &sem->syncobj;
4739 }
4740
4741 switch(pImportSemaphoreFdInfo->handleType) {
4742 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4743 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4744 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4745 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4746 default:
4747 unreachable("Unhandled semaphore handle type");
4748 }
4749 }
4750
4751 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4752 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4753 int *pFd)
4754 {
4755 RADV_FROM_HANDLE(radv_device, device, _device);
4756 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4757 int ret;
4758 uint32_t syncobj_handle;
4759
4760 if (sem->temp_syncobj)
4761 syncobj_handle = sem->temp_syncobj;
4762 else
4763 syncobj_handle = sem->syncobj;
4764
4765 switch(pGetFdInfo->handleType) {
4766 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4767 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4768 break;
4769 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4770 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4771 if (!ret) {
4772 if (sem->temp_syncobj) {
4773 close (sem->temp_syncobj);
4774 sem->temp_syncobj = 0;
4775 } else {
4776 device->ws->reset_syncobj(device->ws, syncobj_handle);
4777 }
4778 }
4779 break;
4780 default:
4781 unreachable("Unhandled semaphore handle type");
4782 }
4783
4784 if (ret)
4785 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4786 return VK_SUCCESS;
4787 }
4788
4789 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4790 VkPhysicalDevice physicalDevice,
4791 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4792 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4793 {
4794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4795
4796 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4797 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4798 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4799 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4800 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4801 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4802 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4803 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4804 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4805 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4806 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4807 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4808 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4809 } else {
4810 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4811 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4812 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4813 }
4814 }
4815
4816 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4817 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4818 {
4819 RADV_FROM_HANDLE(radv_device, device, _device);
4820 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4821 uint32_t *syncobj_dst = NULL;
4822
4823
4824 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4825 syncobj_dst = &fence->temp_syncobj;
4826 } else {
4827 syncobj_dst = &fence->syncobj;
4828 }
4829
4830 switch(pImportFenceFdInfo->handleType) {
4831 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4832 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4833 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4834 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4835 default:
4836 unreachable("Unhandled fence handle type");
4837 }
4838 }
4839
4840 VkResult radv_GetFenceFdKHR(VkDevice _device,
4841 const VkFenceGetFdInfoKHR *pGetFdInfo,
4842 int *pFd)
4843 {
4844 RADV_FROM_HANDLE(radv_device, device, _device);
4845 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4846 int ret;
4847 uint32_t syncobj_handle;
4848
4849 if (fence->temp_syncobj)
4850 syncobj_handle = fence->temp_syncobj;
4851 else
4852 syncobj_handle = fence->syncobj;
4853
4854 switch(pGetFdInfo->handleType) {
4855 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4856 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4857 break;
4858 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4859 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4860 if (!ret) {
4861 if (fence->temp_syncobj) {
4862 close (fence->temp_syncobj);
4863 fence->temp_syncobj = 0;
4864 } else {
4865 device->ws->reset_syncobj(device->ws, syncobj_handle);
4866 }
4867 }
4868 break;
4869 default:
4870 unreachable("Unhandled fence handle type");
4871 }
4872
4873 if (ret)
4874 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4875 return VK_SUCCESS;
4876 }
4877
4878 void radv_GetPhysicalDeviceExternalFenceProperties(
4879 VkPhysicalDevice physicalDevice,
4880 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4881 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4882 {
4883 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4884
4885 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4886 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4887 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4888 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4889 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4890 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4891 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4892 } else {
4893 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4894 pExternalFenceProperties->compatibleHandleTypes = 0;
4895 pExternalFenceProperties->externalFenceFeatures = 0;
4896 }
4897 }
4898
4899 VkResult
4900 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4901 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4902 const VkAllocationCallbacks* pAllocator,
4903 VkDebugReportCallbackEXT* pCallback)
4904 {
4905 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4906 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4907 pCreateInfo, pAllocator, &instance->alloc,
4908 pCallback);
4909 }
4910
4911 void
4912 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4913 VkDebugReportCallbackEXT _callback,
4914 const VkAllocationCallbacks* pAllocator)
4915 {
4916 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4917 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4918 _callback, pAllocator, &instance->alloc);
4919 }
4920
4921 void
4922 radv_DebugReportMessageEXT(VkInstance _instance,
4923 VkDebugReportFlagsEXT flags,
4924 VkDebugReportObjectTypeEXT objectType,
4925 uint64_t object,
4926 size_t location,
4927 int32_t messageCode,
4928 const char* pLayerPrefix,
4929 const char* pMessage)
4930 {
4931 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4932 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4933 object, location, messageCode, pLayerPrefix, pMessage);
4934 }
4935
4936 void
4937 radv_GetDeviceGroupPeerMemoryFeatures(
4938 VkDevice device,
4939 uint32_t heapIndex,
4940 uint32_t localDeviceIndex,
4941 uint32_t remoteDeviceIndex,
4942 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4943 {
4944 assert(localDeviceIndex == remoteDeviceIndex);
4945
4946 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4947 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4948 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4949 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4950 }