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radv: always check the return error when submitting a CS
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {NULL, 0}
440 };
441
442 const char *
443 radv_get_debug_option_name(int id)
444 {
445 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
446 return radv_debug_options[id].string;
447 }
448
449 static const struct debug_control radv_perftest_options[] = {
450 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
451 {"sisched", RADV_PERFTEST_SISCHED},
452 {"localbos", RADV_PERFTEST_LOCAL_BOS},
453 {"binning", RADV_PERFTEST_BINNING},
454 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
455 {NULL, 0}
456 };
457
458 const char *
459 radv_get_perftest_option_name(int id)
460 {
461 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
462 return radv_perftest_options[id].string;
463 }
464
465 static void
466 radv_handle_per_app_options(struct radv_instance *instance,
467 const VkApplicationInfo *info)
468 {
469 const char *name = info ? info->pApplicationName : NULL;
470
471 if (!name)
472 return;
473
474 if (!strcmp(name, "Talos - Linux - 32bit") ||
475 !strcmp(name, "Talos - Linux - 64bit")) {
476 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
477 /* Force enable LLVM sisched for Talos because it looks
478 * safe and it gives few more FPS.
479 */
480 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
481 }
482 }
483 }
484
485 static int radv_get_instance_extension_index(const char *name)
486 {
487 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
488 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
489 return i;
490 }
491 return -1;
492 }
493
494
495 VkResult radv_CreateInstance(
496 const VkInstanceCreateInfo* pCreateInfo,
497 const VkAllocationCallbacks* pAllocator,
498 VkInstance* pInstance)
499 {
500 struct radv_instance *instance;
501 VkResult result;
502
503 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
504
505 uint32_t client_version;
506 if (pCreateInfo->pApplicationInfo &&
507 pCreateInfo->pApplicationInfo->apiVersion != 0) {
508 client_version = pCreateInfo->pApplicationInfo->apiVersion;
509 } else {
510 radv_EnumerateInstanceVersion(&client_version);
511 }
512
513 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
514 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
515 if (!instance)
516 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
517
518 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
519
520 if (pAllocator)
521 instance->alloc = *pAllocator;
522 else
523 instance->alloc = default_alloc;
524
525 instance->apiVersion = client_version;
526 instance->physicalDeviceCount = -1;
527
528 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
529 radv_debug_options);
530
531 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
532 radv_perftest_options);
533
534
535 if (instance->debug_flags & RADV_DEBUG_STARTUP)
536 radv_logi("Created an instance");
537
538 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
539 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
540 int index = radv_get_instance_extension_index(ext_name);
541
542 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
543 vk_free2(&default_alloc, pAllocator, instance);
544 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
545 }
546
547 instance->enabled_extensions.extensions[index] = true;
548 }
549
550 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
551 if (result != VK_SUCCESS) {
552 vk_free2(&default_alloc, pAllocator, instance);
553 return vk_error(instance, result);
554 }
555
556 _mesa_locale_init();
557
558 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
559
560 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
561
562 *pInstance = radv_instance_to_handle(instance);
563
564 return VK_SUCCESS;
565 }
566
567 void radv_DestroyInstance(
568 VkInstance _instance,
569 const VkAllocationCallbacks* pAllocator)
570 {
571 RADV_FROM_HANDLE(radv_instance, instance, _instance);
572
573 if (!instance)
574 return;
575
576 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
577 radv_physical_device_finish(instance->physicalDevices + i);
578 }
579
580 VG(VALGRIND_DESTROY_MEMPOOL(instance));
581
582 _mesa_locale_fini();
583
584 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
585
586 vk_free(&instance->alloc, instance);
587 }
588
589 static VkResult
590 radv_enumerate_devices(struct radv_instance *instance)
591 {
592 /* TODO: Check for more devices ? */
593 drmDevicePtr devices[8];
594 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
595 int max_devices;
596
597 instance->physicalDeviceCount = 0;
598
599 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
600
601 if (instance->debug_flags & RADV_DEBUG_STARTUP)
602 radv_logi("Found %d drm nodes", max_devices);
603
604 if (max_devices < 1)
605 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
606
607 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
608 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
609 devices[i]->bustype == DRM_BUS_PCI &&
610 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
611
612 result = radv_physical_device_init(instance->physicalDevices +
613 instance->physicalDeviceCount,
614 instance,
615 devices[i]);
616 if (result == VK_SUCCESS)
617 ++instance->physicalDeviceCount;
618 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
619 break;
620 }
621 }
622 drmFreeDevices(devices, max_devices);
623
624 return result;
625 }
626
627 VkResult radv_EnumeratePhysicalDevices(
628 VkInstance _instance,
629 uint32_t* pPhysicalDeviceCount,
630 VkPhysicalDevice* pPhysicalDevices)
631 {
632 RADV_FROM_HANDLE(radv_instance, instance, _instance);
633 VkResult result;
634
635 if (instance->physicalDeviceCount < 0) {
636 result = radv_enumerate_devices(instance);
637 if (result != VK_SUCCESS &&
638 result != VK_ERROR_INCOMPATIBLE_DRIVER)
639 return result;
640 }
641
642 if (!pPhysicalDevices) {
643 *pPhysicalDeviceCount = instance->physicalDeviceCount;
644 } else {
645 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
646 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
647 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
648 }
649
650 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
651 : VK_SUCCESS;
652 }
653
654 VkResult radv_EnumeratePhysicalDeviceGroups(
655 VkInstance _instance,
656 uint32_t* pPhysicalDeviceGroupCount,
657 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660 VkResult result;
661
662 if (instance->physicalDeviceCount < 0) {
663 result = radv_enumerate_devices(instance);
664 if (result != VK_SUCCESS &&
665 result != VK_ERROR_INCOMPATIBLE_DRIVER)
666 return result;
667 }
668
669 if (!pPhysicalDeviceGroupProperties) {
670 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
671 } else {
672 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
673 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
674 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
675 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
676 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
677 }
678 }
679 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
680 : VK_SUCCESS;
681 }
682
683 void radv_GetPhysicalDeviceFeatures(
684 VkPhysicalDevice physicalDevice,
685 VkPhysicalDeviceFeatures* pFeatures)
686 {
687 memset(pFeatures, 0, sizeof(*pFeatures));
688
689 *pFeatures = (VkPhysicalDeviceFeatures) {
690 .robustBufferAccess = true,
691 .fullDrawIndexUint32 = true,
692 .imageCubeArray = true,
693 .independentBlend = true,
694 .geometryShader = true,
695 .tessellationShader = true,
696 .sampleRateShading = true,
697 .dualSrcBlend = true,
698 .logicOp = true,
699 .multiDrawIndirect = true,
700 .drawIndirectFirstInstance = true,
701 .depthClamp = true,
702 .depthBiasClamp = true,
703 .fillModeNonSolid = true,
704 .depthBounds = true,
705 .wideLines = true,
706 .largePoints = true,
707 .alphaToOne = true,
708 .multiViewport = true,
709 .samplerAnisotropy = true,
710 .textureCompressionETC2 = false,
711 .textureCompressionASTC_LDR = false,
712 .textureCompressionBC = true,
713 .occlusionQueryPrecise = true,
714 .pipelineStatisticsQuery = true,
715 .vertexPipelineStoresAndAtomics = true,
716 .fragmentStoresAndAtomics = true,
717 .shaderTessellationAndGeometryPointSize = true,
718 .shaderImageGatherExtended = true,
719 .shaderStorageImageExtendedFormats = true,
720 .shaderStorageImageMultisample = false,
721 .shaderUniformBufferArrayDynamicIndexing = true,
722 .shaderSampledImageArrayDynamicIndexing = true,
723 .shaderStorageBufferArrayDynamicIndexing = true,
724 .shaderStorageImageArrayDynamicIndexing = true,
725 .shaderStorageImageReadWithoutFormat = true,
726 .shaderStorageImageWriteWithoutFormat = true,
727 .shaderClipDistance = true,
728 .shaderCullDistance = true,
729 .shaderFloat64 = true,
730 .shaderInt64 = true,
731 .shaderInt16 = false,
732 .sparseBinding = true,
733 .variableMultisampleRate = true,
734 .inheritedQueries = true,
735 };
736 }
737
738 void radv_GetPhysicalDeviceFeatures2(
739 VkPhysicalDevice physicalDevice,
740 VkPhysicalDeviceFeatures2KHR *pFeatures)
741 {
742 vk_foreach_struct(ext, pFeatures->pNext) {
743 switch (ext->sType) {
744 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
745 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
746 features->variablePointersStorageBuffer = true;
747 features->variablePointers = false;
748 break;
749 }
750 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
751 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
752 features->multiview = true;
753 features->multiviewGeometryShader = true;
754 features->multiviewTessellationShader = true;
755 break;
756 }
757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
758 VkPhysicalDeviceShaderDrawParameterFeatures *features =
759 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
760 features->shaderDrawParameters = true;
761 break;
762 }
763 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
764 VkPhysicalDeviceProtectedMemoryFeatures *features =
765 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
766 features->protectedMemory = false;
767 break;
768 }
769 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
770 VkPhysicalDevice16BitStorageFeatures *features =
771 (VkPhysicalDevice16BitStorageFeatures*)ext;
772 features->storageBuffer16BitAccess = false;
773 features->uniformAndStorageBuffer16BitAccess = false;
774 features->storagePushConstant16 = false;
775 features->storageInputOutput16 = false;
776 break;
777 }
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
779 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
780 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
781 features->samplerYcbcrConversion = false;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
785 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
786 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
787 features->shaderInputAttachmentArrayDynamicIndexing = true;
788 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
789 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
790 features->shaderUniformBufferArrayNonUniformIndexing = false;
791 features->shaderSampledImageArrayNonUniformIndexing = false;
792 features->shaderStorageBufferArrayNonUniformIndexing = false;
793 features->shaderStorageImageArrayNonUniformIndexing = false;
794 features->shaderInputAttachmentArrayNonUniformIndexing = false;
795 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
796 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
797 features->descriptorBindingUniformBufferUpdateAfterBind = true;
798 features->descriptorBindingSampledImageUpdateAfterBind = true;
799 features->descriptorBindingStorageImageUpdateAfterBind = true;
800 features->descriptorBindingStorageBufferUpdateAfterBind = true;
801 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
802 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
803 features->descriptorBindingUpdateUnusedWhilePending = true;
804 features->descriptorBindingPartiallyBound = true;
805 features->descriptorBindingVariableDescriptorCount = true;
806 features->runtimeDescriptorArray = true;
807 break;
808 }
809 default:
810 break;
811 }
812 }
813 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
814 }
815
816 void radv_GetPhysicalDeviceProperties(
817 VkPhysicalDevice physicalDevice,
818 VkPhysicalDeviceProperties* pProperties)
819 {
820 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
821 VkSampleCountFlags sample_counts = 0xf;
822
823 /* make sure that the entire descriptor set is addressable with a signed
824 * 32-bit int. So the sum of all limits scaled by descriptor size has to
825 * be at most 2 GiB. the combined image & samples object count as one of
826 * both. This limit is for the pipeline layout, not for the set layout, but
827 * there is no set limit, so we just set a pipeline limit. I don't think
828 * any app is going to hit this soon. */
829 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
830 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
831 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
832 32 /* sampler, largest when combined with image */ +
833 64 /* sampled image */ +
834 64 /* storage image */);
835
836 VkPhysicalDeviceLimits limits = {
837 .maxImageDimension1D = (1 << 14),
838 .maxImageDimension2D = (1 << 14),
839 .maxImageDimension3D = (1 << 11),
840 .maxImageDimensionCube = (1 << 14),
841 .maxImageArrayLayers = (1 << 11),
842 .maxTexelBufferElements = 128 * 1024 * 1024,
843 .maxUniformBufferRange = UINT32_MAX,
844 .maxStorageBufferRange = UINT32_MAX,
845 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
846 .maxMemoryAllocationCount = UINT32_MAX,
847 .maxSamplerAllocationCount = 64 * 1024,
848 .bufferImageGranularity = 64, /* A cache line */
849 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
850 .maxBoundDescriptorSets = MAX_SETS,
851 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
852 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
853 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
854 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
855 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
856 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
857 .maxPerStageResources = max_descriptor_set_size,
858 .maxDescriptorSetSamplers = max_descriptor_set_size,
859 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
860 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
861 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
862 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
863 .maxDescriptorSetSampledImages = max_descriptor_set_size,
864 .maxDescriptorSetStorageImages = max_descriptor_set_size,
865 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
866 .maxVertexInputAttributes = 32,
867 .maxVertexInputBindings = 32,
868 .maxVertexInputAttributeOffset = 2047,
869 .maxVertexInputBindingStride = 2048,
870 .maxVertexOutputComponents = 128,
871 .maxTessellationGenerationLevel = 64,
872 .maxTessellationPatchSize = 32,
873 .maxTessellationControlPerVertexInputComponents = 128,
874 .maxTessellationControlPerVertexOutputComponents = 128,
875 .maxTessellationControlPerPatchOutputComponents = 120,
876 .maxTessellationControlTotalOutputComponents = 4096,
877 .maxTessellationEvaluationInputComponents = 128,
878 .maxTessellationEvaluationOutputComponents = 128,
879 .maxGeometryShaderInvocations = 127,
880 .maxGeometryInputComponents = 64,
881 .maxGeometryOutputComponents = 128,
882 .maxGeometryOutputVertices = 256,
883 .maxGeometryTotalOutputComponents = 1024,
884 .maxFragmentInputComponents = 128,
885 .maxFragmentOutputAttachments = 8,
886 .maxFragmentDualSrcAttachments = 1,
887 .maxFragmentCombinedOutputResources = 8,
888 .maxComputeSharedMemorySize = 32768,
889 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
890 .maxComputeWorkGroupInvocations = 2048,
891 .maxComputeWorkGroupSize = {
892 2048,
893 2048,
894 2048
895 },
896 .subPixelPrecisionBits = 4 /* FIXME */,
897 .subTexelPrecisionBits = 4 /* FIXME */,
898 .mipmapPrecisionBits = 4 /* FIXME */,
899 .maxDrawIndexedIndexValue = UINT32_MAX,
900 .maxDrawIndirectCount = UINT32_MAX,
901 .maxSamplerLodBias = 16,
902 .maxSamplerAnisotropy = 16,
903 .maxViewports = MAX_VIEWPORTS,
904 .maxViewportDimensions = { (1 << 14), (1 << 14) },
905 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
906 .viewportSubPixelBits = 8,
907 .minMemoryMapAlignment = 4096, /* A page */
908 .minTexelBufferOffsetAlignment = 1,
909 .minUniformBufferOffsetAlignment = 4,
910 .minStorageBufferOffsetAlignment = 4,
911 .minTexelOffset = -32,
912 .maxTexelOffset = 31,
913 .minTexelGatherOffset = -32,
914 .maxTexelGatherOffset = 31,
915 .minInterpolationOffset = -2,
916 .maxInterpolationOffset = 2,
917 .subPixelInterpolationOffsetBits = 8,
918 .maxFramebufferWidth = (1 << 14),
919 .maxFramebufferHeight = (1 << 14),
920 .maxFramebufferLayers = (1 << 10),
921 .framebufferColorSampleCounts = sample_counts,
922 .framebufferDepthSampleCounts = sample_counts,
923 .framebufferStencilSampleCounts = sample_counts,
924 .framebufferNoAttachmentsSampleCounts = sample_counts,
925 .maxColorAttachments = MAX_RTS,
926 .sampledImageColorSampleCounts = sample_counts,
927 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
928 .sampledImageDepthSampleCounts = sample_counts,
929 .sampledImageStencilSampleCounts = sample_counts,
930 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
931 .maxSampleMaskWords = 1,
932 .timestampComputeAndGraphics = true,
933 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
934 .maxClipDistances = 8,
935 .maxCullDistances = 8,
936 .maxCombinedClipAndCullDistances = 8,
937 .discreteQueuePriorities = 1,
938 .pointSizeRange = { 0.125, 255.875 },
939 .lineWidthRange = { 0.0, 7.9921875 },
940 .pointSizeGranularity = (1.0 / 8.0),
941 .lineWidthGranularity = (1.0 / 128.0),
942 .strictLines = false, /* FINISHME */
943 .standardSampleLocations = true,
944 .optimalBufferCopyOffsetAlignment = 128,
945 .optimalBufferCopyRowPitchAlignment = 128,
946 .nonCoherentAtomSize = 64,
947 };
948
949 *pProperties = (VkPhysicalDeviceProperties) {
950 .apiVersion = radv_physical_device_api_version(pdevice),
951 .driverVersion = vk_get_driver_version(),
952 .vendorID = ATI_VENDOR_ID,
953 .deviceID = pdevice->rad_info.pci_id,
954 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
955 .limits = limits,
956 .sparseProperties = {0},
957 };
958
959 strcpy(pProperties->deviceName, pdevice->name);
960 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
961 }
962
963 void radv_GetPhysicalDeviceProperties2(
964 VkPhysicalDevice physicalDevice,
965 VkPhysicalDeviceProperties2KHR *pProperties)
966 {
967 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
968 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
969
970 vk_foreach_struct(ext, pProperties->pNext) {
971 switch (ext->sType) {
972 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
973 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
974 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
975 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
979 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
980 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
981 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
982 properties->deviceLUIDValid = false;
983 break;
984 }
985 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
986 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
987 properties->maxMultiviewViewCount = MAX_VIEWS;
988 properties->maxMultiviewInstanceIndex = INT_MAX;
989 break;
990 }
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
992 VkPhysicalDevicePointClippingPropertiesKHR *properties =
993 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
994 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
995 break;
996 }
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
998 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
999 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1000 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1001 break;
1002 }
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1004 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1005 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1006 properties->minImportedHostPointerAlignment = 4096;
1007 break;
1008 }
1009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1010 VkPhysicalDeviceSubgroupProperties *properties =
1011 (VkPhysicalDeviceSubgroupProperties*)ext;
1012 properties->subgroupSize = 64;
1013 properties->supportedStages = VK_SHADER_STAGE_ALL;
1014 properties->supportedOperations =
1015 VK_SUBGROUP_FEATURE_BASIC_BIT |
1016 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1017 VK_SUBGROUP_FEATURE_QUAD_BIT |
1018 VK_SUBGROUP_FEATURE_VOTE_BIT;
1019 if (pdevice->rad_info.chip_class >= VI) {
1020 properties->supportedOperations |=
1021 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1022 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1023 }
1024 properties->quadOperationsInAllStages = true;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1028 VkPhysicalDeviceMaintenance3Properties *properties =
1029 (VkPhysicalDeviceMaintenance3Properties*)ext;
1030 /* Make sure everything is addressable by a signed 32-bit int, and
1031 * our largest descriptors are 96 bytes. */
1032 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1033 /* Our buffer size fields allow only this much */
1034 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1038 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1039 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1040 /* GFX6-8 only support single channel min/max filter. */
1041 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1042 properties->filterMinmaxSingleComponentFormats = true;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1046 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1047 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1048
1049 /* Shader engines. */
1050 properties->shaderEngineCount =
1051 pdevice->rad_info.max_se;
1052 properties->shaderArraysPerEngineCount =
1053 pdevice->rad_info.max_sh_per_se;
1054 properties->computeUnitsPerShaderArray =
1055 pdevice->rad_info.num_good_compute_units /
1056 (pdevice->rad_info.max_se *
1057 pdevice->rad_info.max_sh_per_se);
1058 properties->simdPerComputeUnit = 4;
1059 properties->wavefrontsPerSimd =
1060 pdevice->rad_info.family == CHIP_TONGA ||
1061 pdevice->rad_info.family == CHIP_ICELAND ||
1062 pdevice->rad_info.family == CHIP_POLARIS10 ||
1063 pdevice->rad_info.family == CHIP_POLARIS11 ||
1064 pdevice->rad_info.family == CHIP_POLARIS12 ||
1065 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1066 properties->wavefrontSize = 64;
1067
1068 /* SGPR. */
1069 properties->sgprsPerSimd =
1070 radv_get_num_physical_sgprs(pdevice);
1071 properties->minSgprAllocation =
1072 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1073 properties->maxSgprAllocation =
1074 pdevice->rad_info.family == CHIP_TONGA ||
1075 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1076 properties->sgprAllocationGranularity =
1077 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1078
1079 /* VGPR. */
1080 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1081 properties->minVgprAllocation = 4;
1082 properties->maxVgprAllocation = 256;
1083 properties->vgprAllocationGranularity = 4;
1084 break;
1085 }
1086 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1087 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1088 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1089 properties->maxVertexAttribDivisor = UINT32_MAX;
1090 break;
1091 }
1092 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1093 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1094 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1095 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1096 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1097 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1098 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1099 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1100 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1101 properties->robustBufferAccessUpdateAfterBind = false;
1102 properties->quadDivergentImplicitLod = false;
1103
1104 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1105 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1106 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1107 32 /* sampler, largest when combined with image */ +
1108 64 /* sampled image */ +
1109 64 /* storage image */);
1110 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1111 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1112 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1113 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1114 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1115 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1116 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1117 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1118 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1119 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1120 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1121 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1122 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1123 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1124 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1125 break;
1126 }
1127 default:
1128 break;
1129 }
1130 }
1131 }
1132
1133 static void radv_get_physical_device_queue_family_properties(
1134 struct radv_physical_device* pdevice,
1135 uint32_t* pCount,
1136 VkQueueFamilyProperties** pQueueFamilyProperties)
1137 {
1138 int num_queue_families = 1;
1139 int idx;
1140 if (pdevice->rad_info.num_compute_rings > 0 &&
1141 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1142 num_queue_families++;
1143
1144 if (pQueueFamilyProperties == NULL) {
1145 *pCount = num_queue_families;
1146 return;
1147 }
1148
1149 if (!*pCount)
1150 return;
1151
1152 idx = 0;
1153 if (*pCount >= 1) {
1154 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1155 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1156 VK_QUEUE_COMPUTE_BIT |
1157 VK_QUEUE_TRANSFER_BIT |
1158 VK_QUEUE_SPARSE_BINDING_BIT,
1159 .queueCount = 1,
1160 .timestampValidBits = 64,
1161 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1162 };
1163 idx++;
1164 }
1165
1166 if (pdevice->rad_info.num_compute_rings > 0 &&
1167 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1168 if (*pCount > idx) {
1169 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1170 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1171 VK_QUEUE_TRANSFER_BIT |
1172 VK_QUEUE_SPARSE_BINDING_BIT,
1173 .queueCount = pdevice->rad_info.num_compute_rings,
1174 .timestampValidBits = 64,
1175 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1176 };
1177 idx++;
1178 }
1179 }
1180 *pCount = idx;
1181 }
1182
1183 void radv_GetPhysicalDeviceQueueFamilyProperties(
1184 VkPhysicalDevice physicalDevice,
1185 uint32_t* pCount,
1186 VkQueueFamilyProperties* pQueueFamilyProperties)
1187 {
1188 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1189 if (!pQueueFamilyProperties) {
1190 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1191 return;
1192 }
1193 VkQueueFamilyProperties *properties[] = {
1194 pQueueFamilyProperties + 0,
1195 pQueueFamilyProperties + 1,
1196 pQueueFamilyProperties + 2,
1197 };
1198 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1199 assert(*pCount <= 3);
1200 }
1201
1202 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1203 VkPhysicalDevice physicalDevice,
1204 uint32_t* pCount,
1205 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1206 {
1207 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1208 if (!pQueueFamilyProperties) {
1209 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1210 return;
1211 }
1212 VkQueueFamilyProperties *properties[] = {
1213 &pQueueFamilyProperties[0].queueFamilyProperties,
1214 &pQueueFamilyProperties[1].queueFamilyProperties,
1215 &pQueueFamilyProperties[2].queueFamilyProperties,
1216 };
1217 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1218 assert(*pCount <= 3);
1219 }
1220
1221 void radv_GetPhysicalDeviceMemoryProperties(
1222 VkPhysicalDevice physicalDevice,
1223 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1224 {
1225 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1226
1227 *pMemoryProperties = physical_device->memory_properties;
1228 }
1229
1230 void radv_GetPhysicalDeviceMemoryProperties2(
1231 VkPhysicalDevice physicalDevice,
1232 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1233 {
1234 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1235 &pMemoryProperties->memoryProperties);
1236 }
1237
1238 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1239 VkDevice _device,
1240 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1241 const void *pHostPointer,
1242 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1243 {
1244 RADV_FROM_HANDLE(radv_device, device, _device);
1245
1246 switch (handleType)
1247 {
1248 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1249 const struct radv_physical_device *physical_device = device->physical_device;
1250 uint32_t memoryTypeBits = 0;
1251 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1252 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1253 memoryTypeBits = (1 << i);
1254 break;
1255 }
1256 }
1257 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1258 return VK_SUCCESS;
1259 }
1260 default:
1261 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1262 }
1263 }
1264
1265 static enum radeon_ctx_priority
1266 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1267 {
1268 /* Default to MEDIUM when a specific global priority isn't requested */
1269 if (!pObj)
1270 return RADEON_CTX_PRIORITY_MEDIUM;
1271
1272 switch(pObj->globalPriority) {
1273 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1274 return RADEON_CTX_PRIORITY_REALTIME;
1275 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1276 return RADEON_CTX_PRIORITY_HIGH;
1277 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1278 return RADEON_CTX_PRIORITY_MEDIUM;
1279 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1280 return RADEON_CTX_PRIORITY_LOW;
1281 default:
1282 unreachable("Illegal global priority value");
1283 return RADEON_CTX_PRIORITY_INVALID;
1284 }
1285 }
1286
1287 static int
1288 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1289 uint32_t queue_family_index, int idx,
1290 VkDeviceQueueCreateFlags flags,
1291 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1292 {
1293 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1294 queue->device = device;
1295 queue->queue_family_index = queue_family_index;
1296 queue->queue_idx = idx;
1297 queue->priority = radv_get_queue_global_priority(global_priority);
1298 queue->flags = flags;
1299
1300 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1301 if (!queue->hw_ctx)
1302 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1303
1304 return VK_SUCCESS;
1305 }
1306
1307 static void
1308 radv_queue_finish(struct radv_queue *queue)
1309 {
1310 if (queue->hw_ctx)
1311 queue->device->ws->ctx_destroy(queue->hw_ctx);
1312
1313 if (queue->initial_full_flush_preamble_cs)
1314 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1315 if (queue->initial_preamble_cs)
1316 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1317 if (queue->continue_preamble_cs)
1318 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1319 if (queue->descriptor_bo)
1320 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1321 if (queue->scratch_bo)
1322 queue->device->ws->buffer_destroy(queue->scratch_bo);
1323 if (queue->esgs_ring_bo)
1324 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1325 if (queue->gsvs_ring_bo)
1326 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1327 if (queue->tess_rings_bo)
1328 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1329 if (queue->compute_scratch_bo)
1330 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1331 }
1332
1333 static void
1334 radv_bo_list_init(struct radv_bo_list *bo_list)
1335 {
1336 pthread_mutex_init(&bo_list->mutex, NULL);
1337 bo_list->list.count = bo_list->capacity = 0;
1338 bo_list->list.bos = NULL;
1339 }
1340
1341 static void
1342 radv_bo_list_finish(struct radv_bo_list *bo_list)
1343 {
1344 free(bo_list->list.bos);
1345 pthread_mutex_destroy(&bo_list->mutex);
1346 }
1347
1348 static VkResult radv_bo_list_add(struct radv_device *device,
1349 struct radeon_winsys_bo *bo)
1350 {
1351 struct radv_bo_list *bo_list = &device->bo_list;
1352
1353 if (unlikely(!device->use_global_bo_list))
1354 return VK_SUCCESS;
1355
1356 pthread_mutex_lock(&bo_list->mutex);
1357 if (bo_list->list.count == bo_list->capacity) {
1358 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1359 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1360
1361 if (!data) {
1362 pthread_mutex_unlock(&bo_list->mutex);
1363 return VK_ERROR_OUT_OF_HOST_MEMORY;
1364 }
1365
1366 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1367 bo_list->capacity = capacity;
1368 }
1369
1370 bo_list->list.bos[bo_list->list.count++] = bo;
1371 pthread_mutex_unlock(&bo_list->mutex);
1372 return VK_SUCCESS;
1373 }
1374
1375 static void radv_bo_list_remove(struct radv_device *device,
1376 struct radeon_winsys_bo *bo)
1377 {
1378 struct radv_bo_list *bo_list = &device->bo_list;
1379
1380 if (unlikely(!device->use_global_bo_list))
1381 return;
1382
1383 pthread_mutex_lock(&bo_list->mutex);
1384 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1385 if (bo_list->list.bos[i] == bo) {
1386 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1387 --bo_list->list.count;
1388 break;
1389 }
1390 }
1391 pthread_mutex_unlock(&bo_list->mutex);
1392 }
1393
1394 static void
1395 radv_device_init_gs_info(struct radv_device *device)
1396 {
1397 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1398 device->physical_device->rad_info.family);
1399 }
1400
1401 static int radv_get_device_extension_index(const char *name)
1402 {
1403 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1404 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1405 return i;
1406 }
1407 return -1;
1408 }
1409
1410 VkResult radv_CreateDevice(
1411 VkPhysicalDevice physicalDevice,
1412 const VkDeviceCreateInfo* pCreateInfo,
1413 const VkAllocationCallbacks* pAllocator,
1414 VkDevice* pDevice)
1415 {
1416 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1417 VkResult result;
1418 struct radv_device *device;
1419
1420 bool keep_shader_info = false;
1421
1422 /* Check enabled features */
1423 if (pCreateInfo->pEnabledFeatures) {
1424 VkPhysicalDeviceFeatures supported_features;
1425 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1426 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1427 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1428 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1429 for (uint32_t i = 0; i < num_features; i++) {
1430 if (enabled_feature[i] && !supported_feature[i])
1431 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1432 }
1433 }
1434
1435 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1436 sizeof(*device), 8,
1437 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1438 if (!device)
1439 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1440
1441 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1442 device->instance = physical_device->instance;
1443 device->physical_device = physical_device;
1444
1445 device->ws = physical_device->ws;
1446 if (pAllocator)
1447 device->alloc = *pAllocator;
1448 else
1449 device->alloc = physical_device->instance->alloc;
1450
1451 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1452 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1453 int index = radv_get_device_extension_index(ext_name);
1454 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1455 vk_free(&device->alloc, device);
1456 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1457 }
1458
1459 device->enabled_extensions.extensions[index] = true;
1460 }
1461
1462 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1463
1464 /* With update after bind we can't attach bo's to the command buffer
1465 * from the descriptor set anymore, so we have to use a global BO list.
1466 */
1467 device->use_global_bo_list =
1468 device->enabled_extensions.EXT_descriptor_indexing;
1469
1470 mtx_init(&device->shader_slab_mutex, mtx_plain);
1471 list_inithead(&device->shader_slabs);
1472
1473 radv_bo_list_init(&device->bo_list);
1474
1475 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1476 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1477 uint32_t qfi = queue_create->queueFamilyIndex;
1478 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1479 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1480
1481 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1482
1483 device->queues[qfi] = vk_alloc(&device->alloc,
1484 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1485 if (!device->queues[qfi]) {
1486 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1487 goto fail;
1488 }
1489
1490 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1491
1492 device->queue_count[qfi] = queue_create->queueCount;
1493
1494 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1495 result = radv_queue_init(device, &device->queues[qfi][q],
1496 qfi, q, queue_create->flags,
1497 global_priority);
1498 if (result != VK_SUCCESS)
1499 goto fail;
1500 }
1501 }
1502
1503 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1504 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1505
1506 /* Disabled and not implemented for now. */
1507 device->dfsm_allowed = device->pbb_allowed && false;
1508
1509 #ifdef ANDROID
1510 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1511 #endif
1512
1513 /* The maximum number of scratch waves. Scratch space isn't divided
1514 * evenly between CUs. The number is only a function of the number of CUs.
1515 * We can decrease the constant to decrease the scratch buffer size.
1516 *
1517 * sctx->scratch_waves must be >= the maximum possible size of
1518 * 1 threadgroup, so that the hw doesn't hang from being unable
1519 * to start any.
1520 *
1521 * The recommended value is 4 per CU at most. Higher numbers don't
1522 * bring much benefit, but they still occupy chip resources (think
1523 * async compute). I've seen ~2% performance difference between 4 and 32.
1524 */
1525 uint32_t max_threads_per_block = 2048;
1526 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1527 max_threads_per_block / 64);
1528
1529 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1530
1531 if (device->physical_device->rad_info.chip_class >= CIK) {
1532 /* If the KMD allows it (there is a KMD hw register for it),
1533 * allow launching waves out-of-order.
1534 */
1535 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1536 }
1537
1538 radv_device_init_gs_info(device);
1539
1540 device->tess_offchip_block_dw_size =
1541 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1542 device->has_distributed_tess =
1543 device->physical_device->rad_info.chip_class >= VI &&
1544 device->physical_device->rad_info.max_se >= 2;
1545
1546 if (getenv("RADV_TRACE_FILE")) {
1547 const char *filename = getenv("RADV_TRACE_FILE");
1548
1549 keep_shader_info = true;
1550
1551 if (!radv_init_trace(device))
1552 goto fail;
1553
1554 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1555 radv_dump_enabled_options(device, stderr);
1556 }
1557
1558 device->keep_shader_info = keep_shader_info;
1559
1560 result = radv_device_init_meta(device);
1561 if (result != VK_SUCCESS)
1562 goto fail;
1563
1564 radv_device_init_msaa(device);
1565
1566 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1567 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1568 switch (family) {
1569 case RADV_QUEUE_GENERAL:
1570 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1571 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1572 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1573 break;
1574 case RADV_QUEUE_COMPUTE:
1575 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1576 radeon_emit(device->empty_cs[family], 0);
1577 break;
1578 }
1579 device->ws->cs_finalize(device->empty_cs[family]);
1580 }
1581
1582 if (device->physical_device->rad_info.chip_class >= CIK)
1583 cik_create_gfx_config(device);
1584
1585 VkPipelineCacheCreateInfo ci;
1586 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1587 ci.pNext = NULL;
1588 ci.flags = 0;
1589 ci.pInitialData = NULL;
1590 ci.initialDataSize = 0;
1591 VkPipelineCache pc;
1592 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1593 &ci, NULL, &pc);
1594 if (result != VK_SUCCESS)
1595 goto fail_meta;
1596
1597 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1598
1599 *pDevice = radv_device_to_handle(device);
1600 return VK_SUCCESS;
1601
1602 fail_meta:
1603 radv_device_finish_meta(device);
1604 fail:
1605 radv_bo_list_finish(&device->bo_list);
1606
1607 if (device->trace_bo)
1608 device->ws->buffer_destroy(device->trace_bo);
1609
1610 if (device->gfx_init)
1611 device->ws->buffer_destroy(device->gfx_init);
1612
1613 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1614 for (unsigned q = 0; q < device->queue_count[i]; q++)
1615 radv_queue_finish(&device->queues[i][q]);
1616 if (device->queue_count[i])
1617 vk_free(&device->alloc, device->queues[i]);
1618 }
1619
1620 vk_free(&device->alloc, device);
1621 return result;
1622 }
1623
1624 void radv_DestroyDevice(
1625 VkDevice _device,
1626 const VkAllocationCallbacks* pAllocator)
1627 {
1628 RADV_FROM_HANDLE(radv_device, device, _device);
1629
1630 if (!device)
1631 return;
1632
1633 if (device->trace_bo)
1634 device->ws->buffer_destroy(device->trace_bo);
1635
1636 if (device->gfx_init)
1637 device->ws->buffer_destroy(device->gfx_init);
1638
1639 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1640 for (unsigned q = 0; q < device->queue_count[i]; q++)
1641 radv_queue_finish(&device->queues[i][q]);
1642 if (device->queue_count[i])
1643 vk_free(&device->alloc, device->queues[i]);
1644 if (device->empty_cs[i])
1645 device->ws->cs_destroy(device->empty_cs[i]);
1646 }
1647 radv_device_finish_meta(device);
1648
1649 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1650 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1651
1652 radv_destroy_shader_slabs(device);
1653
1654 radv_bo_list_finish(&device->bo_list);
1655 vk_free(&device->alloc, device);
1656 }
1657
1658 VkResult radv_EnumerateInstanceLayerProperties(
1659 uint32_t* pPropertyCount,
1660 VkLayerProperties* pProperties)
1661 {
1662 if (pProperties == NULL) {
1663 *pPropertyCount = 0;
1664 return VK_SUCCESS;
1665 }
1666
1667 /* None supported at this time */
1668 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1669 }
1670
1671 VkResult radv_EnumerateDeviceLayerProperties(
1672 VkPhysicalDevice physicalDevice,
1673 uint32_t* pPropertyCount,
1674 VkLayerProperties* pProperties)
1675 {
1676 if (pProperties == NULL) {
1677 *pPropertyCount = 0;
1678 return VK_SUCCESS;
1679 }
1680
1681 /* None supported at this time */
1682 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1683 }
1684
1685 void radv_GetDeviceQueue2(
1686 VkDevice _device,
1687 const VkDeviceQueueInfo2* pQueueInfo,
1688 VkQueue* pQueue)
1689 {
1690 RADV_FROM_HANDLE(radv_device, device, _device);
1691 struct radv_queue *queue;
1692
1693 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1694 if (pQueueInfo->flags != queue->flags) {
1695 /* From the Vulkan 1.1.70 spec:
1696 *
1697 * "The queue returned by vkGetDeviceQueue2 must have the same
1698 * flags value from this structure as that used at device
1699 * creation time in a VkDeviceQueueCreateInfo instance. If no
1700 * matching flags were specified at device creation time then
1701 * pQueue will return VK_NULL_HANDLE."
1702 */
1703 *pQueue = VK_NULL_HANDLE;
1704 return;
1705 }
1706
1707 *pQueue = radv_queue_to_handle(queue);
1708 }
1709
1710 void radv_GetDeviceQueue(
1711 VkDevice _device,
1712 uint32_t queueFamilyIndex,
1713 uint32_t queueIndex,
1714 VkQueue* pQueue)
1715 {
1716 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1717 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1718 .queueFamilyIndex = queueFamilyIndex,
1719 .queueIndex = queueIndex
1720 };
1721
1722 radv_GetDeviceQueue2(_device, &info, pQueue);
1723 }
1724
1725 static void
1726 fill_geom_tess_rings(struct radv_queue *queue,
1727 uint32_t *map,
1728 bool add_sample_positions,
1729 uint32_t esgs_ring_size,
1730 struct radeon_winsys_bo *esgs_ring_bo,
1731 uint32_t gsvs_ring_size,
1732 struct radeon_winsys_bo *gsvs_ring_bo,
1733 uint32_t tess_factor_ring_size,
1734 uint32_t tess_offchip_ring_offset,
1735 uint32_t tess_offchip_ring_size,
1736 struct radeon_winsys_bo *tess_rings_bo)
1737 {
1738 uint64_t esgs_va = 0, gsvs_va = 0;
1739 uint64_t tess_va = 0, tess_offchip_va = 0;
1740 uint32_t *desc = &map[4];
1741
1742 if (esgs_ring_bo)
1743 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1744 if (gsvs_ring_bo)
1745 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1746 if (tess_rings_bo) {
1747 tess_va = radv_buffer_get_va(tess_rings_bo);
1748 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1749 }
1750
1751 /* stride 0, num records - size, add tid, swizzle, elsize4,
1752 index stride 64 */
1753 desc[0] = esgs_va;
1754 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1755 S_008F04_STRIDE(0) |
1756 S_008F04_SWIZZLE_ENABLE(true);
1757 desc[2] = esgs_ring_size;
1758 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1759 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1760 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1761 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1762 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1763 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1764 S_008F0C_ELEMENT_SIZE(1) |
1765 S_008F0C_INDEX_STRIDE(3) |
1766 S_008F0C_ADD_TID_ENABLE(true);
1767
1768 desc += 4;
1769 /* GS entry for ES->GS ring */
1770 /* stride 0, num records - size, elsize0,
1771 index stride 0 */
1772 desc[0] = esgs_va;
1773 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1774 S_008F04_STRIDE(0) |
1775 S_008F04_SWIZZLE_ENABLE(false);
1776 desc[2] = esgs_ring_size;
1777 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1778 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1779 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1780 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1781 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1782 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1783 S_008F0C_ELEMENT_SIZE(0) |
1784 S_008F0C_INDEX_STRIDE(0) |
1785 S_008F0C_ADD_TID_ENABLE(false);
1786
1787 desc += 4;
1788 /* VS entry for GS->VS ring */
1789 /* stride 0, num records - size, elsize0,
1790 index stride 0 */
1791 desc[0] = gsvs_va;
1792 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1793 S_008F04_STRIDE(0) |
1794 S_008F04_SWIZZLE_ENABLE(false);
1795 desc[2] = gsvs_ring_size;
1796 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1797 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1798 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1799 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1800 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1801 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1802 S_008F0C_ELEMENT_SIZE(0) |
1803 S_008F0C_INDEX_STRIDE(0) |
1804 S_008F0C_ADD_TID_ENABLE(false);
1805 desc += 4;
1806
1807 /* stride gsvs_itemsize, num records 64
1808 elsize 4, index stride 16 */
1809 /* shader will patch stride and desc[2] */
1810 desc[0] = gsvs_va;
1811 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1812 S_008F04_STRIDE(0) |
1813 S_008F04_SWIZZLE_ENABLE(true);
1814 desc[2] = 0;
1815 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1816 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1817 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1818 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1819 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1820 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1821 S_008F0C_ELEMENT_SIZE(1) |
1822 S_008F0C_INDEX_STRIDE(1) |
1823 S_008F0C_ADD_TID_ENABLE(true);
1824 desc += 4;
1825
1826 desc[0] = tess_va;
1827 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1828 S_008F04_STRIDE(0) |
1829 S_008F04_SWIZZLE_ENABLE(false);
1830 desc[2] = tess_factor_ring_size;
1831 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1832 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1833 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1834 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1835 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1836 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1837 S_008F0C_ELEMENT_SIZE(0) |
1838 S_008F0C_INDEX_STRIDE(0) |
1839 S_008F0C_ADD_TID_ENABLE(false);
1840 desc += 4;
1841
1842 desc[0] = tess_offchip_va;
1843 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1844 S_008F04_STRIDE(0) |
1845 S_008F04_SWIZZLE_ENABLE(false);
1846 desc[2] = tess_offchip_ring_size;
1847 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1848 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1849 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1850 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1851 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1852 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1853 S_008F0C_ELEMENT_SIZE(0) |
1854 S_008F0C_INDEX_STRIDE(0) |
1855 S_008F0C_ADD_TID_ENABLE(false);
1856 desc += 4;
1857
1858 /* add sample positions after all rings */
1859 memcpy(desc, queue->device->sample_locations_1x, 8);
1860 desc += 2;
1861 memcpy(desc, queue->device->sample_locations_2x, 16);
1862 desc += 4;
1863 memcpy(desc, queue->device->sample_locations_4x, 32);
1864 desc += 8;
1865 memcpy(desc, queue->device->sample_locations_8x, 64);
1866 desc += 16;
1867 memcpy(desc, queue->device->sample_locations_16x, 128);
1868 }
1869
1870 static unsigned
1871 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1872 {
1873 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1874 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1875 device->physical_device->rad_info.family != CHIP_STONEY;
1876 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1877 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1878 device->physical_device->rad_info.max_se;
1879 unsigned offchip_granularity;
1880 unsigned hs_offchip_param;
1881 switch (device->tess_offchip_block_dw_size) {
1882 default:
1883 assert(0);
1884 /* fall through */
1885 case 8192:
1886 offchip_granularity = V_03093C_X_8K_DWORDS;
1887 break;
1888 case 4096:
1889 offchip_granularity = V_03093C_X_4K_DWORDS;
1890 break;
1891 }
1892
1893 switch (device->physical_device->rad_info.chip_class) {
1894 case SI:
1895 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1896 break;
1897 case CIK:
1898 case VI:
1899 case GFX9:
1900 default:
1901 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1902 break;
1903 }
1904
1905 *max_offchip_buffers_p = max_offchip_buffers;
1906 if (device->physical_device->rad_info.chip_class >= CIK) {
1907 if (device->physical_device->rad_info.chip_class >= VI)
1908 --max_offchip_buffers;
1909 hs_offchip_param =
1910 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1911 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1912 } else {
1913 hs_offchip_param =
1914 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1915 }
1916 return hs_offchip_param;
1917 }
1918
1919 static void
1920 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1921 struct radeon_winsys_bo *esgs_ring_bo,
1922 uint32_t esgs_ring_size,
1923 struct radeon_winsys_bo *gsvs_ring_bo,
1924 uint32_t gsvs_ring_size)
1925 {
1926 if (!esgs_ring_bo && !gsvs_ring_bo)
1927 return;
1928
1929 if (esgs_ring_bo)
1930 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1931
1932 if (gsvs_ring_bo)
1933 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1934
1935 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1936 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1937 radeon_emit(cs, esgs_ring_size >> 8);
1938 radeon_emit(cs, gsvs_ring_size >> 8);
1939 } else {
1940 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1941 radeon_emit(cs, esgs_ring_size >> 8);
1942 radeon_emit(cs, gsvs_ring_size >> 8);
1943 }
1944 }
1945
1946 static void
1947 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1948 unsigned hs_offchip_param, unsigned tf_ring_size,
1949 struct radeon_winsys_bo *tess_rings_bo)
1950 {
1951 uint64_t tf_va;
1952
1953 if (!tess_rings_bo)
1954 return;
1955
1956 tf_va = radv_buffer_get_va(tess_rings_bo);
1957
1958 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1959
1960 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1961 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1962 S_030938_SIZE(tf_ring_size / 4));
1963 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1964 tf_va >> 8);
1965 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1966 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1967 S_030944_BASE_HI(tf_va >> 40));
1968 }
1969 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1970 hs_offchip_param);
1971 } else {
1972 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1973 S_008988_SIZE(tf_ring_size / 4));
1974 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1975 tf_va >> 8);
1976 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1977 hs_offchip_param);
1978 }
1979 }
1980
1981 static void
1982 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1983 struct radeon_winsys_bo *compute_scratch_bo)
1984 {
1985 uint64_t scratch_va;
1986
1987 if (!compute_scratch_bo)
1988 return;
1989
1990 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1991
1992 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1993
1994 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1995 radeon_emit(cs, scratch_va);
1996 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1997 S_008F04_SWIZZLE_ENABLE(1));
1998 }
1999
2000 static void
2001 radv_emit_global_shader_pointers(struct radv_queue *queue,
2002 struct radeon_cmdbuf *cs,
2003 struct radeon_winsys_bo *descriptor_bo)
2004 {
2005 uint64_t va;
2006
2007 if (!descriptor_bo)
2008 return;
2009
2010 va = radv_buffer_get_va(descriptor_bo);
2011
2012 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2013
2014 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2015 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2016 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2017 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2018 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2019
2020 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2021 radv_emit_shader_pointer(queue->device, cs, regs[i],
2022 va, true);
2023 }
2024 } else {
2025 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2026 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2027 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2028 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2029 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2030 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2031
2032 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2033 radv_emit_shader_pointer(queue->device, cs, regs[i],
2034 va, true);
2035 }
2036 }
2037 }
2038
2039 static VkResult
2040 radv_get_preamble_cs(struct radv_queue *queue,
2041 uint32_t scratch_size,
2042 uint32_t compute_scratch_size,
2043 uint32_t esgs_ring_size,
2044 uint32_t gsvs_ring_size,
2045 bool needs_tess_rings,
2046 bool needs_sample_positions,
2047 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2048 struct radeon_cmdbuf **initial_preamble_cs,
2049 struct radeon_cmdbuf **continue_preamble_cs)
2050 {
2051 struct radeon_winsys_bo *scratch_bo = NULL;
2052 struct radeon_winsys_bo *descriptor_bo = NULL;
2053 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2054 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2055 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2056 struct radeon_winsys_bo *tess_rings_bo = NULL;
2057 struct radeon_cmdbuf *dest_cs[3] = {0};
2058 bool add_tess_rings = false, add_sample_positions = false;
2059 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2060 unsigned max_offchip_buffers;
2061 unsigned hs_offchip_param = 0;
2062 unsigned tess_offchip_ring_offset;
2063 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2064 if (!queue->has_tess_rings) {
2065 if (needs_tess_rings)
2066 add_tess_rings = true;
2067 }
2068 if (!queue->has_sample_positions) {
2069 if (needs_sample_positions)
2070 add_sample_positions = true;
2071 }
2072 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2073 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2074 &max_offchip_buffers);
2075 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2076 tess_offchip_ring_size = max_offchip_buffers *
2077 queue->device->tess_offchip_block_dw_size * 4;
2078
2079 if (scratch_size <= queue->scratch_size &&
2080 compute_scratch_size <= queue->compute_scratch_size &&
2081 esgs_ring_size <= queue->esgs_ring_size &&
2082 gsvs_ring_size <= queue->gsvs_ring_size &&
2083 !add_tess_rings && !add_sample_positions &&
2084 queue->initial_preamble_cs) {
2085 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2086 *initial_preamble_cs = queue->initial_preamble_cs;
2087 *continue_preamble_cs = queue->continue_preamble_cs;
2088 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2089 *continue_preamble_cs = NULL;
2090 return VK_SUCCESS;
2091 }
2092
2093 if (scratch_size > queue->scratch_size) {
2094 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2095 scratch_size,
2096 4096,
2097 RADEON_DOMAIN_VRAM,
2098 ring_bo_flags);
2099 if (!scratch_bo)
2100 goto fail;
2101 } else
2102 scratch_bo = queue->scratch_bo;
2103
2104 if (compute_scratch_size > queue->compute_scratch_size) {
2105 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2106 compute_scratch_size,
2107 4096,
2108 RADEON_DOMAIN_VRAM,
2109 ring_bo_flags);
2110 if (!compute_scratch_bo)
2111 goto fail;
2112
2113 } else
2114 compute_scratch_bo = queue->compute_scratch_bo;
2115
2116 if (esgs_ring_size > queue->esgs_ring_size) {
2117 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2118 esgs_ring_size,
2119 4096,
2120 RADEON_DOMAIN_VRAM,
2121 ring_bo_flags);
2122 if (!esgs_ring_bo)
2123 goto fail;
2124 } else {
2125 esgs_ring_bo = queue->esgs_ring_bo;
2126 esgs_ring_size = queue->esgs_ring_size;
2127 }
2128
2129 if (gsvs_ring_size > queue->gsvs_ring_size) {
2130 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2131 gsvs_ring_size,
2132 4096,
2133 RADEON_DOMAIN_VRAM,
2134 ring_bo_flags);
2135 if (!gsvs_ring_bo)
2136 goto fail;
2137 } else {
2138 gsvs_ring_bo = queue->gsvs_ring_bo;
2139 gsvs_ring_size = queue->gsvs_ring_size;
2140 }
2141
2142 if (add_tess_rings) {
2143 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2144 tess_offchip_ring_offset + tess_offchip_ring_size,
2145 256,
2146 RADEON_DOMAIN_VRAM,
2147 ring_bo_flags);
2148 if (!tess_rings_bo)
2149 goto fail;
2150 } else {
2151 tess_rings_bo = queue->tess_rings_bo;
2152 }
2153
2154 if (scratch_bo != queue->scratch_bo ||
2155 esgs_ring_bo != queue->esgs_ring_bo ||
2156 gsvs_ring_bo != queue->gsvs_ring_bo ||
2157 tess_rings_bo != queue->tess_rings_bo ||
2158 add_sample_positions) {
2159 uint32_t size = 0;
2160 if (gsvs_ring_bo || esgs_ring_bo ||
2161 tess_rings_bo || add_sample_positions) {
2162 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2163 if (add_sample_positions)
2164 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2165 }
2166 else if (scratch_bo)
2167 size = 8; /* 2 dword */
2168
2169 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2170 size,
2171 4096,
2172 RADEON_DOMAIN_VRAM,
2173 RADEON_FLAG_CPU_ACCESS |
2174 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2175 RADEON_FLAG_READ_ONLY);
2176 if (!descriptor_bo)
2177 goto fail;
2178 } else
2179 descriptor_bo = queue->descriptor_bo;
2180
2181 for(int i = 0; i < 3; ++i) {
2182 struct radeon_cmdbuf *cs = NULL;
2183 cs = queue->device->ws->cs_create(queue->device->ws,
2184 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2185 if (!cs)
2186 goto fail;
2187
2188 dest_cs[i] = cs;
2189
2190 if (scratch_bo)
2191 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2192
2193 if (descriptor_bo != queue->descriptor_bo) {
2194 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2195
2196 if (scratch_bo) {
2197 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2198 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2199 S_008F04_SWIZZLE_ENABLE(1);
2200 map[0] = scratch_va;
2201 map[1] = rsrc1;
2202 }
2203
2204 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2205 add_sample_positions)
2206 fill_geom_tess_rings(queue, map, add_sample_positions,
2207 esgs_ring_size, esgs_ring_bo,
2208 gsvs_ring_size, gsvs_ring_bo,
2209 tess_factor_ring_size,
2210 tess_offchip_ring_offset,
2211 tess_offchip_ring_size,
2212 tess_rings_bo);
2213
2214 queue->device->ws->buffer_unmap(descriptor_bo);
2215 }
2216
2217 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2218 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2219 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2220 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2221 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2222 }
2223
2224 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2225 gsvs_ring_bo, gsvs_ring_size);
2226 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2227 tess_factor_ring_size, tess_rings_bo);
2228 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2229 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2230
2231 if (i == 0) {
2232 si_cs_emit_cache_flush(cs,
2233 queue->device->physical_device->rad_info.chip_class,
2234 NULL, 0,
2235 queue->queue_family_index == RING_COMPUTE &&
2236 queue->device->physical_device->rad_info.chip_class >= CIK,
2237 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2238 RADV_CMD_FLAG_INV_ICACHE |
2239 RADV_CMD_FLAG_INV_SMEM_L1 |
2240 RADV_CMD_FLAG_INV_VMEM_L1 |
2241 RADV_CMD_FLAG_INV_GLOBAL_L2);
2242 } else if (i == 1) {
2243 si_cs_emit_cache_flush(cs,
2244 queue->device->physical_device->rad_info.chip_class,
2245 NULL, 0,
2246 queue->queue_family_index == RING_COMPUTE &&
2247 queue->device->physical_device->rad_info.chip_class >= CIK,
2248 RADV_CMD_FLAG_INV_ICACHE |
2249 RADV_CMD_FLAG_INV_SMEM_L1 |
2250 RADV_CMD_FLAG_INV_VMEM_L1 |
2251 RADV_CMD_FLAG_INV_GLOBAL_L2);
2252 }
2253
2254 if (!queue->device->ws->cs_finalize(cs))
2255 goto fail;
2256 }
2257
2258 if (queue->initial_full_flush_preamble_cs)
2259 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2260
2261 if (queue->initial_preamble_cs)
2262 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2263
2264 if (queue->continue_preamble_cs)
2265 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2266
2267 queue->initial_full_flush_preamble_cs = dest_cs[0];
2268 queue->initial_preamble_cs = dest_cs[1];
2269 queue->continue_preamble_cs = dest_cs[2];
2270
2271 if (scratch_bo != queue->scratch_bo) {
2272 if (queue->scratch_bo)
2273 queue->device->ws->buffer_destroy(queue->scratch_bo);
2274 queue->scratch_bo = scratch_bo;
2275 queue->scratch_size = scratch_size;
2276 }
2277
2278 if (compute_scratch_bo != queue->compute_scratch_bo) {
2279 if (queue->compute_scratch_bo)
2280 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2281 queue->compute_scratch_bo = compute_scratch_bo;
2282 queue->compute_scratch_size = compute_scratch_size;
2283 }
2284
2285 if (esgs_ring_bo != queue->esgs_ring_bo) {
2286 if (queue->esgs_ring_bo)
2287 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2288 queue->esgs_ring_bo = esgs_ring_bo;
2289 queue->esgs_ring_size = esgs_ring_size;
2290 }
2291
2292 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2293 if (queue->gsvs_ring_bo)
2294 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2295 queue->gsvs_ring_bo = gsvs_ring_bo;
2296 queue->gsvs_ring_size = gsvs_ring_size;
2297 }
2298
2299 if (tess_rings_bo != queue->tess_rings_bo) {
2300 queue->tess_rings_bo = tess_rings_bo;
2301 queue->has_tess_rings = true;
2302 }
2303
2304 if (descriptor_bo != queue->descriptor_bo) {
2305 if (queue->descriptor_bo)
2306 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2307
2308 queue->descriptor_bo = descriptor_bo;
2309 }
2310
2311 if (add_sample_positions)
2312 queue->has_sample_positions = true;
2313
2314 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2315 *initial_preamble_cs = queue->initial_preamble_cs;
2316 *continue_preamble_cs = queue->continue_preamble_cs;
2317 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2318 *continue_preamble_cs = NULL;
2319 return VK_SUCCESS;
2320 fail:
2321 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2322 if (dest_cs[i])
2323 queue->device->ws->cs_destroy(dest_cs[i]);
2324 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2325 queue->device->ws->buffer_destroy(descriptor_bo);
2326 if (scratch_bo && scratch_bo != queue->scratch_bo)
2327 queue->device->ws->buffer_destroy(scratch_bo);
2328 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2329 queue->device->ws->buffer_destroy(compute_scratch_bo);
2330 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2331 queue->device->ws->buffer_destroy(esgs_ring_bo);
2332 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2333 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2334 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2335 queue->device->ws->buffer_destroy(tess_rings_bo);
2336 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2337 }
2338
2339 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2340 struct radv_winsys_sem_counts *counts,
2341 int num_sems,
2342 const VkSemaphore *sems,
2343 VkFence _fence,
2344 bool reset_temp)
2345 {
2346 int syncobj_idx = 0, sem_idx = 0;
2347
2348 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2349 return VK_SUCCESS;
2350
2351 for (uint32_t i = 0; i < num_sems; i++) {
2352 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2353
2354 if (sem->temp_syncobj || sem->syncobj)
2355 counts->syncobj_count++;
2356 else
2357 counts->sem_count++;
2358 }
2359
2360 if (_fence != VK_NULL_HANDLE) {
2361 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2362 if (fence->temp_syncobj || fence->syncobj)
2363 counts->syncobj_count++;
2364 }
2365
2366 if (counts->syncobj_count) {
2367 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2368 if (!counts->syncobj)
2369 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2370 }
2371
2372 if (counts->sem_count) {
2373 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2374 if (!counts->sem) {
2375 free(counts->syncobj);
2376 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2377 }
2378 }
2379
2380 for (uint32_t i = 0; i < num_sems; i++) {
2381 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2382
2383 if (sem->temp_syncobj) {
2384 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2385 }
2386 else if (sem->syncobj)
2387 counts->syncobj[syncobj_idx++] = sem->syncobj;
2388 else {
2389 assert(sem->sem);
2390 counts->sem[sem_idx++] = sem->sem;
2391 }
2392 }
2393
2394 if (_fence != VK_NULL_HANDLE) {
2395 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2396 if (fence->temp_syncobj)
2397 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2398 else if (fence->syncobj)
2399 counts->syncobj[syncobj_idx++] = fence->syncobj;
2400 }
2401
2402 return VK_SUCCESS;
2403 }
2404
2405 static void
2406 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2407 {
2408 free(sem_info->wait.syncobj);
2409 free(sem_info->wait.sem);
2410 free(sem_info->signal.syncobj);
2411 free(sem_info->signal.sem);
2412 }
2413
2414
2415 static void radv_free_temp_syncobjs(struct radv_device *device,
2416 int num_sems,
2417 const VkSemaphore *sems)
2418 {
2419 for (uint32_t i = 0; i < num_sems; i++) {
2420 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2421
2422 if (sem->temp_syncobj) {
2423 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2424 sem->temp_syncobj = 0;
2425 }
2426 }
2427 }
2428
2429 static VkResult
2430 radv_alloc_sem_info(struct radv_instance *instance,
2431 struct radv_winsys_sem_info *sem_info,
2432 int num_wait_sems,
2433 const VkSemaphore *wait_sems,
2434 int num_signal_sems,
2435 const VkSemaphore *signal_sems,
2436 VkFence fence)
2437 {
2438 VkResult ret;
2439 memset(sem_info, 0, sizeof(*sem_info));
2440
2441 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2442 if (ret)
2443 return ret;
2444 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2445 if (ret)
2446 radv_free_sem_info(sem_info);
2447
2448 /* caller can override these */
2449 sem_info->cs_emit_wait = true;
2450 sem_info->cs_emit_signal = true;
2451 return ret;
2452 }
2453
2454 /* Signals fence as soon as all the work currently put on queue is done. */
2455 static VkResult radv_signal_fence(struct radv_queue *queue,
2456 struct radv_fence *fence)
2457 {
2458 int ret;
2459 VkResult result;
2460 struct radv_winsys_sem_info sem_info;
2461
2462 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2463 radv_fence_to_handle(fence));
2464 if (result != VK_SUCCESS)
2465 return result;
2466
2467 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2468 &queue->device->empty_cs[queue->queue_family_index],
2469 1, NULL, NULL, &sem_info, NULL,
2470 false, fence->fence);
2471 radv_free_sem_info(&sem_info);
2472
2473 if (ret)
2474 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2475
2476 return VK_SUCCESS;
2477 }
2478
2479 VkResult radv_QueueSubmit(
2480 VkQueue _queue,
2481 uint32_t submitCount,
2482 const VkSubmitInfo* pSubmits,
2483 VkFence _fence)
2484 {
2485 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2486 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2487 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2488 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2489 int ret;
2490 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2491 uint32_t scratch_size = 0;
2492 uint32_t compute_scratch_size = 0;
2493 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2494 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2495 VkResult result;
2496 bool fence_emitted = false;
2497 bool tess_rings_needed = false;
2498 bool sample_positions_needed = false;
2499
2500 /* Do this first so failing to allocate scratch buffers can't result in
2501 * partially executed submissions. */
2502 for (uint32_t i = 0; i < submitCount; i++) {
2503 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2504 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2505 pSubmits[i].pCommandBuffers[j]);
2506
2507 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2508 compute_scratch_size = MAX2(compute_scratch_size,
2509 cmd_buffer->compute_scratch_size_needed);
2510 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2511 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2512 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2513 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2514 }
2515 }
2516
2517 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2518 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2519 sample_positions_needed, &initial_flush_preamble_cs,
2520 &initial_preamble_cs, &continue_preamble_cs);
2521 if (result != VK_SUCCESS)
2522 return result;
2523
2524 for (uint32_t i = 0; i < submitCount; i++) {
2525 struct radeon_cmdbuf **cs_array;
2526 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2527 bool can_patch = true;
2528 uint32_t advance;
2529 struct radv_winsys_sem_info sem_info;
2530
2531 result = radv_alloc_sem_info(queue->device->instance,
2532 &sem_info,
2533 pSubmits[i].waitSemaphoreCount,
2534 pSubmits[i].pWaitSemaphores,
2535 pSubmits[i].signalSemaphoreCount,
2536 pSubmits[i].pSignalSemaphores,
2537 _fence);
2538 if (result != VK_SUCCESS)
2539 return result;
2540
2541 if (!pSubmits[i].commandBufferCount) {
2542 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2543 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2544 &queue->device->empty_cs[queue->queue_family_index],
2545 1, NULL, NULL,
2546 &sem_info, NULL,
2547 false, base_fence);
2548 if (ret) {
2549 radv_loge("failed to submit CS %d\n", i);
2550 abort();
2551 }
2552 fence_emitted = true;
2553 }
2554 radv_free_sem_info(&sem_info);
2555 continue;
2556 }
2557
2558 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2559 (pSubmits[i].commandBufferCount));
2560
2561 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2562 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2563 pSubmits[i].pCommandBuffers[j]);
2564 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2565
2566 cs_array[j] = cmd_buffer->cs;
2567 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2568 can_patch = false;
2569
2570 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2571 }
2572
2573 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2574 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2575 const struct radv_winsys_bo_list *bo_list = NULL;
2576
2577 advance = MIN2(max_cs_submission,
2578 pSubmits[i].commandBufferCount - j);
2579
2580 if (queue->device->trace_bo)
2581 *queue->device->trace_id_ptr = 0;
2582
2583 sem_info.cs_emit_wait = j == 0;
2584 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2585
2586 if (unlikely(queue->device->use_global_bo_list)) {
2587 pthread_mutex_lock(&queue->device->bo_list.mutex);
2588 bo_list = &queue->device->bo_list.list;
2589 }
2590
2591 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2592 advance, initial_preamble, continue_preamble_cs,
2593 &sem_info, bo_list,
2594 can_patch, base_fence);
2595
2596 if (unlikely(queue->device->use_global_bo_list))
2597 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2598
2599 if (ret) {
2600 radv_loge("failed to submit CS %d\n", i);
2601 abort();
2602 }
2603 fence_emitted = true;
2604 if (queue->device->trace_bo) {
2605 radv_check_gpu_hangs(queue, cs_array[j]);
2606 }
2607 }
2608
2609 radv_free_temp_syncobjs(queue->device,
2610 pSubmits[i].waitSemaphoreCount,
2611 pSubmits[i].pWaitSemaphores);
2612 radv_free_sem_info(&sem_info);
2613 free(cs_array);
2614 }
2615
2616 if (fence) {
2617 if (!fence_emitted) {
2618 result = radv_signal_fence(queue, fence);
2619 if (result != VK_SUCCESS)
2620 return result;
2621 }
2622 fence->submitted = true;
2623 }
2624
2625 return VK_SUCCESS;
2626 }
2627
2628 VkResult radv_QueueWaitIdle(
2629 VkQueue _queue)
2630 {
2631 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2632
2633 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2634 radv_queue_family_to_ring(queue->queue_family_index),
2635 queue->queue_idx);
2636 return VK_SUCCESS;
2637 }
2638
2639 VkResult radv_DeviceWaitIdle(
2640 VkDevice _device)
2641 {
2642 RADV_FROM_HANDLE(radv_device, device, _device);
2643
2644 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2645 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2646 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2647 }
2648 }
2649 return VK_SUCCESS;
2650 }
2651
2652 VkResult radv_EnumerateInstanceExtensionProperties(
2653 const char* pLayerName,
2654 uint32_t* pPropertyCount,
2655 VkExtensionProperties* pProperties)
2656 {
2657 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2658
2659 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2660 if (radv_supported_instance_extensions.extensions[i]) {
2661 vk_outarray_append(&out, prop) {
2662 *prop = radv_instance_extensions[i];
2663 }
2664 }
2665 }
2666
2667 return vk_outarray_status(&out);
2668 }
2669
2670 VkResult radv_EnumerateDeviceExtensionProperties(
2671 VkPhysicalDevice physicalDevice,
2672 const char* pLayerName,
2673 uint32_t* pPropertyCount,
2674 VkExtensionProperties* pProperties)
2675 {
2676 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2677 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2678
2679 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2680 if (device->supported_extensions.extensions[i]) {
2681 vk_outarray_append(&out, prop) {
2682 *prop = radv_device_extensions[i];
2683 }
2684 }
2685 }
2686
2687 return vk_outarray_status(&out);
2688 }
2689
2690 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2691 VkInstance _instance,
2692 const char* pName)
2693 {
2694 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2695
2696 return radv_lookup_entrypoint_checked(pName,
2697 instance ? instance->apiVersion : 0,
2698 instance ? &instance->enabled_extensions : NULL,
2699 NULL);
2700 }
2701
2702 /* The loader wants us to expose a second GetInstanceProcAddr function
2703 * to work around certain LD_PRELOAD issues seen in apps.
2704 */
2705 PUBLIC
2706 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2707 VkInstance instance,
2708 const char* pName);
2709
2710 PUBLIC
2711 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2712 VkInstance instance,
2713 const char* pName)
2714 {
2715 return radv_GetInstanceProcAddr(instance, pName);
2716 }
2717
2718 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2719 VkDevice _device,
2720 const char* pName)
2721 {
2722 RADV_FROM_HANDLE(radv_device, device, _device);
2723
2724 return radv_lookup_entrypoint_checked(pName,
2725 device->instance->apiVersion,
2726 &device->instance->enabled_extensions,
2727 &device->enabled_extensions);
2728 }
2729
2730 bool radv_get_memory_fd(struct radv_device *device,
2731 struct radv_device_memory *memory,
2732 int *pFD)
2733 {
2734 struct radeon_bo_metadata metadata;
2735
2736 if (memory->image) {
2737 radv_init_metadata(device, memory->image, &metadata);
2738 device->ws->buffer_set_metadata(memory->bo, &metadata);
2739 }
2740
2741 return device->ws->buffer_get_fd(device->ws, memory->bo,
2742 pFD);
2743 }
2744
2745 static VkResult radv_alloc_memory(struct radv_device *device,
2746 const VkMemoryAllocateInfo* pAllocateInfo,
2747 const VkAllocationCallbacks* pAllocator,
2748 VkDeviceMemory* pMem)
2749 {
2750 struct radv_device_memory *mem;
2751 VkResult result;
2752 enum radeon_bo_domain domain;
2753 uint32_t flags = 0;
2754 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2755
2756 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2757
2758 if (pAllocateInfo->allocationSize == 0) {
2759 /* Apparently, this is allowed */
2760 *pMem = VK_NULL_HANDLE;
2761 return VK_SUCCESS;
2762 }
2763
2764 const VkImportMemoryFdInfoKHR *import_info =
2765 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2766 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2767 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2768 const VkExportMemoryAllocateInfoKHR *export_info =
2769 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2770 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2771 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2772
2773 const struct wsi_memory_allocate_info *wsi_info =
2774 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2775
2776 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2777 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2778 if (mem == NULL)
2779 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2780
2781 if (wsi_info && wsi_info->implicit_sync)
2782 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2783
2784 if (dedicate_info) {
2785 mem->image = radv_image_from_handle(dedicate_info->image);
2786 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2787 } else {
2788 mem->image = NULL;
2789 mem->buffer = NULL;
2790 }
2791
2792 mem->user_ptr = NULL;
2793
2794 if (import_info) {
2795 assert(import_info->handleType ==
2796 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2797 import_info->handleType ==
2798 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2799 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2800 NULL, NULL);
2801 if (!mem->bo) {
2802 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2803 goto fail;
2804 } else {
2805 close(import_info->fd);
2806 }
2807 } else if (host_ptr_info) {
2808 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2809 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2810 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2811 pAllocateInfo->allocationSize);
2812 if (!mem->bo) {
2813 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2814 goto fail;
2815 } else {
2816 mem->user_ptr = host_ptr_info->pHostPointer;
2817 }
2818 } else {
2819 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2820 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2821 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2822 domain = RADEON_DOMAIN_GTT;
2823 else
2824 domain = RADEON_DOMAIN_VRAM;
2825
2826 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2827 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2828 else
2829 flags |= RADEON_FLAG_CPU_ACCESS;
2830
2831 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2832 flags |= RADEON_FLAG_GTT_WC;
2833
2834 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2835 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2836
2837 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2838 domain, flags);
2839
2840 if (!mem->bo) {
2841 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2842 goto fail;
2843 }
2844 mem->type_index = mem_type_index;
2845 }
2846
2847 result = radv_bo_list_add(device, mem->bo);
2848 if (result != VK_SUCCESS)
2849 goto fail_bo;
2850
2851 *pMem = radv_device_memory_to_handle(mem);
2852
2853 return VK_SUCCESS;
2854
2855 fail_bo:
2856 device->ws->buffer_destroy(mem->bo);
2857 fail:
2858 vk_free2(&device->alloc, pAllocator, mem);
2859
2860 return result;
2861 }
2862
2863 VkResult radv_AllocateMemory(
2864 VkDevice _device,
2865 const VkMemoryAllocateInfo* pAllocateInfo,
2866 const VkAllocationCallbacks* pAllocator,
2867 VkDeviceMemory* pMem)
2868 {
2869 RADV_FROM_HANDLE(radv_device, device, _device);
2870 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2871 }
2872
2873 void radv_FreeMemory(
2874 VkDevice _device,
2875 VkDeviceMemory _mem,
2876 const VkAllocationCallbacks* pAllocator)
2877 {
2878 RADV_FROM_HANDLE(radv_device, device, _device);
2879 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2880
2881 if (mem == NULL)
2882 return;
2883
2884 radv_bo_list_remove(device, mem->bo);
2885 device->ws->buffer_destroy(mem->bo);
2886 mem->bo = NULL;
2887
2888 vk_free2(&device->alloc, pAllocator, mem);
2889 }
2890
2891 VkResult radv_MapMemory(
2892 VkDevice _device,
2893 VkDeviceMemory _memory,
2894 VkDeviceSize offset,
2895 VkDeviceSize size,
2896 VkMemoryMapFlags flags,
2897 void** ppData)
2898 {
2899 RADV_FROM_HANDLE(radv_device, device, _device);
2900 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2901
2902 if (mem == NULL) {
2903 *ppData = NULL;
2904 return VK_SUCCESS;
2905 }
2906
2907 if (mem->user_ptr)
2908 *ppData = mem->user_ptr;
2909 else
2910 *ppData = device->ws->buffer_map(mem->bo);
2911
2912 if (*ppData) {
2913 *ppData += offset;
2914 return VK_SUCCESS;
2915 }
2916
2917 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2918 }
2919
2920 void radv_UnmapMemory(
2921 VkDevice _device,
2922 VkDeviceMemory _memory)
2923 {
2924 RADV_FROM_HANDLE(radv_device, device, _device);
2925 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2926
2927 if (mem == NULL)
2928 return;
2929
2930 if (mem->user_ptr == NULL)
2931 device->ws->buffer_unmap(mem->bo);
2932 }
2933
2934 VkResult radv_FlushMappedMemoryRanges(
2935 VkDevice _device,
2936 uint32_t memoryRangeCount,
2937 const VkMappedMemoryRange* pMemoryRanges)
2938 {
2939 return VK_SUCCESS;
2940 }
2941
2942 VkResult radv_InvalidateMappedMemoryRanges(
2943 VkDevice _device,
2944 uint32_t memoryRangeCount,
2945 const VkMappedMemoryRange* pMemoryRanges)
2946 {
2947 return VK_SUCCESS;
2948 }
2949
2950 void radv_GetBufferMemoryRequirements(
2951 VkDevice _device,
2952 VkBuffer _buffer,
2953 VkMemoryRequirements* pMemoryRequirements)
2954 {
2955 RADV_FROM_HANDLE(radv_device, device, _device);
2956 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2957
2958 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2959
2960 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2961 pMemoryRequirements->alignment = 4096;
2962 else
2963 pMemoryRequirements->alignment = 16;
2964
2965 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2966 }
2967
2968 void radv_GetBufferMemoryRequirements2(
2969 VkDevice device,
2970 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2971 VkMemoryRequirements2KHR* pMemoryRequirements)
2972 {
2973 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2974 &pMemoryRequirements->memoryRequirements);
2975 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2976 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2977 switch (ext->sType) {
2978 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2979 VkMemoryDedicatedRequirementsKHR *req =
2980 (VkMemoryDedicatedRequirementsKHR *) ext;
2981 req->requiresDedicatedAllocation = buffer->shareable;
2982 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2983 break;
2984 }
2985 default:
2986 break;
2987 }
2988 }
2989 }
2990
2991 void radv_GetImageMemoryRequirements(
2992 VkDevice _device,
2993 VkImage _image,
2994 VkMemoryRequirements* pMemoryRequirements)
2995 {
2996 RADV_FROM_HANDLE(radv_device, device, _device);
2997 RADV_FROM_HANDLE(radv_image, image, _image);
2998
2999 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3000
3001 pMemoryRequirements->size = image->size;
3002 pMemoryRequirements->alignment = image->alignment;
3003 }
3004
3005 void radv_GetImageMemoryRequirements2(
3006 VkDevice device,
3007 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3008 VkMemoryRequirements2KHR* pMemoryRequirements)
3009 {
3010 radv_GetImageMemoryRequirements(device, pInfo->image,
3011 &pMemoryRequirements->memoryRequirements);
3012
3013 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3014
3015 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3016 switch (ext->sType) {
3017 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3018 VkMemoryDedicatedRequirementsKHR *req =
3019 (VkMemoryDedicatedRequirementsKHR *) ext;
3020 req->requiresDedicatedAllocation = image->shareable;
3021 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3022 break;
3023 }
3024 default:
3025 break;
3026 }
3027 }
3028 }
3029
3030 void radv_GetImageSparseMemoryRequirements(
3031 VkDevice device,
3032 VkImage image,
3033 uint32_t* pSparseMemoryRequirementCount,
3034 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3035 {
3036 stub();
3037 }
3038
3039 void radv_GetImageSparseMemoryRequirements2(
3040 VkDevice device,
3041 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3042 uint32_t* pSparseMemoryRequirementCount,
3043 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3044 {
3045 stub();
3046 }
3047
3048 void radv_GetDeviceMemoryCommitment(
3049 VkDevice device,
3050 VkDeviceMemory memory,
3051 VkDeviceSize* pCommittedMemoryInBytes)
3052 {
3053 *pCommittedMemoryInBytes = 0;
3054 }
3055
3056 VkResult radv_BindBufferMemory2(VkDevice device,
3057 uint32_t bindInfoCount,
3058 const VkBindBufferMemoryInfoKHR *pBindInfos)
3059 {
3060 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3061 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3062 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3063
3064 if (mem) {
3065 buffer->bo = mem->bo;
3066 buffer->offset = pBindInfos[i].memoryOffset;
3067 } else {
3068 buffer->bo = NULL;
3069 }
3070 }
3071 return VK_SUCCESS;
3072 }
3073
3074 VkResult radv_BindBufferMemory(
3075 VkDevice device,
3076 VkBuffer buffer,
3077 VkDeviceMemory memory,
3078 VkDeviceSize memoryOffset)
3079 {
3080 const VkBindBufferMemoryInfoKHR info = {
3081 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3082 .buffer = buffer,
3083 .memory = memory,
3084 .memoryOffset = memoryOffset
3085 };
3086
3087 return radv_BindBufferMemory2(device, 1, &info);
3088 }
3089
3090 VkResult radv_BindImageMemory2(VkDevice device,
3091 uint32_t bindInfoCount,
3092 const VkBindImageMemoryInfoKHR *pBindInfos)
3093 {
3094 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3095 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3096 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3097
3098 if (mem) {
3099 image->bo = mem->bo;
3100 image->offset = pBindInfos[i].memoryOffset;
3101 } else {
3102 image->bo = NULL;
3103 image->offset = 0;
3104 }
3105 }
3106 return VK_SUCCESS;
3107 }
3108
3109
3110 VkResult radv_BindImageMemory(
3111 VkDevice device,
3112 VkImage image,
3113 VkDeviceMemory memory,
3114 VkDeviceSize memoryOffset)
3115 {
3116 const VkBindImageMemoryInfoKHR info = {
3117 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3118 .image = image,
3119 .memory = memory,
3120 .memoryOffset = memoryOffset
3121 };
3122
3123 return radv_BindImageMemory2(device, 1, &info);
3124 }
3125
3126
3127 static void
3128 radv_sparse_buffer_bind_memory(struct radv_device *device,
3129 const VkSparseBufferMemoryBindInfo *bind)
3130 {
3131 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3132
3133 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3134 struct radv_device_memory *mem = NULL;
3135
3136 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3137 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3138
3139 device->ws->buffer_virtual_bind(buffer->bo,
3140 bind->pBinds[i].resourceOffset,
3141 bind->pBinds[i].size,
3142 mem ? mem->bo : NULL,
3143 bind->pBinds[i].memoryOffset);
3144 }
3145 }
3146
3147 static void
3148 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3149 const VkSparseImageOpaqueMemoryBindInfo *bind)
3150 {
3151 RADV_FROM_HANDLE(radv_image, image, bind->image);
3152
3153 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3154 struct radv_device_memory *mem = NULL;
3155
3156 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3157 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3158
3159 device->ws->buffer_virtual_bind(image->bo,
3160 bind->pBinds[i].resourceOffset,
3161 bind->pBinds[i].size,
3162 mem ? mem->bo : NULL,
3163 bind->pBinds[i].memoryOffset);
3164 }
3165 }
3166
3167 VkResult radv_QueueBindSparse(
3168 VkQueue _queue,
3169 uint32_t bindInfoCount,
3170 const VkBindSparseInfo* pBindInfo,
3171 VkFence _fence)
3172 {
3173 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3174 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3175 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3176 bool fence_emitted = false;
3177 VkResult result;
3178 int ret;
3179
3180 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3181 struct radv_winsys_sem_info sem_info;
3182 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3183 radv_sparse_buffer_bind_memory(queue->device,
3184 pBindInfo[i].pBufferBinds + j);
3185 }
3186
3187 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3188 radv_sparse_image_opaque_bind_memory(queue->device,
3189 pBindInfo[i].pImageOpaqueBinds + j);
3190 }
3191
3192 VkResult result;
3193 result = radv_alloc_sem_info(queue->device->instance,
3194 &sem_info,
3195 pBindInfo[i].waitSemaphoreCount,
3196 pBindInfo[i].pWaitSemaphores,
3197 pBindInfo[i].signalSemaphoreCount,
3198 pBindInfo[i].pSignalSemaphores,
3199 _fence);
3200 if (result != VK_SUCCESS)
3201 return result;
3202
3203 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3204 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3205 &queue->device->empty_cs[queue->queue_family_index],
3206 1, NULL, NULL,
3207 &sem_info, NULL,
3208 false, base_fence);
3209 if (ret) {
3210 radv_loge("failed to submit CS %d\n", i);
3211 abort();
3212 }
3213
3214 fence_emitted = true;
3215 if (fence)
3216 fence->submitted = true;
3217 }
3218
3219 radv_free_sem_info(&sem_info);
3220
3221 }
3222
3223 if (fence) {
3224 if (!fence_emitted) {
3225 result = radv_signal_fence(queue, fence);
3226 if (result != VK_SUCCESS)
3227 return result;
3228 }
3229 fence->submitted = true;
3230 }
3231
3232 return VK_SUCCESS;
3233 }
3234
3235 VkResult radv_CreateFence(
3236 VkDevice _device,
3237 const VkFenceCreateInfo* pCreateInfo,
3238 const VkAllocationCallbacks* pAllocator,
3239 VkFence* pFence)
3240 {
3241 RADV_FROM_HANDLE(radv_device, device, _device);
3242 const VkExportFenceCreateInfoKHR *export =
3243 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3244 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3245 export ? export->handleTypes : 0;
3246
3247 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3248 sizeof(*fence), 8,
3249 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3250
3251 if (!fence)
3252 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3253
3254 fence->submitted = false;
3255 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3256 fence->temp_syncobj = 0;
3257 if (device->always_use_syncobj || handleTypes) {
3258 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3259 if (ret) {
3260 vk_free2(&device->alloc, pAllocator, fence);
3261 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3262 }
3263 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3264 device->ws->signal_syncobj(device->ws, fence->syncobj);
3265 }
3266 fence->fence = NULL;
3267 } else {
3268 fence->fence = device->ws->create_fence();
3269 if (!fence->fence) {
3270 vk_free2(&device->alloc, pAllocator, fence);
3271 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3272 }
3273 fence->syncobj = 0;
3274 }
3275
3276 *pFence = radv_fence_to_handle(fence);
3277
3278 return VK_SUCCESS;
3279 }
3280
3281 void radv_DestroyFence(
3282 VkDevice _device,
3283 VkFence _fence,
3284 const VkAllocationCallbacks* pAllocator)
3285 {
3286 RADV_FROM_HANDLE(radv_device, device, _device);
3287 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3288
3289 if (!fence)
3290 return;
3291
3292 if (fence->temp_syncobj)
3293 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3294 if (fence->syncobj)
3295 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3296 if (fence->fence)
3297 device->ws->destroy_fence(fence->fence);
3298 vk_free2(&device->alloc, pAllocator, fence);
3299 }
3300
3301
3302 static uint64_t radv_get_current_time()
3303 {
3304 struct timespec tv;
3305 clock_gettime(CLOCK_MONOTONIC, &tv);
3306 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3307 }
3308
3309 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3310 {
3311 uint64_t current_time = radv_get_current_time();
3312
3313 timeout = MIN2(UINT64_MAX - current_time, timeout);
3314
3315 return current_time + timeout;
3316 }
3317
3318
3319 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3320 {
3321 for (uint32_t i = 0; i < fenceCount; ++i) {
3322 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3323 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3324 return false;
3325 }
3326 return true;
3327 }
3328
3329 VkResult radv_WaitForFences(
3330 VkDevice _device,
3331 uint32_t fenceCount,
3332 const VkFence* pFences,
3333 VkBool32 waitAll,
3334 uint64_t timeout)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337 timeout = radv_get_absolute_timeout(timeout);
3338
3339 if (device->always_use_syncobj) {
3340 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3341 if (!handles)
3342 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3343
3344 for (uint32_t i = 0; i < fenceCount; ++i) {
3345 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3346 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3347 }
3348
3349 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3350
3351 free(handles);
3352 return success ? VK_SUCCESS : VK_TIMEOUT;
3353 }
3354
3355 if (!waitAll && fenceCount > 1) {
3356 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3357 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3358 uint32_t wait_count = 0;
3359 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3360 if (!fences)
3361 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3362
3363 for (uint32_t i = 0; i < fenceCount; ++i) {
3364 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3365
3366 if (fence->signalled) {
3367 free(fences);
3368 return VK_SUCCESS;
3369 }
3370
3371 fences[wait_count++] = fence->fence;
3372 }
3373
3374 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3375 waitAll, timeout - radv_get_current_time());
3376
3377 free(fences);
3378 return success ? VK_SUCCESS : VK_TIMEOUT;
3379 }
3380
3381 while(radv_get_current_time() <= timeout) {
3382 for (uint32_t i = 0; i < fenceCount; ++i) {
3383 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3384 return VK_SUCCESS;
3385 }
3386 }
3387 return VK_TIMEOUT;
3388 }
3389
3390 for (uint32_t i = 0; i < fenceCount; ++i) {
3391 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3392 bool expired = false;
3393
3394 if (fence->temp_syncobj) {
3395 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3396 return VK_TIMEOUT;
3397 continue;
3398 }
3399
3400 if (fence->syncobj) {
3401 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3402 return VK_TIMEOUT;
3403 continue;
3404 }
3405
3406 if (fence->signalled)
3407 continue;
3408
3409 if (!fence->submitted) {
3410 while(radv_get_current_time() <= timeout && !fence->submitted)
3411 /* Do nothing */;
3412
3413 if (!fence->submitted)
3414 return VK_TIMEOUT;
3415
3416 /* Recheck as it may have been set by submitting operations. */
3417 if (fence->signalled)
3418 continue;
3419 }
3420
3421 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3422 if (!expired)
3423 return VK_TIMEOUT;
3424
3425 fence->signalled = true;
3426 }
3427
3428 return VK_SUCCESS;
3429 }
3430
3431 VkResult radv_ResetFences(VkDevice _device,
3432 uint32_t fenceCount,
3433 const VkFence *pFences)
3434 {
3435 RADV_FROM_HANDLE(radv_device, device, _device);
3436
3437 for (unsigned i = 0; i < fenceCount; ++i) {
3438 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3439 fence->submitted = fence->signalled = false;
3440
3441 /* Per spec, we first restore the permanent payload, and then reset, so
3442 * having a temp syncobj should not skip resetting the permanent syncobj. */
3443 if (fence->temp_syncobj) {
3444 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3445 fence->temp_syncobj = 0;
3446 }
3447
3448 if (fence->syncobj) {
3449 device->ws->reset_syncobj(device->ws, fence->syncobj);
3450 }
3451 }
3452
3453 return VK_SUCCESS;
3454 }
3455
3456 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3457 {
3458 RADV_FROM_HANDLE(radv_device, device, _device);
3459 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3460
3461 if (fence->temp_syncobj) {
3462 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3463 return success ? VK_SUCCESS : VK_NOT_READY;
3464 }
3465
3466 if (fence->syncobj) {
3467 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3468 return success ? VK_SUCCESS : VK_NOT_READY;
3469 }
3470
3471 if (fence->signalled)
3472 return VK_SUCCESS;
3473 if (!fence->submitted)
3474 return VK_NOT_READY;
3475 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3476 return VK_NOT_READY;
3477
3478 return VK_SUCCESS;
3479 }
3480
3481
3482 // Queue semaphore functions
3483
3484 VkResult radv_CreateSemaphore(
3485 VkDevice _device,
3486 const VkSemaphoreCreateInfo* pCreateInfo,
3487 const VkAllocationCallbacks* pAllocator,
3488 VkSemaphore* pSemaphore)
3489 {
3490 RADV_FROM_HANDLE(radv_device, device, _device);
3491 const VkExportSemaphoreCreateInfoKHR *export =
3492 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3493 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3494 export ? export->handleTypes : 0;
3495
3496 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3497 sizeof(*sem), 8,
3498 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3499 if (!sem)
3500 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3501
3502 sem->temp_syncobj = 0;
3503 /* create a syncobject if we are going to export this semaphore */
3504 if (device->always_use_syncobj || handleTypes) {
3505 assert (device->physical_device->rad_info.has_syncobj);
3506 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3507 if (ret) {
3508 vk_free2(&device->alloc, pAllocator, sem);
3509 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3510 }
3511 sem->sem = NULL;
3512 } else {
3513 sem->sem = device->ws->create_sem(device->ws);
3514 if (!sem->sem) {
3515 vk_free2(&device->alloc, pAllocator, sem);
3516 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3517 }
3518 sem->syncobj = 0;
3519 }
3520
3521 *pSemaphore = radv_semaphore_to_handle(sem);
3522 return VK_SUCCESS;
3523 }
3524
3525 void radv_DestroySemaphore(
3526 VkDevice _device,
3527 VkSemaphore _semaphore,
3528 const VkAllocationCallbacks* pAllocator)
3529 {
3530 RADV_FROM_HANDLE(radv_device, device, _device);
3531 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3532 if (!_semaphore)
3533 return;
3534
3535 if (sem->syncobj)
3536 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3537 else
3538 device->ws->destroy_sem(sem->sem);
3539 vk_free2(&device->alloc, pAllocator, sem);
3540 }
3541
3542 VkResult radv_CreateEvent(
3543 VkDevice _device,
3544 const VkEventCreateInfo* pCreateInfo,
3545 const VkAllocationCallbacks* pAllocator,
3546 VkEvent* pEvent)
3547 {
3548 RADV_FROM_HANDLE(radv_device, device, _device);
3549 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3550 sizeof(*event), 8,
3551 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3552
3553 if (!event)
3554 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3555
3556 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3557 RADEON_DOMAIN_GTT,
3558 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3559 if (!event->bo) {
3560 vk_free2(&device->alloc, pAllocator, event);
3561 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3562 }
3563
3564 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3565
3566 *pEvent = radv_event_to_handle(event);
3567
3568 return VK_SUCCESS;
3569 }
3570
3571 void radv_DestroyEvent(
3572 VkDevice _device,
3573 VkEvent _event,
3574 const VkAllocationCallbacks* pAllocator)
3575 {
3576 RADV_FROM_HANDLE(radv_device, device, _device);
3577 RADV_FROM_HANDLE(radv_event, event, _event);
3578
3579 if (!event)
3580 return;
3581 device->ws->buffer_destroy(event->bo);
3582 vk_free2(&device->alloc, pAllocator, event);
3583 }
3584
3585 VkResult radv_GetEventStatus(
3586 VkDevice _device,
3587 VkEvent _event)
3588 {
3589 RADV_FROM_HANDLE(radv_event, event, _event);
3590
3591 if (*event->map == 1)
3592 return VK_EVENT_SET;
3593 return VK_EVENT_RESET;
3594 }
3595
3596 VkResult radv_SetEvent(
3597 VkDevice _device,
3598 VkEvent _event)
3599 {
3600 RADV_FROM_HANDLE(radv_event, event, _event);
3601 *event->map = 1;
3602
3603 return VK_SUCCESS;
3604 }
3605
3606 VkResult radv_ResetEvent(
3607 VkDevice _device,
3608 VkEvent _event)
3609 {
3610 RADV_FROM_HANDLE(radv_event, event, _event);
3611 *event->map = 0;
3612
3613 return VK_SUCCESS;
3614 }
3615
3616 VkResult radv_CreateBuffer(
3617 VkDevice _device,
3618 const VkBufferCreateInfo* pCreateInfo,
3619 const VkAllocationCallbacks* pAllocator,
3620 VkBuffer* pBuffer)
3621 {
3622 RADV_FROM_HANDLE(radv_device, device, _device);
3623 struct radv_buffer *buffer;
3624
3625 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3626
3627 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3628 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3629 if (buffer == NULL)
3630 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3631
3632 buffer->size = pCreateInfo->size;
3633 buffer->usage = pCreateInfo->usage;
3634 buffer->bo = NULL;
3635 buffer->offset = 0;
3636 buffer->flags = pCreateInfo->flags;
3637
3638 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3639 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3640
3641 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3642 buffer->bo = device->ws->buffer_create(device->ws,
3643 align64(buffer->size, 4096),
3644 4096, 0, RADEON_FLAG_VIRTUAL);
3645 if (!buffer->bo) {
3646 vk_free2(&device->alloc, pAllocator, buffer);
3647 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3648 }
3649 }
3650
3651 *pBuffer = radv_buffer_to_handle(buffer);
3652
3653 return VK_SUCCESS;
3654 }
3655
3656 void radv_DestroyBuffer(
3657 VkDevice _device,
3658 VkBuffer _buffer,
3659 const VkAllocationCallbacks* pAllocator)
3660 {
3661 RADV_FROM_HANDLE(radv_device, device, _device);
3662 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3663
3664 if (!buffer)
3665 return;
3666
3667 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3668 device->ws->buffer_destroy(buffer->bo);
3669
3670 vk_free2(&device->alloc, pAllocator, buffer);
3671 }
3672
3673 static inline unsigned
3674 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3675 {
3676 if (stencil)
3677 return image->surface.u.legacy.stencil_tiling_index[level];
3678 else
3679 return image->surface.u.legacy.tiling_index[level];
3680 }
3681
3682 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3683 {
3684 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3685 }
3686
3687 static uint32_t
3688 radv_init_dcc_control_reg(struct radv_device *device,
3689 struct radv_image_view *iview)
3690 {
3691 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3692 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3693 unsigned max_compressed_block_size;
3694 unsigned independent_64b_blocks;
3695
3696 if (device->physical_device->rad_info.chip_class < VI)
3697 return 0;
3698
3699 if (iview->image->info.samples > 1) {
3700 if (iview->image->surface.bpe == 1)
3701 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3702 else if (iview->image->surface.bpe == 2)
3703 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3704 }
3705
3706 if (!device->physical_device->rad_info.has_dedicated_vram) {
3707 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3708 * dGPU and 64 for APU because all of our APUs to date use
3709 * DIMMs which have a request granularity size of 64B while all
3710 * other chips have a 32B request size.
3711 */
3712 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3713 }
3714
3715 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3716 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3717 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3718 /* If this DCC image is potentially going to be used in texture
3719 * fetches, we need some special settings.
3720 */
3721 independent_64b_blocks = 1;
3722 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3723 } else {
3724 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3725 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3726 * big as possible for better compression state.
3727 */
3728 independent_64b_blocks = 0;
3729 max_compressed_block_size = max_uncompressed_block_size;
3730 }
3731
3732 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3733 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3734 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3735 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3736 }
3737
3738 static void
3739 radv_initialise_color_surface(struct radv_device *device,
3740 struct radv_color_buffer_info *cb,
3741 struct radv_image_view *iview)
3742 {
3743 const struct vk_format_description *desc;
3744 unsigned ntype, format, swap, endian;
3745 unsigned blend_clamp = 0, blend_bypass = 0;
3746 uint64_t va;
3747 const struct radeon_surf *surf = &iview->image->surface;
3748
3749 desc = vk_format_description(iview->vk_format);
3750
3751 memset(cb, 0, sizeof(*cb));
3752
3753 /* Intensity is implemented as Red, so treat it that way. */
3754 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3755
3756 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3757
3758 cb->cb_color_base = va >> 8;
3759
3760 if (device->physical_device->rad_info.chip_class >= GFX9) {
3761 struct gfx9_surf_meta_flags meta;
3762 if (iview->image->dcc_offset)
3763 meta = iview->image->surface.u.gfx9.dcc;
3764 else
3765 meta = iview->image->surface.u.gfx9.cmask;
3766
3767 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3768 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3769 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3770 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3771
3772 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3773 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3774 } else {
3775 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3776 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3777
3778 cb->cb_color_base += level_info->offset >> 8;
3779 if (level_info->mode == RADEON_SURF_MODE_2D)
3780 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3781
3782 pitch_tile_max = level_info->nblk_x / 8 - 1;
3783 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3784 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3785
3786 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3787 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3788 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3789
3790 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3791
3792 if (radv_image_has_fmask(iview->image)) {
3793 if (device->physical_device->rad_info.chip_class >= CIK)
3794 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3795 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3796 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3797 } else {
3798 /* This must be set for fast clear to work without FMASK. */
3799 if (device->physical_device->rad_info.chip_class >= CIK)
3800 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3801 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3802 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3803 }
3804 }
3805
3806 /* CMASK variables */
3807 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3808 va += iview->image->cmask.offset;
3809 cb->cb_color_cmask = va >> 8;
3810
3811 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3812 va += iview->image->dcc_offset;
3813 cb->cb_dcc_base = va >> 8;
3814 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3815
3816 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3817 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3818 S_028C6C_SLICE_MAX(max_slice);
3819
3820 if (iview->image->info.samples > 1) {
3821 unsigned log_samples = util_logbase2(iview->image->info.samples);
3822
3823 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3824 S_028C74_NUM_FRAGMENTS(log_samples);
3825 }
3826
3827 if (radv_image_has_fmask(iview->image)) {
3828 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3829 cb->cb_color_fmask = va >> 8;
3830 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3831 } else {
3832 cb->cb_color_fmask = cb->cb_color_base;
3833 }
3834
3835 ntype = radv_translate_color_numformat(iview->vk_format,
3836 desc,
3837 vk_format_get_first_non_void_channel(iview->vk_format));
3838 format = radv_translate_colorformat(iview->vk_format);
3839 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3840 radv_finishme("Illegal color\n");
3841 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3842 endian = radv_colorformat_endian_swap(format);
3843
3844 /* blend clamp should be set for all NORM/SRGB types */
3845 if (ntype == V_028C70_NUMBER_UNORM ||
3846 ntype == V_028C70_NUMBER_SNORM ||
3847 ntype == V_028C70_NUMBER_SRGB)
3848 blend_clamp = 1;
3849
3850 /* set blend bypass according to docs if SINT/UINT or
3851 8/24 COLOR variants */
3852 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3853 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3854 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3855 blend_clamp = 0;
3856 blend_bypass = 1;
3857 }
3858 #if 0
3859 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3860 (format == V_028C70_COLOR_8 ||
3861 format == V_028C70_COLOR_8_8 ||
3862 format == V_028C70_COLOR_8_8_8_8))
3863 ->color_is_int8 = true;
3864 #endif
3865 cb->cb_color_info = S_028C70_FORMAT(format) |
3866 S_028C70_COMP_SWAP(swap) |
3867 S_028C70_BLEND_CLAMP(blend_clamp) |
3868 S_028C70_BLEND_BYPASS(blend_bypass) |
3869 S_028C70_SIMPLE_FLOAT(1) |
3870 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3871 ntype != V_028C70_NUMBER_SNORM &&
3872 ntype != V_028C70_NUMBER_SRGB &&
3873 format != V_028C70_COLOR_8_24 &&
3874 format != V_028C70_COLOR_24_8) |
3875 S_028C70_NUMBER_TYPE(ntype) |
3876 S_028C70_ENDIAN(endian);
3877 if (radv_image_has_fmask(iview->image)) {
3878 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3879 if (device->physical_device->rad_info.chip_class == SI) {
3880 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3881 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3882 }
3883 }
3884
3885 if (radv_image_has_cmask(iview->image) &&
3886 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3887 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3888
3889 if (radv_dcc_enabled(iview->image, iview->base_mip))
3890 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3891
3892 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3893
3894 /* This must be set for fast clear to work without FMASK. */
3895 if (!radv_image_has_fmask(iview->image) &&
3896 device->physical_device->rad_info.chip_class == SI) {
3897 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3898 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3899 }
3900
3901 if (device->physical_device->rad_info.chip_class >= GFX9) {
3902 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3903 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3904
3905 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3906 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3907 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3908 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3909 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3910 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3911 }
3912 }
3913
3914 static unsigned
3915 radv_calc_decompress_on_z_planes(struct radv_device *device,
3916 struct radv_image_view *iview)
3917 {
3918 unsigned max_zplanes = 0;
3919
3920 assert(radv_image_is_tc_compat_htile(iview->image));
3921
3922 if (device->physical_device->rad_info.chip_class >= GFX9) {
3923 /* Default value for 32-bit depth surfaces. */
3924 max_zplanes = 4;
3925
3926 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3927 iview->image->info.samples > 1)
3928 max_zplanes = 2;
3929
3930 max_zplanes = max_zplanes + 1;
3931 } else {
3932 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3933 /* Do not enable Z plane compression for 16-bit depth
3934 * surfaces because isn't supported on GFX8. Only
3935 * 32-bit depth surfaces are supported by the hardware.
3936 * This allows to maintain shader compatibility and to
3937 * reduce the number of depth decompressions.
3938 */
3939 max_zplanes = 1;
3940 } else {
3941 if (iview->image->info.samples <= 1)
3942 max_zplanes = 5;
3943 else if (iview->image->info.samples <= 4)
3944 max_zplanes = 3;
3945 else
3946 max_zplanes = 2;
3947 }
3948 }
3949
3950 return max_zplanes;
3951 }
3952
3953 static void
3954 radv_initialise_ds_surface(struct radv_device *device,
3955 struct radv_ds_buffer_info *ds,
3956 struct radv_image_view *iview)
3957 {
3958 unsigned level = iview->base_mip;
3959 unsigned format, stencil_format;
3960 uint64_t va, s_offs, z_offs;
3961 bool stencil_only = false;
3962 memset(ds, 0, sizeof(*ds));
3963 switch (iview->image->vk_format) {
3964 case VK_FORMAT_D24_UNORM_S8_UINT:
3965 case VK_FORMAT_X8_D24_UNORM_PACK32:
3966 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3967 ds->offset_scale = 2.0f;
3968 break;
3969 case VK_FORMAT_D16_UNORM:
3970 case VK_FORMAT_D16_UNORM_S8_UINT:
3971 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3972 ds->offset_scale = 4.0f;
3973 break;
3974 case VK_FORMAT_D32_SFLOAT:
3975 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3976 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3977 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3978 ds->offset_scale = 1.0f;
3979 break;
3980 case VK_FORMAT_S8_UINT:
3981 stencil_only = true;
3982 break;
3983 default:
3984 break;
3985 }
3986
3987 format = radv_translate_dbformat(iview->image->vk_format);
3988 stencil_format = iview->image->surface.has_stencil ?
3989 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3990
3991 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3992 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3993 S_028008_SLICE_MAX(max_slice);
3994
3995 ds->db_htile_data_base = 0;
3996 ds->db_htile_surface = 0;
3997
3998 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3999 s_offs = z_offs = va;
4000
4001 if (device->physical_device->rad_info.chip_class >= GFX9) {
4002 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4003 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4004
4005 ds->db_z_info = S_028038_FORMAT(format) |
4006 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4007 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4008 S_028038_MAXMIP(iview->image->info.levels - 1) |
4009 S_028038_ZRANGE_PRECISION(1);
4010 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4011 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4012
4013 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4014 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4015 ds->db_depth_view |= S_028008_MIPID(level);
4016
4017 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4018 S_02801C_Y_MAX(iview->image->info.height - 1);
4019
4020 if (radv_htile_enabled(iview->image, level)) {
4021 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4022
4023 if (radv_image_is_tc_compat_htile(iview->image)) {
4024 unsigned max_zplanes =
4025 radv_calc_decompress_on_z_planes(device, iview);
4026
4027 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4028 S_028038_ITERATE_FLUSH(1);
4029 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4030 }
4031
4032 if (!iview->image->surface.has_stencil)
4033 /* Use all of the htile_buffer for depth if there's no stencil. */
4034 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4035 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4036 iview->image->htile_offset;
4037 ds->db_htile_data_base = va >> 8;
4038 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4039 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4040 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4041 }
4042 } else {
4043 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4044
4045 if (stencil_only)
4046 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4047
4048 z_offs += iview->image->surface.u.legacy.level[level].offset;
4049 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4050
4051 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4052 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4053 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4054
4055 if (iview->image->info.samples > 1)
4056 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4057
4058 if (device->physical_device->rad_info.chip_class >= CIK) {
4059 struct radeon_info *info = &device->physical_device->rad_info;
4060 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4061 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4062 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4063 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4064 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4065 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4066
4067 if (stencil_only)
4068 tile_mode = stencil_tile_mode;
4069
4070 ds->db_depth_info |=
4071 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4072 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4073 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4074 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4075 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4076 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4077 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4078 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4079 } else {
4080 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4081 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4082 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4083 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4084 if (stencil_only)
4085 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4086 }
4087
4088 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4089 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4090 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4091
4092 if (radv_htile_enabled(iview->image, level)) {
4093 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4094
4095 if (!iview->image->surface.has_stencil &&
4096 !radv_image_is_tc_compat_htile(iview->image))
4097 /* Use all of the htile_buffer for depth if there's no stencil. */
4098 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4099
4100 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4101 iview->image->htile_offset;
4102 ds->db_htile_data_base = va >> 8;
4103 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4104
4105 if (radv_image_is_tc_compat_htile(iview->image)) {
4106 unsigned max_zplanes =
4107 radv_calc_decompress_on_z_planes(device, iview);
4108
4109 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4110 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4111 }
4112 }
4113 }
4114
4115 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4116 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4117 }
4118
4119 VkResult radv_CreateFramebuffer(
4120 VkDevice _device,
4121 const VkFramebufferCreateInfo* pCreateInfo,
4122 const VkAllocationCallbacks* pAllocator,
4123 VkFramebuffer* pFramebuffer)
4124 {
4125 RADV_FROM_HANDLE(radv_device, device, _device);
4126 struct radv_framebuffer *framebuffer;
4127
4128 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4129
4130 size_t size = sizeof(*framebuffer) +
4131 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4132 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4133 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4134 if (framebuffer == NULL)
4135 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4136
4137 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4138 framebuffer->width = pCreateInfo->width;
4139 framebuffer->height = pCreateInfo->height;
4140 framebuffer->layers = pCreateInfo->layers;
4141 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4142 VkImageView _iview = pCreateInfo->pAttachments[i];
4143 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4144 framebuffer->attachments[i].attachment = iview;
4145 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4146 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4147 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4148 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4149 }
4150 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4151 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4152 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4153 }
4154
4155 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4156 return VK_SUCCESS;
4157 }
4158
4159 void radv_DestroyFramebuffer(
4160 VkDevice _device,
4161 VkFramebuffer _fb,
4162 const VkAllocationCallbacks* pAllocator)
4163 {
4164 RADV_FROM_HANDLE(radv_device, device, _device);
4165 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4166
4167 if (!fb)
4168 return;
4169 vk_free2(&device->alloc, pAllocator, fb);
4170 }
4171
4172 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4173 {
4174 switch (address_mode) {
4175 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4176 return V_008F30_SQ_TEX_WRAP;
4177 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4178 return V_008F30_SQ_TEX_MIRROR;
4179 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4180 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4181 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4182 return V_008F30_SQ_TEX_CLAMP_BORDER;
4183 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4184 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4185 default:
4186 unreachable("illegal tex wrap mode");
4187 break;
4188 }
4189 }
4190
4191 static unsigned
4192 radv_tex_compare(VkCompareOp op)
4193 {
4194 switch (op) {
4195 case VK_COMPARE_OP_NEVER:
4196 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4197 case VK_COMPARE_OP_LESS:
4198 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4199 case VK_COMPARE_OP_EQUAL:
4200 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4201 case VK_COMPARE_OP_LESS_OR_EQUAL:
4202 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4203 case VK_COMPARE_OP_GREATER:
4204 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4205 case VK_COMPARE_OP_NOT_EQUAL:
4206 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4207 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4208 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4209 case VK_COMPARE_OP_ALWAYS:
4210 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4211 default:
4212 unreachable("illegal compare mode");
4213 break;
4214 }
4215 }
4216
4217 static unsigned
4218 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4219 {
4220 switch (filter) {
4221 case VK_FILTER_NEAREST:
4222 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4223 V_008F38_SQ_TEX_XY_FILTER_POINT);
4224 case VK_FILTER_LINEAR:
4225 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4226 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4227 case VK_FILTER_CUBIC_IMG:
4228 default:
4229 fprintf(stderr, "illegal texture filter");
4230 return 0;
4231 }
4232 }
4233
4234 static unsigned
4235 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4236 {
4237 switch (mode) {
4238 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4239 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4240 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4241 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4242 default:
4243 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4244 }
4245 }
4246
4247 static unsigned
4248 radv_tex_bordercolor(VkBorderColor bcolor)
4249 {
4250 switch (bcolor) {
4251 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4252 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4253 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4254 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4255 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4256 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4257 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4258 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4259 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4260 default:
4261 break;
4262 }
4263 return 0;
4264 }
4265
4266 static unsigned
4267 radv_tex_aniso_filter(unsigned filter)
4268 {
4269 if (filter < 2)
4270 return 0;
4271 if (filter < 4)
4272 return 1;
4273 if (filter < 8)
4274 return 2;
4275 if (filter < 16)
4276 return 3;
4277 return 4;
4278 }
4279
4280 static unsigned
4281 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4282 {
4283 switch (mode) {
4284 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4285 return SQ_IMG_FILTER_MODE_BLEND;
4286 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4287 return SQ_IMG_FILTER_MODE_MIN;
4288 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4289 return SQ_IMG_FILTER_MODE_MAX;
4290 default:
4291 break;
4292 }
4293 return 0;
4294 }
4295
4296 static void
4297 radv_init_sampler(struct radv_device *device,
4298 struct radv_sampler *sampler,
4299 const VkSamplerCreateInfo *pCreateInfo)
4300 {
4301 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4302 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4303 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4304 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4305 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4306
4307 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4308 vk_find_struct_const(pCreateInfo->pNext,
4309 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4310 if (sampler_reduction)
4311 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4312
4313 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4314 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4315 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4316 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4317 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4318 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4319 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4320 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4321 S_008F30_DISABLE_CUBE_WRAP(0) |
4322 S_008F30_COMPAT_MODE(is_vi) |
4323 S_008F30_FILTER_MODE(filter_mode));
4324 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4325 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4326 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4327 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4328 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4329 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4330 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4331 S_008F38_MIP_POINT_PRECLAMP(0) |
4332 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4333 S_008F38_FILTER_PREC_FIX(1) |
4334 S_008F38_ANISO_OVERRIDE(is_vi));
4335 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4336 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4337 }
4338
4339 VkResult radv_CreateSampler(
4340 VkDevice _device,
4341 const VkSamplerCreateInfo* pCreateInfo,
4342 const VkAllocationCallbacks* pAllocator,
4343 VkSampler* pSampler)
4344 {
4345 RADV_FROM_HANDLE(radv_device, device, _device);
4346 struct radv_sampler *sampler;
4347
4348 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4349
4350 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4351 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4352 if (!sampler)
4353 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4354
4355 radv_init_sampler(device, sampler, pCreateInfo);
4356 *pSampler = radv_sampler_to_handle(sampler);
4357
4358 return VK_SUCCESS;
4359 }
4360
4361 void radv_DestroySampler(
4362 VkDevice _device,
4363 VkSampler _sampler,
4364 const VkAllocationCallbacks* pAllocator)
4365 {
4366 RADV_FROM_HANDLE(radv_device, device, _device);
4367 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4368
4369 if (!sampler)
4370 return;
4371 vk_free2(&device->alloc, pAllocator, sampler);
4372 }
4373
4374 /* vk_icd.h does not declare this function, so we declare it here to
4375 * suppress Wmissing-prototypes.
4376 */
4377 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4378 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4379
4380 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4381 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4382 {
4383 /* For the full details on loader interface versioning, see
4384 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4385 * What follows is a condensed summary, to help you navigate the large and
4386 * confusing official doc.
4387 *
4388 * - Loader interface v0 is incompatible with later versions. We don't
4389 * support it.
4390 *
4391 * - In loader interface v1:
4392 * - The first ICD entrypoint called by the loader is
4393 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4394 * entrypoint.
4395 * - The ICD must statically expose no other Vulkan symbol unless it is
4396 * linked with -Bsymbolic.
4397 * - Each dispatchable Vulkan handle created by the ICD must be
4398 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4399 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4400 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4401 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4402 * such loader-managed surfaces.
4403 *
4404 * - Loader interface v2 differs from v1 in:
4405 * - The first ICD entrypoint called by the loader is
4406 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4407 * statically expose this entrypoint.
4408 *
4409 * - Loader interface v3 differs from v2 in:
4410 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4411 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4412 * because the loader no longer does so.
4413 */
4414 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4415 return VK_SUCCESS;
4416 }
4417
4418 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4419 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4420 int *pFD)
4421 {
4422 RADV_FROM_HANDLE(radv_device, device, _device);
4423 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4424
4425 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4426
4427 /* At the moment, we support only the below handle types. */
4428 assert(pGetFdInfo->handleType ==
4429 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4430 pGetFdInfo->handleType ==
4431 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4432
4433 bool ret = radv_get_memory_fd(device, memory, pFD);
4434 if (ret == false)
4435 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4436 return VK_SUCCESS;
4437 }
4438
4439 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4440 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4441 int fd,
4442 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4443 {
4444 RADV_FROM_HANDLE(radv_device, device, _device);
4445
4446 switch (handleType) {
4447 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4448 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4449 return VK_SUCCESS;
4450
4451 default:
4452 /* The valid usage section for this function says:
4453 *
4454 * "handleType must not be one of the handle types defined as
4455 * opaque."
4456 *
4457 * So opaque handle types fall into the default "unsupported" case.
4458 */
4459 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4460 }
4461 }
4462
4463 static VkResult radv_import_opaque_fd(struct radv_device *device,
4464 int fd,
4465 uint32_t *syncobj)
4466 {
4467 uint32_t syncobj_handle = 0;
4468 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4469 if (ret != 0)
4470 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4471
4472 if (*syncobj)
4473 device->ws->destroy_syncobj(device->ws, *syncobj);
4474
4475 *syncobj = syncobj_handle;
4476 close(fd);
4477
4478 return VK_SUCCESS;
4479 }
4480
4481 static VkResult radv_import_sync_fd(struct radv_device *device,
4482 int fd,
4483 uint32_t *syncobj)
4484 {
4485 /* If we create a syncobj we do it locally so that if we have an error, we don't
4486 * leave a syncobj in an undetermined state in the fence. */
4487 uint32_t syncobj_handle = *syncobj;
4488 if (!syncobj_handle) {
4489 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4490 if (ret) {
4491 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4492 }
4493 }
4494
4495 if (fd == -1) {
4496 device->ws->signal_syncobj(device->ws, syncobj_handle);
4497 } else {
4498 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4499 if (ret != 0)
4500 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4501 }
4502
4503 *syncobj = syncobj_handle;
4504 if (fd != -1)
4505 close(fd);
4506
4507 return VK_SUCCESS;
4508 }
4509
4510 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4511 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4512 {
4513 RADV_FROM_HANDLE(radv_device, device, _device);
4514 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4515 uint32_t *syncobj_dst = NULL;
4516
4517 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4518 syncobj_dst = &sem->temp_syncobj;
4519 } else {
4520 syncobj_dst = &sem->syncobj;
4521 }
4522
4523 switch(pImportSemaphoreFdInfo->handleType) {
4524 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4525 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4526 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4527 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4528 default:
4529 unreachable("Unhandled semaphore handle type");
4530 }
4531 }
4532
4533 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4534 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4535 int *pFd)
4536 {
4537 RADV_FROM_HANDLE(radv_device, device, _device);
4538 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4539 int ret;
4540 uint32_t syncobj_handle;
4541
4542 if (sem->temp_syncobj)
4543 syncobj_handle = sem->temp_syncobj;
4544 else
4545 syncobj_handle = sem->syncobj;
4546
4547 switch(pGetFdInfo->handleType) {
4548 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4549 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4550 break;
4551 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4552 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4553 if (!ret) {
4554 if (sem->temp_syncobj) {
4555 close (sem->temp_syncobj);
4556 sem->temp_syncobj = 0;
4557 } else {
4558 device->ws->reset_syncobj(device->ws, syncobj_handle);
4559 }
4560 }
4561 break;
4562 default:
4563 unreachable("Unhandled semaphore handle type");
4564 }
4565
4566 if (ret)
4567 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4568 return VK_SUCCESS;
4569 }
4570
4571 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4572 VkPhysicalDevice physicalDevice,
4573 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4574 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4575 {
4576 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4577
4578 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4579 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4580 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4581 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4582 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4583 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4584 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4585 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4586 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4587 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4588 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4589 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4590 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4591 } else {
4592 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4593 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4594 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4595 }
4596 }
4597
4598 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4599 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4600 {
4601 RADV_FROM_HANDLE(radv_device, device, _device);
4602 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4603 uint32_t *syncobj_dst = NULL;
4604
4605
4606 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4607 syncobj_dst = &fence->temp_syncobj;
4608 } else {
4609 syncobj_dst = &fence->syncobj;
4610 }
4611
4612 switch(pImportFenceFdInfo->handleType) {
4613 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4614 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4615 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4616 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4617 default:
4618 unreachable("Unhandled fence handle type");
4619 }
4620 }
4621
4622 VkResult radv_GetFenceFdKHR(VkDevice _device,
4623 const VkFenceGetFdInfoKHR *pGetFdInfo,
4624 int *pFd)
4625 {
4626 RADV_FROM_HANDLE(radv_device, device, _device);
4627 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4628 int ret;
4629 uint32_t syncobj_handle;
4630
4631 if (fence->temp_syncobj)
4632 syncobj_handle = fence->temp_syncobj;
4633 else
4634 syncobj_handle = fence->syncobj;
4635
4636 switch(pGetFdInfo->handleType) {
4637 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4638 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4639 break;
4640 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4641 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4642 if (!ret) {
4643 if (fence->temp_syncobj) {
4644 close (fence->temp_syncobj);
4645 fence->temp_syncobj = 0;
4646 } else {
4647 device->ws->reset_syncobj(device->ws, syncobj_handle);
4648 }
4649 }
4650 break;
4651 default:
4652 unreachable("Unhandled fence handle type");
4653 }
4654
4655 if (ret)
4656 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4657 return VK_SUCCESS;
4658 }
4659
4660 void radv_GetPhysicalDeviceExternalFenceProperties(
4661 VkPhysicalDevice physicalDevice,
4662 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4663 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4664 {
4665 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4666
4667 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4668 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4669 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4670 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4671 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4672 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4673 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4674 } else {
4675 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4676 pExternalFenceProperties->compatibleHandleTypes = 0;
4677 pExternalFenceProperties->externalFenceFeatures = 0;
4678 }
4679 }
4680
4681 VkResult
4682 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4683 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4684 const VkAllocationCallbacks* pAllocator,
4685 VkDebugReportCallbackEXT* pCallback)
4686 {
4687 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4688 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4689 pCreateInfo, pAllocator, &instance->alloc,
4690 pCallback);
4691 }
4692
4693 void
4694 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4695 VkDebugReportCallbackEXT _callback,
4696 const VkAllocationCallbacks* pAllocator)
4697 {
4698 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4699 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4700 _callback, pAllocator, &instance->alloc);
4701 }
4702
4703 void
4704 radv_DebugReportMessageEXT(VkInstance _instance,
4705 VkDebugReportFlagsEXT flags,
4706 VkDebugReportObjectTypeEXT objectType,
4707 uint64_t object,
4708 size_t location,
4709 int32_t messageCode,
4710 const char* pLayerPrefix,
4711 const char* pMessage)
4712 {
4713 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4714 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4715 object, location, messageCode, pLayerPrefix, pMessage);
4716 }
4717
4718 void
4719 radv_GetDeviceGroupPeerMemoryFeatures(
4720 VkDevice device,
4721 uint32_t heapIndex,
4722 uint32_t localDeviceIndex,
4723 uint32_t remoteDeviceIndex,
4724 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4725 {
4726 assert(localDeviceIndex == remoteDeviceIndex);
4727
4728 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4729 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4730 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4731 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4732 }