projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: add a workaround for Monster Hunter World and LLVM 7&8
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
116 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
117 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
118 default: chip_string = "AMD RADV unknown"; break;
119 }
120
121 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
122 }
123
124 static uint64_t
125 radv_get_visible_vram_size(struct radv_physical_device *device)
126 {
127 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
128 }
129
130 static uint64_t
131 radv_get_vram_size(struct radv_physical_device *device)
132 {
133 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
134 }
135
136 static void
137 radv_physical_device_init_mem_types(struct radv_physical_device *device)
138 {
139 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
140 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
141 uint64_t vram_size = radv_get_vram_size(device);
142 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
143 device->memory_properties.memoryHeapCount = 0;
144 if (vram_size > 0) {
145 vram_index = device->memory_properties.memoryHeapCount++;
146 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
147 .size = vram_size,
148 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
149 };
150 }
151 if (visible_vram_size) {
152 visible_vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
154 .size = visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (device->rad_info.gart_size > 0) {
159 gart_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
161 .size = device->rad_info.gart_size,
162 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165
166 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
167 unsigned type_count = 0;
168 if (vram_index >= 0) {
169 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
170 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
171 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
172 .heapIndex = vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
197 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
198 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
199 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
200 .heapIndex = gart_index,
201 };
202 }
203 device->memory_properties.memoryTypeCount = type_count;
204 }
205
206 static void
207 radv_handle_env_var_force_family(struct radv_physical_device *device)
208 {
209 const char *family = getenv("RADV_FORCE_FAMILY");
210 unsigned i;
211
212 if (!family)
213 return;
214
215 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
216 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
217 /* Override family and chip_class. */
218 device->rad_info.family = i;
219
220 if (i >= CHIP_VEGA10)
221 device->rad_info.chip_class = GFX9;
222 else if (i >= CHIP_TONGA)
223 device->rad_info.chip_class = GFX8;
224 else if (i >= CHIP_BONAIRE)
225 device->rad_info.chip_class = GFX7;
226 else
227 device->rad_info.chip_class = GFX6;
228
229 return;
230 }
231 }
232
233 fprintf(stderr, "radv: Unknown family: %s\n", family);
234 exit(1);
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246 int master_fd = -1;
247
248 fd = open(path, O_RDWR | O_CLOEXEC);
249 if (fd < 0) {
250 if (instance->debug_flags & RADV_DEBUG_STARTUP)
251 radv_logi("Could not open device '%s'", path);
252
253 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
254 }
255
256 version = drmGetVersion(fd);
257 if (!version) {
258 close(fd);
259
260 if (instance->debug_flags & RADV_DEBUG_STARTUP)
261 radv_logi("Could not get the kernel driver version for device '%s'", path);
262
263 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
264 "failed to get version %s: %m", path);
265 }
266
267 if (strcmp(version->name, "amdgpu")) {
268 drmFreeVersion(version);
269 close(fd);
270
271 if (instance->debug_flags & RADV_DEBUG_STARTUP)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
273
274 return VK_ERROR_INCOMPATIBLE_DRIVER;
275 }
276 drmFreeVersion(version);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Found compatible device '%s'.", path);
280
281 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
282 device->instance = instance;
283
284 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
285 instance->perftest_flags);
286 if (!device->ws) {
287 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 goto fail;
289 }
290
291 if (instance->enabled_extensions.KHR_display) {
292 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
293 if (master_fd >= 0) {
294 uint32_t accel_working = 0;
295 struct drm_amdgpu_info request = {
296 .return_pointer = (uintptr_t)&accel_working,
297 .return_size = sizeof(accel_working),
298 .query = AMDGPU_INFO_ACCEL_WORKING
299 };
300
301 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
302 close(master_fd);
303 master_fd = -1;
304 }
305 }
306 }
307
308 device->master_fd = master_fd;
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311
312 radv_handle_env_var_force_family(device);
313
314 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
315
316 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
317 device->ws->destroy(device->ws);
318 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
319 "cannot generate UUID");
320 goto fail;
321 }
322
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags =
325 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
326 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
327
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
330 */
331 char buf[VK_UUID_SIZE * 2 + 1];
332 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
333 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
334
335 if (device->rad_info.chip_class < GFX8 ||
336 device->rad_info.chip_class > GFX9)
337 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338
339 radv_get_driver_uuid(&device->driver_uuid);
340 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
341
342 if (device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.chip_class >= GFX9) {
344 device->has_rbplus = true;
345 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.family == CHIP_VEGA12 ||
347 device->rad_info.family == CHIP_RAVEN ||
348 device->rad_info.family == CHIP_RAVEN2;
349 }
350
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 * on GFX6.
353 */
354 device->has_clear_state = device->rad_info.chip_class >= GFX7;
355
356 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
357
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
360 device->rad_info.family == CHIP_RAVEN;
361
362 /* Out-of-order primitive rasterization. */
363 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
364 device->rad_info.max_se >= 2;
365 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
366 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
367
368 device->dcc_msaa_allowed =
369 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
370
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
372 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
373 (device->rad_info.chip_class >= GFX8 &&
374 device->rad_info.me_fw_feature >= 41);
375
376 radv_physical_device_init_mem_types(device);
377 radv_fill_device_extension_table(device, &device->supported_extensions);
378
379 device->bus_info = *drm_device->businfo.pci;
380
381 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
382 ac_print_gpu_info(&device->rad_info);
383
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
386 * semi-layers).
387 */
388 result = radv_init_wsi(device);
389 if (result != VK_SUCCESS) {
390 device->ws->destroy(device->ws);
391 vk_error(instance, result);
392 goto fail;
393 }
394
395 return VK_SUCCESS;
396
397 fail:
398 close(fd);
399 if (master_fd != -1)
400 close(master_fd);
401 return result;
402 }
403
404 static void
405 radv_physical_device_finish(struct radv_physical_device *device)
406 {
407 radv_finish_wsi(device);
408 device->ws->destroy(device->ws);
409 disk_cache_destroy(device->disk_cache);
410 close(device->local_fd);
411 if (device->master_fd != -1)
412 close(device->master_fd);
413 }
414
415 static void *
416 default_alloc_func(void *pUserData, size_t size, size_t align,
417 VkSystemAllocationScope allocationScope)
418 {
419 return malloc(size);
420 }
421
422 static void *
423 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
424 size_t align, VkSystemAllocationScope allocationScope)
425 {
426 return realloc(pOriginal, size);
427 }
428
429 static void
430 default_free_func(void *pUserData, void *pMemory)
431 {
432 free(pMemory);
433 }
434
435 static const VkAllocationCallbacks default_alloc = {
436 .pUserData = NULL,
437 .pfnAllocation = default_alloc_func,
438 .pfnReallocation = default_realloc_func,
439 .pfnFree = default_free_func,
440 };
441
442 static const struct debug_control radv_debug_options[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
444 {"nodcc", RADV_DEBUG_NO_DCC},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS},
446 {"nocache", RADV_DEBUG_NO_CACHE},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
448 {"nohiz", RADV_DEBUG_NO_HIZ},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
451 {"allbos", RADV_DEBUG_ALL_BOS},
452 {"noibs", RADV_DEBUG_NO_IBS},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
457 {"nosisched", RADV_DEBUG_NO_SISCHED},
458 {"preoptir", RADV_DEBUG_PREOPTIR},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
461 {"info", RADV_DEBUG_INFO},
462 {"errors", RADV_DEBUG_ERRORS},
463 {"startup", RADV_DEBUG_STARTUP},
464 {"checkir", RADV_DEBUG_CHECKIR},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
466 {"nobinning", RADV_DEBUG_NOBINNING},
467 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {"bolist", RADV_PERFTEST_BO_LIST},
484 {NULL, 0}
485 };
486
487 const char *
488 radv_get_perftest_option_name(int id)
489 {
490 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
491 return radv_perftest_options[id].string;
492 }
493
494 static void
495 radv_handle_per_app_options(struct radv_instance *instance,
496 const VkApplicationInfo *info)
497 {
498 const char *name = info ? info->pApplicationName : NULL;
499
500 if (!name)
501 return;
502
503 if (!strcmp(name, "Talos - Linux - 32bit") ||
504 !strcmp(name, "Talos - Linux - 64bit")) {
505 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
506 /* Force enable LLVM sisched for Talos because it looks
507 * safe and it gives few more FPS.
508 */
509 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
510 }
511 } else if (!strcmp(name, "DOOM_VFR")) {
512 /* Work around a Doom VFR game bug */
513 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
514 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
515 /* Workaround for a WaW hazard when LLVM moves/merges
516 * load/store memory operations.
517 * See https://reviews.llvm.org/D61313
518 */
519 if (HAVE_LLVM < 0x900)
520 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
521 }
522 }
523
524 static int radv_get_instance_extension_index(const char *name)
525 {
526 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
527 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
528 return i;
529 }
530 return -1;
531 }
532
533 static const char radv_dri_options_xml[] =
534 DRI_CONF_BEGIN
535 DRI_CONF_SECTION_QUALITY
536 DRI_CONF_ADAPTIVE_SYNC("true")
537 DRI_CONF_SECTION_END
538 DRI_CONF_END;
539
540 static void radv_init_dri_options(struct radv_instance *instance)
541 {
542 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
543 driParseConfigFiles(&instance->dri_options,
544 &instance->available_dri_options,
545 0, "radv", NULL);
546 }
547
548 VkResult radv_CreateInstance(
549 const VkInstanceCreateInfo* pCreateInfo,
550 const VkAllocationCallbacks* pAllocator,
551 VkInstance* pInstance)
552 {
553 struct radv_instance *instance;
554 VkResult result;
555
556 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
557
558 uint32_t client_version;
559 if (pCreateInfo->pApplicationInfo &&
560 pCreateInfo->pApplicationInfo->apiVersion != 0) {
561 client_version = pCreateInfo->pApplicationInfo->apiVersion;
562 } else {
563 client_version = VK_API_VERSION_1_0;
564 }
565
566 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
567 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
568 if (!instance)
569 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
570
571 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
572
573 if (pAllocator)
574 instance->alloc = *pAllocator;
575 else
576 instance->alloc = default_alloc;
577
578 instance->apiVersion = client_version;
579 instance->physicalDeviceCount = -1;
580
581 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
582 radv_debug_options);
583
584 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
585 radv_perftest_options);
586
587
588 if (instance->debug_flags & RADV_DEBUG_STARTUP)
589 radv_logi("Created an instance");
590
591 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
592 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
593 int index = radv_get_instance_extension_index(ext_name);
594
595 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
596 vk_free2(&default_alloc, pAllocator, instance);
597 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
598 }
599
600 instance->enabled_extensions.extensions[index] = true;
601 }
602
603 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
604 if (result != VK_SUCCESS) {
605 vk_free2(&default_alloc, pAllocator, instance);
606 return vk_error(instance, result);
607 }
608
609 _mesa_locale_init();
610 glsl_type_singleton_init_or_ref();
611
612 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
613
614 radv_init_dri_options(instance);
615 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
616
617 *pInstance = radv_instance_to_handle(instance);
618
619 return VK_SUCCESS;
620 }
621
622 void radv_DestroyInstance(
623 VkInstance _instance,
624 const VkAllocationCallbacks* pAllocator)
625 {
626 RADV_FROM_HANDLE(radv_instance, instance, _instance);
627
628 if (!instance)
629 return;
630
631 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
632 radv_physical_device_finish(instance->physicalDevices + i);
633 }
634
635 VG(VALGRIND_DESTROY_MEMPOOL(instance));
636
637 glsl_type_singleton_decref();
638 _mesa_locale_fini();
639
640 driDestroyOptionCache(&instance->dri_options);
641 driDestroyOptionInfo(&instance->available_dri_options);
642
643 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
644
645 vk_free(&instance->alloc, instance);
646 }
647
648 static VkResult
649 radv_enumerate_devices(struct radv_instance *instance)
650 {
651 /* TODO: Check for more devices ? */
652 drmDevicePtr devices[8];
653 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
654 int max_devices;
655
656 instance->physicalDeviceCount = 0;
657
658 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
659
660 if (instance->debug_flags & RADV_DEBUG_STARTUP)
661 radv_logi("Found %d drm nodes", max_devices);
662
663 if (max_devices < 1)
664 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
665
666 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
667 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
668 devices[i]->bustype == DRM_BUS_PCI &&
669 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
670
671 result = radv_physical_device_init(instance->physicalDevices +
672 instance->physicalDeviceCount,
673 instance,
674 devices[i]);
675 if (result == VK_SUCCESS)
676 ++instance->physicalDeviceCount;
677 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
678 break;
679 }
680 }
681 drmFreeDevices(devices, max_devices);
682
683 return result;
684 }
685
686 VkResult radv_EnumeratePhysicalDevices(
687 VkInstance _instance,
688 uint32_t* pPhysicalDeviceCount,
689 VkPhysicalDevice* pPhysicalDevices)
690 {
691 RADV_FROM_HANDLE(radv_instance, instance, _instance);
692 VkResult result;
693
694 if (instance->physicalDeviceCount < 0) {
695 result = radv_enumerate_devices(instance);
696 if (result != VK_SUCCESS &&
697 result != VK_ERROR_INCOMPATIBLE_DRIVER)
698 return result;
699 }
700
701 if (!pPhysicalDevices) {
702 *pPhysicalDeviceCount = instance->physicalDeviceCount;
703 } else {
704 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
705 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
706 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 }
708
709 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
710 : VK_SUCCESS;
711 }
712
713 VkResult radv_EnumeratePhysicalDeviceGroups(
714 VkInstance _instance,
715 uint32_t* pPhysicalDeviceGroupCount,
716 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
717 {
718 RADV_FROM_HANDLE(radv_instance, instance, _instance);
719 VkResult result;
720
721 if (instance->physicalDeviceCount < 0) {
722 result = radv_enumerate_devices(instance);
723 if (result != VK_SUCCESS &&
724 result != VK_ERROR_INCOMPATIBLE_DRIVER)
725 return result;
726 }
727
728 if (!pPhysicalDeviceGroupProperties) {
729 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
730 } else {
731 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
732 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
733 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
734 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
735 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
736 }
737 }
738 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
739 : VK_SUCCESS;
740 }
741
742 void radv_GetPhysicalDeviceFeatures(
743 VkPhysicalDevice physicalDevice,
744 VkPhysicalDeviceFeatures* pFeatures)
745 {
746 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
747 memset(pFeatures, 0, sizeof(*pFeatures));
748
749 *pFeatures = (VkPhysicalDeviceFeatures) {
750 .robustBufferAccess = true,
751 .fullDrawIndexUint32 = true,
752 .imageCubeArray = true,
753 .independentBlend = true,
754 .geometryShader = true,
755 .tessellationShader = true,
756 .sampleRateShading = true,
757 .dualSrcBlend = true,
758 .logicOp = true,
759 .multiDrawIndirect = true,
760 .drawIndirectFirstInstance = true,
761 .depthClamp = true,
762 .depthBiasClamp = true,
763 .fillModeNonSolid = true,
764 .depthBounds = true,
765 .wideLines = true,
766 .largePoints = true,
767 .alphaToOne = true,
768 .multiViewport = true,
769 .samplerAnisotropy = true,
770 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
771 .textureCompressionASTC_LDR = false,
772 .textureCompressionBC = true,
773 .occlusionQueryPrecise = true,
774 .pipelineStatisticsQuery = true,
775 .vertexPipelineStoresAndAtomics = true,
776 .fragmentStoresAndAtomics = true,
777 .shaderTessellationAndGeometryPointSize = true,
778 .shaderImageGatherExtended = true,
779 .shaderStorageImageExtendedFormats = true,
780 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
781 .shaderUniformBufferArrayDynamicIndexing = true,
782 .shaderSampledImageArrayDynamicIndexing = true,
783 .shaderStorageBufferArrayDynamicIndexing = true,
784 .shaderStorageImageArrayDynamicIndexing = true,
785 .shaderStorageImageReadWithoutFormat = true,
786 .shaderStorageImageWriteWithoutFormat = true,
787 .shaderClipDistance = true,
788 .shaderCullDistance = true,
789 .shaderFloat64 = true,
790 .shaderInt64 = true,
791 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
792 .sparseBinding = true,
793 .variableMultisampleRate = true,
794 .inheritedQueries = true,
795 };
796 }
797
798 void radv_GetPhysicalDeviceFeatures2(
799 VkPhysicalDevice physicalDevice,
800 VkPhysicalDeviceFeatures2 *pFeatures)
801 {
802 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
803 vk_foreach_struct(ext, pFeatures->pNext) {
804 switch (ext->sType) {
805 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
806 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
807 features->variablePointersStorageBuffer = true;
808 features->variablePointers = true;
809 break;
810 }
811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
812 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
813 features->multiview = true;
814 features->multiviewGeometryShader = true;
815 features->multiviewTessellationShader = true;
816 break;
817 }
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
819 VkPhysicalDeviceShaderDrawParametersFeatures *features =
820 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
821 features->shaderDrawParameters = true;
822 break;
823 }
824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
825 VkPhysicalDeviceProtectedMemoryFeatures *features =
826 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
827 features->protectedMemory = false;
828 break;
829 }
830 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
831 VkPhysicalDevice16BitStorageFeatures *features =
832 (VkPhysicalDevice16BitStorageFeatures*)ext;
833 bool enabled = pdevice->rad_info.chip_class >= GFX8;
834 features->storageBuffer16BitAccess = enabled;
835 features->uniformAndStorageBuffer16BitAccess = enabled;
836 features->storagePushConstant16 = enabled;
837 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
838 break;
839 }
840 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
841 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
842 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
843 features->samplerYcbcrConversion = true;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
847 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
848 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
849 features->shaderInputAttachmentArrayDynamicIndexing = true;
850 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
851 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
852 features->shaderUniformBufferArrayNonUniformIndexing = true;
853 features->shaderSampledImageArrayNonUniformIndexing = true;
854 features->shaderStorageBufferArrayNonUniformIndexing = true;
855 features->shaderStorageImageArrayNonUniformIndexing = true;
856 features->shaderInputAttachmentArrayNonUniformIndexing = true;
857 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
858 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
859 features->descriptorBindingUniformBufferUpdateAfterBind = true;
860 features->descriptorBindingSampledImageUpdateAfterBind = true;
861 features->descriptorBindingStorageImageUpdateAfterBind = true;
862 features->descriptorBindingStorageBufferUpdateAfterBind = true;
863 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
864 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
865 features->descriptorBindingUpdateUnusedWhilePending = true;
866 features->descriptorBindingPartiallyBound = true;
867 features->descriptorBindingVariableDescriptorCount = true;
868 features->runtimeDescriptorArray = true;
869 break;
870 }
871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
872 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
873 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
874 features->conditionalRendering = true;
875 features->inheritedConditionalRendering = false;
876 break;
877 }
878 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
879 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
880 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
881 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
882 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
883 break;
884 }
885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
886 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
887 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
888 features->transformFeedback = true;
889 features->geometryStreams = true;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
893 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
894 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
895 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
896 break;
897 }
898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
899 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
900 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
901 features->memoryPriority = VK_TRUE;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
905 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
906 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
907 features->bufferDeviceAddress = true;
908 features->bufferDeviceAddressCaptureReplay = false;
909 features->bufferDeviceAddressMultiDevice = false;
910 break;
911 }
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
913 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
914 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
915 features->depthClipEnable = true;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
919 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
920 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
921 features->hostQueryReset = true;
922 break;
923 }
924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
925 VkPhysicalDevice8BitStorageFeaturesKHR *features =
926 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
927 bool enabled = pdevice->rad_info.chip_class >= GFX8;
928 features->storageBuffer8BitAccess = enabled;
929 features->uniformAndStorageBuffer8BitAccess = enabled;
930 features->storagePushConstant8 = enabled;
931 break;
932 }
933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
934 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
935 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
936 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
937 features->shaderInt8 = true;
938 break;
939 }
940 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
941 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
942 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
943 /* TODO: Enable this once the driver supports 64-bit
944 * compare&swap atomic operations.
945 */
946 features->shaderBufferInt64Atomics = false;
947 features->shaderSharedInt64Atomics = false;
948 break;
949 }
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
951 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
952 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
953
954 features->inlineUniformBlock = true;
955 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
956 break;
957 }
958 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
959 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
960 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
961 features->computeDerivativeGroupQuads = false;
962 features->computeDerivativeGroupLinear = true;
963 break;
964 }
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
966 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
967 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
968 features->ycbcrImageArrays = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
972 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
973 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
974 features->uniformBufferStandardLayout = true;
975 break;
976 }
977 default:
978 break;
979 }
980 }
981 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
982 }
983
984 void radv_GetPhysicalDeviceProperties(
985 VkPhysicalDevice physicalDevice,
986 VkPhysicalDeviceProperties* pProperties)
987 {
988 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
989 VkSampleCountFlags sample_counts = 0xf;
990
991 /* make sure that the entire descriptor set is addressable with a signed
992 * 32-bit int. So the sum of all limits scaled by descriptor size has to
993 * be at most 2 GiB. the combined image & samples object count as one of
994 * both. This limit is for the pipeline layout, not for the set layout, but
995 * there is no set limit, so we just set a pipeline limit. I don't think
996 * any app is going to hit this soon. */
997 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
998 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
999 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1000 32 /* sampler, largest when combined with image */ +
1001 64 /* sampled image */ +
1002 64 /* storage image */);
1003
1004 VkPhysicalDeviceLimits limits = {
1005 .maxImageDimension1D = (1 << 14),
1006 .maxImageDimension2D = (1 << 14),
1007 .maxImageDimension3D = (1 << 11),
1008 .maxImageDimensionCube = (1 << 14),
1009 .maxImageArrayLayers = (1 << 11),
1010 .maxTexelBufferElements = 128 * 1024 * 1024,
1011 .maxUniformBufferRange = UINT32_MAX,
1012 .maxStorageBufferRange = UINT32_MAX,
1013 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1014 .maxMemoryAllocationCount = UINT32_MAX,
1015 .maxSamplerAllocationCount = 64 * 1024,
1016 .bufferImageGranularity = 64, /* A cache line */
1017 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1018 .maxBoundDescriptorSets = MAX_SETS,
1019 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1020 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1021 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1022 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1023 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1024 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1025 .maxPerStageResources = max_descriptor_set_size,
1026 .maxDescriptorSetSamplers = max_descriptor_set_size,
1027 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1028 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1029 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1030 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1031 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1032 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1033 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1034 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1035 .maxVertexInputBindings = MAX_VBS,
1036 .maxVertexInputAttributeOffset = 2047,
1037 .maxVertexInputBindingStride = 2048,
1038 .maxVertexOutputComponents = 128,
1039 .maxTessellationGenerationLevel = 64,
1040 .maxTessellationPatchSize = 32,
1041 .maxTessellationControlPerVertexInputComponents = 128,
1042 .maxTessellationControlPerVertexOutputComponents = 128,
1043 .maxTessellationControlPerPatchOutputComponents = 120,
1044 .maxTessellationControlTotalOutputComponents = 4096,
1045 .maxTessellationEvaluationInputComponents = 128,
1046 .maxTessellationEvaluationOutputComponents = 128,
1047 .maxGeometryShaderInvocations = 127,
1048 .maxGeometryInputComponents = 64,
1049 .maxGeometryOutputComponents = 128,
1050 .maxGeometryOutputVertices = 256,
1051 .maxGeometryTotalOutputComponents = 1024,
1052 .maxFragmentInputComponents = 128,
1053 .maxFragmentOutputAttachments = 8,
1054 .maxFragmentDualSrcAttachments = 1,
1055 .maxFragmentCombinedOutputResources = 8,
1056 .maxComputeSharedMemorySize = 32768,
1057 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1058 .maxComputeWorkGroupInvocations = 2048,
1059 .maxComputeWorkGroupSize = {
1060 2048,
1061 2048,
1062 2048
1063 },
1064 .subPixelPrecisionBits = 8,
1065 .subTexelPrecisionBits = 8,
1066 .mipmapPrecisionBits = 8,
1067 .maxDrawIndexedIndexValue = UINT32_MAX,
1068 .maxDrawIndirectCount = UINT32_MAX,
1069 .maxSamplerLodBias = 16,
1070 .maxSamplerAnisotropy = 16,
1071 .maxViewports = MAX_VIEWPORTS,
1072 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1073 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1074 .viewportSubPixelBits = 8,
1075 .minMemoryMapAlignment = 4096, /* A page */
1076 .minTexelBufferOffsetAlignment = 1,
1077 .minUniformBufferOffsetAlignment = 4,
1078 .minStorageBufferOffsetAlignment = 4,
1079 .minTexelOffset = -32,
1080 .maxTexelOffset = 31,
1081 .minTexelGatherOffset = -32,
1082 .maxTexelGatherOffset = 31,
1083 .minInterpolationOffset = -2,
1084 .maxInterpolationOffset = 2,
1085 .subPixelInterpolationOffsetBits = 8,
1086 .maxFramebufferWidth = (1 << 14),
1087 .maxFramebufferHeight = (1 << 14),
1088 .maxFramebufferLayers = (1 << 10),
1089 .framebufferColorSampleCounts = sample_counts,
1090 .framebufferDepthSampleCounts = sample_counts,
1091 .framebufferStencilSampleCounts = sample_counts,
1092 .framebufferNoAttachmentsSampleCounts = sample_counts,
1093 .maxColorAttachments = MAX_RTS,
1094 .sampledImageColorSampleCounts = sample_counts,
1095 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1096 .sampledImageDepthSampleCounts = sample_counts,
1097 .sampledImageStencilSampleCounts = sample_counts,
1098 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1099 .maxSampleMaskWords = 1,
1100 .timestampComputeAndGraphics = true,
1101 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1102 .maxClipDistances = 8,
1103 .maxCullDistances = 8,
1104 .maxCombinedClipAndCullDistances = 8,
1105 .discreteQueuePriorities = 2,
1106 .pointSizeRange = { 0.0, 8192.0 },
1107 .lineWidthRange = { 0.0, 7.9921875 },
1108 .pointSizeGranularity = (1.0 / 8.0),
1109 .lineWidthGranularity = (1.0 / 128.0),
1110 .strictLines = false, /* FINISHME */
1111 .standardSampleLocations = true,
1112 .optimalBufferCopyOffsetAlignment = 128,
1113 .optimalBufferCopyRowPitchAlignment = 128,
1114 .nonCoherentAtomSize = 64,
1115 };
1116
1117 *pProperties = (VkPhysicalDeviceProperties) {
1118 .apiVersion = radv_physical_device_api_version(pdevice),
1119 .driverVersion = vk_get_driver_version(),
1120 .vendorID = ATI_VENDOR_ID,
1121 .deviceID = pdevice->rad_info.pci_id,
1122 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1123 .limits = limits,
1124 .sparseProperties = {0},
1125 };
1126
1127 strcpy(pProperties->deviceName, pdevice->name);
1128 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1129 }
1130
1131 void radv_GetPhysicalDeviceProperties2(
1132 VkPhysicalDevice physicalDevice,
1133 VkPhysicalDeviceProperties2 *pProperties)
1134 {
1135 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1136 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1137
1138 vk_foreach_struct(ext, pProperties->pNext) {
1139 switch (ext->sType) {
1140 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1141 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1142 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1143 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1144 break;
1145 }
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1147 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1148 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1149 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1150 properties->deviceLUIDValid = false;
1151 break;
1152 }
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1154 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1155 properties->maxMultiviewViewCount = MAX_VIEWS;
1156 properties->maxMultiviewInstanceIndex = INT_MAX;
1157 break;
1158 }
1159 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1160 VkPhysicalDevicePointClippingProperties *properties =
1161 (VkPhysicalDevicePointClippingProperties*)ext;
1162 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1163 break;
1164 }
1165 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1166 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1167 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1168 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1169 break;
1170 }
1171 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1172 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1173 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1174 properties->minImportedHostPointerAlignment = 4096;
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1178 VkPhysicalDeviceSubgroupProperties *properties =
1179 (VkPhysicalDeviceSubgroupProperties*)ext;
1180 properties->subgroupSize = 64;
1181 properties->supportedStages = VK_SHADER_STAGE_ALL;
1182 properties->supportedOperations =
1183 VK_SUBGROUP_FEATURE_BASIC_BIT |
1184 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1185 VK_SUBGROUP_FEATURE_QUAD_BIT |
1186 VK_SUBGROUP_FEATURE_VOTE_BIT;
1187 if (pdevice->rad_info.chip_class >= GFX8) {
1188 properties->supportedOperations |=
1189 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1190 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1191 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1192 }
1193 properties->quadOperationsInAllStages = true;
1194 break;
1195 }
1196 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1197 VkPhysicalDeviceMaintenance3Properties *properties =
1198 (VkPhysicalDeviceMaintenance3Properties*)ext;
1199 /* Make sure everything is addressable by a signed 32-bit int, and
1200 * our largest descriptors are 96 bytes. */
1201 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1202 /* Our buffer size fields allow only this much */
1203 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1204 break;
1205 }
1206 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1207 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1208 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1209 /* GFX6-8 only support single channel min/max filter. */
1210 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1211 properties->filterMinmaxSingleComponentFormats = true;
1212 break;
1213 }
1214 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1215 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1216 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1217
1218 /* Shader engines. */
1219 properties->shaderEngineCount =
1220 pdevice->rad_info.max_se;
1221 properties->shaderArraysPerEngineCount =
1222 pdevice->rad_info.max_sh_per_se;
1223 properties->computeUnitsPerShaderArray =
1224 pdevice->rad_info.num_good_cu_per_sh;
1225 properties->simdPerComputeUnit = 4;
1226 properties->wavefrontsPerSimd =
1227 pdevice->rad_info.family == CHIP_TONGA ||
1228 pdevice->rad_info.family == CHIP_ICELAND ||
1229 pdevice->rad_info.family == CHIP_POLARIS10 ||
1230 pdevice->rad_info.family == CHIP_POLARIS11 ||
1231 pdevice->rad_info.family == CHIP_POLARIS12 ||
1232 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1233 properties->wavefrontSize = 64;
1234
1235 /* SGPR. */
1236 properties->sgprsPerSimd =
1237 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1238 properties->minSgprAllocation =
1239 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1240 properties->maxSgprAllocation =
1241 pdevice->rad_info.family == CHIP_TONGA ||
1242 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1243 properties->sgprAllocationGranularity =
1244 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1245
1246 /* VGPR. */
1247 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1248 properties->minVgprAllocation = 4;
1249 properties->maxVgprAllocation = 256;
1250 properties->vgprAllocationGranularity = 4;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1254 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1255 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1256 properties->maxVertexAttribDivisor = UINT32_MAX;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1260 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1261 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1262 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1263 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1264 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1265 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1266 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1267 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1268 properties->robustBufferAccessUpdateAfterBind = false;
1269 properties->quadDivergentImplicitLod = false;
1270
1271 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1272 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1273 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1274 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1275 32 /* sampler, largest when combined with image */ +
1276 64 /* sampled image */ +
1277 64 /* storage image */);
1278 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1279 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1280 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1281 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1282 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1283 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1284 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1285 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1286 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1287 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1288 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1289 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1290 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1292 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1293 break;
1294 }
1295 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1296 VkPhysicalDeviceProtectedMemoryProperties *properties =
1297 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1298 properties->protectedNoFault = false;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1302 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1303 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1304 properties->primitiveOverestimationSize = 0;
1305 properties->maxExtraPrimitiveOverestimationSize = 0;
1306 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1307 properties->primitiveUnderestimation = VK_FALSE;
1308 properties->conservativePointAndLineRasterization = VK_FALSE;
1309 properties->degenerateTrianglesRasterized = VK_FALSE;
1310 properties->degenerateLinesRasterized = VK_FALSE;
1311 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1312 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1313 break;
1314 }
1315 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1316 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1317 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1318 properties->pciDomain = pdevice->bus_info.domain;
1319 properties->pciBus = pdevice->bus_info.bus;
1320 properties->pciDevice = pdevice->bus_info.dev;
1321 properties->pciFunction = pdevice->bus_info.func;
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1325 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1326 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1327
1328 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1329 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1330 strcpy(driver_props->driverName, "radv");
1331
1332 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1333 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1334 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1335 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1336
1337 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1338 .major = 1,
1339 .minor = 1,
1340 .subminor = 2,
1341 .patch = 0,
1342 };
1343 break;
1344 }
1345 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1346 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1347 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1348 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1349 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1350 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1351 properties->maxTransformFeedbackStreamDataSize = 512;
1352 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1353 properties->maxTransformFeedbackBufferDataStride = 512;
1354 properties->transformFeedbackQueries = true;
1355 properties->transformFeedbackStreamsLinesTriangles = false;
1356 properties->transformFeedbackRasterizationStreamSelect = false;
1357 properties->transformFeedbackDraw = true;
1358 break;
1359 }
1360 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1361 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1362 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1363
1364 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1365 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1366 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1367 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1368 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1369 break;
1370 }
1371 default:
1372 break;
1373 }
1374 }
1375 }
1376
1377 static void radv_get_physical_device_queue_family_properties(
1378 struct radv_physical_device* pdevice,
1379 uint32_t* pCount,
1380 VkQueueFamilyProperties** pQueueFamilyProperties)
1381 {
1382 int num_queue_families = 1;
1383 int idx;
1384 if (pdevice->rad_info.num_compute_rings > 0 &&
1385 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1386 num_queue_families++;
1387
1388 if (pQueueFamilyProperties == NULL) {
1389 *pCount = num_queue_families;
1390 return;
1391 }
1392
1393 if (!*pCount)
1394 return;
1395
1396 idx = 0;
1397 if (*pCount >= 1) {
1398 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1399 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1400 VK_QUEUE_COMPUTE_BIT |
1401 VK_QUEUE_TRANSFER_BIT |
1402 VK_QUEUE_SPARSE_BINDING_BIT,
1403 .queueCount = 1,
1404 .timestampValidBits = 64,
1405 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1406 };
1407 idx++;
1408 }
1409
1410 if (pdevice->rad_info.num_compute_rings > 0 &&
1411 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1412 if (*pCount > idx) {
1413 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1414 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1415 VK_QUEUE_TRANSFER_BIT |
1416 VK_QUEUE_SPARSE_BINDING_BIT,
1417 .queueCount = pdevice->rad_info.num_compute_rings,
1418 .timestampValidBits = 64,
1419 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1420 };
1421 idx++;
1422 }
1423 }
1424 *pCount = idx;
1425 }
1426
1427 void radv_GetPhysicalDeviceQueueFamilyProperties(
1428 VkPhysicalDevice physicalDevice,
1429 uint32_t* pCount,
1430 VkQueueFamilyProperties* pQueueFamilyProperties)
1431 {
1432 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1433 if (!pQueueFamilyProperties) {
1434 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1435 return;
1436 }
1437 VkQueueFamilyProperties *properties[] = {
1438 pQueueFamilyProperties + 0,
1439 pQueueFamilyProperties + 1,
1440 pQueueFamilyProperties + 2,
1441 };
1442 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1443 assert(*pCount <= 3);
1444 }
1445
1446 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1447 VkPhysicalDevice physicalDevice,
1448 uint32_t* pCount,
1449 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1450 {
1451 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1452 if (!pQueueFamilyProperties) {
1453 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1454 return;
1455 }
1456 VkQueueFamilyProperties *properties[] = {
1457 &pQueueFamilyProperties[0].queueFamilyProperties,
1458 &pQueueFamilyProperties[1].queueFamilyProperties,
1459 &pQueueFamilyProperties[2].queueFamilyProperties,
1460 };
1461 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1462 assert(*pCount <= 3);
1463 }
1464
1465 void radv_GetPhysicalDeviceMemoryProperties(
1466 VkPhysicalDevice physicalDevice,
1467 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1468 {
1469 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1470
1471 *pMemoryProperties = physical_device->memory_properties;
1472 }
1473
1474 static void
1475 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1476 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1477 {
1478 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1479 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1480 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1481 uint64_t vram_size = radv_get_vram_size(device);
1482 uint64_t gtt_size = device->rad_info.gart_size;
1483 uint64_t heap_budget, heap_usage;
1484
1485 /* For all memory heaps, the computation of budget is as follow:
1486 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1487 *
1488 * The Vulkan spec 1.1.97 says that the budget should include any
1489 * currently allocated device memory.
1490 *
1491 * Note that the application heap usages are not really accurate (eg.
1492 * in presence of shared buffers).
1493 */
1494 if (vram_size) {
1495 heap_usage = device->ws->query_value(device->ws,
1496 RADEON_ALLOCATED_VRAM);
1497
1498 heap_budget = vram_size -
1499 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1500 heap_usage;
1501
1502 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1503 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1504 }
1505
1506 if (visible_vram_size) {
1507 heap_usage = device->ws->query_value(device->ws,
1508 RADEON_ALLOCATED_VRAM_VIS);
1509
1510 heap_budget = visible_vram_size -
1511 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1512 heap_usage;
1513
1514 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1515 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1516 }
1517
1518 if (gtt_size) {
1519 heap_usage = device->ws->query_value(device->ws,
1520 RADEON_ALLOCATED_GTT);
1521
1522 heap_budget = gtt_size -
1523 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1524 heap_usage;
1525
1526 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1527 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1528 }
1529
1530 /* The heapBudget and heapUsage values must be zero for array elements
1531 * greater than or equal to
1532 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1533 */
1534 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1535 memoryBudget->heapBudget[i] = 0;
1536 memoryBudget->heapUsage[i] = 0;
1537 }
1538 }
1539
1540 void radv_GetPhysicalDeviceMemoryProperties2(
1541 VkPhysicalDevice physicalDevice,
1542 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1543 {
1544 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1545 &pMemoryProperties->memoryProperties);
1546
1547 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1548 vk_find_struct(pMemoryProperties->pNext,
1549 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1550 if (memory_budget)
1551 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1552 }
1553
1554 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1555 VkDevice _device,
1556 VkExternalMemoryHandleTypeFlagBits handleType,
1557 const void *pHostPointer,
1558 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1559 {
1560 RADV_FROM_HANDLE(radv_device, device, _device);
1561
1562 switch (handleType)
1563 {
1564 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1565 const struct radv_physical_device *physical_device = device->physical_device;
1566 uint32_t memoryTypeBits = 0;
1567 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1568 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1569 memoryTypeBits = (1 << i);
1570 break;
1571 }
1572 }
1573 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1574 return VK_SUCCESS;
1575 }
1576 default:
1577 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1578 }
1579 }
1580
1581 static enum radeon_ctx_priority
1582 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1583 {
1584 /* Default to MEDIUM when a specific global priority isn't requested */
1585 if (!pObj)
1586 return RADEON_CTX_PRIORITY_MEDIUM;
1587
1588 switch(pObj->globalPriority) {
1589 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1590 return RADEON_CTX_PRIORITY_REALTIME;
1591 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1592 return RADEON_CTX_PRIORITY_HIGH;
1593 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1594 return RADEON_CTX_PRIORITY_MEDIUM;
1595 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1596 return RADEON_CTX_PRIORITY_LOW;
1597 default:
1598 unreachable("Illegal global priority value");
1599 return RADEON_CTX_PRIORITY_INVALID;
1600 }
1601 }
1602
1603 static int
1604 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1605 uint32_t queue_family_index, int idx,
1606 VkDeviceQueueCreateFlags flags,
1607 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1608 {
1609 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1610 queue->device = device;
1611 queue->queue_family_index = queue_family_index;
1612 queue->queue_idx = idx;
1613 queue->priority = radv_get_queue_global_priority(global_priority);
1614 queue->flags = flags;
1615
1616 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1617 if (!queue->hw_ctx)
1618 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1619
1620 return VK_SUCCESS;
1621 }
1622
1623 static void
1624 radv_queue_finish(struct radv_queue *queue)
1625 {
1626 if (queue->hw_ctx)
1627 queue->device->ws->ctx_destroy(queue->hw_ctx);
1628
1629 if (queue->initial_full_flush_preamble_cs)
1630 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1631 if (queue->initial_preamble_cs)
1632 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1633 if (queue->continue_preamble_cs)
1634 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1635 if (queue->descriptor_bo)
1636 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1637 if (queue->scratch_bo)
1638 queue->device->ws->buffer_destroy(queue->scratch_bo);
1639 if (queue->esgs_ring_bo)
1640 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1641 if (queue->gsvs_ring_bo)
1642 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1643 if (queue->tess_rings_bo)
1644 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1645 if (queue->compute_scratch_bo)
1646 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1647 }
1648
1649 static void
1650 radv_bo_list_init(struct radv_bo_list *bo_list)
1651 {
1652 pthread_mutex_init(&bo_list->mutex, NULL);
1653 bo_list->list.count = bo_list->capacity = 0;
1654 bo_list->list.bos = NULL;
1655 }
1656
1657 static void
1658 radv_bo_list_finish(struct radv_bo_list *bo_list)
1659 {
1660 free(bo_list->list.bos);
1661 pthread_mutex_destroy(&bo_list->mutex);
1662 }
1663
1664 static VkResult radv_bo_list_add(struct radv_device *device,
1665 struct radeon_winsys_bo *bo)
1666 {
1667 struct radv_bo_list *bo_list = &device->bo_list;
1668
1669 if (bo->is_local)
1670 return VK_SUCCESS;
1671
1672 if (unlikely(!device->use_global_bo_list))
1673 return VK_SUCCESS;
1674
1675 pthread_mutex_lock(&bo_list->mutex);
1676 if (bo_list->list.count == bo_list->capacity) {
1677 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1678 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1679
1680 if (!data) {
1681 pthread_mutex_unlock(&bo_list->mutex);
1682 return VK_ERROR_OUT_OF_HOST_MEMORY;
1683 }
1684
1685 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1686 bo_list->capacity = capacity;
1687 }
1688
1689 bo_list->list.bos[bo_list->list.count++] = bo;
1690 pthread_mutex_unlock(&bo_list->mutex);
1691 return VK_SUCCESS;
1692 }
1693
1694 static void radv_bo_list_remove(struct radv_device *device,
1695 struct radeon_winsys_bo *bo)
1696 {
1697 struct radv_bo_list *bo_list = &device->bo_list;
1698
1699 if (bo->is_local)
1700 return;
1701
1702 if (unlikely(!device->use_global_bo_list))
1703 return;
1704
1705 pthread_mutex_lock(&bo_list->mutex);
1706 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1707 if (bo_list->list.bos[i] == bo) {
1708 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1709 --bo_list->list.count;
1710 break;
1711 }
1712 }
1713 pthread_mutex_unlock(&bo_list->mutex);
1714 }
1715
1716 static void
1717 radv_device_init_gs_info(struct radv_device *device)
1718 {
1719 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1720 device->physical_device->rad_info.family);
1721 }
1722
1723 static int radv_get_device_extension_index(const char *name)
1724 {
1725 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1726 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1727 return i;
1728 }
1729 return -1;
1730 }
1731
1732 static int
1733 radv_get_int_debug_option(const char *name, int default_value)
1734 {
1735 const char *str;
1736 int result;
1737
1738 str = getenv(name);
1739 if (!str) {
1740 result = default_value;
1741 } else {
1742 char *endptr;
1743
1744 result = strtol(str, &endptr, 0);
1745 if (str == endptr) {
1746 /* No digits founs. */
1747 result = default_value;
1748 }
1749 }
1750
1751 return result;
1752 }
1753
1754 VkResult radv_CreateDevice(
1755 VkPhysicalDevice physicalDevice,
1756 const VkDeviceCreateInfo* pCreateInfo,
1757 const VkAllocationCallbacks* pAllocator,
1758 VkDevice* pDevice)
1759 {
1760 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1761 VkResult result;
1762 struct radv_device *device;
1763
1764 bool keep_shader_info = false;
1765
1766 /* Check enabled features */
1767 if (pCreateInfo->pEnabledFeatures) {
1768 VkPhysicalDeviceFeatures supported_features;
1769 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1770 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1771 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1772 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1773 for (uint32_t i = 0; i < num_features; i++) {
1774 if (enabled_feature[i] && !supported_feature[i])
1775 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1776 }
1777 }
1778
1779 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1780 sizeof(*device), 8,
1781 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1782 if (!device)
1783 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1784
1785 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1786 device->instance = physical_device->instance;
1787 device->physical_device = physical_device;
1788
1789 device->ws = physical_device->ws;
1790 if (pAllocator)
1791 device->alloc = *pAllocator;
1792 else
1793 device->alloc = physical_device->instance->alloc;
1794
1795 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1796 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1797 int index = radv_get_device_extension_index(ext_name);
1798 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1799 vk_free(&device->alloc, device);
1800 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1801 }
1802
1803 device->enabled_extensions.extensions[index] = true;
1804 }
1805
1806 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1807
1808 /* With update after bind we can't attach bo's to the command buffer
1809 * from the descriptor set anymore, so we have to use a global BO list.
1810 */
1811 device->use_global_bo_list =
1812 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1813 device->enabled_extensions.EXT_descriptor_indexing ||
1814 device->enabled_extensions.EXT_buffer_device_address;
1815
1816 mtx_init(&device->shader_slab_mutex, mtx_plain);
1817 list_inithead(&device->shader_slabs);
1818
1819 radv_bo_list_init(&device->bo_list);
1820
1821 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1822 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1823 uint32_t qfi = queue_create->queueFamilyIndex;
1824 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1825 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1826
1827 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1828
1829 device->queues[qfi] = vk_alloc(&device->alloc,
1830 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1831 if (!device->queues[qfi]) {
1832 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1833 goto fail;
1834 }
1835
1836 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1837
1838 device->queue_count[qfi] = queue_create->queueCount;
1839
1840 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1841 result = radv_queue_init(device, &device->queues[qfi][q],
1842 qfi, q, queue_create->flags,
1843 global_priority);
1844 if (result != VK_SUCCESS)
1845 goto fail;
1846 }
1847 }
1848
1849 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1850 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1851
1852 /* Disabled and not implemented for now. */
1853 device->dfsm_allowed = device->pbb_allowed &&
1854 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1855 device->physical_device->rad_info.family == CHIP_RAVEN2);
1856
1857 #ifdef ANDROID
1858 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1859 #endif
1860
1861 /* The maximum number of scratch waves. Scratch space isn't divided
1862 * evenly between CUs. The number is only a function of the number of CUs.
1863 * We can decrease the constant to decrease the scratch buffer size.
1864 *
1865 * sctx->scratch_waves must be >= the maximum possible size of
1866 * 1 threadgroup, so that the hw doesn't hang from being unable
1867 * to start any.
1868 *
1869 * The recommended value is 4 per CU at most. Higher numbers don't
1870 * bring much benefit, but they still occupy chip resources (think
1871 * async compute). I've seen ~2% performance difference between 4 and 32.
1872 */
1873 uint32_t max_threads_per_block = 2048;
1874 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1875 max_threads_per_block / 64);
1876
1877 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1878
1879 if (device->physical_device->rad_info.chip_class >= GFX7) {
1880 /* If the KMD allows it (there is a KMD hw register for it),
1881 * allow launching waves out-of-order.
1882 */
1883 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1884 }
1885
1886 radv_device_init_gs_info(device);
1887
1888 device->tess_offchip_block_dw_size =
1889 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1890 device->has_distributed_tess =
1891 device->physical_device->rad_info.chip_class >= GFX8 &&
1892 device->physical_device->rad_info.max_se >= 2;
1893
1894 if (getenv("RADV_TRACE_FILE")) {
1895 const char *filename = getenv("RADV_TRACE_FILE");
1896
1897 keep_shader_info = true;
1898
1899 if (!radv_init_trace(device))
1900 goto fail;
1901
1902 fprintf(stderr, "*****************************************************************************\n");
1903 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1904 fprintf(stderr, "*****************************************************************************\n");
1905
1906 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1907 radv_dump_enabled_options(device, stderr);
1908 }
1909
1910 device->keep_shader_info = keep_shader_info;
1911
1912 result = radv_device_init_meta(device);
1913 if (result != VK_SUCCESS)
1914 goto fail;
1915
1916 radv_device_init_msaa(device);
1917
1918 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1919 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1920 switch (family) {
1921 case RADV_QUEUE_GENERAL:
1922 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1923 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1924 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1925 break;
1926 case RADV_QUEUE_COMPUTE:
1927 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1928 radeon_emit(device->empty_cs[family], 0);
1929 break;
1930 }
1931 device->ws->cs_finalize(device->empty_cs[family]);
1932 }
1933
1934 if (device->physical_device->rad_info.chip_class >= GFX7)
1935 cik_create_gfx_config(device);
1936
1937 VkPipelineCacheCreateInfo ci;
1938 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1939 ci.pNext = NULL;
1940 ci.flags = 0;
1941 ci.pInitialData = NULL;
1942 ci.initialDataSize = 0;
1943 VkPipelineCache pc;
1944 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1945 &ci, NULL, &pc);
1946 if (result != VK_SUCCESS)
1947 goto fail_meta;
1948
1949 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1950
1951 device->force_aniso =
1952 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1953 if (device->force_aniso >= 0) {
1954 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1955 1 << util_logbase2(device->force_aniso));
1956 }
1957
1958 *pDevice = radv_device_to_handle(device);
1959 return VK_SUCCESS;
1960
1961 fail_meta:
1962 radv_device_finish_meta(device);
1963 fail:
1964 radv_bo_list_finish(&device->bo_list);
1965
1966 if (device->trace_bo)
1967 device->ws->buffer_destroy(device->trace_bo);
1968
1969 if (device->gfx_init)
1970 device->ws->buffer_destroy(device->gfx_init);
1971
1972 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1973 for (unsigned q = 0; q < device->queue_count[i]; q++)
1974 radv_queue_finish(&device->queues[i][q]);
1975 if (device->queue_count[i])
1976 vk_free(&device->alloc, device->queues[i]);
1977 }
1978
1979 vk_free(&device->alloc, device);
1980 return result;
1981 }
1982
1983 void radv_DestroyDevice(
1984 VkDevice _device,
1985 const VkAllocationCallbacks* pAllocator)
1986 {
1987 RADV_FROM_HANDLE(radv_device, device, _device);
1988
1989 if (!device)
1990 return;
1991
1992 if (device->trace_bo)
1993 device->ws->buffer_destroy(device->trace_bo);
1994
1995 if (device->gfx_init)
1996 device->ws->buffer_destroy(device->gfx_init);
1997
1998 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1999 for (unsigned q = 0; q < device->queue_count[i]; q++)
2000 radv_queue_finish(&device->queues[i][q]);
2001 if (device->queue_count[i])
2002 vk_free(&device->alloc, device->queues[i]);
2003 if (device->empty_cs[i])
2004 device->ws->cs_destroy(device->empty_cs[i]);
2005 }
2006 radv_device_finish_meta(device);
2007
2008 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2009 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2010
2011 radv_destroy_shader_slabs(device);
2012
2013 radv_bo_list_finish(&device->bo_list);
2014 vk_free(&device->alloc, device);
2015 }
2016
2017 VkResult radv_EnumerateInstanceLayerProperties(
2018 uint32_t* pPropertyCount,
2019 VkLayerProperties* pProperties)
2020 {
2021 if (pProperties == NULL) {
2022 *pPropertyCount = 0;
2023 return VK_SUCCESS;
2024 }
2025
2026 /* None supported at this time */
2027 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2028 }
2029
2030 VkResult radv_EnumerateDeviceLayerProperties(
2031 VkPhysicalDevice physicalDevice,
2032 uint32_t* pPropertyCount,
2033 VkLayerProperties* pProperties)
2034 {
2035 if (pProperties == NULL) {
2036 *pPropertyCount = 0;
2037 return VK_SUCCESS;
2038 }
2039
2040 /* None supported at this time */
2041 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2042 }
2043
2044 void radv_GetDeviceQueue2(
2045 VkDevice _device,
2046 const VkDeviceQueueInfo2* pQueueInfo,
2047 VkQueue* pQueue)
2048 {
2049 RADV_FROM_HANDLE(radv_device, device, _device);
2050 struct radv_queue *queue;
2051
2052 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2053 if (pQueueInfo->flags != queue->flags) {
2054 /* From the Vulkan 1.1.70 spec:
2055 *
2056 * "The queue returned by vkGetDeviceQueue2 must have the same
2057 * flags value from this structure as that used at device
2058 * creation time in a VkDeviceQueueCreateInfo instance. If no
2059 * matching flags were specified at device creation time then
2060 * pQueue will return VK_NULL_HANDLE."
2061 */
2062 *pQueue = VK_NULL_HANDLE;
2063 return;
2064 }
2065
2066 *pQueue = radv_queue_to_handle(queue);
2067 }
2068
2069 void radv_GetDeviceQueue(
2070 VkDevice _device,
2071 uint32_t queueFamilyIndex,
2072 uint32_t queueIndex,
2073 VkQueue* pQueue)
2074 {
2075 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2076 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2077 .queueFamilyIndex = queueFamilyIndex,
2078 .queueIndex = queueIndex
2079 };
2080
2081 radv_GetDeviceQueue2(_device, &info, pQueue);
2082 }
2083
2084 static void
2085 fill_geom_tess_rings(struct radv_queue *queue,
2086 uint32_t *map,
2087 bool add_sample_positions,
2088 uint32_t esgs_ring_size,
2089 struct radeon_winsys_bo *esgs_ring_bo,
2090 uint32_t gsvs_ring_size,
2091 struct radeon_winsys_bo *gsvs_ring_bo,
2092 uint32_t tess_factor_ring_size,
2093 uint32_t tess_offchip_ring_offset,
2094 uint32_t tess_offchip_ring_size,
2095 struct radeon_winsys_bo *tess_rings_bo)
2096 {
2097 uint32_t *desc = &map[4];
2098
2099 if (esgs_ring_bo) {
2100 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2101
2102 /* stride 0, num records - size, add tid, swizzle, elsize4,
2103 index stride 64 */
2104 desc[0] = esgs_va;
2105 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2106 S_008F04_STRIDE(0) |
2107 S_008F04_SWIZZLE_ENABLE(true);
2108 desc[2] = esgs_ring_size;
2109 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2110 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2111 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2112 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2113 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2114 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2115 S_008F0C_ELEMENT_SIZE(1) |
2116 S_008F0C_INDEX_STRIDE(3) |
2117 S_008F0C_ADD_TID_ENABLE(true);
2118
2119 /* GS entry for ES->GS ring */
2120 /* stride 0, num records - size, elsize0,
2121 index stride 0 */
2122 desc[4] = esgs_va;
2123 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2124 S_008F04_STRIDE(0) |
2125 S_008F04_SWIZZLE_ENABLE(false);
2126 desc[6] = esgs_ring_size;
2127 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2128 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2129 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2130 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2131 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2132 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2133 S_008F0C_ELEMENT_SIZE(0) |
2134 S_008F0C_INDEX_STRIDE(0) |
2135 S_008F0C_ADD_TID_ENABLE(false);
2136 }
2137
2138 desc += 8;
2139
2140 if (gsvs_ring_bo) {
2141 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2142
2143 /* VS entry for GS->VS ring */
2144 /* stride 0, num records - size, elsize0,
2145 index stride 0 */
2146 desc[0] = gsvs_va;
2147 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2148 S_008F04_STRIDE(0) |
2149 S_008F04_SWIZZLE_ENABLE(false);
2150 desc[2] = gsvs_ring_size;
2151 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2152 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2153 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2154 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2155 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2156 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2157 S_008F0C_ELEMENT_SIZE(0) |
2158 S_008F0C_INDEX_STRIDE(0) |
2159 S_008F0C_ADD_TID_ENABLE(false);
2160
2161 /* stride gsvs_itemsize, num records 64
2162 elsize 4, index stride 16 */
2163 /* shader will patch stride and desc[2] */
2164 desc[4] = gsvs_va;
2165 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2166 S_008F04_STRIDE(0) |
2167 S_008F04_SWIZZLE_ENABLE(true);
2168 desc[6] = 0;
2169 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2170 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2171 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2172 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2173 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2174 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2175 S_008F0C_ELEMENT_SIZE(1) |
2176 S_008F0C_INDEX_STRIDE(1) |
2177 S_008F0C_ADD_TID_ENABLE(true);
2178 }
2179
2180 desc += 8;
2181
2182 if (tess_rings_bo) {
2183 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2184 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2185
2186 desc[0] = tess_va;
2187 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2188 S_008F04_STRIDE(0) |
2189 S_008F04_SWIZZLE_ENABLE(false);
2190 desc[2] = tess_factor_ring_size;
2191 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2192 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2193 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2194 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2195 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2196 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2197 S_008F0C_ELEMENT_SIZE(0) |
2198 S_008F0C_INDEX_STRIDE(0) |
2199 S_008F0C_ADD_TID_ENABLE(false);
2200
2201 desc[4] = tess_offchip_va;
2202 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2203 S_008F04_STRIDE(0) |
2204 S_008F04_SWIZZLE_ENABLE(false);
2205 desc[6] = tess_offchip_ring_size;
2206 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2207 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2208 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2209 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2210 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2211 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2212 S_008F0C_ELEMENT_SIZE(0) |
2213 S_008F0C_INDEX_STRIDE(0) |
2214 S_008F0C_ADD_TID_ENABLE(false);
2215 }
2216
2217 desc += 8;
2218
2219 if (add_sample_positions) {
2220 /* add sample positions after all rings */
2221 memcpy(desc, queue->device->sample_locations_1x, 8);
2222 desc += 2;
2223 memcpy(desc, queue->device->sample_locations_2x, 16);
2224 desc += 4;
2225 memcpy(desc, queue->device->sample_locations_4x, 32);
2226 desc += 8;
2227 memcpy(desc, queue->device->sample_locations_8x, 64);
2228 }
2229 }
2230
2231 static unsigned
2232 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2233 {
2234 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2235 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2236 device->physical_device->rad_info.family != CHIP_STONEY;
2237 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2238 unsigned max_offchip_buffers;
2239 unsigned offchip_granularity;
2240 unsigned hs_offchip_param;
2241
2242 /*
2243 * Per RadeonSI:
2244 * This must be one less than the maximum number due to a hw limitation.
2245 * Various hardware bugs need thGFX7
2246 *
2247 * Per AMDVLK:
2248 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2249 * Gfx7 should limit max_offchip_buffers to 508
2250 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2251 *
2252 * Follow AMDVLK here.
2253 */
2254 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2255 device->physical_device->rad_info.chip_class == GFX7 ||
2256 device->physical_device->rad_info.chip_class == GFX6)
2257 --max_offchip_buffers_per_se;
2258
2259 max_offchip_buffers = max_offchip_buffers_per_se *
2260 device->physical_device->rad_info.max_se;
2261
2262 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2263 * around by setting 4K granularity.
2264 */
2265 if (device->tess_offchip_block_dw_size == 4096) {
2266 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2267 offchip_granularity = V_03093C_X_4K_DWORDS;
2268 } else {
2269 assert(device->tess_offchip_block_dw_size == 8192);
2270 offchip_granularity = V_03093C_X_8K_DWORDS;
2271 }
2272
2273 switch (device->physical_device->rad_info.chip_class) {
2274 case GFX6:
2275 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2276 break;
2277 case GFX7:
2278 case GFX8:
2279 case GFX9:
2280 default:
2281 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2282 break;
2283 }
2284
2285 *max_offchip_buffers_p = max_offchip_buffers;
2286 if (device->physical_device->rad_info.chip_class >= GFX7) {
2287 if (device->physical_device->rad_info.chip_class >= GFX8)
2288 --max_offchip_buffers;
2289 hs_offchip_param =
2290 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2291 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2292 } else {
2293 hs_offchip_param =
2294 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2295 }
2296 return hs_offchip_param;
2297 }
2298
2299 static void
2300 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2301 struct radeon_winsys_bo *esgs_ring_bo,
2302 uint32_t esgs_ring_size,
2303 struct radeon_winsys_bo *gsvs_ring_bo,
2304 uint32_t gsvs_ring_size)
2305 {
2306 if (!esgs_ring_bo && !gsvs_ring_bo)
2307 return;
2308
2309 if (esgs_ring_bo)
2310 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2311
2312 if (gsvs_ring_bo)
2313 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2314
2315 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2316 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2317 radeon_emit(cs, esgs_ring_size >> 8);
2318 radeon_emit(cs, gsvs_ring_size >> 8);
2319 } else {
2320 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2321 radeon_emit(cs, esgs_ring_size >> 8);
2322 radeon_emit(cs, gsvs_ring_size >> 8);
2323 }
2324 }
2325
2326 static void
2327 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2328 unsigned hs_offchip_param, unsigned tf_ring_size,
2329 struct radeon_winsys_bo *tess_rings_bo)
2330 {
2331 uint64_t tf_va;
2332
2333 if (!tess_rings_bo)
2334 return;
2335
2336 tf_va = radv_buffer_get_va(tess_rings_bo);
2337
2338 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2339
2340 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2341 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2342 S_030938_SIZE(tf_ring_size / 4));
2343 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2344 tf_va >> 8);
2345 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2346 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2347 S_030944_BASE_HI(tf_va >> 40));
2348 }
2349 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2350 hs_offchip_param);
2351 } else {
2352 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2353 S_008988_SIZE(tf_ring_size / 4));
2354 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2355 tf_va >> 8);
2356 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2357 hs_offchip_param);
2358 }
2359 }
2360
2361 static void
2362 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2363 struct radeon_winsys_bo *compute_scratch_bo)
2364 {
2365 uint64_t scratch_va;
2366
2367 if (!compute_scratch_bo)
2368 return;
2369
2370 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2371
2372 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2373
2374 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2375 radeon_emit(cs, scratch_va);
2376 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2377 S_008F04_SWIZZLE_ENABLE(1));
2378 }
2379
2380 static void
2381 radv_emit_global_shader_pointers(struct radv_queue *queue,
2382 struct radeon_cmdbuf *cs,
2383 struct radeon_winsys_bo *descriptor_bo)
2384 {
2385 uint64_t va;
2386
2387 if (!descriptor_bo)
2388 return;
2389
2390 va = radv_buffer_get_va(descriptor_bo);
2391
2392 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2393
2394 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2395 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2396 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2397 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2398 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2399
2400 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2401 radv_emit_shader_pointer(queue->device, cs, regs[i],
2402 va, true);
2403 }
2404 } else {
2405 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2406 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2407 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2408 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2409 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2410 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2411
2412 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2413 radv_emit_shader_pointer(queue->device, cs, regs[i],
2414 va, true);
2415 }
2416 }
2417 }
2418
2419 static void
2420 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2421 {
2422 struct radv_device *device = queue->device;
2423
2424 if (device->gfx_init) {
2425 uint64_t va = radv_buffer_get_va(device->gfx_init);
2426
2427 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2428 radeon_emit(cs, va);
2429 radeon_emit(cs, va >> 32);
2430 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2431
2432 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2433 } else {
2434 struct radv_physical_device *physical_device = device->physical_device;
2435 si_emit_graphics(physical_device, cs);
2436 }
2437 }
2438
2439 static void
2440 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2441 {
2442 struct radv_physical_device *physical_device = queue->device->physical_device;
2443 si_emit_compute(physical_device, cs);
2444 }
2445
2446 static VkResult
2447 radv_get_preamble_cs(struct radv_queue *queue,
2448 uint32_t scratch_size,
2449 uint32_t compute_scratch_size,
2450 uint32_t esgs_ring_size,
2451 uint32_t gsvs_ring_size,
2452 bool needs_tess_rings,
2453 bool needs_sample_positions,
2454 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2455 struct radeon_cmdbuf **initial_preamble_cs,
2456 struct radeon_cmdbuf **continue_preamble_cs)
2457 {
2458 struct radeon_winsys_bo *scratch_bo = NULL;
2459 struct radeon_winsys_bo *descriptor_bo = NULL;
2460 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2461 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2462 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2463 struct radeon_winsys_bo *tess_rings_bo = NULL;
2464 struct radeon_cmdbuf *dest_cs[3] = {0};
2465 bool add_tess_rings = false, add_sample_positions = false;
2466 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2467 unsigned max_offchip_buffers;
2468 unsigned hs_offchip_param = 0;
2469 unsigned tess_offchip_ring_offset;
2470 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2471 if (!queue->has_tess_rings) {
2472 if (needs_tess_rings)
2473 add_tess_rings = true;
2474 }
2475 if (!queue->has_sample_positions) {
2476 if (needs_sample_positions)
2477 add_sample_positions = true;
2478 }
2479 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2480 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2481 &max_offchip_buffers);
2482 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2483 tess_offchip_ring_size = max_offchip_buffers *
2484 queue->device->tess_offchip_block_dw_size * 4;
2485
2486 if (scratch_size <= queue->scratch_size &&
2487 compute_scratch_size <= queue->compute_scratch_size &&
2488 esgs_ring_size <= queue->esgs_ring_size &&
2489 gsvs_ring_size <= queue->gsvs_ring_size &&
2490 !add_tess_rings && !add_sample_positions &&
2491 queue->initial_preamble_cs) {
2492 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2493 *initial_preamble_cs = queue->initial_preamble_cs;
2494 *continue_preamble_cs = queue->continue_preamble_cs;
2495 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2496 *continue_preamble_cs = NULL;
2497 return VK_SUCCESS;
2498 }
2499
2500 if (scratch_size > queue->scratch_size) {
2501 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2502 scratch_size,
2503 4096,
2504 RADEON_DOMAIN_VRAM,
2505 ring_bo_flags,
2506 RADV_BO_PRIORITY_SCRATCH);
2507 if (!scratch_bo)
2508 goto fail;
2509 } else
2510 scratch_bo = queue->scratch_bo;
2511
2512 if (compute_scratch_size > queue->compute_scratch_size) {
2513 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2514 compute_scratch_size,
2515 4096,
2516 RADEON_DOMAIN_VRAM,
2517 ring_bo_flags,
2518 RADV_BO_PRIORITY_SCRATCH);
2519 if (!compute_scratch_bo)
2520 goto fail;
2521
2522 } else
2523 compute_scratch_bo = queue->compute_scratch_bo;
2524
2525 if (esgs_ring_size > queue->esgs_ring_size) {
2526 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2527 esgs_ring_size,
2528 4096,
2529 RADEON_DOMAIN_VRAM,
2530 ring_bo_flags,
2531 RADV_BO_PRIORITY_SCRATCH);
2532 if (!esgs_ring_bo)
2533 goto fail;
2534 } else {
2535 esgs_ring_bo = queue->esgs_ring_bo;
2536 esgs_ring_size = queue->esgs_ring_size;
2537 }
2538
2539 if (gsvs_ring_size > queue->gsvs_ring_size) {
2540 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2541 gsvs_ring_size,
2542 4096,
2543 RADEON_DOMAIN_VRAM,
2544 ring_bo_flags,
2545 RADV_BO_PRIORITY_SCRATCH);
2546 if (!gsvs_ring_bo)
2547 goto fail;
2548 } else {
2549 gsvs_ring_bo = queue->gsvs_ring_bo;
2550 gsvs_ring_size = queue->gsvs_ring_size;
2551 }
2552
2553 if (add_tess_rings) {
2554 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2555 tess_offchip_ring_offset + tess_offchip_ring_size,
2556 256,
2557 RADEON_DOMAIN_VRAM,
2558 ring_bo_flags,
2559 RADV_BO_PRIORITY_SCRATCH);
2560 if (!tess_rings_bo)
2561 goto fail;
2562 } else {
2563 tess_rings_bo = queue->tess_rings_bo;
2564 }
2565
2566 if (scratch_bo != queue->scratch_bo ||
2567 esgs_ring_bo != queue->esgs_ring_bo ||
2568 gsvs_ring_bo != queue->gsvs_ring_bo ||
2569 tess_rings_bo != queue->tess_rings_bo ||
2570 add_sample_positions) {
2571 uint32_t size = 0;
2572 if (gsvs_ring_bo || esgs_ring_bo ||
2573 tess_rings_bo || add_sample_positions) {
2574 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2575 if (add_sample_positions)
2576 size += 128; /* 64+32+16+8 = 120 bytes */
2577 }
2578 else if (scratch_bo)
2579 size = 8; /* 2 dword */
2580
2581 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2582 size,
2583 4096,
2584 RADEON_DOMAIN_VRAM,
2585 RADEON_FLAG_CPU_ACCESS |
2586 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2587 RADEON_FLAG_READ_ONLY,
2588 RADV_BO_PRIORITY_DESCRIPTOR);
2589 if (!descriptor_bo)
2590 goto fail;
2591 } else
2592 descriptor_bo = queue->descriptor_bo;
2593
2594 if (descriptor_bo != queue->descriptor_bo) {
2595 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2596
2597 if (scratch_bo) {
2598 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2599 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2600 S_008F04_SWIZZLE_ENABLE(1);
2601 map[0] = scratch_va;
2602 map[1] = rsrc1;
2603 }
2604
2605 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2606 fill_geom_tess_rings(queue, map, add_sample_positions,
2607 esgs_ring_size, esgs_ring_bo,
2608 gsvs_ring_size, gsvs_ring_bo,
2609 tess_factor_ring_size,
2610 tess_offchip_ring_offset,
2611 tess_offchip_ring_size,
2612 tess_rings_bo);
2613
2614 queue->device->ws->buffer_unmap(descriptor_bo);
2615 }
2616
2617 for(int i = 0; i < 3; ++i) {
2618 struct radeon_cmdbuf *cs = NULL;
2619 cs = queue->device->ws->cs_create(queue->device->ws,
2620 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2621 if (!cs)
2622 goto fail;
2623
2624 dest_cs[i] = cs;
2625
2626 if (scratch_bo)
2627 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2628
2629 /* Emit initial configuration. */
2630 switch (queue->queue_family_index) {
2631 case RADV_QUEUE_GENERAL:
2632 radv_init_graphics_state(cs, queue);
2633 break;
2634 case RADV_QUEUE_COMPUTE:
2635 radv_init_compute_state(cs, queue);
2636 break;
2637 case RADV_QUEUE_TRANSFER:
2638 break;
2639 }
2640
2641 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2642 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2643 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2644 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2645 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2646 }
2647
2648 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2649 gsvs_ring_bo, gsvs_ring_size);
2650 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2651 tess_factor_ring_size, tess_rings_bo);
2652 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2653 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2654
2655 if (i == 0) {
2656 si_cs_emit_cache_flush(cs,
2657 queue->device->physical_device->rad_info.chip_class,
2658 NULL, 0,
2659 queue->queue_family_index == RING_COMPUTE &&
2660 queue->device->physical_device->rad_info.chip_class >= GFX7,
2661 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2662 RADV_CMD_FLAG_INV_ICACHE |
2663 RADV_CMD_FLAG_INV_SMEM_L1 |
2664 RADV_CMD_FLAG_INV_VMEM_L1 |
2665 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2666 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2667 } else if (i == 1) {
2668 si_cs_emit_cache_flush(cs,
2669 queue->device->physical_device->rad_info.chip_class,
2670 NULL, 0,
2671 queue->queue_family_index == RING_COMPUTE &&
2672 queue->device->physical_device->rad_info.chip_class >= GFX7,
2673 RADV_CMD_FLAG_INV_ICACHE |
2674 RADV_CMD_FLAG_INV_SMEM_L1 |
2675 RADV_CMD_FLAG_INV_VMEM_L1 |
2676 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2677 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2678 }
2679
2680 if (!queue->device->ws->cs_finalize(cs))
2681 goto fail;
2682 }
2683
2684 if (queue->initial_full_flush_preamble_cs)
2685 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2686
2687 if (queue->initial_preamble_cs)
2688 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2689
2690 if (queue->continue_preamble_cs)
2691 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2692
2693 queue->initial_full_flush_preamble_cs = dest_cs[0];
2694 queue->initial_preamble_cs = dest_cs[1];
2695 queue->continue_preamble_cs = dest_cs[2];
2696
2697 if (scratch_bo != queue->scratch_bo) {
2698 if (queue->scratch_bo)
2699 queue->device->ws->buffer_destroy(queue->scratch_bo);
2700 queue->scratch_bo = scratch_bo;
2701 queue->scratch_size = scratch_size;
2702 }
2703
2704 if (compute_scratch_bo != queue->compute_scratch_bo) {
2705 if (queue->compute_scratch_bo)
2706 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2707 queue->compute_scratch_bo = compute_scratch_bo;
2708 queue->compute_scratch_size = compute_scratch_size;
2709 }
2710
2711 if (esgs_ring_bo != queue->esgs_ring_bo) {
2712 if (queue->esgs_ring_bo)
2713 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2714 queue->esgs_ring_bo = esgs_ring_bo;
2715 queue->esgs_ring_size = esgs_ring_size;
2716 }
2717
2718 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2719 if (queue->gsvs_ring_bo)
2720 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2721 queue->gsvs_ring_bo = gsvs_ring_bo;
2722 queue->gsvs_ring_size = gsvs_ring_size;
2723 }
2724
2725 if (tess_rings_bo != queue->tess_rings_bo) {
2726 queue->tess_rings_bo = tess_rings_bo;
2727 queue->has_tess_rings = true;
2728 }
2729
2730 if (descriptor_bo != queue->descriptor_bo) {
2731 if (queue->descriptor_bo)
2732 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2733
2734 queue->descriptor_bo = descriptor_bo;
2735 }
2736
2737 if (add_sample_positions)
2738 queue->has_sample_positions = true;
2739
2740 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2741 *initial_preamble_cs = queue->initial_preamble_cs;
2742 *continue_preamble_cs = queue->continue_preamble_cs;
2743 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2744 *continue_preamble_cs = NULL;
2745 return VK_SUCCESS;
2746 fail:
2747 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2748 if (dest_cs[i])
2749 queue->device->ws->cs_destroy(dest_cs[i]);
2750 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2751 queue->device->ws->buffer_destroy(descriptor_bo);
2752 if (scratch_bo && scratch_bo != queue->scratch_bo)
2753 queue->device->ws->buffer_destroy(scratch_bo);
2754 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2755 queue->device->ws->buffer_destroy(compute_scratch_bo);
2756 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2757 queue->device->ws->buffer_destroy(esgs_ring_bo);
2758 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2759 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2760 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2761 queue->device->ws->buffer_destroy(tess_rings_bo);
2762 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2763 }
2764
2765 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2766 struct radv_winsys_sem_counts *counts,
2767 int num_sems,
2768 const VkSemaphore *sems,
2769 VkFence _fence,
2770 bool reset_temp)
2771 {
2772 int syncobj_idx = 0, sem_idx = 0;
2773
2774 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2775 return VK_SUCCESS;
2776
2777 for (uint32_t i = 0; i < num_sems; i++) {
2778 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2779
2780 if (sem->temp_syncobj || sem->syncobj)
2781 counts->syncobj_count++;
2782 else
2783 counts->sem_count++;
2784 }
2785
2786 if (_fence != VK_NULL_HANDLE) {
2787 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2788 if (fence->temp_syncobj || fence->syncobj)
2789 counts->syncobj_count++;
2790 }
2791
2792 if (counts->syncobj_count) {
2793 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2794 if (!counts->syncobj)
2795 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2796 }
2797
2798 if (counts->sem_count) {
2799 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2800 if (!counts->sem) {
2801 free(counts->syncobj);
2802 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2803 }
2804 }
2805
2806 for (uint32_t i = 0; i < num_sems; i++) {
2807 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2808
2809 if (sem->temp_syncobj) {
2810 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2811 }
2812 else if (sem->syncobj)
2813 counts->syncobj[syncobj_idx++] = sem->syncobj;
2814 else {
2815 assert(sem->sem);
2816 counts->sem[sem_idx++] = sem->sem;
2817 }
2818 }
2819
2820 if (_fence != VK_NULL_HANDLE) {
2821 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2822 if (fence->temp_syncobj)
2823 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2824 else if (fence->syncobj)
2825 counts->syncobj[syncobj_idx++] = fence->syncobj;
2826 }
2827
2828 return VK_SUCCESS;
2829 }
2830
2831 static void
2832 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2833 {
2834 free(sem_info->wait.syncobj);
2835 free(sem_info->wait.sem);
2836 free(sem_info->signal.syncobj);
2837 free(sem_info->signal.sem);
2838 }
2839
2840
2841 static void radv_free_temp_syncobjs(struct radv_device *device,
2842 int num_sems,
2843 const VkSemaphore *sems)
2844 {
2845 for (uint32_t i = 0; i < num_sems; i++) {
2846 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2847
2848 if (sem->temp_syncobj) {
2849 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2850 sem->temp_syncobj = 0;
2851 }
2852 }
2853 }
2854
2855 static VkResult
2856 radv_alloc_sem_info(struct radv_instance *instance,
2857 struct radv_winsys_sem_info *sem_info,
2858 int num_wait_sems,
2859 const VkSemaphore *wait_sems,
2860 int num_signal_sems,
2861 const VkSemaphore *signal_sems,
2862 VkFence fence)
2863 {
2864 VkResult ret;
2865 memset(sem_info, 0, sizeof(*sem_info));
2866
2867 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2868 if (ret)
2869 return ret;
2870 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2871 if (ret)
2872 radv_free_sem_info(sem_info);
2873
2874 /* caller can override these */
2875 sem_info->cs_emit_wait = true;
2876 sem_info->cs_emit_signal = true;
2877 return ret;
2878 }
2879
2880 /* Signals fence as soon as all the work currently put on queue is done. */
2881 static VkResult radv_signal_fence(struct radv_queue *queue,
2882 struct radv_fence *fence)
2883 {
2884 int ret;
2885 VkResult result;
2886 struct radv_winsys_sem_info sem_info;
2887
2888 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2889 radv_fence_to_handle(fence));
2890 if (result != VK_SUCCESS)
2891 return result;
2892
2893 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2894 &queue->device->empty_cs[queue->queue_family_index],
2895 1, NULL, NULL, &sem_info, NULL,
2896 false, fence->fence);
2897 radv_free_sem_info(&sem_info);
2898
2899 if (ret)
2900 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2901
2902 return VK_SUCCESS;
2903 }
2904
2905 VkResult radv_QueueSubmit(
2906 VkQueue _queue,
2907 uint32_t submitCount,
2908 const VkSubmitInfo* pSubmits,
2909 VkFence _fence)
2910 {
2911 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2912 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2913 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2914 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2915 int ret;
2916 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2917 uint32_t scratch_size = 0;
2918 uint32_t compute_scratch_size = 0;
2919 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2920 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2921 VkResult result;
2922 bool fence_emitted = false;
2923 bool tess_rings_needed = false;
2924 bool sample_positions_needed = false;
2925
2926 /* Do this first so failing to allocate scratch buffers can't result in
2927 * partially executed submissions. */
2928 for (uint32_t i = 0; i < submitCount; i++) {
2929 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2931 pSubmits[i].pCommandBuffers[j]);
2932
2933 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2934 compute_scratch_size = MAX2(compute_scratch_size,
2935 cmd_buffer->compute_scratch_size_needed);
2936 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2937 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2938 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2939 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2940 }
2941 }
2942
2943 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2944 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2945 sample_positions_needed, &initial_flush_preamble_cs,
2946 &initial_preamble_cs, &continue_preamble_cs);
2947 if (result != VK_SUCCESS)
2948 return result;
2949
2950 for (uint32_t i = 0; i < submitCount; i++) {
2951 struct radeon_cmdbuf **cs_array;
2952 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2953 bool can_patch = true;
2954 uint32_t advance;
2955 struct radv_winsys_sem_info sem_info;
2956
2957 result = radv_alloc_sem_info(queue->device->instance,
2958 &sem_info,
2959 pSubmits[i].waitSemaphoreCount,
2960 pSubmits[i].pWaitSemaphores,
2961 pSubmits[i].signalSemaphoreCount,
2962 pSubmits[i].pSignalSemaphores,
2963 _fence);
2964 if (result != VK_SUCCESS)
2965 return result;
2966
2967 if (!pSubmits[i].commandBufferCount) {
2968 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2969 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2970 &queue->device->empty_cs[queue->queue_family_index],
2971 1, NULL, NULL,
2972 &sem_info, NULL,
2973 false, base_fence);
2974 if (ret) {
2975 radv_loge("failed to submit CS %d\n", i);
2976 abort();
2977 }
2978 fence_emitted = true;
2979 }
2980 radv_free_sem_info(&sem_info);
2981 continue;
2982 }
2983
2984 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2985 (pSubmits[i].commandBufferCount));
2986
2987 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2989 pSubmits[i].pCommandBuffers[j]);
2990 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2991
2992 cs_array[j] = cmd_buffer->cs;
2993 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2994 can_patch = false;
2995
2996 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2997 }
2998
2999 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3000 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3001 const struct radv_winsys_bo_list *bo_list = NULL;
3002
3003 advance = MIN2(max_cs_submission,
3004 pSubmits[i].commandBufferCount - j);
3005
3006 if (queue->device->trace_bo)
3007 *queue->device->trace_id_ptr = 0;
3008
3009 sem_info.cs_emit_wait = j == 0;
3010 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3011
3012 if (unlikely(queue->device->use_global_bo_list)) {
3013 pthread_mutex_lock(&queue->device->bo_list.mutex);
3014 bo_list = &queue->device->bo_list.list;
3015 }
3016
3017 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3018 advance, initial_preamble, continue_preamble_cs,
3019 &sem_info, bo_list,
3020 can_patch, base_fence);
3021
3022 if (unlikely(queue->device->use_global_bo_list))
3023 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3024
3025 if (ret) {
3026 radv_loge("failed to submit CS %d\n", i);
3027 abort();
3028 }
3029 fence_emitted = true;
3030 if (queue->device->trace_bo) {
3031 radv_check_gpu_hangs(queue, cs_array[j]);
3032 }
3033 }
3034
3035 radv_free_temp_syncobjs(queue->device,
3036 pSubmits[i].waitSemaphoreCount,
3037 pSubmits[i].pWaitSemaphores);
3038 radv_free_sem_info(&sem_info);
3039 free(cs_array);
3040 }
3041
3042 if (fence) {
3043 if (!fence_emitted) {
3044 result = radv_signal_fence(queue, fence);
3045 if (result != VK_SUCCESS)
3046 return result;
3047 }
3048 }
3049
3050 return VK_SUCCESS;
3051 }
3052
3053 VkResult radv_QueueWaitIdle(
3054 VkQueue _queue)
3055 {
3056 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3057
3058 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3059 radv_queue_family_to_ring(queue->queue_family_index),
3060 queue->queue_idx);
3061 return VK_SUCCESS;
3062 }
3063
3064 VkResult radv_DeviceWaitIdle(
3065 VkDevice _device)
3066 {
3067 RADV_FROM_HANDLE(radv_device, device, _device);
3068
3069 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3070 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3071 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3072 }
3073 }
3074 return VK_SUCCESS;
3075 }
3076
3077 VkResult radv_EnumerateInstanceExtensionProperties(
3078 const char* pLayerName,
3079 uint32_t* pPropertyCount,
3080 VkExtensionProperties* pProperties)
3081 {
3082 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3083
3084 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3085 if (radv_supported_instance_extensions.extensions[i]) {
3086 vk_outarray_append(&out, prop) {
3087 *prop = radv_instance_extensions[i];
3088 }
3089 }
3090 }
3091
3092 return vk_outarray_status(&out);
3093 }
3094
3095 VkResult radv_EnumerateDeviceExtensionProperties(
3096 VkPhysicalDevice physicalDevice,
3097 const char* pLayerName,
3098 uint32_t* pPropertyCount,
3099 VkExtensionProperties* pProperties)
3100 {
3101 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3102 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3103
3104 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3105 if (device->supported_extensions.extensions[i]) {
3106 vk_outarray_append(&out, prop) {
3107 *prop = radv_device_extensions[i];
3108 }
3109 }
3110 }
3111
3112 return vk_outarray_status(&out);
3113 }
3114
3115 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3116 VkInstance _instance,
3117 const char* pName)
3118 {
3119 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3120
3121 return radv_lookup_entrypoint_checked(pName,
3122 instance ? instance->apiVersion : 0,
3123 instance ? &instance->enabled_extensions : NULL,
3124 NULL);
3125 }
3126
3127 /* The loader wants us to expose a second GetInstanceProcAddr function
3128 * to work around certain LD_PRELOAD issues seen in apps.
3129 */
3130 PUBLIC
3131 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3132 VkInstance instance,
3133 const char* pName);
3134
3135 PUBLIC
3136 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3137 VkInstance instance,
3138 const char* pName)
3139 {
3140 return radv_GetInstanceProcAddr(instance, pName);
3141 }
3142
3143 PUBLIC
3144 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3145 VkInstance _instance,
3146 const char* pName);
3147
3148 PUBLIC
3149 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3150 VkInstance _instance,
3151 const char* pName)
3152 {
3153 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3154
3155 return radv_lookup_physical_device_entrypoint_checked(pName,
3156 instance ? instance->apiVersion : 0,
3157 instance ? &instance->enabled_extensions : NULL);
3158 }
3159
3160 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3161 VkDevice _device,
3162 const char* pName)
3163 {
3164 RADV_FROM_HANDLE(radv_device, device, _device);
3165
3166 return radv_lookup_entrypoint_checked(pName,
3167 device->instance->apiVersion,
3168 &device->instance->enabled_extensions,
3169 &device->enabled_extensions);
3170 }
3171
3172 bool radv_get_memory_fd(struct radv_device *device,
3173 struct radv_device_memory *memory,
3174 int *pFD)
3175 {
3176 struct radeon_bo_metadata metadata;
3177
3178 if (memory->image) {
3179 radv_init_metadata(device, memory->image, &metadata);
3180 device->ws->buffer_set_metadata(memory->bo, &metadata);
3181 }
3182
3183 return device->ws->buffer_get_fd(device->ws, memory->bo,
3184 pFD);
3185 }
3186
3187 static VkResult radv_alloc_memory(struct radv_device *device,
3188 const VkMemoryAllocateInfo* pAllocateInfo,
3189 const VkAllocationCallbacks* pAllocator,
3190 VkDeviceMemory* pMem)
3191 {
3192 struct radv_device_memory *mem;
3193 VkResult result;
3194 enum radeon_bo_domain domain;
3195 uint32_t flags = 0;
3196 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3197
3198 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3199
3200 if (pAllocateInfo->allocationSize == 0) {
3201 /* Apparently, this is allowed */
3202 *pMem = VK_NULL_HANDLE;
3203 return VK_SUCCESS;
3204 }
3205
3206 const VkImportMemoryFdInfoKHR *import_info =
3207 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3208 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3209 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3210 const VkExportMemoryAllocateInfo *export_info =
3211 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3212 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3213 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3214
3215 const struct wsi_memory_allocate_info *wsi_info =
3216 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3217
3218 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3219 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3220 if (mem == NULL)
3221 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3222
3223 if (wsi_info && wsi_info->implicit_sync)
3224 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3225
3226 if (dedicate_info) {
3227 mem->image = radv_image_from_handle(dedicate_info->image);
3228 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3229 } else {
3230 mem->image = NULL;
3231 mem->buffer = NULL;
3232 }
3233
3234 float priority_float = 0.5;
3235 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3236 vk_find_struct_const(pAllocateInfo->pNext,
3237 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3238 if (priority_ext)
3239 priority_float = priority_ext->priority;
3240
3241 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3242 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3243
3244 mem->user_ptr = NULL;
3245
3246 if (import_info) {
3247 assert(import_info->handleType ==
3248 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3249 import_info->handleType ==
3250 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3251 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3252 priority, NULL, NULL);
3253 if (!mem->bo) {
3254 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3255 goto fail;
3256 } else {
3257 close(import_info->fd);
3258 }
3259 } else if (host_ptr_info) {
3260 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3261 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3262 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3263 pAllocateInfo->allocationSize,
3264 priority);
3265 if (!mem->bo) {
3266 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3267 goto fail;
3268 } else {
3269 mem->user_ptr = host_ptr_info->pHostPointer;
3270 }
3271 } else {
3272 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3273 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3274 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3275 domain = RADEON_DOMAIN_GTT;
3276 else
3277 domain = RADEON_DOMAIN_VRAM;
3278
3279 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3280 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3281 else
3282 flags |= RADEON_FLAG_CPU_ACCESS;
3283
3284 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3285 flags |= RADEON_FLAG_GTT_WC;
3286
3287 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3288 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3289 if (device->use_global_bo_list) {
3290 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3291 }
3292 }
3293
3294 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3295 domain, flags, priority);
3296
3297 if (!mem->bo) {
3298 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3299 goto fail;
3300 }
3301 mem->type_index = mem_type_index;
3302 }
3303
3304 result = radv_bo_list_add(device, mem->bo);
3305 if (result != VK_SUCCESS)
3306 goto fail_bo;
3307
3308 *pMem = radv_device_memory_to_handle(mem);
3309
3310 return VK_SUCCESS;
3311
3312 fail_bo:
3313 device->ws->buffer_destroy(mem->bo);
3314 fail:
3315 vk_free2(&device->alloc, pAllocator, mem);
3316
3317 return result;
3318 }
3319
3320 VkResult radv_AllocateMemory(
3321 VkDevice _device,
3322 const VkMemoryAllocateInfo* pAllocateInfo,
3323 const VkAllocationCallbacks* pAllocator,
3324 VkDeviceMemory* pMem)
3325 {
3326 RADV_FROM_HANDLE(radv_device, device, _device);
3327 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3328 }
3329
3330 void radv_FreeMemory(
3331 VkDevice _device,
3332 VkDeviceMemory _mem,
3333 const VkAllocationCallbacks* pAllocator)
3334 {
3335 RADV_FROM_HANDLE(radv_device, device, _device);
3336 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3337
3338 if (mem == NULL)
3339 return;
3340
3341 radv_bo_list_remove(device, mem->bo);
3342 device->ws->buffer_destroy(mem->bo);
3343 mem->bo = NULL;
3344
3345 vk_free2(&device->alloc, pAllocator, mem);
3346 }
3347
3348 VkResult radv_MapMemory(
3349 VkDevice _device,
3350 VkDeviceMemory _memory,
3351 VkDeviceSize offset,
3352 VkDeviceSize size,
3353 VkMemoryMapFlags flags,
3354 void** ppData)
3355 {
3356 RADV_FROM_HANDLE(radv_device, device, _device);
3357 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3358
3359 if (mem == NULL) {
3360 *ppData = NULL;
3361 return VK_SUCCESS;
3362 }
3363
3364 if (mem->user_ptr)
3365 *ppData = mem->user_ptr;
3366 else
3367 *ppData = device->ws->buffer_map(mem->bo);
3368
3369 if (*ppData) {
3370 *ppData += offset;
3371 return VK_SUCCESS;
3372 }
3373
3374 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3375 }
3376
3377 void radv_UnmapMemory(
3378 VkDevice _device,
3379 VkDeviceMemory _memory)
3380 {
3381 RADV_FROM_HANDLE(radv_device, device, _device);
3382 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3383
3384 if (mem == NULL)
3385 return;
3386
3387 if (mem->user_ptr == NULL)
3388 device->ws->buffer_unmap(mem->bo);
3389 }
3390
3391 VkResult radv_FlushMappedMemoryRanges(
3392 VkDevice _device,
3393 uint32_t memoryRangeCount,
3394 const VkMappedMemoryRange* pMemoryRanges)
3395 {
3396 return VK_SUCCESS;
3397 }
3398
3399 VkResult radv_InvalidateMappedMemoryRanges(
3400 VkDevice _device,
3401 uint32_t memoryRangeCount,
3402 const VkMappedMemoryRange* pMemoryRanges)
3403 {
3404 return VK_SUCCESS;
3405 }
3406
3407 void radv_GetBufferMemoryRequirements(
3408 VkDevice _device,
3409 VkBuffer _buffer,
3410 VkMemoryRequirements* pMemoryRequirements)
3411 {
3412 RADV_FROM_HANDLE(radv_device, device, _device);
3413 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3414
3415 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3416
3417 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3418 pMemoryRequirements->alignment = 4096;
3419 else
3420 pMemoryRequirements->alignment = 16;
3421
3422 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3423 }
3424
3425 void radv_GetBufferMemoryRequirements2(
3426 VkDevice device,
3427 const VkBufferMemoryRequirementsInfo2 *pInfo,
3428 VkMemoryRequirements2 *pMemoryRequirements)
3429 {
3430 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3431 &pMemoryRequirements->memoryRequirements);
3432 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3433 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3434 switch (ext->sType) {
3435 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3436 VkMemoryDedicatedRequirements *req =
3437 (VkMemoryDedicatedRequirements *) ext;
3438 req->requiresDedicatedAllocation = buffer->shareable;
3439 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3440 break;
3441 }
3442 default:
3443 break;
3444 }
3445 }
3446 }
3447
3448 void radv_GetImageMemoryRequirements(
3449 VkDevice _device,
3450 VkImage _image,
3451 VkMemoryRequirements* pMemoryRequirements)
3452 {
3453 RADV_FROM_HANDLE(radv_device, device, _device);
3454 RADV_FROM_HANDLE(radv_image, image, _image);
3455
3456 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3457
3458 pMemoryRequirements->size = image->size;
3459 pMemoryRequirements->alignment = image->alignment;
3460 }
3461
3462 void radv_GetImageMemoryRequirements2(
3463 VkDevice device,
3464 const VkImageMemoryRequirementsInfo2 *pInfo,
3465 VkMemoryRequirements2 *pMemoryRequirements)
3466 {
3467 radv_GetImageMemoryRequirements(device, pInfo->image,
3468 &pMemoryRequirements->memoryRequirements);
3469
3470 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3471
3472 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3473 switch (ext->sType) {
3474 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3475 VkMemoryDedicatedRequirements *req =
3476 (VkMemoryDedicatedRequirements *) ext;
3477 req->requiresDedicatedAllocation = image->shareable;
3478 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3479 break;
3480 }
3481 default:
3482 break;
3483 }
3484 }
3485 }
3486
3487 void radv_GetImageSparseMemoryRequirements(
3488 VkDevice device,
3489 VkImage image,
3490 uint32_t* pSparseMemoryRequirementCount,
3491 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3492 {
3493 stub();
3494 }
3495
3496 void radv_GetImageSparseMemoryRequirements2(
3497 VkDevice device,
3498 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3499 uint32_t* pSparseMemoryRequirementCount,
3500 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3501 {
3502 stub();
3503 }
3504
3505 void radv_GetDeviceMemoryCommitment(
3506 VkDevice device,
3507 VkDeviceMemory memory,
3508 VkDeviceSize* pCommittedMemoryInBytes)
3509 {
3510 *pCommittedMemoryInBytes = 0;
3511 }
3512
3513 VkResult radv_BindBufferMemory2(VkDevice device,
3514 uint32_t bindInfoCount,
3515 const VkBindBufferMemoryInfo *pBindInfos)
3516 {
3517 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3518 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3519 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3520
3521 if (mem) {
3522 buffer->bo = mem->bo;
3523 buffer->offset = pBindInfos[i].memoryOffset;
3524 } else {
3525 buffer->bo = NULL;
3526 }
3527 }
3528 return VK_SUCCESS;
3529 }
3530
3531 VkResult radv_BindBufferMemory(
3532 VkDevice device,
3533 VkBuffer buffer,
3534 VkDeviceMemory memory,
3535 VkDeviceSize memoryOffset)
3536 {
3537 const VkBindBufferMemoryInfo info = {
3538 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3539 .buffer = buffer,
3540 .memory = memory,
3541 .memoryOffset = memoryOffset
3542 };
3543
3544 return radv_BindBufferMemory2(device, 1, &info);
3545 }
3546
3547 VkResult radv_BindImageMemory2(VkDevice device,
3548 uint32_t bindInfoCount,
3549 const VkBindImageMemoryInfo *pBindInfos)
3550 {
3551 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3552 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3553 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3554
3555 if (mem) {
3556 image->bo = mem->bo;
3557 image->offset = pBindInfos[i].memoryOffset;
3558 } else {
3559 image->bo = NULL;
3560 image->offset = 0;
3561 }
3562 }
3563 return VK_SUCCESS;
3564 }
3565
3566
3567 VkResult radv_BindImageMemory(
3568 VkDevice device,
3569 VkImage image,
3570 VkDeviceMemory memory,
3571 VkDeviceSize memoryOffset)
3572 {
3573 const VkBindImageMemoryInfo info = {
3574 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3575 .image = image,
3576 .memory = memory,
3577 .memoryOffset = memoryOffset
3578 };
3579
3580 return radv_BindImageMemory2(device, 1, &info);
3581 }
3582
3583
3584 static void
3585 radv_sparse_buffer_bind_memory(struct radv_device *device,
3586 const VkSparseBufferMemoryBindInfo *bind)
3587 {
3588 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3589
3590 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3591 struct radv_device_memory *mem = NULL;
3592
3593 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3594 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3595
3596 device->ws->buffer_virtual_bind(buffer->bo,
3597 bind->pBinds[i].resourceOffset,
3598 bind->pBinds[i].size,
3599 mem ? mem->bo : NULL,
3600 bind->pBinds[i].memoryOffset);
3601 }
3602 }
3603
3604 static void
3605 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3606 const VkSparseImageOpaqueMemoryBindInfo *bind)
3607 {
3608 RADV_FROM_HANDLE(radv_image, image, bind->image);
3609
3610 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3611 struct radv_device_memory *mem = NULL;
3612
3613 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3614 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3615
3616 device->ws->buffer_virtual_bind(image->bo,
3617 bind->pBinds[i].resourceOffset,
3618 bind->pBinds[i].size,
3619 mem ? mem->bo : NULL,
3620 bind->pBinds[i].memoryOffset);
3621 }
3622 }
3623
3624 VkResult radv_QueueBindSparse(
3625 VkQueue _queue,
3626 uint32_t bindInfoCount,
3627 const VkBindSparseInfo* pBindInfo,
3628 VkFence _fence)
3629 {
3630 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3631 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3632 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3633 bool fence_emitted = false;
3634 VkResult result;
3635 int ret;
3636
3637 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3638 struct radv_winsys_sem_info sem_info;
3639 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3640 radv_sparse_buffer_bind_memory(queue->device,
3641 pBindInfo[i].pBufferBinds + j);
3642 }
3643
3644 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3645 radv_sparse_image_opaque_bind_memory(queue->device,
3646 pBindInfo[i].pImageOpaqueBinds + j);
3647 }
3648
3649 VkResult result;
3650 result = radv_alloc_sem_info(queue->device->instance,
3651 &sem_info,
3652 pBindInfo[i].waitSemaphoreCount,
3653 pBindInfo[i].pWaitSemaphores,
3654 pBindInfo[i].signalSemaphoreCount,
3655 pBindInfo[i].pSignalSemaphores,
3656 _fence);
3657 if (result != VK_SUCCESS)
3658 return result;
3659
3660 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3661 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3662 &queue->device->empty_cs[queue->queue_family_index],
3663 1, NULL, NULL,
3664 &sem_info, NULL,
3665 false, base_fence);
3666 if (ret) {
3667 radv_loge("failed to submit CS %d\n", i);
3668 abort();
3669 }
3670
3671 fence_emitted = true;
3672 }
3673
3674 radv_free_sem_info(&sem_info);
3675
3676 }
3677
3678 if (fence) {
3679 if (!fence_emitted) {
3680 result = radv_signal_fence(queue, fence);
3681 if (result != VK_SUCCESS)
3682 return result;
3683 }
3684 }
3685
3686 return VK_SUCCESS;
3687 }
3688
3689 VkResult radv_CreateFence(
3690 VkDevice _device,
3691 const VkFenceCreateInfo* pCreateInfo,
3692 const VkAllocationCallbacks* pAllocator,
3693 VkFence* pFence)
3694 {
3695 RADV_FROM_HANDLE(radv_device, device, _device);
3696 const VkExportFenceCreateInfo *export =
3697 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3698 VkExternalFenceHandleTypeFlags handleTypes =
3699 export ? export->handleTypes : 0;
3700
3701 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3702 sizeof(*fence), 8,
3703 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3704
3705 if (!fence)
3706 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3707
3708 fence->fence_wsi = NULL;
3709 fence->temp_syncobj = 0;
3710 if (device->always_use_syncobj || handleTypes) {
3711 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3712 if (ret) {
3713 vk_free2(&device->alloc, pAllocator, fence);
3714 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3715 }
3716 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3717 device->ws->signal_syncobj(device->ws, fence->syncobj);
3718 }
3719 fence->fence = NULL;
3720 } else {
3721 fence->fence = device->ws->create_fence();
3722 if (!fence->fence) {
3723 vk_free2(&device->alloc, pAllocator, fence);
3724 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3725 }
3726 fence->syncobj = 0;
3727 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3728 device->ws->signal_fence(fence->fence);
3729 }
3730
3731 *pFence = radv_fence_to_handle(fence);
3732
3733 return VK_SUCCESS;
3734 }
3735
3736 void radv_DestroyFence(
3737 VkDevice _device,
3738 VkFence _fence,
3739 const VkAllocationCallbacks* pAllocator)
3740 {
3741 RADV_FROM_HANDLE(radv_device, device, _device);
3742 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3743
3744 if (!fence)
3745 return;
3746
3747 if (fence->temp_syncobj)
3748 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3749 if (fence->syncobj)
3750 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3751 if (fence->fence)
3752 device->ws->destroy_fence(fence->fence);
3753 if (fence->fence_wsi)
3754 fence->fence_wsi->destroy(fence->fence_wsi);
3755 vk_free2(&device->alloc, pAllocator, fence);
3756 }
3757
3758
3759 uint64_t radv_get_current_time(void)
3760 {
3761 struct timespec tv;
3762 clock_gettime(CLOCK_MONOTONIC, &tv);
3763 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3764 }
3765
3766 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3767 {
3768 uint64_t current_time = radv_get_current_time();
3769
3770 timeout = MIN2(UINT64_MAX - current_time, timeout);
3771
3772 return current_time + timeout;
3773 }
3774
3775
3776 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3777 uint32_t fenceCount, const VkFence *pFences)
3778 {
3779 for (uint32_t i = 0; i < fenceCount; ++i) {
3780 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3781 if (fence->fence == NULL || fence->syncobj ||
3782 fence->temp_syncobj || fence->fence_wsi ||
3783 (!device->ws->is_fence_waitable(fence->fence)))
3784 return false;
3785 }
3786 return true;
3787 }
3788
3789 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3790 {
3791 for (uint32_t i = 0; i < fenceCount; ++i) {
3792 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3793 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3794 return false;
3795 }
3796 return true;
3797 }
3798
3799 VkResult radv_WaitForFences(
3800 VkDevice _device,
3801 uint32_t fenceCount,
3802 const VkFence* pFences,
3803 VkBool32 waitAll,
3804 uint64_t timeout)
3805 {
3806 RADV_FROM_HANDLE(radv_device, device, _device);
3807 timeout = radv_get_absolute_timeout(timeout);
3808
3809 if (device->always_use_syncobj &&
3810 radv_all_fences_syncobj(fenceCount, pFences))
3811 {
3812 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3813 if (!handles)
3814 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3815
3816 for (uint32_t i = 0; i < fenceCount; ++i) {
3817 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3818 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3819 }
3820
3821 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3822
3823 free(handles);
3824 return success ? VK_SUCCESS : VK_TIMEOUT;
3825 }
3826
3827 if (!waitAll && fenceCount > 1) {
3828 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3829 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3830 uint32_t wait_count = 0;
3831 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3832 if (!fences)
3833 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3834
3835 for (uint32_t i = 0; i < fenceCount; ++i) {
3836 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3837
3838 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3839 free(fences);
3840 return VK_SUCCESS;
3841 }
3842
3843 fences[wait_count++] = fence->fence;
3844 }
3845
3846 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3847 waitAll, timeout - radv_get_current_time());
3848
3849 free(fences);
3850 return success ? VK_SUCCESS : VK_TIMEOUT;
3851 }
3852
3853 while(radv_get_current_time() <= timeout) {
3854 for (uint32_t i = 0; i < fenceCount; ++i) {
3855 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3856 return VK_SUCCESS;
3857 }
3858 }
3859 return VK_TIMEOUT;
3860 }
3861
3862 for (uint32_t i = 0; i < fenceCount; ++i) {
3863 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3864 bool expired = false;
3865
3866 if (fence->temp_syncobj) {
3867 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3868 return VK_TIMEOUT;
3869 continue;
3870 }
3871
3872 if (fence->syncobj) {
3873 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3874 return VK_TIMEOUT;
3875 continue;
3876 }
3877
3878 if (fence->fence) {
3879 if (!device->ws->is_fence_waitable(fence->fence)) {
3880 while(!device->ws->is_fence_waitable(fence->fence) &&
3881 radv_get_current_time() <= timeout)
3882 /* Do nothing */;
3883 }
3884
3885 expired = device->ws->fence_wait(device->ws,
3886 fence->fence,
3887 true, timeout);
3888 if (!expired)
3889 return VK_TIMEOUT;
3890 }
3891
3892 if (fence->fence_wsi) {
3893 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3894 if (result != VK_SUCCESS)
3895 return result;
3896 }
3897 }
3898
3899 return VK_SUCCESS;
3900 }
3901
3902 VkResult radv_ResetFences(VkDevice _device,
3903 uint32_t fenceCount,
3904 const VkFence *pFences)
3905 {
3906 RADV_FROM_HANDLE(radv_device, device, _device);
3907
3908 for (unsigned i = 0; i < fenceCount; ++i) {
3909 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3910 if (fence->fence)
3911 device->ws->reset_fence(fence->fence);
3912
3913 /* Per spec, we first restore the permanent payload, and then reset, so
3914 * having a temp syncobj should not skip resetting the permanent syncobj. */
3915 if (fence->temp_syncobj) {
3916 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3917 fence->temp_syncobj = 0;
3918 }
3919
3920 if (fence->syncobj) {
3921 device->ws->reset_syncobj(device->ws, fence->syncobj);
3922 }
3923 }
3924
3925 return VK_SUCCESS;
3926 }
3927
3928 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3929 {
3930 RADV_FROM_HANDLE(radv_device, device, _device);
3931 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3932
3933 if (fence->temp_syncobj) {
3934 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3935 return success ? VK_SUCCESS : VK_NOT_READY;
3936 }
3937
3938 if (fence->syncobj) {
3939 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3940 return success ? VK_SUCCESS : VK_NOT_READY;
3941 }
3942
3943 if (fence->fence) {
3944 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3945 return VK_NOT_READY;
3946 }
3947 if (fence->fence_wsi) {
3948 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3949
3950 if (result != VK_SUCCESS) {
3951 if (result == VK_TIMEOUT)
3952 return VK_NOT_READY;
3953 return result;
3954 }
3955 }
3956 return VK_SUCCESS;
3957 }
3958
3959
3960 // Queue semaphore functions
3961
3962 VkResult radv_CreateSemaphore(
3963 VkDevice _device,
3964 const VkSemaphoreCreateInfo* pCreateInfo,
3965 const VkAllocationCallbacks* pAllocator,
3966 VkSemaphore* pSemaphore)
3967 {
3968 RADV_FROM_HANDLE(radv_device, device, _device);
3969 const VkExportSemaphoreCreateInfo *export =
3970 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3971 VkExternalSemaphoreHandleTypeFlags handleTypes =
3972 export ? export->handleTypes : 0;
3973
3974 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3975 sizeof(*sem), 8,
3976 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3977 if (!sem)
3978 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3979
3980 sem->temp_syncobj = 0;
3981 /* create a syncobject if we are going to export this semaphore */
3982 if (device->always_use_syncobj || handleTypes) {
3983 assert (device->physical_device->rad_info.has_syncobj);
3984 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3985 if (ret) {
3986 vk_free2(&device->alloc, pAllocator, sem);
3987 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3988 }
3989 sem->sem = NULL;
3990 } else {
3991 sem->sem = device->ws->create_sem(device->ws);
3992 if (!sem->sem) {
3993 vk_free2(&device->alloc, pAllocator, sem);
3994 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3995 }
3996 sem->syncobj = 0;
3997 }
3998
3999 *pSemaphore = radv_semaphore_to_handle(sem);
4000 return VK_SUCCESS;
4001 }
4002
4003 void radv_DestroySemaphore(
4004 VkDevice _device,
4005 VkSemaphore _semaphore,
4006 const VkAllocationCallbacks* pAllocator)
4007 {
4008 RADV_FROM_HANDLE(radv_device, device, _device);
4009 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4010 if (!_semaphore)
4011 return;
4012
4013 if (sem->syncobj)
4014 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4015 else
4016 device->ws->destroy_sem(sem->sem);
4017 vk_free2(&device->alloc, pAllocator, sem);
4018 }
4019
4020 VkResult radv_CreateEvent(
4021 VkDevice _device,
4022 const VkEventCreateInfo* pCreateInfo,
4023 const VkAllocationCallbacks* pAllocator,
4024 VkEvent* pEvent)
4025 {
4026 RADV_FROM_HANDLE(radv_device, device, _device);
4027 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4028 sizeof(*event), 8,
4029 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4030
4031 if (!event)
4032 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4033
4034 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4035 RADEON_DOMAIN_GTT,
4036 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4037 RADV_BO_PRIORITY_FENCE);
4038 if (!event->bo) {
4039 vk_free2(&device->alloc, pAllocator, event);
4040 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4041 }
4042
4043 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4044
4045 *pEvent = radv_event_to_handle(event);
4046
4047 return VK_SUCCESS;
4048 }
4049
4050 void radv_DestroyEvent(
4051 VkDevice _device,
4052 VkEvent _event,
4053 const VkAllocationCallbacks* pAllocator)
4054 {
4055 RADV_FROM_HANDLE(radv_device, device, _device);
4056 RADV_FROM_HANDLE(radv_event, event, _event);
4057
4058 if (!event)
4059 return;
4060 device->ws->buffer_destroy(event->bo);
4061 vk_free2(&device->alloc, pAllocator, event);
4062 }
4063
4064 VkResult radv_GetEventStatus(
4065 VkDevice _device,
4066 VkEvent _event)
4067 {
4068 RADV_FROM_HANDLE(radv_event, event, _event);
4069
4070 if (*event->map == 1)
4071 return VK_EVENT_SET;
4072 return VK_EVENT_RESET;
4073 }
4074
4075 VkResult radv_SetEvent(
4076 VkDevice _device,
4077 VkEvent _event)
4078 {
4079 RADV_FROM_HANDLE(radv_event, event, _event);
4080 *event->map = 1;
4081
4082 return VK_SUCCESS;
4083 }
4084
4085 VkResult radv_ResetEvent(
4086 VkDevice _device,
4087 VkEvent _event)
4088 {
4089 RADV_FROM_HANDLE(radv_event, event, _event);
4090 *event->map = 0;
4091
4092 return VK_SUCCESS;
4093 }
4094
4095 VkResult radv_CreateBuffer(
4096 VkDevice _device,
4097 const VkBufferCreateInfo* pCreateInfo,
4098 const VkAllocationCallbacks* pAllocator,
4099 VkBuffer* pBuffer)
4100 {
4101 RADV_FROM_HANDLE(radv_device, device, _device);
4102 struct radv_buffer *buffer;
4103
4104 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4105
4106 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4107 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4108 if (buffer == NULL)
4109 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4110
4111 buffer->size = pCreateInfo->size;
4112 buffer->usage = pCreateInfo->usage;
4113 buffer->bo = NULL;
4114 buffer->offset = 0;
4115 buffer->flags = pCreateInfo->flags;
4116
4117 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4118 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4119
4120 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4121 buffer->bo = device->ws->buffer_create(device->ws,
4122 align64(buffer->size, 4096),
4123 4096, 0, RADEON_FLAG_VIRTUAL,
4124 RADV_BO_PRIORITY_VIRTUAL);
4125 if (!buffer->bo) {
4126 vk_free2(&device->alloc, pAllocator, buffer);
4127 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4128 }
4129 }
4130
4131 *pBuffer = radv_buffer_to_handle(buffer);
4132
4133 return VK_SUCCESS;
4134 }
4135
4136 void radv_DestroyBuffer(
4137 VkDevice _device,
4138 VkBuffer _buffer,
4139 const VkAllocationCallbacks* pAllocator)
4140 {
4141 RADV_FROM_HANDLE(radv_device, device, _device);
4142 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4143
4144 if (!buffer)
4145 return;
4146
4147 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4148 device->ws->buffer_destroy(buffer->bo);
4149
4150 vk_free2(&device->alloc, pAllocator, buffer);
4151 }
4152
4153 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4154 VkDevice device,
4155 const VkBufferDeviceAddressInfoEXT* pInfo)
4156 {
4157 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4158 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4159 }
4160
4161
4162 static inline unsigned
4163 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4164 {
4165 if (stencil)
4166 return plane->surface.u.legacy.stencil_tiling_index[level];
4167 else
4168 return plane->surface.u.legacy.tiling_index[level];
4169 }
4170
4171 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4172 {
4173 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4174 }
4175
4176 static uint32_t
4177 radv_init_dcc_control_reg(struct radv_device *device,
4178 struct radv_image_view *iview)
4179 {
4180 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4181 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4182 unsigned max_compressed_block_size;
4183 unsigned independent_64b_blocks;
4184
4185 if (!radv_image_has_dcc(iview->image))
4186 return 0;
4187
4188 if (iview->image->info.samples > 1) {
4189 if (iview->image->planes[0].surface.bpe == 1)
4190 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4191 else if (iview->image->planes[0].surface.bpe == 2)
4192 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4193 }
4194
4195 if (!device->physical_device->rad_info.has_dedicated_vram) {
4196 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4197 * dGPU and 64 for APU because all of our APUs to date use
4198 * DIMMs which have a request granularity size of 64B while all
4199 * other chips have a 32B request size.
4200 */
4201 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4202 }
4203
4204 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4205 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4206 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4207 /* If this DCC image is potentially going to be used in texture
4208 * fetches, we need some special settings.
4209 */
4210 independent_64b_blocks = 1;
4211 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4212 } else {
4213 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4214 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4215 * big as possible for better compression state.
4216 */
4217 independent_64b_blocks = 0;
4218 max_compressed_block_size = max_uncompressed_block_size;
4219 }
4220
4221 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4222 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4223 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4224 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4225 }
4226
4227 static void
4228 radv_initialise_color_surface(struct radv_device *device,
4229 struct radv_color_buffer_info *cb,
4230 struct radv_image_view *iview)
4231 {
4232 const struct vk_format_description *desc;
4233 unsigned ntype, format, swap, endian;
4234 unsigned blend_clamp = 0, blend_bypass = 0;
4235 uint64_t va;
4236 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4237 const struct radeon_surf *surf = &plane->surface;
4238
4239 desc = vk_format_description(iview->vk_format);
4240
4241 memset(cb, 0, sizeof(*cb));
4242
4243 /* Intensity is implemented as Red, so treat it that way. */
4244 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4245
4246 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4247
4248 cb->cb_color_base = va >> 8;
4249
4250 if (device->physical_device->rad_info.chip_class >= GFX9) {
4251 struct gfx9_surf_meta_flags meta;
4252 if (iview->image->dcc_offset)
4253 meta = surf->u.gfx9.dcc;
4254 else
4255 meta = surf->u.gfx9.cmask;
4256
4257 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4258 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4259 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4260 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4261
4262 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4263 cb->cb_color_base |= surf->tile_swizzle;
4264
4265 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4266 } else {
4267 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4268 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4269
4270 cb->cb_color_base += level_info->offset >> 8;
4271 if (level_info->mode == RADEON_SURF_MODE_2D)
4272 cb->cb_color_base |= surf->tile_swizzle;
4273
4274 pitch_tile_max = level_info->nblk_x / 8 - 1;
4275 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4276 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4277
4278 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4279 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4280 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4281
4282 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4283
4284 if (radv_image_has_fmask(iview->image)) {
4285 if (device->physical_device->rad_info.chip_class >= GFX7)
4286 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4287 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4288 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4289 } else {
4290 /* This must be set for fast clear to work without FMASK. */
4291 if (device->physical_device->rad_info.chip_class >= GFX7)
4292 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4293 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4294 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4295 }
4296 }
4297
4298 /* CMASK variables */
4299 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4300 va += iview->image->cmask.offset;
4301 cb->cb_color_cmask = va >> 8;
4302
4303 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4304 va += iview->image->dcc_offset;
4305 cb->cb_dcc_base = va >> 8;
4306 cb->cb_dcc_base |= surf->tile_swizzle;
4307
4308 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4309 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4310 S_028C6C_SLICE_MAX(max_slice);
4311
4312 if (iview->image->info.samples > 1) {
4313 unsigned log_samples = util_logbase2(iview->image->info.samples);
4314
4315 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4316 S_028C74_NUM_FRAGMENTS(log_samples);
4317 }
4318
4319 if (radv_image_has_fmask(iview->image)) {
4320 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4321 cb->cb_color_fmask = va >> 8;
4322 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4323 } else {
4324 cb->cb_color_fmask = cb->cb_color_base;
4325 }
4326
4327 ntype = radv_translate_color_numformat(iview->vk_format,
4328 desc,
4329 vk_format_get_first_non_void_channel(iview->vk_format));
4330 format = radv_translate_colorformat(iview->vk_format);
4331 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4332 radv_finishme("Illegal color\n");
4333 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4334 endian = radv_colorformat_endian_swap(format);
4335
4336 /* blend clamp should be set for all NORM/SRGB types */
4337 if (ntype == V_028C70_NUMBER_UNORM ||
4338 ntype == V_028C70_NUMBER_SNORM ||
4339 ntype == V_028C70_NUMBER_SRGB)
4340 blend_clamp = 1;
4341
4342 /* set blend bypass according to docs if SINT/UINT or
4343 8/24 COLOR variants */
4344 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4345 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4346 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4347 blend_clamp = 0;
4348 blend_bypass = 1;
4349 }
4350 #if 0
4351 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4352 (format == V_028C70_COLOR_8 ||
4353 format == V_028C70_COLOR_8_8 ||
4354 format == V_028C70_COLOR_8_8_8_8))
4355 ->color_is_int8 = true;
4356 #endif
4357 cb->cb_color_info = S_028C70_FORMAT(format) |
4358 S_028C70_COMP_SWAP(swap) |
4359 S_028C70_BLEND_CLAMP(blend_clamp) |
4360 S_028C70_BLEND_BYPASS(blend_bypass) |
4361 S_028C70_SIMPLE_FLOAT(1) |
4362 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4363 ntype != V_028C70_NUMBER_SNORM &&
4364 ntype != V_028C70_NUMBER_SRGB &&
4365 format != V_028C70_COLOR_8_24 &&
4366 format != V_028C70_COLOR_24_8) |
4367 S_028C70_NUMBER_TYPE(ntype) |
4368 S_028C70_ENDIAN(endian);
4369 if (radv_image_has_fmask(iview->image)) {
4370 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4371 if (device->physical_device->rad_info.chip_class == GFX6) {
4372 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4373 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4374 }
4375 }
4376
4377 if (radv_image_has_cmask(iview->image) &&
4378 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4379 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4380
4381 if (radv_dcc_enabled(iview->image, iview->base_mip))
4382 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4383
4384 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4385
4386 /* This must be set for fast clear to work without FMASK. */
4387 if (!radv_image_has_fmask(iview->image) &&
4388 device->physical_device->rad_info.chip_class == GFX6) {
4389 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4390 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4391 }
4392
4393 if (device->physical_device->rad_info.chip_class >= GFX9) {
4394 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4395
4396 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4397 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4398 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4399 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4400
4401 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4402 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4403 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4404 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4405 S_028C68_MIP0_HEIGHT(height - 1) |
4406 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4407 }
4408 }
4409
4410 static unsigned
4411 radv_calc_decompress_on_z_planes(struct radv_device *device,
4412 struct radv_image_view *iview)
4413 {
4414 unsigned max_zplanes = 0;
4415
4416 assert(radv_image_is_tc_compat_htile(iview->image));
4417
4418 if (device->physical_device->rad_info.chip_class >= GFX9) {
4419 /* Default value for 32-bit depth surfaces. */
4420 max_zplanes = 4;
4421
4422 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4423 iview->image->info.samples > 1)
4424 max_zplanes = 2;
4425
4426 max_zplanes = max_zplanes + 1;
4427 } else {
4428 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4429 /* Do not enable Z plane compression for 16-bit depth
4430 * surfaces because isn't supported on GFX8. Only
4431 * 32-bit depth surfaces are supported by the hardware.
4432 * This allows to maintain shader compatibility and to
4433 * reduce the number of depth decompressions.
4434 */
4435 max_zplanes = 1;
4436 } else {
4437 if (iview->image->info.samples <= 1)
4438 max_zplanes = 5;
4439 else if (iview->image->info.samples <= 4)
4440 max_zplanes = 3;
4441 else
4442 max_zplanes = 2;
4443 }
4444 }
4445
4446 return max_zplanes;
4447 }
4448
4449 static void
4450 radv_initialise_ds_surface(struct radv_device *device,
4451 struct radv_ds_buffer_info *ds,
4452 struct radv_image_view *iview)
4453 {
4454 unsigned level = iview->base_mip;
4455 unsigned format, stencil_format;
4456 uint64_t va, s_offs, z_offs;
4457 bool stencil_only = false;
4458 const struct radv_image_plane *plane = &iview->image->planes[0];
4459 const struct radeon_surf *surf = &plane->surface;
4460
4461 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4462
4463 memset(ds, 0, sizeof(*ds));
4464 switch (iview->image->vk_format) {
4465 case VK_FORMAT_D24_UNORM_S8_UINT:
4466 case VK_FORMAT_X8_D24_UNORM_PACK32:
4467 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4468 ds->offset_scale = 2.0f;
4469 break;
4470 case VK_FORMAT_D16_UNORM:
4471 case VK_FORMAT_D16_UNORM_S8_UINT:
4472 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4473 ds->offset_scale = 4.0f;
4474 break;
4475 case VK_FORMAT_D32_SFLOAT:
4476 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4477 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4478 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4479 ds->offset_scale = 1.0f;
4480 break;
4481 case VK_FORMAT_S8_UINT:
4482 stencil_only = true;
4483 break;
4484 default:
4485 break;
4486 }
4487
4488 format = radv_translate_dbformat(iview->image->vk_format);
4489 stencil_format = surf->has_stencil ?
4490 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4491
4492 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4493 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4494 S_028008_SLICE_MAX(max_slice);
4495
4496 ds->db_htile_data_base = 0;
4497 ds->db_htile_surface = 0;
4498
4499 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4500 s_offs = z_offs = va;
4501
4502 if (device->physical_device->rad_info.chip_class >= GFX9) {
4503 assert(surf->u.gfx9.surf_offset == 0);
4504 s_offs += surf->u.gfx9.stencil_offset;
4505
4506 ds->db_z_info = S_028038_FORMAT(format) |
4507 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4508 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4509 S_028038_MAXMIP(iview->image->info.levels - 1) |
4510 S_028038_ZRANGE_PRECISION(1);
4511 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4512 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4513
4514 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4515 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4516 ds->db_depth_view |= S_028008_MIPID(level);
4517
4518 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4519 S_02801C_Y_MAX(iview->image->info.height - 1);
4520
4521 if (radv_htile_enabled(iview->image, level)) {
4522 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4523
4524 if (radv_image_is_tc_compat_htile(iview->image)) {
4525 unsigned max_zplanes =
4526 radv_calc_decompress_on_z_planes(device, iview);
4527
4528 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4529 S_028038_ITERATE_FLUSH(1);
4530 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4531 }
4532
4533 if (!surf->has_stencil)
4534 /* Use all of the htile_buffer for depth if there's no stencil. */
4535 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4536 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4537 iview->image->htile_offset;
4538 ds->db_htile_data_base = va >> 8;
4539 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4540 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4541 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4542 }
4543 } else {
4544 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4545
4546 if (stencil_only)
4547 level_info = &surf->u.legacy.stencil_level[level];
4548
4549 z_offs += surf->u.legacy.level[level].offset;
4550 s_offs += surf->u.legacy.stencil_level[level].offset;
4551
4552 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4553 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4554 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4555
4556 if (iview->image->info.samples > 1)
4557 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4558
4559 if (device->physical_device->rad_info.chip_class >= GFX7) {
4560 struct radeon_info *info = &device->physical_device->rad_info;
4561 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4562 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4563 unsigned macro_index = surf->u.legacy.macro_tile_index;
4564 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4565 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4566 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4567
4568 if (stencil_only)
4569 tile_mode = stencil_tile_mode;
4570
4571 ds->db_depth_info |=
4572 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4573 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4574 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4575 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4576 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4577 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4578 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4579 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4580 } else {
4581 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4582 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4583 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4584 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4585 if (stencil_only)
4586 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4587 }
4588
4589 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4590 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4591 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4592
4593 if (radv_htile_enabled(iview->image, level)) {
4594 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4595
4596 if (!surf->has_stencil &&
4597 !radv_image_is_tc_compat_htile(iview->image))
4598 /* Use all of the htile_buffer for depth if there's no stencil. */
4599 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4600
4601 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4602 iview->image->htile_offset;
4603 ds->db_htile_data_base = va >> 8;
4604 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4605
4606 if (radv_image_is_tc_compat_htile(iview->image)) {
4607 unsigned max_zplanes =
4608 radv_calc_decompress_on_z_planes(device, iview);
4609
4610 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4611 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4612 }
4613 }
4614 }
4615
4616 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4617 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4618 }
4619
4620 VkResult radv_CreateFramebuffer(
4621 VkDevice _device,
4622 const VkFramebufferCreateInfo* pCreateInfo,
4623 const VkAllocationCallbacks* pAllocator,
4624 VkFramebuffer* pFramebuffer)
4625 {
4626 RADV_FROM_HANDLE(radv_device, device, _device);
4627 struct radv_framebuffer *framebuffer;
4628
4629 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4630
4631 size_t size = sizeof(*framebuffer) +
4632 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4633 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4634 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4635 if (framebuffer == NULL)
4636 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4637
4638 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4639 framebuffer->width = pCreateInfo->width;
4640 framebuffer->height = pCreateInfo->height;
4641 framebuffer->layers = pCreateInfo->layers;
4642 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4643 VkImageView _iview = pCreateInfo->pAttachments[i];
4644 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4645 framebuffer->attachments[i].attachment = iview;
4646 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4647 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4648 } else {
4649 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4650 }
4651 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4652 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4653 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4654 }
4655
4656 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4657 return VK_SUCCESS;
4658 }
4659
4660 void radv_DestroyFramebuffer(
4661 VkDevice _device,
4662 VkFramebuffer _fb,
4663 const VkAllocationCallbacks* pAllocator)
4664 {
4665 RADV_FROM_HANDLE(radv_device, device, _device);
4666 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4667
4668 if (!fb)
4669 return;
4670 vk_free2(&device->alloc, pAllocator, fb);
4671 }
4672
4673 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4674 {
4675 switch (address_mode) {
4676 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4677 return V_008F30_SQ_TEX_WRAP;
4678 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4679 return V_008F30_SQ_TEX_MIRROR;
4680 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4681 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4682 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4683 return V_008F30_SQ_TEX_CLAMP_BORDER;
4684 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4685 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4686 default:
4687 unreachable("illegal tex wrap mode");
4688 break;
4689 }
4690 }
4691
4692 static unsigned
4693 radv_tex_compare(VkCompareOp op)
4694 {
4695 switch (op) {
4696 case VK_COMPARE_OP_NEVER:
4697 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4698 case VK_COMPARE_OP_LESS:
4699 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4700 case VK_COMPARE_OP_EQUAL:
4701 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4702 case VK_COMPARE_OP_LESS_OR_EQUAL:
4703 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4704 case VK_COMPARE_OP_GREATER:
4705 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4706 case VK_COMPARE_OP_NOT_EQUAL:
4707 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4708 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4709 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4710 case VK_COMPARE_OP_ALWAYS:
4711 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4712 default:
4713 unreachable("illegal compare mode");
4714 break;
4715 }
4716 }
4717
4718 static unsigned
4719 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4720 {
4721 switch (filter) {
4722 case VK_FILTER_NEAREST:
4723 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4724 V_008F38_SQ_TEX_XY_FILTER_POINT);
4725 case VK_FILTER_LINEAR:
4726 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4727 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4728 case VK_FILTER_CUBIC_IMG:
4729 default:
4730 fprintf(stderr, "illegal texture filter");
4731 return 0;
4732 }
4733 }
4734
4735 static unsigned
4736 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4737 {
4738 switch (mode) {
4739 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4740 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4741 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4742 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4743 default:
4744 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4745 }
4746 }
4747
4748 static unsigned
4749 radv_tex_bordercolor(VkBorderColor bcolor)
4750 {
4751 switch (bcolor) {
4752 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4753 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4754 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4755 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4756 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4757 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4758 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4759 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4760 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4761 default:
4762 break;
4763 }
4764 return 0;
4765 }
4766
4767 static unsigned
4768 radv_tex_aniso_filter(unsigned filter)
4769 {
4770 if (filter < 2)
4771 return 0;
4772 if (filter < 4)
4773 return 1;
4774 if (filter < 8)
4775 return 2;
4776 if (filter < 16)
4777 return 3;
4778 return 4;
4779 }
4780
4781 static unsigned
4782 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4783 {
4784 switch (mode) {
4785 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4786 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4787 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4788 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4789 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4790 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4791 default:
4792 break;
4793 }
4794 return 0;
4795 }
4796
4797 static uint32_t
4798 radv_get_max_anisotropy(struct radv_device *device,
4799 const VkSamplerCreateInfo *pCreateInfo)
4800 {
4801 if (device->force_aniso >= 0)
4802 return device->force_aniso;
4803
4804 if (pCreateInfo->anisotropyEnable &&
4805 pCreateInfo->maxAnisotropy > 1.0f)
4806 return (uint32_t)pCreateInfo->maxAnisotropy;
4807
4808 return 0;
4809 }
4810
4811 static void
4812 radv_init_sampler(struct radv_device *device,
4813 struct radv_sampler *sampler,
4814 const VkSamplerCreateInfo *pCreateInfo)
4815 {
4816 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4817 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4818 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4819 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4820
4821 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4822 vk_find_struct_const(pCreateInfo->pNext,
4823 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4824 if (sampler_reduction)
4825 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4826
4827 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4828 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4829 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4830 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4831 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4832 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4833 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4834 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4835 S_008F30_DISABLE_CUBE_WRAP(0) |
4836 S_008F30_COMPAT_MODE(is_vi) |
4837 S_008F30_FILTER_MODE(filter_mode));
4838 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4839 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4840 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4841 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4842 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4843 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4844 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4845 S_008F38_MIP_POINT_PRECLAMP(0) |
4846 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4847 S_008F38_FILTER_PREC_FIX(1) |
4848 S_008F38_ANISO_OVERRIDE(is_vi));
4849 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4850 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4851 }
4852
4853 VkResult radv_CreateSampler(
4854 VkDevice _device,
4855 const VkSamplerCreateInfo* pCreateInfo,
4856 const VkAllocationCallbacks* pAllocator,
4857 VkSampler* pSampler)
4858 {
4859 RADV_FROM_HANDLE(radv_device, device, _device);
4860 struct radv_sampler *sampler;
4861
4862 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4863 vk_find_struct_const(pCreateInfo->pNext,
4864 SAMPLER_YCBCR_CONVERSION_INFO);
4865
4866 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4867
4868 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4869 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4870 if (!sampler)
4871 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4872
4873 radv_init_sampler(device, sampler, pCreateInfo);
4874
4875 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4876 *pSampler = radv_sampler_to_handle(sampler);
4877
4878 return VK_SUCCESS;
4879 }
4880
4881 void radv_DestroySampler(
4882 VkDevice _device,
4883 VkSampler _sampler,
4884 const VkAllocationCallbacks* pAllocator)
4885 {
4886 RADV_FROM_HANDLE(radv_device, device, _device);
4887 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4888
4889 if (!sampler)
4890 return;
4891 vk_free2(&device->alloc, pAllocator, sampler);
4892 }
4893
4894 /* vk_icd.h does not declare this function, so we declare it here to
4895 * suppress Wmissing-prototypes.
4896 */
4897 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4898 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4899
4900 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4901 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4902 {
4903 /* For the full details on loader interface versioning, see
4904 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4905 * What follows is a condensed summary, to help you navigate the large and
4906 * confusing official doc.
4907 *
4908 * - Loader interface v0 is incompatible with later versions. We don't
4909 * support it.
4910 *
4911 * - In loader interface v1:
4912 * - The first ICD entrypoint called by the loader is
4913 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4914 * entrypoint.
4915 * - The ICD must statically expose no other Vulkan symbol unless it is
4916 * linked with -Bsymbolic.
4917 * - Each dispatchable Vulkan handle created by the ICD must be
4918 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4919 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4920 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4921 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4922 * such loader-managed surfaces.
4923 *
4924 * - Loader interface v2 differs from v1 in:
4925 * - The first ICD entrypoint called by the loader is
4926 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4927 * statically expose this entrypoint.
4928 *
4929 * - Loader interface v3 differs from v2 in:
4930 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4931 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4932 * because the loader no longer does so.
4933 */
4934 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4935 return VK_SUCCESS;
4936 }
4937
4938 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4939 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4940 int *pFD)
4941 {
4942 RADV_FROM_HANDLE(radv_device, device, _device);
4943 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4944
4945 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4946
4947 /* At the moment, we support only the below handle types. */
4948 assert(pGetFdInfo->handleType ==
4949 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4950 pGetFdInfo->handleType ==
4951 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4952
4953 bool ret = radv_get_memory_fd(device, memory, pFD);
4954 if (ret == false)
4955 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4956 return VK_SUCCESS;
4957 }
4958
4959 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4960 VkExternalMemoryHandleTypeFlagBits handleType,
4961 int fd,
4962 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4963 {
4964 RADV_FROM_HANDLE(radv_device, device, _device);
4965
4966 switch (handleType) {
4967 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4968 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4969 return VK_SUCCESS;
4970
4971 default:
4972 /* The valid usage section for this function says:
4973 *
4974 * "handleType must not be one of the handle types defined as
4975 * opaque."
4976 *
4977 * So opaque handle types fall into the default "unsupported" case.
4978 */
4979 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4980 }
4981 }
4982
4983 static VkResult radv_import_opaque_fd(struct radv_device *device,
4984 int fd,
4985 uint32_t *syncobj)
4986 {
4987 uint32_t syncobj_handle = 0;
4988 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4989 if (ret != 0)
4990 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4991
4992 if (*syncobj)
4993 device->ws->destroy_syncobj(device->ws, *syncobj);
4994
4995 *syncobj = syncobj_handle;
4996 close(fd);
4997
4998 return VK_SUCCESS;
4999 }
5000
5001 static VkResult radv_import_sync_fd(struct radv_device *device,
5002 int fd,
5003 uint32_t *syncobj)
5004 {
5005 /* If we create a syncobj we do it locally so that if we have an error, we don't
5006 * leave a syncobj in an undetermined state in the fence. */
5007 uint32_t syncobj_handle = *syncobj;
5008 if (!syncobj_handle) {
5009 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5010 if (ret) {
5011 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5012 }
5013 }
5014
5015 if (fd == -1) {
5016 device->ws->signal_syncobj(device->ws, syncobj_handle);
5017 } else {
5018 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5019 if (ret != 0)
5020 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5021 }
5022
5023 *syncobj = syncobj_handle;
5024 if (fd != -1)
5025 close(fd);
5026
5027 return VK_SUCCESS;
5028 }
5029
5030 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5031 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5032 {
5033 RADV_FROM_HANDLE(radv_device, device, _device);
5034 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5035 uint32_t *syncobj_dst = NULL;
5036
5037 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5038 syncobj_dst = &sem->temp_syncobj;
5039 } else {
5040 syncobj_dst = &sem->syncobj;
5041 }
5042
5043 switch(pImportSemaphoreFdInfo->handleType) {
5044 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5045 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5046 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5047 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5048 default:
5049 unreachable("Unhandled semaphore handle type");
5050 }
5051 }
5052
5053 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5054 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5055 int *pFd)
5056 {
5057 RADV_FROM_HANDLE(radv_device, device, _device);
5058 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5059 int ret;
5060 uint32_t syncobj_handle;
5061
5062 if (sem->temp_syncobj)
5063 syncobj_handle = sem->temp_syncobj;
5064 else
5065 syncobj_handle = sem->syncobj;
5066
5067 switch(pGetFdInfo->handleType) {
5068 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5069 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5070 break;
5071 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5072 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5073 if (!ret) {
5074 if (sem->temp_syncobj) {
5075 close (sem->temp_syncobj);
5076 sem->temp_syncobj = 0;
5077 } else {
5078 device->ws->reset_syncobj(device->ws, syncobj_handle);
5079 }
5080 }
5081 break;
5082 default:
5083 unreachable("Unhandled semaphore handle type");
5084 }
5085
5086 if (ret)
5087 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5088 return VK_SUCCESS;
5089 }
5090
5091 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5092 VkPhysicalDevice physicalDevice,
5093 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5094 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5095 {
5096 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5097
5098 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5099 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5100 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5101 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5102 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5103 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5104 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5105 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5106 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5107 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5108 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5109 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5110 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5111 } else {
5112 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5113 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5114 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5115 }
5116 }
5117
5118 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5119 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5120 {
5121 RADV_FROM_HANDLE(radv_device, device, _device);
5122 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5123 uint32_t *syncobj_dst = NULL;
5124
5125
5126 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5127 syncobj_dst = &fence->temp_syncobj;
5128 } else {
5129 syncobj_dst = &fence->syncobj;
5130 }
5131
5132 switch(pImportFenceFdInfo->handleType) {
5133 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5134 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5135 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5136 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5137 default:
5138 unreachable("Unhandled fence handle type");
5139 }
5140 }
5141
5142 VkResult radv_GetFenceFdKHR(VkDevice _device,
5143 const VkFenceGetFdInfoKHR *pGetFdInfo,
5144 int *pFd)
5145 {
5146 RADV_FROM_HANDLE(radv_device, device, _device);
5147 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5148 int ret;
5149 uint32_t syncobj_handle;
5150
5151 if (fence->temp_syncobj)
5152 syncobj_handle = fence->temp_syncobj;
5153 else
5154 syncobj_handle = fence->syncobj;
5155
5156 switch(pGetFdInfo->handleType) {
5157 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5158 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5159 break;
5160 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5161 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5162 if (!ret) {
5163 if (fence->temp_syncobj) {
5164 close (fence->temp_syncobj);
5165 fence->temp_syncobj = 0;
5166 } else {
5167 device->ws->reset_syncobj(device->ws, syncobj_handle);
5168 }
5169 }
5170 break;
5171 default:
5172 unreachable("Unhandled fence handle type");
5173 }
5174
5175 if (ret)
5176 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5177 return VK_SUCCESS;
5178 }
5179
5180 void radv_GetPhysicalDeviceExternalFenceProperties(
5181 VkPhysicalDevice physicalDevice,
5182 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5183 VkExternalFenceProperties *pExternalFenceProperties)
5184 {
5185 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5186
5187 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5188 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5189 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5190 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5191 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5192 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5193 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5194 } else {
5195 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5196 pExternalFenceProperties->compatibleHandleTypes = 0;
5197 pExternalFenceProperties->externalFenceFeatures = 0;
5198 }
5199 }
5200
5201 VkResult
5202 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5203 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5204 const VkAllocationCallbacks* pAllocator,
5205 VkDebugReportCallbackEXT* pCallback)
5206 {
5207 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5208 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5209 pCreateInfo, pAllocator, &instance->alloc,
5210 pCallback);
5211 }
5212
5213 void
5214 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5215 VkDebugReportCallbackEXT _callback,
5216 const VkAllocationCallbacks* pAllocator)
5217 {
5218 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5219 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5220 _callback, pAllocator, &instance->alloc);
5221 }
5222
5223 void
5224 radv_DebugReportMessageEXT(VkInstance _instance,
5225 VkDebugReportFlagsEXT flags,
5226 VkDebugReportObjectTypeEXT objectType,
5227 uint64_t object,
5228 size_t location,
5229 int32_t messageCode,
5230 const char* pLayerPrefix,
5231 const char* pMessage)
5232 {
5233 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5234 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5235 object, location, messageCode, pLayerPrefix, pMessage);
5236 }
5237
5238 void
5239 radv_GetDeviceGroupPeerMemoryFeatures(
5240 VkDevice device,
5241 uint32_t heapIndex,
5242 uint32_t localDeviceIndex,
5243 uint32_t remoteDeviceIndex,
5244 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5245 {
5246 assert(localDeviceIndex == remoteDeviceIndex);
5247
5248 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5249 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5250 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5251 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5252 }
5253
5254 static const VkTimeDomainEXT radv_time_domains[] = {
5255 VK_TIME_DOMAIN_DEVICE_EXT,
5256 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5257 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5258 };
5259
5260 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5261 VkPhysicalDevice physicalDevice,
5262 uint32_t *pTimeDomainCount,
5263 VkTimeDomainEXT *pTimeDomains)
5264 {
5265 int d;
5266 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5267
5268 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5269 vk_outarray_append(&out, i) {
5270 *i = radv_time_domains[d];
5271 }
5272 }
5273
5274 return vk_outarray_status(&out);
5275 }
5276
5277 static uint64_t
5278 radv_clock_gettime(clockid_t clock_id)
5279 {
5280 struct timespec current;
5281 int ret;
5282
5283 ret = clock_gettime(clock_id, &current);
5284 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5285 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5286 if (ret < 0)
5287 return 0;
5288
5289 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5290 }
5291
5292 VkResult radv_GetCalibratedTimestampsEXT(
5293 VkDevice _device,
5294 uint32_t timestampCount,
5295 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5296 uint64_t *pTimestamps,
5297 uint64_t *pMaxDeviation)
5298 {
5299 RADV_FROM_HANDLE(radv_device, device, _device);
5300 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5301 int d;
5302 uint64_t begin, end;
5303 uint64_t max_clock_period = 0;
5304
5305 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5306
5307 for (d = 0; d < timestampCount; d++) {
5308 switch (pTimestampInfos[d].timeDomain) {
5309 case VK_TIME_DOMAIN_DEVICE_EXT:
5310 pTimestamps[d] = device->ws->query_value(device->ws,
5311 RADEON_TIMESTAMP);
5312 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5313 max_clock_period = MAX2(max_clock_period, device_period);
5314 break;
5315 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5316 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5317 max_clock_period = MAX2(max_clock_period, 1);
5318 break;
5319
5320 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5321 pTimestamps[d] = begin;
5322 break;
5323 default:
5324 pTimestamps[d] = 0;
5325 break;
5326 }
5327 }
5328
5329 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5330
5331 /*
5332 * The maximum deviation is the sum of the interval over which we
5333 * perform the sampling and the maximum period of any sampled
5334 * clock. That's because the maximum skew between any two sampled
5335 * clock edges is when the sampled clock with the largest period is
5336 * sampled at the end of that period but right at the beginning of the
5337 * sampling interval and some other clock is sampled right at the
5338 * begining of its sampling period and right at the end of the
5339 * sampling interval. Let's assume the GPU has the longest clock
5340 * period and that the application is sampling GPU and monotonic:
5341 *
5342 * s e
5343 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5344 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5345 *
5346 * g
5347 * 0 1 2 3
5348 * GPU -----_____-----_____-----_____-----_____
5349 *
5350 * m
5351 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5352 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5353 *
5354 * Interval <----------------->
5355 * Deviation <-------------------------->
5356 *
5357 * s = read(raw) 2
5358 * g = read(GPU) 1
5359 * m = read(monotonic) 2
5360 * e = read(raw) b
5361 *
5362 * We round the sample interval up by one tick to cover sampling error
5363 * in the interval clock
5364 */
5365
5366 uint64_t sample_interval = end - begin + 1;
5367
5368 *pMaxDeviation = sample_interval + max_clock_period;
5369
5370 return VK_SUCCESS;
5371 }