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vulkan: Add KHR_display extension using DRM [v10]
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 device->master_fd = master_fd;
278 device->local_fd = fd;
279 device->ws->query_info(device->ws, &device->rad_info);
280
281 radv_handle_env_var_force_family(device);
282
283 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
284
285 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
286 device->ws->destroy(device->ws);
287 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
288 "cannot generate UUID");
289 goto fail;
290 }
291
292 /* These flags affect shader compilation. */
293 uint64_t shader_env_flags =
294 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
295 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
296
297 /* The gpu id is already embedded in the uuid so we just pass "radv"
298 * when creating the cache.
299 */
300 char buf[VK_UUID_SIZE * 2 + 1];
301 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
302 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
303
304 if (device->rad_info.chip_class < VI ||
305 device->rad_info.chip_class > GFX9)
306 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
307
308 radv_get_driver_uuid(&device->device_uuid);
309 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
310
311 if (device->rad_info.family == CHIP_STONEY ||
312 device->rad_info.chip_class >= GFX9) {
313 device->has_rbplus = true;
314 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
315 device->rad_info.family == CHIP_VEGA12 ||
316 device->rad_info.family == CHIP_RAVEN;
317 }
318
319 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
320 * on SI.
321 */
322 device->has_clear_state = device->rad_info.chip_class >= CIK;
323
324 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
325
326 /* Vega10/Raven need a special workaround for a hardware bug. */
327 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
328 device->rad_info.family == CHIP_RAVEN;
329
330 /* Out-of-order primitive rasterization. */
331 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
332 device->rad_info.max_se >= 2;
333 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
334 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
335
336 device->dcc_msaa_allowed =
337 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
338
339 radv_physical_device_init_mem_types(device);
340 radv_fill_device_extension_table(device, &device->supported_extensions);
341
342 result = radv_init_wsi(device);
343 if (result != VK_SUCCESS) {
344 device->ws->destroy(device->ws);
345 vk_error(instance, result);
346 goto fail;
347 }
348
349 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
350 ac_print_gpu_info(&device->rad_info);
351
352 return VK_SUCCESS;
353
354 fail:
355 close(fd);
356 if (master_fd != -1)
357 close(master_fd);
358 return result;
359 }
360
361 static void
362 radv_physical_device_finish(struct radv_physical_device *device)
363 {
364 radv_finish_wsi(device);
365 device->ws->destroy(device->ws);
366 disk_cache_destroy(device->disk_cache);
367 close(device->local_fd);
368 if (device->master_fd != -1)
369 close(device->master_fd);
370 }
371
372 static void *
373 default_alloc_func(void *pUserData, size_t size, size_t align,
374 VkSystemAllocationScope allocationScope)
375 {
376 return malloc(size);
377 }
378
379 static void *
380 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
381 size_t align, VkSystemAllocationScope allocationScope)
382 {
383 return realloc(pOriginal, size);
384 }
385
386 static void
387 default_free_func(void *pUserData, void *pMemory)
388 {
389 free(pMemory);
390 }
391
392 static const VkAllocationCallbacks default_alloc = {
393 .pUserData = NULL,
394 .pfnAllocation = default_alloc_func,
395 .pfnReallocation = default_realloc_func,
396 .pfnFree = default_free_func,
397 };
398
399 static const struct debug_control radv_debug_options[] = {
400 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
401 {"nodcc", RADV_DEBUG_NO_DCC},
402 {"shaders", RADV_DEBUG_DUMP_SHADERS},
403 {"nocache", RADV_DEBUG_NO_CACHE},
404 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
405 {"nohiz", RADV_DEBUG_NO_HIZ},
406 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
407 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
408 {"allbos", RADV_DEBUG_ALL_BOS},
409 {"noibs", RADV_DEBUG_NO_IBS},
410 {"spirv", RADV_DEBUG_DUMP_SPIRV},
411 {"vmfaults", RADV_DEBUG_VM_FAULTS},
412 {"zerovram", RADV_DEBUG_ZERO_VRAM},
413 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
414 {"nosisched", RADV_DEBUG_NO_SISCHED},
415 {"preoptir", RADV_DEBUG_PREOPTIR},
416 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
417 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
418 {"info", RADV_DEBUG_INFO},
419 {"errors", RADV_DEBUG_ERRORS},
420 {"startup", RADV_DEBUG_STARTUP},
421 {"checkir", RADV_DEBUG_CHECKIR},
422 {NULL, 0}
423 };
424
425 const char *
426 radv_get_debug_option_name(int id)
427 {
428 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
429 return radv_debug_options[id].string;
430 }
431
432 static const struct debug_control radv_perftest_options[] = {
433 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
434 {"sisched", RADV_PERFTEST_SISCHED},
435 {"localbos", RADV_PERFTEST_LOCAL_BOS},
436 {"binning", RADV_PERFTEST_BINNING},
437 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
438 {NULL, 0}
439 };
440
441 const char *
442 radv_get_perftest_option_name(int id)
443 {
444 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
445 return radv_perftest_options[id].string;
446 }
447
448 static void
449 radv_handle_per_app_options(struct radv_instance *instance,
450 const VkApplicationInfo *info)
451 {
452 const char *name = info ? info->pApplicationName : NULL;
453
454 if (!name)
455 return;
456
457 if (!strcmp(name, "Talos - Linux - 32bit") ||
458 !strcmp(name, "Talos - Linux - 64bit")) {
459 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
460 /* Force enable LLVM sisched for Talos because it looks
461 * safe and it gives few more FPS.
462 */
463 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
464 }
465 }
466 }
467
468 static int radv_get_instance_extension_index(const char *name)
469 {
470 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
471 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
472 return i;
473 }
474 return -1;
475 }
476
477
478 VkResult radv_CreateInstance(
479 const VkInstanceCreateInfo* pCreateInfo,
480 const VkAllocationCallbacks* pAllocator,
481 VkInstance* pInstance)
482 {
483 struct radv_instance *instance;
484 VkResult result;
485
486 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
487
488 uint32_t client_version;
489 if (pCreateInfo->pApplicationInfo &&
490 pCreateInfo->pApplicationInfo->apiVersion != 0) {
491 client_version = pCreateInfo->pApplicationInfo->apiVersion;
492 } else {
493 radv_EnumerateInstanceVersion(&client_version);
494 }
495
496 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
497 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
498 if (!instance)
499 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
500
501 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
502
503 if (pAllocator)
504 instance->alloc = *pAllocator;
505 else
506 instance->alloc = default_alloc;
507
508 instance->apiVersion = client_version;
509 instance->physicalDeviceCount = -1;
510
511 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
512 radv_debug_options);
513
514 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
515 radv_perftest_options);
516
517
518 if (instance->debug_flags & RADV_DEBUG_STARTUP)
519 radv_logi("Created an instance");
520
521 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
522 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
523 int index = radv_get_instance_extension_index(ext_name);
524
525 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
526 vk_free2(&default_alloc, pAllocator, instance);
527 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
528 }
529
530 instance->enabled_extensions.extensions[index] = true;
531 }
532
533 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
534 if (result != VK_SUCCESS) {
535 vk_free2(&default_alloc, pAllocator, instance);
536 return vk_error(instance, result);
537 }
538
539 _mesa_locale_init();
540
541 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
542
543 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
544
545 *pInstance = radv_instance_to_handle(instance);
546
547 return VK_SUCCESS;
548 }
549
550 void radv_DestroyInstance(
551 VkInstance _instance,
552 const VkAllocationCallbacks* pAllocator)
553 {
554 RADV_FROM_HANDLE(radv_instance, instance, _instance);
555
556 if (!instance)
557 return;
558
559 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
560 radv_physical_device_finish(instance->physicalDevices + i);
561 }
562
563 VG(VALGRIND_DESTROY_MEMPOOL(instance));
564
565 _mesa_locale_fini();
566
567 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
568
569 vk_free(&instance->alloc, instance);
570 }
571
572 static VkResult
573 radv_enumerate_devices(struct radv_instance *instance)
574 {
575 /* TODO: Check for more devices ? */
576 drmDevicePtr devices[8];
577 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
578 int max_devices;
579
580 instance->physicalDeviceCount = 0;
581
582 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
583
584 if (instance->debug_flags & RADV_DEBUG_STARTUP)
585 radv_logi("Found %d drm nodes", max_devices);
586
587 if (max_devices < 1)
588 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
589
590 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
591 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
592 devices[i]->bustype == DRM_BUS_PCI &&
593 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
594
595 result = radv_physical_device_init(instance->physicalDevices +
596 instance->physicalDeviceCount,
597 instance,
598 devices[i]);
599 if (result == VK_SUCCESS)
600 ++instance->physicalDeviceCount;
601 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
602 break;
603 }
604 }
605 drmFreeDevices(devices, max_devices);
606
607 return result;
608 }
609
610 VkResult radv_EnumeratePhysicalDevices(
611 VkInstance _instance,
612 uint32_t* pPhysicalDeviceCount,
613 VkPhysicalDevice* pPhysicalDevices)
614 {
615 RADV_FROM_HANDLE(radv_instance, instance, _instance);
616 VkResult result;
617
618 if (instance->physicalDeviceCount < 0) {
619 result = radv_enumerate_devices(instance);
620 if (result != VK_SUCCESS &&
621 result != VK_ERROR_INCOMPATIBLE_DRIVER)
622 return result;
623 }
624
625 if (!pPhysicalDevices) {
626 *pPhysicalDeviceCount = instance->physicalDeviceCount;
627 } else {
628 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
629 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
630 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
631 }
632
633 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
634 : VK_SUCCESS;
635 }
636
637 VkResult radv_EnumeratePhysicalDeviceGroups(
638 VkInstance _instance,
639 uint32_t* pPhysicalDeviceGroupCount,
640 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
641 {
642 RADV_FROM_HANDLE(radv_instance, instance, _instance);
643 VkResult result;
644
645 if (instance->physicalDeviceCount < 0) {
646 result = radv_enumerate_devices(instance);
647 if (result != VK_SUCCESS &&
648 result != VK_ERROR_INCOMPATIBLE_DRIVER)
649 return result;
650 }
651
652 if (!pPhysicalDeviceGroupProperties) {
653 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
654 } else {
655 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
656 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
657 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
658 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
659 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
660 }
661 }
662 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
663 : VK_SUCCESS;
664 }
665
666 void radv_GetPhysicalDeviceFeatures(
667 VkPhysicalDevice physicalDevice,
668 VkPhysicalDeviceFeatures* pFeatures)
669 {
670 memset(pFeatures, 0, sizeof(*pFeatures));
671
672 *pFeatures = (VkPhysicalDeviceFeatures) {
673 .robustBufferAccess = true,
674 .fullDrawIndexUint32 = true,
675 .imageCubeArray = true,
676 .independentBlend = true,
677 .geometryShader = true,
678 .tessellationShader = true,
679 .sampleRateShading = true,
680 .dualSrcBlend = true,
681 .logicOp = true,
682 .multiDrawIndirect = true,
683 .drawIndirectFirstInstance = true,
684 .depthClamp = true,
685 .depthBiasClamp = true,
686 .fillModeNonSolid = true,
687 .depthBounds = true,
688 .wideLines = true,
689 .largePoints = true,
690 .alphaToOne = true,
691 .multiViewport = true,
692 .samplerAnisotropy = true,
693 .textureCompressionETC2 = false,
694 .textureCompressionASTC_LDR = false,
695 .textureCompressionBC = true,
696 .occlusionQueryPrecise = true,
697 .pipelineStatisticsQuery = true,
698 .vertexPipelineStoresAndAtomics = true,
699 .fragmentStoresAndAtomics = true,
700 .shaderTessellationAndGeometryPointSize = true,
701 .shaderImageGatherExtended = true,
702 .shaderStorageImageExtendedFormats = true,
703 .shaderStorageImageMultisample = false,
704 .shaderUniformBufferArrayDynamicIndexing = true,
705 .shaderSampledImageArrayDynamicIndexing = true,
706 .shaderStorageBufferArrayDynamicIndexing = true,
707 .shaderStorageImageArrayDynamicIndexing = true,
708 .shaderStorageImageReadWithoutFormat = true,
709 .shaderStorageImageWriteWithoutFormat = true,
710 .shaderClipDistance = true,
711 .shaderCullDistance = true,
712 .shaderFloat64 = true,
713 .shaderInt64 = true,
714 .shaderInt16 = false,
715 .sparseBinding = true,
716 .variableMultisampleRate = true,
717 .inheritedQueries = true,
718 };
719 }
720
721 void radv_GetPhysicalDeviceFeatures2(
722 VkPhysicalDevice physicalDevice,
723 VkPhysicalDeviceFeatures2KHR *pFeatures)
724 {
725 vk_foreach_struct(ext, pFeatures->pNext) {
726 switch (ext->sType) {
727 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
728 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
729 features->variablePointersStorageBuffer = true;
730 features->variablePointers = false;
731 break;
732 }
733 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
734 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
735 features->multiview = true;
736 features->multiviewGeometryShader = true;
737 features->multiviewTessellationShader = true;
738 break;
739 }
740 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
741 VkPhysicalDeviceShaderDrawParameterFeatures *features =
742 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
743 features->shaderDrawParameters = true;
744 break;
745 }
746 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
747 VkPhysicalDeviceProtectedMemoryFeatures *features =
748 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
749 features->protectedMemory = false;
750 break;
751 }
752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
753 VkPhysicalDevice16BitStorageFeatures *features =
754 (VkPhysicalDevice16BitStorageFeatures*)ext;
755 features->storageBuffer16BitAccess = false;
756 features->uniformAndStorageBuffer16BitAccess = false;
757 features->storagePushConstant16 = false;
758 features->storageInputOutput16 = false;
759 break;
760 }
761 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
762 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
763 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
764 features->samplerYcbcrConversion = false;
765 break;
766 }
767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
768 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
769 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
770 features->shaderInputAttachmentArrayDynamicIndexing = true;
771 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
772 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
773 features->shaderUniformBufferArrayNonUniformIndexing = false;
774 features->shaderSampledImageArrayNonUniformIndexing = false;
775 features->shaderStorageBufferArrayNonUniformIndexing = false;
776 features->shaderStorageImageArrayNonUniformIndexing = false;
777 features->shaderInputAttachmentArrayNonUniformIndexing = false;
778 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
779 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
780 features->descriptorBindingUniformBufferUpdateAfterBind = true;
781 features->descriptorBindingSampledImageUpdateAfterBind = true;
782 features->descriptorBindingStorageImageUpdateAfterBind = true;
783 features->descriptorBindingStorageBufferUpdateAfterBind = true;
784 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
785 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
786 features->descriptorBindingUpdateUnusedWhilePending = true;
787 features->descriptorBindingPartiallyBound = true;
788 features->descriptorBindingVariableDescriptorCount = true;
789 features->runtimeDescriptorArray = true;
790 break;
791 }
792 default:
793 break;
794 }
795 }
796 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
797 }
798
799 void radv_GetPhysicalDeviceProperties(
800 VkPhysicalDevice physicalDevice,
801 VkPhysicalDeviceProperties* pProperties)
802 {
803 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
804 VkSampleCountFlags sample_counts = 0xf;
805
806 /* make sure that the entire descriptor set is addressable with a signed
807 * 32-bit int. So the sum of all limits scaled by descriptor size has to
808 * be at most 2 GiB. the combined image & samples object count as one of
809 * both. This limit is for the pipeline layout, not for the set layout, but
810 * there is no set limit, so we just set a pipeline limit. I don't think
811 * any app is going to hit this soon. */
812 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
813 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
814 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
815 32 /* sampler, largest when combined with image */ +
816 64 /* sampled image */ +
817 64 /* storage image */);
818
819 VkPhysicalDeviceLimits limits = {
820 .maxImageDimension1D = (1 << 14),
821 .maxImageDimension2D = (1 << 14),
822 .maxImageDimension3D = (1 << 11),
823 .maxImageDimensionCube = (1 << 14),
824 .maxImageArrayLayers = (1 << 11),
825 .maxTexelBufferElements = 128 * 1024 * 1024,
826 .maxUniformBufferRange = UINT32_MAX,
827 .maxStorageBufferRange = UINT32_MAX,
828 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
829 .maxMemoryAllocationCount = UINT32_MAX,
830 .maxSamplerAllocationCount = 64 * 1024,
831 .bufferImageGranularity = 64, /* A cache line */
832 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
833 .maxBoundDescriptorSets = MAX_SETS,
834 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
835 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
836 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
837 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
838 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
839 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
840 .maxPerStageResources = max_descriptor_set_size,
841 .maxDescriptorSetSamplers = max_descriptor_set_size,
842 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
843 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
844 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
845 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
846 .maxDescriptorSetSampledImages = max_descriptor_set_size,
847 .maxDescriptorSetStorageImages = max_descriptor_set_size,
848 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
849 .maxVertexInputAttributes = 32,
850 .maxVertexInputBindings = 32,
851 .maxVertexInputAttributeOffset = 2047,
852 .maxVertexInputBindingStride = 2048,
853 .maxVertexOutputComponents = 128,
854 .maxTessellationGenerationLevel = 64,
855 .maxTessellationPatchSize = 32,
856 .maxTessellationControlPerVertexInputComponents = 128,
857 .maxTessellationControlPerVertexOutputComponents = 128,
858 .maxTessellationControlPerPatchOutputComponents = 120,
859 .maxTessellationControlTotalOutputComponents = 4096,
860 .maxTessellationEvaluationInputComponents = 128,
861 .maxTessellationEvaluationOutputComponents = 128,
862 .maxGeometryShaderInvocations = 127,
863 .maxGeometryInputComponents = 64,
864 .maxGeometryOutputComponents = 128,
865 .maxGeometryOutputVertices = 256,
866 .maxGeometryTotalOutputComponents = 1024,
867 .maxFragmentInputComponents = 128,
868 .maxFragmentOutputAttachments = 8,
869 .maxFragmentDualSrcAttachments = 1,
870 .maxFragmentCombinedOutputResources = 8,
871 .maxComputeSharedMemorySize = 32768,
872 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
873 .maxComputeWorkGroupInvocations = 2048,
874 .maxComputeWorkGroupSize = {
875 2048,
876 2048,
877 2048
878 },
879 .subPixelPrecisionBits = 4 /* FIXME */,
880 .subTexelPrecisionBits = 4 /* FIXME */,
881 .mipmapPrecisionBits = 4 /* FIXME */,
882 .maxDrawIndexedIndexValue = UINT32_MAX,
883 .maxDrawIndirectCount = UINT32_MAX,
884 .maxSamplerLodBias = 16,
885 .maxSamplerAnisotropy = 16,
886 .maxViewports = MAX_VIEWPORTS,
887 .maxViewportDimensions = { (1 << 14), (1 << 14) },
888 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
889 .viewportSubPixelBits = 8,
890 .minMemoryMapAlignment = 4096, /* A page */
891 .minTexelBufferOffsetAlignment = 1,
892 .minUniformBufferOffsetAlignment = 4,
893 .minStorageBufferOffsetAlignment = 4,
894 .minTexelOffset = -32,
895 .maxTexelOffset = 31,
896 .minTexelGatherOffset = -32,
897 .maxTexelGatherOffset = 31,
898 .minInterpolationOffset = -2,
899 .maxInterpolationOffset = 2,
900 .subPixelInterpolationOffsetBits = 8,
901 .maxFramebufferWidth = (1 << 14),
902 .maxFramebufferHeight = (1 << 14),
903 .maxFramebufferLayers = (1 << 10),
904 .framebufferColorSampleCounts = sample_counts,
905 .framebufferDepthSampleCounts = sample_counts,
906 .framebufferStencilSampleCounts = sample_counts,
907 .framebufferNoAttachmentsSampleCounts = sample_counts,
908 .maxColorAttachments = MAX_RTS,
909 .sampledImageColorSampleCounts = sample_counts,
910 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
911 .sampledImageDepthSampleCounts = sample_counts,
912 .sampledImageStencilSampleCounts = sample_counts,
913 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
914 .maxSampleMaskWords = 1,
915 .timestampComputeAndGraphics = true,
916 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
917 .maxClipDistances = 8,
918 .maxCullDistances = 8,
919 .maxCombinedClipAndCullDistances = 8,
920 .discreteQueuePriorities = 1,
921 .pointSizeRange = { 0.125, 255.875 },
922 .lineWidthRange = { 0.0, 7.9921875 },
923 .pointSizeGranularity = (1.0 / 8.0),
924 .lineWidthGranularity = (1.0 / 128.0),
925 .strictLines = false, /* FINISHME */
926 .standardSampleLocations = true,
927 .optimalBufferCopyOffsetAlignment = 128,
928 .optimalBufferCopyRowPitchAlignment = 128,
929 .nonCoherentAtomSize = 64,
930 };
931
932 *pProperties = (VkPhysicalDeviceProperties) {
933 .apiVersion = radv_physical_device_api_version(pdevice),
934 .driverVersion = vk_get_driver_version(),
935 .vendorID = ATI_VENDOR_ID,
936 .deviceID = pdevice->rad_info.pci_id,
937 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
938 .limits = limits,
939 .sparseProperties = {0},
940 };
941
942 strcpy(pProperties->deviceName, pdevice->name);
943 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
944 }
945
946 void radv_GetPhysicalDeviceProperties2(
947 VkPhysicalDevice physicalDevice,
948 VkPhysicalDeviceProperties2KHR *pProperties)
949 {
950 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
951 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
952
953 vk_foreach_struct(ext, pProperties->pNext) {
954 switch (ext->sType) {
955 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
956 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
957 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
958 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
959 break;
960 }
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
962 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
963 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
964 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
965 properties->deviceLUIDValid = false;
966 break;
967 }
968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
969 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
970 properties->maxMultiviewViewCount = MAX_VIEWS;
971 properties->maxMultiviewInstanceIndex = INT_MAX;
972 break;
973 }
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
975 VkPhysicalDevicePointClippingPropertiesKHR *properties =
976 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
977 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
981 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
982 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
983 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
987 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
988 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
989 properties->minImportedHostPointerAlignment = 4096;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
993 VkPhysicalDeviceSubgroupProperties *properties =
994 (VkPhysicalDeviceSubgroupProperties*)ext;
995 properties->subgroupSize = 64;
996 properties->supportedStages = VK_SHADER_STAGE_ALL;
997 properties->supportedOperations =
998 VK_SUBGROUP_FEATURE_BASIC_BIT |
999 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1000 VK_SUBGROUP_FEATURE_QUAD_BIT |
1001 VK_SUBGROUP_FEATURE_VOTE_BIT;
1002 if (pdevice->rad_info.chip_class >= VI) {
1003 properties->supportedOperations |=
1004 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1005 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1006 }
1007 properties->quadOperationsInAllStages = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1011 VkPhysicalDeviceMaintenance3Properties *properties =
1012 (VkPhysicalDeviceMaintenance3Properties*)ext;
1013 /* Make sure everything is addressable by a signed 32-bit int, and
1014 * our largest descriptors are 96 bytes. */
1015 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1016 /* Our buffer size fields allow only this much */
1017 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1018 break;
1019 }
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1021 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1022 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1023 /* GFX6-8 only support single channel min/max filter. */
1024 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1025 properties->filterMinmaxSingleComponentFormats = true;
1026 break;
1027 }
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1029 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1030 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1031
1032 /* Shader engines. */
1033 properties->shaderEngineCount =
1034 pdevice->rad_info.max_se;
1035 properties->shaderArraysPerEngineCount =
1036 pdevice->rad_info.max_sh_per_se;
1037 properties->computeUnitsPerShaderArray =
1038 pdevice->rad_info.num_good_compute_units /
1039 (pdevice->rad_info.max_se *
1040 pdevice->rad_info.max_sh_per_se);
1041 properties->simdPerComputeUnit = 4;
1042 properties->wavefrontsPerSimd =
1043 pdevice->rad_info.family == CHIP_TONGA ||
1044 pdevice->rad_info.family == CHIP_ICELAND ||
1045 pdevice->rad_info.family == CHIP_POLARIS10 ||
1046 pdevice->rad_info.family == CHIP_POLARIS11 ||
1047 pdevice->rad_info.family == CHIP_POLARIS12 ||
1048 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1049 properties->wavefrontSize = 64;
1050
1051 /* SGPR. */
1052 properties->sgprsPerSimd =
1053 radv_get_num_physical_sgprs(pdevice);
1054 properties->minSgprAllocation =
1055 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1056 properties->maxSgprAllocation =
1057 pdevice->rad_info.family == CHIP_TONGA ||
1058 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1059 properties->sgprAllocationGranularity =
1060 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1061
1062 /* VGPR. */
1063 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1064 properties->minVgprAllocation = 4;
1065 properties->maxVgprAllocation = 256;
1066 properties->vgprAllocationGranularity = 4;
1067 break;
1068 }
1069 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1070 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1071 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1072 properties->maxVertexAttribDivisor = UINT32_MAX;
1073 break;
1074 }
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1076 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1077 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1078 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1079 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1080 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1081 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1082 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1083 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1084 properties->robustBufferAccessUpdateAfterBind = false;
1085 properties->quadDivergentImplicitLod = false;
1086
1087 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1088 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1089 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1090 32 /* sampler, largest when combined with image */ +
1091 64 /* sampled image */ +
1092 64 /* storage image */);
1093 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1094 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1095 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1096 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1097 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1098 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1099 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1100 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1101 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1102 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1103 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1104 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1105 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1106 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1107 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1108 break;
1109 }
1110 default:
1111 break;
1112 }
1113 }
1114 }
1115
1116 static void radv_get_physical_device_queue_family_properties(
1117 struct radv_physical_device* pdevice,
1118 uint32_t* pCount,
1119 VkQueueFamilyProperties** pQueueFamilyProperties)
1120 {
1121 int num_queue_families = 1;
1122 int idx;
1123 if (pdevice->rad_info.num_compute_rings > 0 &&
1124 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1125 num_queue_families++;
1126
1127 if (pQueueFamilyProperties == NULL) {
1128 *pCount = num_queue_families;
1129 return;
1130 }
1131
1132 if (!*pCount)
1133 return;
1134
1135 idx = 0;
1136 if (*pCount >= 1) {
1137 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1138 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1139 VK_QUEUE_COMPUTE_BIT |
1140 VK_QUEUE_TRANSFER_BIT |
1141 VK_QUEUE_SPARSE_BINDING_BIT,
1142 .queueCount = 1,
1143 .timestampValidBits = 64,
1144 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1145 };
1146 idx++;
1147 }
1148
1149 if (pdevice->rad_info.num_compute_rings > 0 &&
1150 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1151 if (*pCount > idx) {
1152 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1153 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1154 VK_QUEUE_TRANSFER_BIT |
1155 VK_QUEUE_SPARSE_BINDING_BIT,
1156 .queueCount = pdevice->rad_info.num_compute_rings,
1157 .timestampValidBits = 64,
1158 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1159 };
1160 idx++;
1161 }
1162 }
1163 *pCount = idx;
1164 }
1165
1166 void radv_GetPhysicalDeviceQueueFamilyProperties(
1167 VkPhysicalDevice physicalDevice,
1168 uint32_t* pCount,
1169 VkQueueFamilyProperties* pQueueFamilyProperties)
1170 {
1171 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1172 if (!pQueueFamilyProperties) {
1173 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1174 return;
1175 }
1176 VkQueueFamilyProperties *properties[] = {
1177 pQueueFamilyProperties + 0,
1178 pQueueFamilyProperties + 1,
1179 pQueueFamilyProperties + 2,
1180 };
1181 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1182 assert(*pCount <= 3);
1183 }
1184
1185 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1186 VkPhysicalDevice physicalDevice,
1187 uint32_t* pCount,
1188 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1189 {
1190 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1191 if (!pQueueFamilyProperties) {
1192 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1193 return;
1194 }
1195 VkQueueFamilyProperties *properties[] = {
1196 &pQueueFamilyProperties[0].queueFamilyProperties,
1197 &pQueueFamilyProperties[1].queueFamilyProperties,
1198 &pQueueFamilyProperties[2].queueFamilyProperties,
1199 };
1200 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1201 assert(*pCount <= 3);
1202 }
1203
1204 void radv_GetPhysicalDeviceMemoryProperties(
1205 VkPhysicalDevice physicalDevice,
1206 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1207 {
1208 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1209
1210 *pMemoryProperties = physical_device->memory_properties;
1211 }
1212
1213 void radv_GetPhysicalDeviceMemoryProperties2(
1214 VkPhysicalDevice physicalDevice,
1215 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1216 {
1217 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1218 &pMemoryProperties->memoryProperties);
1219 }
1220
1221 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1222 VkDevice _device,
1223 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1224 const void *pHostPointer,
1225 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1226 {
1227 RADV_FROM_HANDLE(radv_device, device, _device);
1228
1229 switch (handleType)
1230 {
1231 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1232 const struct radv_physical_device *physical_device = device->physical_device;
1233 uint32_t memoryTypeBits = 0;
1234 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1235 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1236 memoryTypeBits = (1 << i);
1237 break;
1238 }
1239 }
1240 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1241 return VK_SUCCESS;
1242 }
1243 default:
1244 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1245 }
1246 }
1247
1248 static enum radeon_ctx_priority
1249 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1250 {
1251 /* Default to MEDIUM when a specific global priority isn't requested */
1252 if (!pObj)
1253 return RADEON_CTX_PRIORITY_MEDIUM;
1254
1255 switch(pObj->globalPriority) {
1256 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1257 return RADEON_CTX_PRIORITY_REALTIME;
1258 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1259 return RADEON_CTX_PRIORITY_HIGH;
1260 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1261 return RADEON_CTX_PRIORITY_MEDIUM;
1262 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1263 return RADEON_CTX_PRIORITY_LOW;
1264 default:
1265 unreachable("Illegal global priority value");
1266 return RADEON_CTX_PRIORITY_INVALID;
1267 }
1268 }
1269
1270 static int
1271 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1272 uint32_t queue_family_index, int idx,
1273 VkDeviceQueueCreateFlags flags,
1274 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1275 {
1276 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1277 queue->device = device;
1278 queue->queue_family_index = queue_family_index;
1279 queue->queue_idx = idx;
1280 queue->priority = radv_get_queue_global_priority(global_priority);
1281 queue->flags = flags;
1282
1283 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1284 if (!queue->hw_ctx)
1285 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1286
1287 return VK_SUCCESS;
1288 }
1289
1290 static void
1291 radv_queue_finish(struct radv_queue *queue)
1292 {
1293 if (queue->hw_ctx)
1294 queue->device->ws->ctx_destroy(queue->hw_ctx);
1295
1296 if (queue->initial_full_flush_preamble_cs)
1297 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1298 if (queue->initial_preamble_cs)
1299 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1300 if (queue->continue_preamble_cs)
1301 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1302 if (queue->descriptor_bo)
1303 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1304 if (queue->scratch_bo)
1305 queue->device->ws->buffer_destroy(queue->scratch_bo);
1306 if (queue->esgs_ring_bo)
1307 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1308 if (queue->gsvs_ring_bo)
1309 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1310 if (queue->tess_rings_bo)
1311 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1312 if (queue->compute_scratch_bo)
1313 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1314 }
1315
1316 static void
1317 radv_bo_list_init(struct radv_bo_list *bo_list)
1318 {
1319 pthread_mutex_init(&bo_list->mutex, NULL);
1320 bo_list->list.count = bo_list->capacity = 0;
1321 bo_list->list.bos = NULL;
1322 }
1323
1324 static void
1325 radv_bo_list_finish(struct radv_bo_list *bo_list)
1326 {
1327 free(bo_list->list.bos);
1328 pthread_mutex_destroy(&bo_list->mutex);
1329 }
1330
1331 static VkResult radv_bo_list_add(struct radv_device *device,
1332 struct radeon_winsys_bo *bo)
1333 {
1334 struct radv_bo_list *bo_list = &device->bo_list;
1335
1336 if (unlikely(!device->use_global_bo_list))
1337 return VK_SUCCESS;
1338
1339 pthread_mutex_lock(&bo_list->mutex);
1340 if (bo_list->list.count == bo_list->capacity) {
1341 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1342 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1343
1344 if (!data) {
1345 pthread_mutex_unlock(&bo_list->mutex);
1346 return VK_ERROR_OUT_OF_HOST_MEMORY;
1347 }
1348
1349 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1350 bo_list->capacity = capacity;
1351 }
1352
1353 bo_list->list.bos[bo_list->list.count++] = bo;
1354 pthread_mutex_unlock(&bo_list->mutex);
1355 return VK_SUCCESS;
1356 }
1357
1358 static void radv_bo_list_remove(struct radv_device *device,
1359 struct radeon_winsys_bo *bo)
1360 {
1361 struct radv_bo_list *bo_list = &device->bo_list;
1362
1363 if (unlikely(!device->use_global_bo_list))
1364 return;
1365
1366 pthread_mutex_lock(&bo_list->mutex);
1367 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1368 if (bo_list->list.bos[i] == bo) {
1369 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1370 --bo_list->list.count;
1371 break;
1372 }
1373 }
1374 pthread_mutex_unlock(&bo_list->mutex);
1375 }
1376
1377 static void
1378 radv_device_init_gs_info(struct radv_device *device)
1379 {
1380 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1381 device->physical_device->rad_info.family);
1382 }
1383
1384 static int radv_get_device_extension_index(const char *name)
1385 {
1386 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1387 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1388 return i;
1389 }
1390 return -1;
1391 }
1392
1393 VkResult radv_CreateDevice(
1394 VkPhysicalDevice physicalDevice,
1395 const VkDeviceCreateInfo* pCreateInfo,
1396 const VkAllocationCallbacks* pAllocator,
1397 VkDevice* pDevice)
1398 {
1399 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1400 VkResult result;
1401 struct radv_device *device;
1402
1403 bool keep_shader_info = false;
1404
1405 /* Check enabled features */
1406 if (pCreateInfo->pEnabledFeatures) {
1407 VkPhysicalDeviceFeatures supported_features;
1408 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1409 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1410 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1411 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1412 for (uint32_t i = 0; i < num_features; i++) {
1413 if (enabled_feature[i] && !supported_feature[i])
1414 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1415 }
1416 }
1417
1418 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1419 sizeof(*device), 8,
1420 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1421 if (!device)
1422 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1423
1424 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1425 device->instance = physical_device->instance;
1426 device->physical_device = physical_device;
1427
1428 device->ws = physical_device->ws;
1429 if (pAllocator)
1430 device->alloc = *pAllocator;
1431 else
1432 device->alloc = physical_device->instance->alloc;
1433
1434 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1435 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1436 int index = radv_get_device_extension_index(ext_name);
1437 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1438 vk_free(&device->alloc, device);
1439 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1440 }
1441
1442 device->enabled_extensions.extensions[index] = true;
1443 }
1444
1445 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1446
1447 /* With update after bind we can't attach bo's to the command buffer
1448 * from the descriptor set anymore, so we have to use a global BO list.
1449 */
1450 device->use_global_bo_list =
1451 device->enabled_extensions.EXT_descriptor_indexing;
1452
1453 mtx_init(&device->shader_slab_mutex, mtx_plain);
1454 list_inithead(&device->shader_slabs);
1455
1456 radv_bo_list_init(&device->bo_list);
1457
1458 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1459 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1460 uint32_t qfi = queue_create->queueFamilyIndex;
1461 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1462 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1463
1464 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1465
1466 device->queues[qfi] = vk_alloc(&device->alloc,
1467 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1468 if (!device->queues[qfi]) {
1469 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1470 goto fail;
1471 }
1472
1473 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1474
1475 device->queue_count[qfi] = queue_create->queueCount;
1476
1477 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1478 result = radv_queue_init(device, &device->queues[qfi][q],
1479 qfi, q, queue_create->flags,
1480 global_priority);
1481 if (result != VK_SUCCESS)
1482 goto fail;
1483 }
1484 }
1485
1486 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1487 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1488
1489 /* Disabled and not implemented for now. */
1490 device->dfsm_allowed = device->pbb_allowed && false;
1491
1492 #ifdef ANDROID
1493 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1494 #endif
1495
1496 /* The maximum number of scratch waves. Scratch space isn't divided
1497 * evenly between CUs. The number is only a function of the number of CUs.
1498 * We can decrease the constant to decrease the scratch buffer size.
1499 *
1500 * sctx->scratch_waves must be >= the maximum possible size of
1501 * 1 threadgroup, so that the hw doesn't hang from being unable
1502 * to start any.
1503 *
1504 * The recommended value is 4 per CU at most. Higher numbers don't
1505 * bring much benefit, but they still occupy chip resources (think
1506 * async compute). I've seen ~2% performance difference between 4 and 32.
1507 */
1508 uint32_t max_threads_per_block = 2048;
1509 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1510 max_threads_per_block / 64);
1511
1512 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1513
1514 if (device->physical_device->rad_info.chip_class >= CIK) {
1515 /* If the KMD allows it (there is a KMD hw register for it),
1516 * allow launching waves out-of-order.
1517 */
1518 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1519 }
1520
1521 radv_device_init_gs_info(device);
1522
1523 device->tess_offchip_block_dw_size =
1524 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1525 device->has_distributed_tess =
1526 device->physical_device->rad_info.chip_class >= VI &&
1527 device->physical_device->rad_info.max_se >= 2;
1528
1529 if (getenv("RADV_TRACE_FILE")) {
1530 const char *filename = getenv("RADV_TRACE_FILE");
1531
1532 keep_shader_info = true;
1533
1534 if (!radv_init_trace(device))
1535 goto fail;
1536
1537 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1538 radv_dump_enabled_options(device, stderr);
1539 }
1540
1541 device->keep_shader_info = keep_shader_info;
1542
1543 result = radv_device_init_meta(device);
1544 if (result != VK_SUCCESS)
1545 goto fail;
1546
1547 radv_device_init_msaa(device);
1548
1549 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1550 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1551 switch (family) {
1552 case RADV_QUEUE_GENERAL:
1553 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1554 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1555 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1556 break;
1557 case RADV_QUEUE_COMPUTE:
1558 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1559 radeon_emit(device->empty_cs[family], 0);
1560 break;
1561 }
1562 device->ws->cs_finalize(device->empty_cs[family]);
1563 }
1564
1565 if (device->physical_device->rad_info.chip_class >= CIK)
1566 cik_create_gfx_config(device);
1567
1568 VkPipelineCacheCreateInfo ci;
1569 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1570 ci.pNext = NULL;
1571 ci.flags = 0;
1572 ci.pInitialData = NULL;
1573 ci.initialDataSize = 0;
1574 VkPipelineCache pc;
1575 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1576 &ci, NULL, &pc);
1577 if (result != VK_SUCCESS)
1578 goto fail_meta;
1579
1580 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1581
1582 *pDevice = radv_device_to_handle(device);
1583 return VK_SUCCESS;
1584
1585 fail_meta:
1586 radv_device_finish_meta(device);
1587 fail:
1588 radv_bo_list_finish(&device->bo_list);
1589
1590 if (device->trace_bo)
1591 device->ws->buffer_destroy(device->trace_bo);
1592
1593 if (device->gfx_init)
1594 device->ws->buffer_destroy(device->gfx_init);
1595
1596 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1597 for (unsigned q = 0; q < device->queue_count[i]; q++)
1598 radv_queue_finish(&device->queues[i][q]);
1599 if (device->queue_count[i])
1600 vk_free(&device->alloc, device->queues[i]);
1601 }
1602
1603 vk_free(&device->alloc, device);
1604 return result;
1605 }
1606
1607 void radv_DestroyDevice(
1608 VkDevice _device,
1609 const VkAllocationCallbacks* pAllocator)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612
1613 if (!device)
1614 return;
1615
1616 if (device->trace_bo)
1617 device->ws->buffer_destroy(device->trace_bo);
1618
1619 if (device->gfx_init)
1620 device->ws->buffer_destroy(device->gfx_init);
1621
1622 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1623 for (unsigned q = 0; q < device->queue_count[i]; q++)
1624 radv_queue_finish(&device->queues[i][q]);
1625 if (device->queue_count[i])
1626 vk_free(&device->alloc, device->queues[i]);
1627 if (device->empty_cs[i])
1628 device->ws->cs_destroy(device->empty_cs[i]);
1629 }
1630 radv_device_finish_meta(device);
1631
1632 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1633 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1634
1635 radv_destroy_shader_slabs(device);
1636
1637 radv_bo_list_finish(&device->bo_list);
1638 vk_free(&device->alloc, device);
1639 }
1640
1641 VkResult radv_EnumerateInstanceLayerProperties(
1642 uint32_t* pPropertyCount,
1643 VkLayerProperties* pProperties)
1644 {
1645 if (pProperties == NULL) {
1646 *pPropertyCount = 0;
1647 return VK_SUCCESS;
1648 }
1649
1650 /* None supported at this time */
1651 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1652 }
1653
1654 VkResult radv_EnumerateDeviceLayerProperties(
1655 VkPhysicalDevice physicalDevice,
1656 uint32_t* pPropertyCount,
1657 VkLayerProperties* pProperties)
1658 {
1659 if (pProperties == NULL) {
1660 *pPropertyCount = 0;
1661 return VK_SUCCESS;
1662 }
1663
1664 /* None supported at this time */
1665 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1666 }
1667
1668 void radv_GetDeviceQueue2(
1669 VkDevice _device,
1670 const VkDeviceQueueInfo2* pQueueInfo,
1671 VkQueue* pQueue)
1672 {
1673 RADV_FROM_HANDLE(radv_device, device, _device);
1674 struct radv_queue *queue;
1675
1676 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1677 if (pQueueInfo->flags != queue->flags) {
1678 /* From the Vulkan 1.1.70 spec:
1679 *
1680 * "The queue returned by vkGetDeviceQueue2 must have the same
1681 * flags value from this structure as that used at device
1682 * creation time in a VkDeviceQueueCreateInfo instance. If no
1683 * matching flags were specified at device creation time then
1684 * pQueue will return VK_NULL_HANDLE."
1685 */
1686 *pQueue = VK_NULL_HANDLE;
1687 return;
1688 }
1689
1690 *pQueue = radv_queue_to_handle(queue);
1691 }
1692
1693 void radv_GetDeviceQueue(
1694 VkDevice _device,
1695 uint32_t queueFamilyIndex,
1696 uint32_t queueIndex,
1697 VkQueue* pQueue)
1698 {
1699 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1700 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1701 .queueFamilyIndex = queueFamilyIndex,
1702 .queueIndex = queueIndex
1703 };
1704
1705 radv_GetDeviceQueue2(_device, &info, pQueue);
1706 }
1707
1708 static void
1709 fill_geom_tess_rings(struct radv_queue *queue,
1710 uint32_t *map,
1711 bool add_sample_positions,
1712 uint32_t esgs_ring_size,
1713 struct radeon_winsys_bo *esgs_ring_bo,
1714 uint32_t gsvs_ring_size,
1715 struct radeon_winsys_bo *gsvs_ring_bo,
1716 uint32_t tess_factor_ring_size,
1717 uint32_t tess_offchip_ring_offset,
1718 uint32_t tess_offchip_ring_size,
1719 struct radeon_winsys_bo *tess_rings_bo)
1720 {
1721 uint64_t esgs_va = 0, gsvs_va = 0;
1722 uint64_t tess_va = 0, tess_offchip_va = 0;
1723 uint32_t *desc = &map[4];
1724
1725 if (esgs_ring_bo)
1726 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1727 if (gsvs_ring_bo)
1728 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1729 if (tess_rings_bo) {
1730 tess_va = radv_buffer_get_va(tess_rings_bo);
1731 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1732 }
1733
1734 /* stride 0, num records - size, add tid, swizzle, elsize4,
1735 index stride 64 */
1736 desc[0] = esgs_va;
1737 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1738 S_008F04_STRIDE(0) |
1739 S_008F04_SWIZZLE_ENABLE(true);
1740 desc[2] = esgs_ring_size;
1741 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1742 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1743 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1744 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1745 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1746 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1747 S_008F0C_ELEMENT_SIZE(1) |
1748 S_008F0C_INDEX_STRIDE(3) |
1749 S_008F0C_ADD_TID_ENABLE(true);
1750
1751 desc += 4;
1752 /* GS entry for ES->GS ring */
1753 /* stride 0, num records - size, elsize0,
1754 index stride 0 */
1755 desc[0] = esgs_va;
1756 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1757 S_008F04_STRIDE(0) |
1758 S_008F04_SWIZZLE_ENABLE(false);
1759 desc[2] = esgs_ring_size;
1760 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1761 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1762 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1763 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1764 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1765 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1766 S_008F0C_ELEMENT_SIZE(0) |
1767 S_008F0C_INDEX_STRIDE(0) |
1768 S_008F0C_ADD_TID_ENABLE(false);
1769
1770 desc += 4;
1771 /* VS entry for GS->VS ring */
1772 /* stride 0, num records - size, elsize0,
1773 index stride 0 */
1774 desc[0] = gsvs_va;
1775 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1776 S_008F04_STRIDE(0) |
1777 S_008F04_SWIZZLE_ENABLE(false);
1778 desc[2] = gsvs_ring_size;
1779 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1780 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1781 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1782 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1783 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1784 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1785 S_008F0C_ELEMENT_SIZE(0) |
1786 S_008F0C_INDEX_STRIDE(0) |
1787 S_008F0C_ADD_TID_ENABLE(false);
1788 desc += 4;
1789
1790 /* stride gsvs_itemsize, num records 64
1791 elsize 4, index stride 16 */
1792 /* shader will patch stride and desc[2] */
1793 desc[0] = gsvs_va;
1794 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1795 S_008F04_STRIDE(0) |
1796 S_008F04_SWIZZLE_ENABLE(true);
1797 desc[2] = 0;
1798 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1799 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1800 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1801 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1802 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1803 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1804 S_008F0C_ELEMENT_SIZE(1) |
1805 S_008F0C_INDEX_STRIDE(1) |
1806 S_008F0C_ADD_TID_ENABLE(true);
1807 desc += 4;
1808
1809 desc[0] = tess_va;
1810 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1811 S_008F04_STRIDE(0) |
1812 S_008F04_SWIZZLE_ENABLE(false);
1813 desc[2] = tess_factor_ring_size;
1814 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1815 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1816 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1817 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1818 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1819 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1820 S_008F0C_ELEMENT_SIZE(0) |
1821 S_008F0C_INDEX_STRIDE(0) |
1822 S_008F0C_ADD_TID_ENABLE(false);
1823 desc += 4;
1824
1825 desc[0] = tess_offchip_va;
1826 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1827 S_008F04_STRIDE(0) |
1828 S_008F04_SWIZZLE_ENABLE(false);
1829 desc[2] = tess_offchip_ring_size;
1830 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1831 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1832 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1833 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1834 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1835 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1836 S_008F0C_ELEMENT_SIZE(0) |
1837 S_008F0C_INDEX_STRIDE(0) |
1838 S_008F0C_ADD_TID_ENABLE(false);
1839 desc += 4;
1840
1841 /* add sample positions after all rings */
1842 memcpy(desc, queue->device->sample_locations_1x, 8);
1843 desc += 2;
1844 memcpy(desc, queue->device->sample_locations_2x, 16);
1845 desc += 4;
1846 memcpy(desc, queue->device->sample_locations_4x, 32);
1847 desc += 8;
1848 memcpy(desc, queue->device->sample_locations_8x, 64);
1849 desc += 16;
1850 memcpy(desc, queue->device->sample_locations_16x, 128);
1851 }
1852
1853 static unsigned
1854 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1855 {
1856 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1857 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1858 device->physical_device->rad_info.family != CHIP_STONEY;
1859 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1860 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1861 device->physical_device->rad_info.max_se;
1862 unsigned offchip_granularity;
1863 unsigned hs_offchip_param;
1864 switch (device->tess_offchip_block_dw_size) {
1865 default:
1866 assert(0);
1867 /* fall through */
1868 case 8192:
1869 offchip_granularity = V_03093C_X_8K_DWORDS;
1870 break;
1871 case 4096:
1872 offchip_granularity = V_03093C_X_4K_DWORDS;
1873 break;
1874 }
1875
1876 switch (device->physical_device->rad_info.chip_class) {
1877 case SI:
1878 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1879 break;
1880 case CIK:
1881 case VI:
1882 case GFX9:
1883 default:
1884 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1885 break;
1886 }
1887
1888 *max_offchip_buffers_p = max_offchip_buffers;
1889 if (device->physical_device->rad_info.chip_class >= CIK) {
1890 if (device->physical_device->rad_info.chip_class >= VI)
1891 --max_offchip_buffers;
1892 hs_offchip_param =
1893 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1894 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1895 } else {
1896 hs_offchip_param =
1897 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1898 }
1899 return hs_offchip_param;
1900 }
1901
1902 static void
1903 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1904 struct radeon_winsys_bo *esgs_ring_bo,
1905 uint32_t esgs_ring_size,
1906 struct radeon_winsys_bo *gsvs_ring_bo,
1907 uint32_t gsvs_ring_size)
1908 {
1909 if (!esgs_ring_bo && !gsvs_ring_bo)
1910 return;
1911
1912 if (esgs_ring_bo)
1913 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1914
1915 if (gsvs_ring_bo)
1916 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1917
1918 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1919 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1920 radeon_emit(cs, esgs_ring_size >> 8);
1921 radeon_emit(cs, gsvs_ring_size >> 8);
1922 } else {
1923 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1924 radeon_emit(cs, esgs_ring_size >> 8);
1925 radeon_emit(cs, gsvs_ring_size >> 8);
1926 }
1927 }
1928
1929 static void
1930 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1931 unsigned hs_offchip_param, unsigned tf_ring_size,
1932 struct radeon_winsys_bo *tess_rings_bo)
1933 {
1934 uint64_t tf_va;
1935
1936 if (!tess_rings_bo)
1937 return;
1938
1939 tf_va = radv_buffer_get_va(tess_rings_bo);
1940
1941 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1942
1943 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1944 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1945 S_030938_SIZE(tf_ring_size / 4));
1946 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1947 tf_va >> 8);
1948 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1949 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1950 S_030944_BASE_HI(tf_va >> 40));
1951 }
1952 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1953 hs_offchip_param);
1954 } else {
1955 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1956 S_008988_SIZE(tf_ring_size / 4));
1957 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1958 tf_va >> 8);
1959 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1960 hs_offchip_param);
1961 }
1962 }
1963
1964 static void
1965 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1966 struct radeon_winsys_bo *compute_scratch_bo)
1967 {
1968 uint64_t scratch_va;
1969
1970 if (!compute_scratch_bo)
1971 return;
1972
1973 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1974
1975 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1976
1977 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1978 radeon_emit(cs, scratch_va);
1979 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1980 S_008F04_SWIZZLE_ENABLE(1));
1981 }
1982
1983 static void
1984 radv_emit_global_shader_pointers(struct radv_queue *queue,
1985 struct radeon_cmdbuf *cs,
1986 struct radeon_winsys_bo *descriptor_bo)
1987 {
1988 uint64_t va;
1989
1990 if (!descriptor_bo)
1991 return;
1992
1993 va = radv_buffer_get_va(descriptor_bo);
1994
1995 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1996
1997 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1998 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1999 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2000 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2001 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2002
2003 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2004 radv_emit_shader_pointer(queue->device, cs, regs[i],
2005 va, true);
2006 }
2007 } else {
2008 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2009 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2010 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2011 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2012 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2013 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2014
2015 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2016 radv_emit_shader_pointer(queue->device, cs, regs[i],
2017 va, true);
2018 }
2019 }
2020 }
2021
2022 static VkResult
2023 radv_get_preamble_cs(struct radv_queue *queue,
2024 uint32_t scratch_size,
2025 uint32_t compute_scratch_size,
2026 uint32_t esgs_ring_size,
2027 uint32_t gsvs_ring_size,
2028 bool needs_tess_rings,
2029 bool needs_sample_positions,
2030 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2031 struct radeon_cmdbuf **initial_preamble_cs,
2032 struct radeon_cmdbuf **continue_preamble_cs)
2033 {
2034 struct radeon_winsys_bo *scratch_bo = NULL;
2035 struct radeon_winsys_bo *descriptor_bo = NULL;
2036 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2037 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2038 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2039 struct radeon_winsys_bo *tess_rings_bo = NULL;
2040 struct radeon_cmdbuf *dest_cs[3] = {0};
2041 bool add_tess_rings = false, add_sample_positions = false;
2042 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2043 unsigned max_offchip_buffers;
2044 unsigned hs_offchip_param = 0;
2045 unsigned tess_offchip_ring_offset;
2046 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2047 if (!queue->has_tess_rings) {
2048 if (needs_tess_rings)
2049 add_tess_rings = true;
2050 }
2051 if (!queue->has_sample_positions) {
2052 if (needs_sample_positions)
2053 add_sample_positions = true;
2054 }
2055 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2056 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2057 &max_offchip_buffers);
2058 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2059 tess_offchip_ring_size = max_offchip_buffers *
2060 queue->device->tess_offchip_block_dw_size * 4;
2061
2062 if (scratch_size <= queue->scratch_size &&
2063 compute_scratch_size <= queue->compute_scratch_size &&
2064 esgs_ring_size <= queue->esgs_ring_size &&
2065 gsvs_ring_size <= queue->gsvs_ring_size &&
2066 !add_tess_rings && !add_sample_positions &&
2067 queue->initial_preamble_cs) {
2068 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2069 *initial_preamble_cs = queue->initial_preamble_cs;
2070 *continue_preamble_cs = queue->continue_preamble_cs;
2071 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2072 *continue_preamble_cs = NULL;
2073 return VK_SUCCESS;
2074 }
2075
2076 if (scratch_size > queue->scratch_size) {
2077 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2078 scratch_size,
2079 4096,
2080 RADEON_DOMAIN_VRAM,
2081 ring_bo_flags);
2082 if (!scratch_bo)
2083 goto fail;
2084 } else
2085 scratch_bo = queue->scratch_bo;
2086
2087 if (compute_scratch_size > queue->compute_scratch_size) {
2088 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2089 compute_scratch_size,
2090 4096,
2091 RADEON_DOMAIN_VRAM,
2092 ring_bo_flags);
2093 if (!compute_scratch_bo)
2094 goto fail;
2095
2096 } else
2097 compute_scratch_bo = queue->compute_scratch_bo;
2098
2099 if (esgs_ring_size > queue->esgs_ring_size) {
2100 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2101 esgs_ring_size,
2102 4096,
2103 RADEON_DOMAIN_VRAM,
2104 ring_bo_flags);
2105 if (!esgs_ring_bo)
2106 goto fail;
2107 } else {
2108 esgs_ring_bo = queue->esgs_ring_bo;
2109 esgs_ring_size = queue->esgs_ring_size;
2110 }
2111
2112 if (gsvs_ring_size > queue->gsvs_ring_size) {
2113 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2114 gsvs_ring_size,
2115 4096,
2116 RADEON_DOMAIN_VRAM,
2117 ring_bo_flags);
2118 if (!gsvs_ring_bo)
2119 goto fail;
2120 } else {
2121 gsvs_ring_bo = queue->gsvs_ring_bo;
2122 gsvs_ring_size = queue->gsvs_ring_size;
2123 }
2124
2125 if (add_tess_rings) {
2126 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2127 tess_offchip_ring_offset + tess_offchip_ring_size,
2128 256,
2129 RADEON_DOMAIN_VRAM,
2130 ring_bo_flags);
2131 if (!tess_rings_bo)
2132 goto fail;
2133 } else {
2134 tess_rings_bo = queue->tess_rings_bo;
2135 }
2136
2137 if (scratch_bo != queue->scratch_bo ||
2138 esgs_ring_bo != queue->esgs_ring_bo ||
2139 gsvs_ring_bo != queue->gsvs_ring_bo ||
2140 tess_rings_bo != queue->tess_rings_bo ||
2141 add_sample_positions) {
2142 uint32_t size = 0;
2143 if (gsvs_ring_bo || esgs_ring_bo ||
2144 tess_rings_bo || add_sample_positions) {
2145 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2146 if (add_sample_positions)
2147 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2148 }
2149 else if (scratch_bo)
2150 size = 8; /* 2 dword */
2151
2152 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2153 size,
2154 4096,
2155 RADEON_DOMAIN_VRAM,
2156 RADEON_FLAG_CPU_ACCESS |
2157 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2158 RADEON_FLAG_READ_ONLY);
2159 if (!descriptor_bo)
2160 goto fail;
2161 } else
2162 descriptor_bo = queue->descriptor_bo;
2163
2164 for(int i = 0; i < 3; ++i) {
2165 struct radeon_cmdbuf *cs = NULL;
2166 cs = queue->device->ws->cs_create(queue->device->ws,
2167 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2168 if (!cs)
2169 goto fail;
2170
2171 dest_cs[i] = cs;
2172
2173 if (scratch_bo)
2174 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2175
2176 if (descriptor_bo != queue->descriptor_bo) {
2177 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2178
2179 if (scratch_bo) {
2180 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2181 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2182 S_008F04_SWIZZLE_ENABLE(1);
2183 map[0] = scratch_va;
2184 map[1] = rsrc1;
2185 }
2186
2187 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2188 add_sample_positions)
2189 fill_geom_tess_rings(queue, map, add_sample_positions,
2190 esgs_ring_size, esgs_ring_bo,
2191 gsvs_ring_size, gsvs_ring_bo,
2192 tess_factor_ring_size,
2193 tess_offchip_ring_offset,
2194 tess_offchip_ring_size,
2195 tess_rings_bo);
2196
2197 queue->device->ws->buffer_unmap(descriptor_bo);
2198 }
2199
2200 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2202 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2203 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2204 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2205 }
2206
2207 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2208 gsvs_ring_bo, gsvs_ring_size);
2209 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2210 tess_factor_ring_size, tess_rings_bo);
2211 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2212 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2213
2214 if (i == 0) {
2215 si_cs_emit_cache_flush(cs,
2216 queue->device->physical_device->rad_info.chip_class,
2217 NULL, 0,
2218 queue->queue_family_index == RING_COMPUTE &&
2219 queue->device->physical_device->rad_info.chip_class >= CIK,
2220 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2221 RADV_CMD_FLAG_INV_ICACHE |
2222 RADV_CMD_FLAG_INV_SMEM_L1 |
2223 RADV_CMD_FLAG_INV_VMEM_L1 |
2224 RADV_CMD_FLAG_INV_GLOBAL_L2);
2225 } else if (i == 1) {
2226 si_cs_emit_cache_flush(cs,
2227 queue->device->physical_device->rad_info.chip_class,
2228 NULL, 0,
2229 queue->queue_family_index == RING_COMPUTE &&
2230 queue->device->physical_device->rad_info.chip_class >= CIK,
2231 RADV_CMD_FLAG_INV_ICACHE |
2232 RADV_CMD_FLAG_INV_SMEM_L1 |
2233 RADV_CMD_FLAG_INV_VMEM_L1 |
2234 RADV_CMD_FLAG_INV_GLOBAL_L2);
2235 }
2236
2237 if (!queue->device->ws->cs_finalize(cs))
2238 goto fail;
2239 }
2240
2241 if (queue->initial_full_flush_preamble_cs)
2242 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2243
2244 if (queue->initial_preamble_cs)
2245 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2246
2247 if (queue->continue_preamble_cs)
2248 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2249
2250 queue->initial_full_flush_preamble_cs = dest_cs[0];
2251 queue->initial_preamble_cs = dest_cs[1];
2252 queue->continue_preamble_cs = dest_cs[2];
2253
2254 if (scratch_bo != queue->scratch_bo) {
2255 if (queue->scratch_bo)
2256 queue->device->ws->buffer_destroy(queue->scratch_bo);
2257 queue->scratch_bo = scratch_bo;
2258 queue->scratch_size = scratch_size;
2259 }
2260
2261 if (compute_scratch_bo != queue->compute_scratch_bo) {
2262 if (queue->compute_scratch_bo)
2263 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2264 queue->compute_scratch_bo = compute_scratch_bo;
2265 queue->compute_scratch_size = compute_scratch_size;
2266 }
2267
2268 if (esgs_ring_bo != queue->esgs_ring_bo) {
2269 if (queue->esgs_ring_bo)
2270 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2271 queue->esgs_ring_bo = esgs_ring_bo;
2272 queue->esgs_ring_size = esgs_ring_size;
2273 }
2274
2275 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2276 if (queue->gsvs_ring_bo)
2277 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2278 queue->gsvs_ring_bo = gsvs_ring_bo;
2279 queue->gsvs_ring_size = gsvs_ring_size;
2280 }
2281
2282 if (tess_rings_bo != queue->tess_rings_bo) {
2283 queue->tess_rings_bo = tess_rings_bo;
2284 queue->has_tess_rings = true;
2285 }
2286
2287 if (descriptor_bo != queue->descriptor_bo) {
2288 if (queue->descriptor_bo)
2289 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2290
2291 queue->descriptor_bo = descriptor_bo;
2292 }
2293
2294 if (add_sample_positions)
2295 queue->has_sample_positions = true;
2296
2297 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2298 *initial_preamble_cs = queue->initial_preamble_cs;
2299 *continue_preamble_cs = queue->continue_preamble_cs;
2300 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2301 *continue_preamble_cs = NULL;
2302 return VK_SUCCESS;
2303 fail:
2304 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2305 if (dest_cs[i])
2306 queue->device->ws->cs_destroy(dest_cs[i]);
2307 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2308 queue->device->ws->buffer_destroy(descriptor_bo);
2309 if (scratch_bo && scratch_bo != queue->scratch_bo)
2310 queue->device->ws->buffer_destroy(scratch_bo);
2311 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2312 queue->device->ws->buffer_destroy(compute_scratch_bo);
2313 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2314 queue->device->ws->buffer_destroy(esgs_ring_bo);
2315 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2316 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2317 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2318 queue->device->ws->buffer_destroy(tess_rings_bo);
2319 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2320 }
2321
2322 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2323 struct radv_winsys_sem_counts *counts,
2324 int num_sems,
2325 const VkSemaphore *sems,
2326 VkFence _fence,
2327 bool reset_temp)
2328 {
2329 int syncobj_idx = 0, sem_idx = 0;
2330
2331 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2332 return VK_SUCCESS;
2333
2334 for (uint32_t i = 0; i < num_sems; i++) {
2335 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2336
2337 if (sem->temp_syncobj || sem->syncobj)
2338 counts->syncobj_count++;
2339 else
2340 counts->sem_count++;
2341 }
2342
2343 if (_fence != VK_NULL_HANDLE) {
2344 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2345 if (fence->temp_syncobj || fence->syncobj)
2346 counts->syncobj_count++;
2347 }
2348
2349 if (counts->syncobj_count) {
2350 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2351 if (!counts->syncobj)
2352 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2353 }
2354
2355 if (counts->sem_count) {
2356 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2357 if (!counts->sem) {
2358 free(counts->syncobj);
2359 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2360 }
2361 }
2362
2363 for (uint32_t i = 0; i < num_sems; i++) {
2364 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2365
2366 if (sem->temp_syncobj) {
2367 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2368 }
2369 else if (sem->syncobj)
2370 counts->syncobj[syncobj_idx++] = sem->syncobj;
2371 else {
2372 assert(sem->sem);
2373 counts->sem[sem_idx++] = sem->sem;
2374 }
2375 }
2376
2377 if (_fence != VK_NULL_HANDLE) {
2378 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2379 if (fence->temp_syncobj)
2380 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2381 else if (fence->syncobj)
2382 counts->syncobj[syncobj_idx++] = fence->syncobj;
2383 }
2384
2385 return VK_SUCCESS;
2386 }
2387
2388 static void
2389 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2390 {
2391 free(sem_info->wait.syncobj);
2392 free(sem_info->wait.sem);
2393 free(sem_info->signal.syncobj);
2394 free(sem_info->signal.sem);
2395 }
2396
2397
2398 static void radv_free_temp_syncobjs(struct radv_device *device,
2399 int num_sems,
2400 const VkSemaphore *sems)
2401 {
2402 for (uint32_t i = 0; i < num_sems; i++) {
2403 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2404
2405 if (sem->temp_syncobj) {
2406 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2407 sem->temp_syncobj = 0;
2408 }
2409 }
2410 }
2411
2412 static VkResult
2413 radv_alloc_sem_info(struct radv_instance *instance,
2414 struct radv_winsys_sem_info *sem_info,
2415 int num_wait_sems,
2416 const VkSemaphore *wait_sems,
2417 int num_signal_sems,
2418 const VkSemaphore *signal_sems,
2419 VkFence fence)
2420 {
2421 VkResult ret;
2422 memset(sem_info, 0, sizeof(*sem_info));
2423
2424 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2425 if (ret)
2426 return ret;
2427 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2428 if (ret)
2429 radv_free_sem_info(sem_info);
2430
2431 /* caller can override these */
2432 sem_info->cs_emit_wait = true;
2433 sem_info->cs_emit_signal = true;
2434 return ret;
2435 }
2436
2437 /* Signals fence as soon as all the work currently put on queue is done. */
2438 static VkResult radv_signal_fence(struct radv_queue *queue,
2439 struct radv_fence *fence)
2440 {
2441 int ret;
2442 VkResult result;
2443 struct radv_winsys_sem_info sem_info;
2444
2445 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2446 radv_fence_to_handle(fence));
2447 if (result != VK_SUCCESS)
2448 return result;
2449
2450 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2451 &queue->device->empty_cs[queue->queue_family_index],
2452 1, NULL, NULL, &sem_info, NULL,
2453 false, fence->fence);
2454 radv_free_sem_info(&sem_info);
2455
2456 /* TODO: find a better error */
2457 if (ret)
2458 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2459
2460 return VK_SUCCESS;
2461 }
2462
2463 VkResult radv_QueueSubmit(
2464 VkQueue _queue,
2465 uint32_t submitCount,
2466 const VkSubmitInfo* pSubmits,
2467 VkFence _fence)
2468 {
2469 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2470 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2471 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2472 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2473 int ret;
2474 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2475 uint32_t scratch_size = 0;
2476 uint32_t compute_scratch_size = 0;
2477 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2478 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2479 VkResult result;
2480 bool fence_emitted = false;
2481 bool tess_rings_needed = false;
2482 bool sample_positions_needed = false;
2483
2484 /* Do this first so failing to allocate scratch buffers can't result in
2485 * partially executed submissions. */
2486 for (uint32_t i = 0; i < submitCount; i++) {
2487 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2488 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2489 pSubmits[i].pCommandBuffers[j]);
2490
2491 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2492 compute_scratch_size = MAX2(compute_scratch_size,
2493 cmd_buffer->compute_scratch_size_needed);
2494 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2495 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2496 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2497 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2498 }
2499 }
2500
2501 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2502 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2503 sample_positions_needed, &initial_flush_preamble_cs,
2504 &initial_preamble_cs, &continue_preamble_cs);
2505 if (result != VK_SUCCESS)
2506 return result;
2507
2508 for (uint32_t i = 0; i < submitCount; i++) {
2509 struct radeon_cmdbuf **cs_array;
2510 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2511 bool can_patch = true;
2512 uint32_t advance;
2513 struct radv_winsys_sem_info sem_info;
2514
2515 result = radv_alloc_sem_info(queue->device->instance,
2516 &sem_info,
2517 pSubmits[i].waitSemaphoreCount,
2518 pSubmits[i].pWaitSemaphores,
2519 pSubmits[i].signalSemaphoreCount,
2520 pSubmits[i].pSignalSemaphores,
2521 _fence);
2522 if (result != VK_SUCCESS)
2523 return result;
2524
2525 if (!pSubmits[i].commandBufferCount) {
2526 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2527 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2528 &queue->device->empty_cs[queue->queue_family_index],
2529 1, NULL, NULL,
2530 &sem_info, NULL,
2531 false, base_fence);
2532 if (ret) {
2533 radv_loge("failed to submit CS %d\n", i);
2534 abort();
2535 }
2536 fence_emitted = true;
2537 }
2538 radv_free_sem_info(&sem_info);
2539 continue;
2540 }
2541
2542 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2543 (pSubmits[i].commandBufferCount));
2544
2545 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2546 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2547 pSubmits[i].pCommandBuffers[j]);
2548 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2549
2550 cs_array[j] = cmd_buffer->cs;
2551 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2552 can_patch = false;
2553
2554 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2555 }
2556
2557 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2558 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2559 const struct radv_winsys_bo_list *bo_list = NULL;
2560
2561 advance = MIN2(max_cs_submission,
2562 pSubmits[i].commandBufferCount - j);
2563
2564 if (queue->device->trace_bo)
2565 *queue->device->trace_id_ptr = 0;
2566
2567 sem_info.cs_emit_wait = j == 0;
2568 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2569
2570 if (unlikely(queue->device->use_global_bo_list)) {
2571 pthread_mutex_lock(&queue->device->bo_list.mutex);
2572 bo_list = &queue->device->bo_list.list;
2573 }
2574
2575 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2576 advance, initial_preamble, continue_preamble_cs,
2577 &sem_info, bo_list,
2578 can_patch, base_fence);
2579
2580 if (unlikely(queue->device->use_global_bo_list))
2581 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2582
2583 if (ret) {
2584 radv_loge("failed to submit CS %d\n", i);
2585 abort();
2586 }
2587 fence_emitted = true;
2588 if (queue->device->trace_bo) {
2589 radv_check_gpu_hangs(queue, cs_array[j]);
2590 }
2591 }
2592
2593 radv_free_temp_syncobjs(queue->device,
2594 pSubmits[i].waitSemaphoreCount,
2595 pSubmits[i].pWaitSemaphores);
2596 radv_free_sem_info(&sem_info);
2597 free(cs_array);
2598 }
2599
2600 if (fence) {
2601 if (!fence_emitted) {
2602 radv_signal_fence(queue, fence);
2603 }
2604 fence->submitted = true;
2605 }
2606
2607 return VK_SUCCESS;
2608 }
2609
2610 VkResult radv_QueueWaitIdle(
2611 VkQueue _queue)
2612 {
2613 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2614
2615 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2616 radv_queue_family_to_ring(queue->queue_family_index),
2617 queue->queue_idx);
2618 return VK_SUCCESS;
2619 }
2620
2621 VkResult radv_DeviceWaitIdle(
2622 VkDevice _device)
2623 {
2624 RADV_FROM_HANDLE(radv_device, device, _device);
2625
2626 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2627 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2628 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2629 }
2630 }
2631 return VK_SUCCESS;
2632 }
2633
2634 VkResult radv_EnumerateInstanceExtensionProperties(
2635 const char* pLayerName,
2636 uint32_t* pPropertyCount,
2637 VkExtensionProperties* pProperties)
2638 {
2639 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2640
2641 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2642 if (radv_supported_instance_extensions.extensions[i]) {
2643 vk_outarray_append(&out, prop) {
2644 *prop = radv_instance_extensions[i];
2645 }
2646 }
2647 }
2648
2649 return vk_outarray_status(&out);
2650 }
2651
2652 VkResult radv_EnumerateDeviceExtensionProperties(
2653 VkPhysicalDevice physicalDevice,
2654 const char* pLayerName,
2655 uint32_t* pPropertyCount,
2656 VkExtensionProperties* pProperties)
2657 {
2658 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2659 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2660
2661 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2662 if (device->supported_extensions.extensions[i]) {
2663 vk_outarray_append(&out, prop) {
2664 *prop = radv_device_extensions[i];
2665 }
2666 }
2667 }
2668
2669 return vk_outarray_status(&out);
2670 }
2671
2672 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2673 VkInstance _instance,
2674 const char* pName)
2675 {
2676 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2677
2678 return radv_lookup_entrypoint_checked(pName,
2679 instance ? instance->apiVersion : 0,
2680 instance ? &instance->enabled_extensions : NULL,
2681 NULL);
2682 }
2683
2684 /* The loader wants us to expose a second GetInstanceProcAddr function
2685 * to work around certain LD_PRELOAD issues seen in apps.
2686 */
2687 PUBLIC
2688 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2689 VkInstance instance,
2690 const char* pName);
2691
2692 PUBLIC
2693 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2694 VkInstance instance,
2695 const char* pName)
2696 {
2697 return radv_GetInstanceProcAddr(instance, pName);
2698 }
2699
2700 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2701 VkDevice _device,
2702 const char* pName)
2703 {
2704 RADV_FROM_HANDLE(radv_device, device, _device);
2705
2706 return radv_lookup_entrypoint_checked(pName,
2707 device->instance->apiVersion,
2708 &device->instance->enabled_extensions,
2709 &device->enabled_extensions);
2710 }
2711
2712 bool radv_get_memory_fd(struct radv_device *device,
2713 struct radv_device_memory *memory,
2714 int *pFD)
2715 {
2716 struct radeon_bo_metadata metadata;
2717
2718 if (memory->image) {
2719 radv_init_metadata(device, memory->image, &metadata);
2720 device->ws->buffer_set_metadata(memory->bo, &metadata);
2721 }
2722
2723 return device->ws->buffer_get_fd(device->ws, memory->bo,
2724 pFD);
2725 }
2726
2727 static VkResult radv_alloc_memory(struct radv_device *device,
2728 const VkMemoryAllocateInfo* pAllocateInfo,
2729 const VkAllocationCallbacks* pAllocator,
2730 VkDeviceMemory* pMem)
2731 {
2732 struct radv_device_memory *mem;
2733 VkResult result;
2734 enum radeon_bo_domain domain;
2735 uint32_t flags = 0;
2736 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2737
2738 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2739
2740 if (pAllocateInfo->allocationSize == 0) {
2741 /* Apparently, this is allowed */
2742 *pMem = VK_NULL_HANDLE;
2743 return VK_SUCCESS;
2744 }
2745
2746 const VkImportMemoryFdInfoKHR *import_info =
2747 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2748 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2749 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2750 const VkExportMemoryAllocateInfoKHR *export_info =
2751 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2752 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2753 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2754
2755 const struct wsi_memory_allocate_info *wsi_info =
2756 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2757
2758 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2759 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2760 if (mem == NULL)
2761 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2762
2763 if (wsi_info && wsi_info->implicit_sync)
2764 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2765
2766 if (dedicate_info) {
2767 mem->image = radv_image_from_handle(dedicate_info->image);
2768 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2769 } else {
2770 mem->image = NULL;
2771 mem->buffer = NULL;
2772 }
2773
2774 mem->user_ptr = NULL;
2775
2776 if (import_info) {
2777 assert(import_info->handleType ==
2778 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2779 import_info->handleType ==
2780 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2781 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2782 NULL, NULL);
2783 if (!mem->bo) {
2784 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2785 goto fail;
2786 } else {
2787 close(import_info->fd);
2788 }
2789 } else if (host_ptr_info) {
2790 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2791 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2792 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2793 pAllocateInfo->allocationSize);
2794 if (!mem->bo) {
2795 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2796 goto fail;
2797 } else {
2798 mem->user_ptr = host_ptr_info->pHostPointer;
2799 }
2800 } else {
2801 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2802 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2803 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2804 domain = RADEON_DOMAIN_GTT;
2805 else
2806 domain = RADEON_DOMAIN_VRAM;
2807
2808 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2809 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2810 else
2811 flags |= RADEON_FLAG_CPU_ACCESS;
2812
2813 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2814 flags |= RADEON_FLAG_GTT_WC;
2815
2816 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2817 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2818
2819 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2820 domain, flags);
2821
2822 if (!mem->bo) {
2823 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2824 goto fail;
2825 }
2826 mem->type_index = mem_type_index;
2827 }
2828
2829 result = radv_bo_list_add(device, mem->bo);
2830 if (result != VK_SUCCESS)
2831 goto fail_bo;
2832
2833 *pMem = radv_device_memory_to_handle(mem);
2834
2835 return VK_SUCCESS;
2836
2837 fail_bo:
2838 device->ws->buffer_destroy(mem->bo);
2839 fail:
2840 vk_free2(&device->alloc, pAllocator, mem);
2841
2842 return result;
2843 }
2844
2845 VkResult radv_AllocateMemory(
2846 VkDevice _device,
2847 const VkMemoryAllocateInfo* pAllocateInfo,
2848 const VkAllocationCallbacks* pAllocator,
2849 VkDeviceMemory* pMem)
2850 {
2851 RADV_FROM_HANDLE(radv_device, device, _device);
2852 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2853 }
2854
2855 void radv_FreeMemory(
2856 VkDevice _device,
2857 VkDeviceMemory _mem,
2858 const VkAllocationCallbacks* pAllocator)
2859 {
2860 RADV_FROM_HANDLE(radv_device, device, _device);
2861 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2862
2863 if (mem == NULL)
2864 return;
2865
2866 radv_bo_list_remove(device, mem->bo);
2867 device->ws->buffer_destroy(mem->bo);
2868 mem->bo = NULL;
2869
2870 vk_free2(&device->alloc, pAllocator, mem);
2871 }
2872
2873 VkResult radv_MapMemory(
2874 VkDevice _device,
2875 VkDeviceMemory _memory,
2876 VkDeviceSize offset,
2877 VkDeviceSize size,
2878 VkMemoryMapFlags flags,
2879 void** ppData)
2880 {
2881 RADV_FROM_HANDLE(radv_device, device, _device);
2882 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2883
2884 if (mem == NULL) {
2885 *ppData = NULL;
2886 return VK_SUCCESS;
2887 }
2888
2889 if (mem->user_ptr)
2890 *ppData = mem->user_ptr;
2891 else
2892 *ppData = device->ws->buffer_map(mem->bo);
2893
2894 if (*ppData) {
2895 *ppData += offset;
2896 return VK_SUCCESS;
2897 }
2898
2899 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2900 }
2901
2902 void radv_UnmapMemory(
2903 VkDevice _device,
2904 VkDeviceMemory _memory)
2905 {
2906 RADV_FROM_HANDLE(radv_device, device, _device);
2907 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2908
2909 if (mem == NULL)
2910 return;
2911
2912 if (mem->user_ptr == NULL)
2913 device->ws->buffer_unmap(mem->bo);
2914 }
2915
2916 VkResult radv_FlushMappedMemoryRanges(
2917 VkDevice _device,
2918 uint32_t memoryRangeCount,
2919 const VkMappedMemoryRange* pMemoryRanges)
2920 {
2921 return VK_SUCCESS;
2922 }
2923
2924 VkResult radv_InvalidateMappedMemoryRanges(
2925 VkDevice _device,
2926 uint32_t memoryRangeCount,
2927 const VkMappedMemoryRange* pMemoryRanges)
2928 {
2929 return VK_SUCCESS;
2930 }
2931
2932 void radv_GetBufferMemoryRequirements(
2933 VkDevice _device,
2934 VkBuffer _buffer,
2935 VkMemoryRequirements* pMemoryRequirements)
2936 {
2937 RADV_FROM_HANDLE(radv_device, device, _device);
2938 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2939
2940 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2941
2942 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2943 pMemoryRequirements->alignment = 4096;
2944 else
2945 pMemoryRequirements->alignment = 16;
2946
2947 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2948 }
2949
2950 void radv_GetBufferMemoryRequirements2(
2951 VkDevice device,
2952 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2953 VkMemoryRequirements2KHR* pMemoryRequirements)
2954 {
2955 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2956 &pMemoryRequirements->memoryRequirements);
2957 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2958 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2959 switch (ext->sType) {
2960 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2961 VkMemoryDedicatedRequirementsKHR *req =
2962 (VkMemoryDedicatedRequirementsKHR *) ext;
2963 req->requiresDedicatedAllocation = buffer->shareable;
2964 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2965 break;
2966 }
2967 default:
2968 break;
2969 }
2970 }
2971 }
2972
2973 void radv_GetImageMemoryRequirements(
2974 VkDevice _device,
2975 VkImage _image,
2976 VkMemoryRequirements* pMemoryRequirements)
2977 {
2978 RADV_FROM_HANDLE(radv_device, device, _device);
2979 RADV_FROM_HANDLE(radv_image, image, _image);
2980
2981 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2982
2983 pMemoryRequirements->size = image->size;
2984 pMemoryRequirements->alignment = image->alignment;
2985 }
2986
2987 void radv_GetImageMemoryRequirements2(
2988 VkDevice device,
2989 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2990 VkMemoryRequirements2KHR* pMemoryRequirements)
2991 {
2992 radv_GetImageMemoryRequirements(device, pInfo->image,
2993 &pMemoryRequirements->memoryRequirements);
2994
2995 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2996
2997 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2998 switch (ext->sType) {
2999 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3000 VkMemoryDedicatedRequirementsKHR *req =
3001 (VkMemoryDedicatedRequirementsKHR *) ext;
3002 req->requiresDedicatedAllocation = image->shareable;
3003 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3004 break;
3005 }
3006 default:
3007 break;
3008 }
3009 }
3010 }
3011
3012 void radv_GetImageSparseMemoryRequirements(
3013 VkDevice device,
3014 VkImage image,
3015 uint32_t* pSparseMemoryRequirementCount,
3016 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3017 {
3018 stub();
3019 }
3020
3021 void radv_GetImageSparseMemoryRequirements2(
3022 VkDevice device,
3023 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3024 uint32_t* pSparseMemoryRequirementCount,
3025 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3026 {
3027 stub();
3028 }
3029
3030 void radv_GetDeviceMemoryCommitment(
3031 VkDevice device,
3032 VkDeviceMemory memory,
3033 VkDeviceSize* pCommittedMemoryInBytes)
3034 {
3035 *pCommittedMemoryInBytes = 0;
3036 }
3037
3038 VkResult radv_BindBufferMemory2(VkDevice device,
3039 uint32_t bindInfoCount,
3040 const VkBindBufferMemoryInfoKHR *pBindInfos)
3041 {
3042 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3043 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3044 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3045
3046 if (mem) {
3047 buffer->bo = mem->bo;
3048 buffer->offset = pBindInfos[i].memoryOffset;
3049 } else {
3050 buffer->bo = NULL;
3051 }
3052 }
3053 return VK_SUCCESS;
3054 }
3055
3056 VkResult radv_BindBufferMemory(
3057 VkDevice device,
3058 VkBuffer buffer,
3059 VkDeviceMemory memory,
3060 VkDeviceSize memoryOffset)
3061 {
3062 const VkBindBufferMemoryInfoKHR info = {
3063 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3064 .buffer = buffer,
3065 .memory = memory,
3066 .memoryOffset = memoryOffset
3067 };
3068
3069 return radv_BindBufferMemory2(device, 1, &info);
3070 }
3071
3072 VkResult radv_BindImageMemory2(VkDevice device,
3073 uint32_t bindInfoCount,
3074 const VkBindImageMemoryInfoKHR *pBindInfos)
3075 {
3076 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3077 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3078 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3079
3080 if (mem) {
3081 image->bo = mem->bo;
3082 image->offset = pBindInfos[i].memoryOffset;
3083 } else {
3084 image->bo = NULL;
3085 image->offset = 0;
3086 }
3087 }
3088 return VK_SUCCESS;
3089 }
3090
3091
3092 VkResult radv_BindImageMemory(
3093 VkDevice device,
3094 VkImage image,
3095 VkDeviceMemory memory,
3096 VkDeviceSize memoryOffset)
3097 {
3098 const VkBindImageMemoryInfoKHR info = {
3099 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3100 .image = image,
3101 .memory = memory,
3102 .memoryOffset = memoryOffset
3103 };
3104
3105 return radv_BindImageMemory2(device, 1, &info);
3106 }
3107
3108
3109 static void
3110 radv_sparse_buffer_bind_memory(struct radv_device *device,
3111 const VkSparseBufferMemoryBindInfo *bind)
3112 {
3113 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3114
3115 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3116 struct radv_device_memory *mem = NULL;
3117
3118 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3119 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3120
3121 device->ws->buffer_virtual_bind(buffer->bo,
3122 bind->pBinds[i].resourceOffset,
3123 bind->pBinds[i].size,
3124 mem ? mem->bo : NULL,
3125 bind->pBinds[i].memoryOffset);
3126 }
3127 }
3128
3129 static void
3130 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3131 const VkSparseImageOpaqueMemoryBindInfo *bind)
3132 {
3133 RADV_FROM_HANDLE(radv_image, image, bind->image);
3134
3135 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3136 struct radv_device_memory *mem = NULL;
3137
3138 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3139 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3140
3141 device->ws->buffer_virtual_bind(image->bo,
3142 bind->pBinds[i].resourceOffset,
3143 bind->pBinds[i].size,
3144 mem ? mem->bo : NULL,
3145 bind->pBinds[i].memoryOffset);
3146 }
3147 }
3148
3149 VkResult radv_QueueBindSparse(
3150 VkQueue _queue,
3151 uint32_t bindInfoCount,
3152 const VkBindSparseInfo* pBindInfo,
3153 VkFence _fence)
3154 {
3155 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3156 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3157 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3158 bool fence_emitted = false;
3159
3160 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3161 struct radv_winsys_sem_info sem_info;
3162 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3163 radv_sparse_buffer_bind_memory(queue->device,
3164 pBindInfo[i].pBufferBinds + j);
3165 }
3166
3167 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3168 radv_sparse_image_opaque_bind_memory(queue->device,
3169 pBindInfo[i].pImageOpaqueBinds + j);
3170 }
3171
3172 VkResult result;
3173 result = radv_alloc_sem_info(queue->device->instance,
3174 &sem_info,
3175 pBindInfo[i].waitSemaphoreCount,
3176 pBindInfo[i].pWaitSemaphores,
3177 pBindInfo[i].signalSemaphoreCount,
3178 pBindInfo[i].pSignalSemaphores,
3179 _fence);
3180 if (result != VK_SUCCESS)
3181 return result;
3182
3183 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3184 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3185 &queue->device->empty_cs[queue->queue_family_index],
3186 1, NULL, NULL,
3187 &sem_info, NULL,
3188 false, base_fence);
3189 fence_emitted = true;
3190 if (fence)
3191 fence->submitted = true;
3192 }
3193
3194 radv_free_sem_info(&sem_info);
3195
3196 }
3197
3198 if (fence) {
3199 if (!fence_emitted) {
3200 radv_signal_fence(queue, fence);
3201 }
3202 fence->submitted = true;
3203 }
3204
3205 return VK_SUCCESS;
3206 }
3207
3208 VkResult radv_CreateFence(
3209 VkDevice _device,
3210 const VkFenceCreateInfo* pCreateInfo,
3211 const VkAllocationCallbacks* pAllocator,
3212 VkFence* pFence)
3213 {
3214 RADV_FROM_HANDLE(radv_device, device, _device);
3215 const VkExportFenceCreateInfoKHR *export =
3216 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3217 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3218 export ? export->handleTypes : 0;
3219
3220 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3221 sizeof(*fence), 8,
3222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3223
3224 if (!fence)
3225 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3226
3227 fence->submitted = false;
3228 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3229 fence->temp_syncobj = 0;
3230 if (device->always_use_syncobj || handleTypes) {
3231 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3232 if (ret) {
3233 vk_free2(&device->alloc, pAllocator, fence);
3234 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3235 }
3236 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3237 device->ws->signal_syncobj(device->ws, fence->syncobj);
3238 }
3239 fence->fence = NULL;
3240 } else {
3241 fence->fence = device->ws->create_fence();
3242 if (!fence->fence) {
3243 vk_free2(&device->alloc, pAllocator, fence);
3244 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3245 }
3246 fence->syncobj = 0;
3247 }
3248
3249 *pFence = radv_fence_to_handle(fence);
3250
3251 return VK_SUCCESS;
3252 }
3253
3254 void radv_DestroyFence(
3255 VkDevice _device,
3256 VkFence _fence,
3257 const VkAllocationCallbacks* pAllocator)
3258 {
3259 RADV_FROM_HANDLE(radv_device, device, _device);
3260 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3261
3262 if (!fence)
3263 return;
3264
3265 if (fence->temp_syncobj)
3266 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3267 if (fence->syncobj)
3268 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3269 if (fence->fence)
3270 device->ws->destroy_fence(fence->fence);
3271 vk_free2(&device->alloc, pAllocator, fence);
3272 }
3273
3274
3275 static uint64_t radv_get_current_time()
3276 {
3277 struct timespec tv;
3278 clock_gettime(CLOCK_MONOTONIC, &tv);
3279 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3280 }
3281
3282 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3283 {
3284 uint64_t current_time = radv_get_current_time();
3285
3286 timeout = MIN2(UINT64_MAX - current_time, timeout);
3287
3288 return current_time + timeout;
3289 }
3290
3291
3292 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3293 {
3294 for (uint32_t i = 0; i < fenceCount; ++i) {
3295 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3296 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3297 return false;
3298 }
3299 return true;
3300 }
3301
3302 VkResult radv_WaitForFences(
3303 VkDevice _device,
3304 uint32_t fenceCount,
3305 const VkFence* pFences,
3306 VkBool32 waitAll,
3307 uint64_t timeout)
3308 {
3309 RADV_FROM_HANDLE(radv_device, device, _device);
3310 timeout = radv_get_absolute_timeout(timeout);
3311
3312 if (device->always_use_syncobj) {
3313 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3314 if (!handles)
3315 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3316
3317 for (uint32_t i = 0; i < fenceCount; ++i) {
3318 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3319 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3320 }
3321
3322 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3323
3324 free(handles);
3325 return success ? VK_SUCCESS : VK_TIMEOUT;
3326 }
3327
3328 if (!waitAll && fenceCount > 1) {
3329 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3330 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3331 uint32_t wait_count = 0;
3332 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3333 if (!fences)
3334 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3335
3336 for (uint32_t i = 0; i < fenceCount; ++i) {
3337 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3338
3339 if (fence->signalled) {
3340 free(fences);
3341 return VK_SUCCESS;
3342 }
3343
3344 fences[wait_count++] = fence->fence;
3345 }
3346
3347 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3348 waitAll, timeout - radv_get_current_time());
3349
3350 free(fences);
3351 return success ? VK_SUCCESS : VK_TIMEOUT;
3352 }
3353
3354 while(radv_get_current_time() <= timeout) {
3355 for (uint32_t i = 0; i < fenceCount; ++i) {
3356 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3357 return VK_SUCCESS;
3358 }
3359 }
3360 return VK_TIMEOUT;
3361 }
3362
3363 for (uint32_t i = 0; i < fenceCount; ++i) {
3364 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3365 bool expired = false;
3366
3367 if (fence->temp_syncobj) {
3368 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3369 return VK_TIMEOUT;
3370 continue;
3371 }
3372
3373 if (fence->syncobj) {
3374 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3375 return VK_TIMEOUT;
3376 continue;
3377 }
3378
3379 if (fence->signalled)
3380 continue;
3381
3382 if (!fence->submitted) {
3383 while(radv_get_current_time() <= timeout && !fence->submitted)
3384 /* Do nothing */;
3385
3386 if (!fence->submitted)
3387 return VK_TIMEOUT;
3388
3389 /* Recheck as it may have been set by submitting operations. */
3390 if (fence->signalled)
3391 continue;
3392 }
3393
3394 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3395 if (!expired)
3396 return VK_TIMEOUT;
3397
3398 fence->signalled = true;
3399 }
3400
3401 return VK_SUCCESS;
3402 }
3403
3404 VkResult radv_ResetFences(VkDevice _device,
3405 uint32_t fenceCount,
3406 const VkFence *pFences)
3407 {
3408 RADV_FROM_HANDLE(radv_device, device, _device);
3409
3410 for (unsigned i = 0; i < fenceCount; ++i) {
3411 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3412 fence->submitted = fence->signalled = false;
3413
3414 /* Per spec, we first restore the permanent payload, and then reset, so
3415 * having a temp syncobj should not skip resetting the permanent syncobj. */
3416 if (fence->temp_syncobj) {
3417 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3418 fence->temp_syncobj = 0;
3419 }
3420
3421 if (fence->syncobj) {
3422 device->ws->reset_syncobj(device->ws, fence->syncobj);
3423 }
3424 }
3425
3426 return VK_SUCCESS;
3427 }
3428
3429 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3430 {
3431 RADV_FROM_HANDLE(radv_device, device, _device);
3432 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3433
3434 if (fence->temp_syncobj) {
3435 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3436 return success ? VK_SUCCESS : VK_NOT_READY;
3437 }
3438
3439 if (fence->syncobj) {
3440 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3441 return success ? VK_SUCCESS : VK_NOT_READY;
3442 }
3443
3444 if (fence->signalled)
3445 return VK_SUCCESS;
3446 if (!fence->submitted)
3447 return VK_NOT_READY;
3448 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3449 return VK_NOT_READY;
3450
3451 return VK_SUCCESS;
3452 }
3453
3454
3455 // Queue semaphore functions
3456
3457 VkResult radv_CreateSemaphore(
3458 VkDevice _device,
3459 const VkSemaphoreCreateInfo* pCreateInfo,
3460 const VkAllocationCallbacks* pAllocator,
3461 VkSemaphore* pSemaphore)
3462 {
3463 RADV_FROM_HANDLE(radv_device, device, _device);
3464 const VkExportSemaphoreCreateInfoKHR *export =
3465 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3466 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3467 export ? export->handleTypes : 0;
3468
3469 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3470 sizeof(*sem), 8,
3471 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3472 if (!sem)
3473 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3474
3475 sem->temp_syncobj = 0;
3476 /* create a syncobject if we are going to export this semaphore */
3477 if (device->always_use_syncobj || handleTypes) {
3478 assert (device->physical_device->rad_info.has_syncobj);
3479 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3480 if (ret) {
3481 vk_free2(&device->alloc, pAllocator, sem);
3482 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3483 }
3484 sem->sem = NULL;
3485 } else {
3486 sem->sem = device->ws->create_sem(device->ws);
3487 if (!sem->sem) {
3488 vk_free2(&device->alloc, pAllocator, sem);
3489 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3490 }
3491 sem->syncobj = 0;
3492 }
3493
3494 *pSemaphore = radv_semaphore_to_handle(sem);
3495 return VK_SUCCESS;
3496 }
3497
3498 void radv_DestroySemaphore(
3499 VkDevice _device,
3500 VkSemaphore _semaphore,
3501 const VkAllocationCallbacks* pAllocator)
3502 {
3503 RADV_FROM_HANDLE(radv_device, device, _device);
3504 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3505 if (!_semaphore)
3506 return;
3507
3508 if (sem->syncobj)
3509 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3510 else
3511 device->ws->destroy_sem(sem->sem);
3512 vk_free2(&device->alloc, pAllocator, sem);
3513 }
3514
3515 VkResult radv_CreateEvent(
3516 VkDevice _device,
3517 const VkEventCreateInfo* pCreateInfo,
3518 const VkAllocationCallbacks* pAllocator,
3519 VkEvent* pEvent)
3520 {
3521 RADV_FROM_HANDLE(radv_device, device, _device);
3522 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3523 sizeof(*event), 8,
3524 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3525
3526 if (!event)
3527 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3528
3529 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3530 RADEON_DOMAIN_GTT,
3531 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3532 if (!event->bo) {
3533 vk_free2(&device->alloc, pAllocator, event);
3534 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3535 }
3536
3537 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3538
3539 *pEvent = radv_event_to_handle(event);
3540
3541 return VK_SUCCESS;
3542 }
3543
3544 void radv_DestroyEvent(
3545 VkDevice _device,
3546 VkEvent _event,
3547 const VkAllocationCallbacks* pAllocator)
3548 {
3549 RADV_FROM_HANDLE(radv_device, device, _device);
3550 RADV_FROM_HANDLE(radv_event, event, _event);
3551
3552 if (!event)
3553 return;
3554 device->ws->buffer_destroy(event->bo);
3555 vk_free2(&device->alloc, pAllocator, event);
3556 }
3557
3558 VkResult radv_GetEventStatus(
3559 VkDevice _device,
3560 VkEvent _event)
3561 {
3562 RADV_FROM_HANDLE(radv_event, event, _event);
3563
3564 if (*event->map == 1)
3565 return VK_EVENT_SET;
3566 return VK_EVENT_RESET;
3567 }
3568
3569 VkResult radv_SetEvent(
3570 VkDevice _device,
3571 VkEvent _event)
3572 {
3573 RADV_FROM_HANDLE(radv_event, event, _event);
3574 *event->map = 1;
3575
3576 return VK_SUCCESS;
3577 }
3578
3579 VkResult radv_ResetEvent(
3580 VkDevice _device,
3581 VkEvent _event)
3582 {
3583 RADV_FROM_HANDLE(radv_event, event, _event);
3584 *event->map = 0;
3585
3586 return VK_SUCCESS;
3587 }
3588
3589 VkResult radv_CreateBuffer(
3590 VkDevice _device,
3591 const VkBufferCreateInfo* pCreateInfo,
3592 const VkAllocationCallbacks* pAllocator,
3593 VkBuffer* pBuffer)
3594 {
3595 RADV_FROM_HANDLE(radv_device, device, _device);
3596 struct radv_buffer *buffer;
3597
3598 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3599
3600 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3601 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3602 if (buffer == NULL)
3603 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3604
3605 buffer->size = pCreateInfo->size;
3606 buffer->usage = pCreateInfo->usage;
3607 buffer->bo = NULL;
3608 buffer->offset = 0;
3609 buffer->flags = pCreateInfo->flags;
3610
3611 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3612 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3613
3614 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3615 buffer->bo = device->ws->buffer_create(device->ws,
3616 align64(buffer->size, 4096),
3617 4096, 0, RADEON_FLAG_VIRTUAL);
3618 if (!buffer->bo) {
3619 vk_free2(&device->alloc, pAllocator, buffer);
3620 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3621 }
3622 }
3623
3624 *pBuffer = radv_buffer_to_handle(buffer);
3625
3626 return VK_SUCCESS;
3627 }
3628
3629 void radv_DestroyBuffer(
3630 VkDevice _device,
3631 VkBuffer _buffer,
3632 const VkAllocationCallbacks* pAllocator)
3633 {
3634 RADV_FROM_HANDLE(radv_device, device, _device);
3635 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3636
3637 if (!buffer)
3638 return;
3639
3640 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3641 device->ws->buffer_destroy(buffer->bo);
3642
3643 vk_free2(&device->alloc, pAllocator, buffer);
3644 }
3645
3646 static inline unsigned
3647 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3648 {
3649 if (stencil)
3650 return image->surface.u.legacy.stencil_tiling_index[level];
3651 else
3652 return image->surface.u.legacy.tiling_index[level];
3653 }
3654
3655 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3656 {
3657 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3658 }
3659
3660 static uint32_t
3661 radv_init_dcc_control_reg(struct radv_device *device,
3662 struct radv_image_view *iview)
3663 {
3664 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3665 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3666 unsigned max_compressed_block_size;
3667 unsigned independent_64b_blocks;
3668
3669 if (device->physical_device->rad_info.chip_class < VI)
3670 return 0;
3671
3672 if (iview->image->info.samples > 1) {
3673 if (iview->image->surface.bpe == 1)
3674 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3675 else if (iview->image->surface.bpe == 2)
3676 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3677 }
3678
3679 if (!device->physical_device->rad_info.has_dedicated_vram) {
3680 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3681 * dGPU and 64 for APU because all of our APUs to date use
3682 * DIMMs which have a request granularity size of 64B while all
3683 * other chips have a 32B request size.
3684 */
3685 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3686 }
3687
3688 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3689 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3690 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3691 /* If this DCC image is potentially going to be used in texture
3692 * fetches, we need some special settings.
3693 */
3694 independent_64b_blocks = 1;
3695 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3696 } else {
3697 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3698 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3699 * big as possible for better compression state.
3700 */
3701 independent_64b_blocks = 0;
3702 max_compressed_block_size = max_uncompressed_block_size;
3703 }
3704
3705 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3706 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3707 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3708 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3709 }
3710
3711 static void
3712 radv_initialise_color_surface(struct radv_device *device,
3713 struct radv_color_buffer_info *cb,
3714 struct radv_image_view *iview)
3715 {
3716 const struct vk_format_description *desc;
3717 unsigned ntype, format, swap, endian;
3718 unsigned blend_clamp = 0, blend_bypass = 0;
3719 uint64_t va;
3720 const struct radeon_surf *surf = &iview->image->surface;
3721
3722 desc = vk_format_description(iview->vk_format);
3723
3724 memset(cb, 0, sizeof(*cb));
3725
3726 /* Intensity is implemented as Red, so treat it that way. */
3727 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3728
3729 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3730
3731 cb->cb_color_base = va >> 8;
3732
3733 if (device->physical_device->rad_info.chip_class >= GFX9) {
3734 struct gfx9_surf_meta_flags meta;
3735 if (iview->image->dcc_offset)
3736 meta = iview->image->surface.u.gfx9.dcc;
3737 else
3738 meta = iview->image->surface.u.gfx9.cmask;
3739
3740 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3741 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3742 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3743 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3744
3745 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3746 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3747 } else {
3748 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3749 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3750
3751 cb->cb_color_base += level_info->offset >> 8;
3752 if (level_info->mode == RADEON_SURF_MODE_2D)
3753 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3754
3755 pitch_tile_max = level_info->nblk_x / 8 - 1;
3756 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3757 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3758
3759 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3760 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3761 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3762
3763 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3764
3765 if (radv_image_has_fmask(iview->image)) {
3766 if (device->physical_device->rad_info.chip_class >= CIK)
3767 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3768 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3769 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3770 } else {
3771 /* This must be set for fast clear to work without FMASK. */
3772 if (device->physical_device->rad_info.chip_class >= CIK)
3773 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3774 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3775 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3776 }
3777 }
3778
3779 /* CMASK variables */
3780 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3781 va += iview->image->cmask.offset;
3782 cb->cb_color_cmask = va >> 8;
3783
3784 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3785 va += iview->image->dcc_offset;
3786 cb->cb_dcc_base = va >> 8;
3787 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3788
3789 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3790 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3791 S_028C6C_SLICE_MAX(max_slice);
3792
3793 if (iview->image->info.samples > 1) {
3794 unsigned log_samples = util_logbase2(iview->image->info.samples);
3795
3796 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3797 S_028C74_NUM_FRAGMENTS(log_samples);
3798 }
3799
3800 if (radv_image_has_fmask(iview->image)) {
3801 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3802 cb->cb_color_fmask = va >> 8;
3803 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3804 } else {
3805 cb->cb_color_fmask = cb->cb_color_base;
3806 }
3807
3808 ntype = radv_translate_color_numformat(iview->vk_format,
3809 desc,
3810 vk_format_get_first_non_void_channel(iview->vk_format));
3811 format = radv_translate_colorformat(iview->vk_format);
3812 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3813 radv_finishme("Illegal color\n");
3814 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3815 endian = radv_colorformat_endian_swap(format);
3816
3817 /* blend clamp should be set for all NORM/SRGB types */
3818 if (ntype == V_028C70_NUMBER_UNORM ||
3819 ntype == V_028C70_NUMBER_SNORM ||
3820 ntype == V_028C70_NUMBER_SRGB)
3821 blend_clamp = 1;
3822
3823 /* set blend bypass according to docs if SINT/UINT or
3824 8/24 COLOR variants */
3825 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3826 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3827 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3828 blend_clamp = 0;
3829 blend_bypass = 1;
3830 }
3831 #if 0
3832 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3833 (format == V_028C70_COLOR_8 ||
3834 format == V_028C70_COLOR_8_8 ||
3835 format == V_028C70_COLOR_8_8_8_8))
3836 ->color_is_int8 = true;
3837 #endif
3838 cb->cb_color_info = S_028C70_FORMAT(format) |
3839 S_028C70_COMP_SWAP(swap) |
3840 S_028C70_BLEND_CLAMP(blend_clamp) |
3841 S_028C70_BLEND_BYPASS(blend_bypass) |
3842 S_028C70_SIMPLE_FLOAT(1) |
3843 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3844 ntype != V_028C70_NUMBER_SNORM &&
3845 ntype != V_028C70_NUMBER_SRGB &&
3846 format != V_028C70_COLOR_8_24 &&
3847 format != V_028C70_COLOR_24_8) |
3848 S_028C70_NUMBER_TYPE(ntype) |
3849 S_028C70_ENDIAN(endian);
3850 if (radv_image_has_fmask(iview->image)) {
3851 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3852 if (device->physical_device->rad_info.chip_class == SI) {
3853 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3854 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3855 }
3856 }
3857
3858 if (radv_image_has_cmask(iview->image) &&
3859 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3860 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3861
3862 if (radv_dcc_enabled(iview->image, iview->base_mip))
3863 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3864
3865 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3866
3867 /* This must be set for fast clear to work without FMASK. */
3868 if (!radv_image_has_fmask(iview->image) &&
3869 device->physical_device->rad_info.chip_class == SI) {
3870 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3871 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3872 }
3873
3874 if (device->physical_device->rad_info.chip_class >= GFX9) {
3875 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3876 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3877
3878 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3879 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3880 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3881 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3882 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3883 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3884 }
3885 }
3886
3887 static unsigned
3888 radv_calc_decompress_on_z_planes(struct radv_device *device,
3889 struct radv_image_view *iview)
3890 {
3891 unsigned max_zplanes = 0;
3892
3893 assert(radv_image_is_tc_compat_htile(iview->image));
3894
3895 if (device->physical_device->rad_info.chip_class >= GFX9) {
3896 /* Default value for 32-bit depth surfaces. */
3897 max_zplanes = 4;
3898
3899 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3900 iview->image->info.samples > 1)
3901 max_zplanes = 2;
3902
3903 max_zplanes = max_zplanes + 1;
3904 } else {
3905 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3906 /* Do not enable Z plane compression for 16-bit depth
3907 * surfaces because isn't supported on GFX8. Only
3908 * 32-bit depth surfaces are supported by the hardware.
3909 * This allows to maintain shader compatibility and to
3910 * reduce the number of depth decompressions.
3911 */
3912 max_zplanes = 1;
3913 } else {
3914 if (iview->image->info.samples <= 1)
3915 max_zplanes = 5;
3916 else if (iview->image->info.samples <= 4)
3917 max_zplanes = 3;
3918 else
3919 max_zplanes = 2;
3920 }
3921 }
3922
3923 return max_zplanes;
3924 }
3925
3926 static void
3927 radv_initialise_ds_surface(struct radv_device *device,
3928 struct radv_ds_buffer_info *ds,
3929 struct radv_image_view *iview)
3930 {
3931 unsigned level = iview->base_mip;
3932 unsigned format, stencil_format;
3933 uint64_t va, s_offs, z_offs;
3934 bool stencil_only = false;
3935 memset(ds, 0, sizeof(*ds));
3936 switch (iview->image->vk_format) {
3937 case VK_FORMAT_D24_UNORM_S8_UINT:
3938 case VK_FORMAT_X8_D24_UNORM_PACK32:
3939 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3940 ds->offset_scale = 2.0f;
3941 break;
3942 case VK_FORMAT_D16_UNORM:
3943 case VK_FORMAT_D16_UNORM_S8_UINT:
3944 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3945 ds->offset_scale = 4.0f;
3946 break;
3947 case VK_FORMAT_D32_SFLOAT:
3948 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3949 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3950 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3951 ds->offset_scale = 1.0f;
3952 break;
3953 case VK_FORMAT_S8_UINT:
3954 stencil_only = true;
3955 break;
3956 default:
3957 break;
3958 }
3959
3960 format = radv_translate_dbformat(iview->image->vk_format);
3961 stencil_format = iview->image->surface.has_stencil ?
3962 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3963
3964 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3965 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3966 S_028008_SLICE_MAX(max_slice);
3967
3968 ds->db_htile_data_base = 0;
3969 ds->db_htile_surface = 0;
3970
3971 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3972 s_offs = z_offs = va;
3973
3974 if (device->physical_device->rad_info.chip_class >= GFX9) {
3975 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3976 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3977
3978 ds->db_z_info = S_028038_FORMAT(format) |
3979 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3980 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3981 S_028038_MAXMIP(iview->image->info.levels - 1) |
3982 S_028038_ZRANGE_PRECISION(1);
3983 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3984 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3985
3986 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3987 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3988 ds->db_depth_view |= S_028008_MIPID(level);
3989
3990 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3991 S_02801C_Y_MAX(iview->image->info.height - 1);
3992
3993 if (radv_htile_enabled(iview->image, level)) {
3994 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3995
3996 if (radv_image_is_tc_compat_htile(iview->image)) {
3997 unsigned max_zplanes =
3998 radv_calc_decompress_on_z_planes(device, iview);
3999
4000 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4001 S_028038_ITERATE_FLUSH(1);
4002 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4003 }
4004
4005 if (!iview->image->surface.has_stencil)
4006 /* Use all of the htile_buffer for depth if there's no stencil. */
4007 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4008 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4009 iview->image->htile_offset;
4010 ds->db_htile_data_base = va >> 8;
4011 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4012 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4013 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4014 }
4015 } else {
4016 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4017
4018 if (stencil_only)
4019 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4020
4021 z_offs += iview->image->surface.u.legacy.level[level].offset;
4022 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4023
4024 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4025 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4026 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4027
4028 if (iview->image->info.samples > 1)
4029 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4030
4031 if (device->physical_device->rad_info.chip_class >= CIK) {
4032 struct radeon_info *info = &device->physical_device->rad_info;
4033 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4034 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4035 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4036 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4037 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4038 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4039
4040 if (stencil_only)
4041 tile_mode = stencil_tile_mode;
4042
4043 ds->db_depth_info |=
4044 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4045 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4046 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4047 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4048 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4049 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4050 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4051 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4052 } else {
4053 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4054 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4055 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4056 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4057 if (stencil_only)
4058 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4059 }
4060
4061 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4062 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4063 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4064
4065 if (radv_htile_enabled(iview->image, level)) {
4066 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4067
4068 if (!iview->image->surface.has_stencil &&
4069 !radv_image_is_tc_compat_htile(iview->image))
4070 /* Use all of the htile_buffer for depth if there's no stencil. */
4071 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4072
4073 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4074 iview->image->htile_offset;
4075 ds->db_htile_data_base = va >> 8;
4076 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4077
4078 if (radv_image_is_tc_compat_htile(iview->image)) {
4079 unsigned max_zplanes =
4080 radv_calc_decompress_on_z_planes(device, iview);
4081
4082 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4083 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4084 }
4085 }
4086 }
4087
4088 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4089 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4090 }
4091
4092 VkResult radv_CreateFramebuffer(
4093 VkDevice _device,
4094 const VkFramebufferCreateInfo* pCreateInfo,
4095 const VkAllocationCallbacks* pAllocator,
4096 VkFramebuffer* pFramebuffer)
4097 {
4098 RADV_FROM_HANDLE(radv_device, device, _device);
4099 struct radv_framebuffer *framebuffer;
4100
4101 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4102
4103 size_t size = sizeof(*framebuffer) +
4104 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4105 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4106 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4107 if (framebuffer == NULL)
4108 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4109
4110 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4111 framebuffer->width = pCreateInfo->width;
4112 framebuffer->height = pCreateInfo->height;
4113 framebuffer->layers = pCreateInfo->layers;
4114 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4115 VkImageView _iview = pCreateInfo->pAttachments[i];
4116 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4117 framebuffer->attachments[i].attachment = iview;
4118 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4119 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4120 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4121 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4122 }
4123 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4124 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4125 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4126 }
4127
4128 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4129 return VK_SUCCESS;
4130 }
4131
4132 void radv_DestroyFramebuffer(
4133 VkDevice _device,
4134 VkFramebuffer _fb,
4135 const VkAllocationCallbacks* pAllocator)
4136 {
4137 RADV_FROM_HANDLE(radv_device, device, _device);
4138 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4139
4140 if (!fb)
4141 return;
4142 vk_free2(&device->alloc, pAllocator, fb);
4143 }
4144
4145 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4146 {
4147 switch (address_mode) {
4148 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4149 return V_008F30_SQ_TEX_WRAP;
4150 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4151 return V_008F30_SQ_TEX_MIRROR;
4152 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4153 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4154 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4155 return V_008F30_SQ_TEX_CLAMP_BORDER;
4156 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4157 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4158 default:
4159 unreachable("illegal tex wrap mode");
4160 break;
4161 }
4162 }
4163
4164 static unsigned
4165 radv_tex_compare(VkCompareOp op)
4166 {
4167 switch (op) {
4168 case VK_COMPARE_OP_NEVER:
4169 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4170 case VK_COMPARE_OP_LESS:
4171 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4172 case VK_COMPARE_OP_EQUAL:
4173 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4174 case VK_COMPARE_OP_LESS_OR_EQUAL:
4175 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4176 case VK_COMPARE_OP_GREATER:
4177 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4178 case VK_COMPARE_OP_NOT_EQUAL:
4179 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4180 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4181 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4182 case VK_COMPARE_OP_ALWAYS:
4183 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4184 default:
4185 unreachable("illegal compare mode");
4186 break;
4187 }
4188 }
4189
4190 static unsigned
4191 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4192 {
4193 switch (filter) {
4194 case VK_FILTER_NEAREST:
4195 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4196 V_008F38_SQ_TEX_XY_FILTER_POINT);
4197 case VK_FILTER_LINEAR:
4198 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4199 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4200 case VK_FILTER_CUBIC_IMG:
4201 default:
4202 fprintf(stderr, "illegal texture filter");
4203 return 0;
4204 }
4205 }
4206
4207 static unsigned
4208 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4209 {
4210 switch (mode) {
4211 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4212 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4213 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4214 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4215 default:
4216 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4217 }
4218 }
4219
4220 static unsigned
4221 radv_tex_bordercolor(VkBorderColor bcolor)
4222 {
4223 switch (bcolor) {
4224 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4225 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4226 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4227 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4228 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4229 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4230 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4231 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4232 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4233 default:
4234 break;
4235 }
4236 return 0;
4237 }
4238
4239 static unsigned
4240 radv_tex_aniso_filter(unsigned filter)
4241 {
4242 if (filter < 2)
4243 return 0;
4244 if (filter < 4)
4245 return 1;
4246 if (filter < 8)
4247 return 2;
4248 if (filter < 16)
4249 return 3;
4250 return 4;
4251 }
4252
4253 static unsigned
4254 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4255 {
4256 switch (mode) {
4257 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4258 return SQ_IMG_FILTER_MODE_BLEND;
4259 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4260 return SQ_IMG_FILTER_MODE_MIN;
4261 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4262 return SQ_IMG_FILTER_MODE_MAX;
4263 default:
4264 break;
4265 }
4266 return 0;
4267 }
4268
4269 static void
4270 radv_init_sampler(struct radv_device *device,
4271 struct radv_sampler *sampler,
4272 const VkSamplerCreateInfo *pCreateInfo)
4273 {
4274 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4275 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4276 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4277 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4278 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4279
4280 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4281 vk_find_struct_const(pCreateInfo->pNext,
4282 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4283 if (sampler_reduction)
4284 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4285
4286 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4287 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4288 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4289 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4290 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4291 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4292 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4293 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4294 S_008F30_DISABLE_CUBE_WRAP(0) |
4295 S_008F30_COMPAT_MODE(is_vi) |
4296 S_008F30_FILTER_MODE(filter_mode));
4297 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4298 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4299 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4300 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4301 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4302 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4303 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4304 S_008F38_MIP_POINT_PRECLAMP(0) |
4305 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4306 S_008F38_FILTER_PREC_FIX(1) |
4307 S_008F38_ANISO_OVERRIDE(is_vi));
4308 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4309 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4310 }
4311
4312 VkResult radv_CreateSampler(
4313 VkDevice _device,
4314 const VkSamplerCreateInfo* pCreateInfo,
4315 const VkAllocationCallbacks* pAllocator,
4316 VkSampler* pSampler)
4317 {
4318 RADV_FROM_HANDLE(radv_device, device, _device);
4319 struct radv_sampler *sampler;
4320
4321 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4322
4323 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4324 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4325 if (!sampler)
4326 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4327
4328 radv_init_sampler(device, sampler, pCreateInfo);
4329 *pSampler = radv_sampler_to_handle(sampler);
4330
4331 return VK_SUCCESS;
4332 }
4333
4334 void radv_DestroySampler(
4335 VkDevice _device,
4336 VkSampler _sampler,
4337 const VkAllocationCallbacks* pAllocator)
4338 {
4339 RADV_FROM_HANDLE(radv_device, device, _device);
4340 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4341
4342 if (!sampler)
4343 return;
4344 vk_free2(&device->alloc, pAllocator, sampler);
4345 }
4346
4347 /* vk_icd.h does not declare this function, so we declare it here to
4348 * suppress Wmissing-prototypes.
4349 */
4350 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4351 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4352
4353 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4354 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4355 {
4356 /* For the full details on loader interface versioning, see
4357 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4358 * What follows is a condensed summary, to help you navigate the large and
4359 * confusing official doc.
4360 *
4361 * - Loader interface v0 is incompatible with later versions. We don't
4362 * support it.
4363 *
4364 * - In loader interface v1:
4365 * - The first ICD entrypoint called by the loader is
4366 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4367 * entrypoint.
4368 * - The ICD must statically expose no other Vulkan symbol unless it is
4369 * linked with -Bsymbolic.
4370 * - Each dispatchable Vulkan handle created by the ICD must be
4371 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4372 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4373 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4374 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4375 * such loader-managed surfaces.
4376 *
4377 * - Loader interface v2 differs from v1 in:
4378 * - The first ICD entrypoint called by the loader is
4379 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4380 * statically expose this entrypoint.
4381 *
4382 * - Loader interface v3 differs from v2 in:
4383 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4384 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4385 * because the loader no longer does so.
4386 */
4387 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4388 return VK_SUCCESS;
4389 }
4390
4391 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4392 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4393 int *pFD)
4394 {
4395 RADV_FROM_HANDLE(radv_device, device, _device);
4396 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4397
4398 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4399
4400 /* At the moment, we support only the below handle types. */
4401 assert(pGetFdInfo->handleType ==
4402 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4403 pGetFdInfo->handleType ==
4404 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4405
4406 bool ret = radv_get_memory_fd(device, memory, pFD);
4407 if (ret == false)
4408 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4409 return VK_SUCCESS;
4410 }
4411
4412 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4413 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4414 int fd,
4415 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4416 {
4417 RADV_FROM_HANDLE(radv_device, device, _device);
4418
4419 switch (handleType) {
4420 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4421 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4422 return VK_SUCCESS;
4423
4424 default:
4425 /* The valid usage section for this function says:
4426 *
4427 * "handleType must not be one of the handle types defined as
4428 * opaque."
4429 *
4430 * So opaque handle types fall into the default "unsupported" case.
4431 */
4432 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4433 }
4434 }
4435
4436 static VkResult radv_import_opaque_fd(struct radv_device *device,
4437 int fd,
4438 uint32_t *syncobj)
4439 {
4440 uint32_t syncobj_handle = 0;
4441 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4442 if (ret != 0)
4443 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4444
4445 if (*syncobj)
4446 device->ws->destroy_syncobj(device->ws, *syncobj);
4447
4448 *syncobj = syncobj_handle;
4449 close(fd);
4450
4451 return VK_SUCCESS;
4452 }
4453
4454 static VkResult radv_import_sync_fd(struct radv_device *device,
4455 int fd,
4456 uint32_t *syncobj)
4457 {
4458 /* If we create a syncobj we do it locally so that if we have an error, we don't
4459 * leave a syncobj in an undetermined state in the fence. */
4460 uint32_t syncobj_handle = *syncobj;
4461 if (!syncobj_handle) {
4462 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4463 if (ret) {
4464 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4465 }
4466 }
4467
4468 if (fd == -1) {
4469 device->ws->signal_syncobj(device->ws, syncobj_handle);
4470 } else {
4471 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4472 if (ret != 0)
4473 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4474 }
4475
4476 *syncobj = syncobj_handle;
4477 if (fd != -1)
4478 close(fd);
4479
4480 return VK_SUCCESS;
4481 }
4482
4483 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4484 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4485 {
4486 RADV_FROM_HANDLE(radv_device, device, _device);
4487 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4488 uint32_t *syncobj_dst = NULL;
4489
4490 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4491 syncobj_dst = &sem->temp_syncobj;
4492 } else {
4493 syncobj_dst = &sem->syncobj;
4494 }
4495
4496 switch(pImportSemaphoreFdInfo->handleType) {
4497 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4498 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4499 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4500 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4501 default:
4502 unreachable("Unhandled semaphore handle type");
4503 }
4504 }
4505
4506 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4507 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4508 int *pFd)
4509 {
4510 RADV_FROM_HANDLE(radv_device, device, _device);
4511 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4512 int ret;
4513 uint32_t syncobj_handle;
4514
4515 if (sem->temp_syncobj)
4516 syncobj_handle = sem->temp_syncobj;
4517 else
4518 syncobj_handle = sem->syncobj;
4519
4520 switch(pGetFdInfo->handleType) {
4521 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4522 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4523 break;
4524 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4525 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4526 if (!ret) {
4527 if (sem->temp_syncobj) {
4528 close (sem->temp_syncobj);
4529 sem->temp_syncobj = 0;
4530 } else {
4531 device->ws->reset_syncobj(device->ws, syncobj_handle);
4532 }
4533 }
4534 break;
4535 default:
4536 unreachable("Unhandled semaphore handle type");
4537 }
4538
4539 if (ret)
4540 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4541 return VK_SUCCESS;
4542 }
4543
4544 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4545 VkPhysicalDevice physicalDevice,
4546 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4547 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4548 {
4549 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4550
4551 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4552 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4553 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4554 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4555 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4556 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4557 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4558 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4559 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4560 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4561 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4562 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4563 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4564 } else {
4565 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4566 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4567 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4568 }
4569 }
4570
4571 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4572 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4573 {
4574 RADV_FROM_HANDLE(radv_device, device, _device);
4575 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4576 uint32_t *syncobj_dst = NULL;
4577
4578
4579 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4580 syncobj_dst = &fence->temp_syncobj;
4581 } else {
4582 syncobj_dst = &fence->syncobj;
4583 }
4584
4585 switch(pImportFenceFdInfo->handleType) {
4586 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4587 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4588 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4589 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4590 default:
4591 unreachable("Unhandled fence handle type");
4592 }
4593 }
4594
4595 VkResult radv_GetFenceFdKHR(VkDevice _device,
4596 const VkFenceGetFdInfoKHR *pGetFdInfo,
4597 int *pFd)
4598 {
4599 RADV_FROM_HANDLE(radv_device, device, _device);
4600 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4601 int ret;
4602 uint32_t syncobj_handle;
4603
4604 if (fence->temp_syncobj)
4605 syncobj_handle = fence->temp_syncobj;
4606 else
4607 syncobj_handle = fence->syncobj;
4608
4609 switch(pGetFdInfo->handleType) {
4610 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4611 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4612 break;
4613 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4614 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4615 if (!ret) {
4616 if (fence->temp_syncobj) {
4617 close (fence->temp_syncobj);
4618 fence->temp_syncobj = 0;
4619 } else {
4620 device->ws->reset_syncobj(device->ws, syncobj_handle);
4621 }
4622 }
4623 break;
4624 default:
4625 unreachable("Unhandled fence handle type");
4626 }
4627
4628 if (ret)
4629 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4630 return VK_SUCCESS;
4631 }
4632
4633 void radv_GetPhysicalDeviceExternalFenceProperties(
4634 VkPhysicalDevice physicalDevice,
4635 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4636 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4637 {
4638 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4639
4640 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4641 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4642 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4643 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4644 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4645 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4646 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4647 } else {
4648 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4649 pExternalFenceProperties->compatibleHandleTypes = 0;
4650 pExternalFenceProperties->externalFenceFeatures = 0;
4651 }
4652 }
4653
4654 VkResult
4655 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4656 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4657 const VkAllocationCallbacks* pAllocator,
4658 VkDebugReportCallbackEXT* pCallback)
4659 {
4660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4661 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4662 pCreateInfo, pAllocator, &instance->alloc,
4663 pCallback);
4664 }
4665
4666 void
4667 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4668 VkDebugReportCallbackEXT _callback,
4669 const VkAllocationCallbacks* pAllocator)
4670 {
4671 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4672 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4673 _callback, pAllocator, &instance->alloc);
4674 }
4675
4676 void
4677 radv_DebugReportMessageEXT(VkInstance _instance,
4678 VkDebugReportFlagsEXT flags,
4679 VkDebugReportObjectTypeEXT objectType,
4680 uint64_t object,
4681 size_t location,
4682 int32_t messageCode,
4683 const char* pLayerPrefix,
4684 const char* pMessage)
4685 {
4686 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4687 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4688 object, location, messageCode, pLayerPrefix, pMessage);
4689 }
4690
4691 void
4692 radv_GetDeviceGroupPeerMemoryFeatures(
4693 VkDevice device,
4694 uint32_t heapIndex,
4695 uint32_t localDeviceIndex,
4696 uint32_t remoteDeviceIndex,
4697 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4698 {
4699 assert(localDeviceIndex == remoteDeviceIndex);
4700
4701 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4702 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4703 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4704 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4705 }