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radv: Add Vega M support.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 if (HAVE_LLVM > 0) {
112 snprintf(llvm_string, sizeof(llvm_string),
113 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
114 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
115 }
116
117 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
118 }
119
120 static void
121 radv_physical_device_init_mem_types(struct radv_physical_device *device)
122 {
123 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
124 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
125 device->rad_info.vram_vis_size);
126
127 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
128 device->memory_properties.memoryHeapCount = 0;
129 if (device->rad_info.vram_size - visible_vram_size > 0) {
130 vram_index = device->memory_properties.memoryHeapCount++;
131 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
132 .size = device->rad_info.vram_size - visible_vram_size,
133 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
134 };
135 }
136 if (visible_vram_size) {
137 visible_vram_index = device->memory_properties.memoryHeapCount++;
138 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
139 .size = visible_vram_size,
140 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
141 };
142 }
143 if (device->rad_info.gart_size > 0) {
144 gart_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
146 .size = device->rad_info.gart_size,
147 .flags = 0,
148 };
149 }
150
151 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
152 unsigned type_count = 0;
153 if (vram_index >= 0) {
154 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
155 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
156 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
157 .heapIndex = vram_index,
158 };
159 }
160 if (gart_index >= 0) {
161 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
162 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
163 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
164 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
165 .heapIndex = gart_index,
166 };
167 }
168 if (visible_vram_index >= 0) {
169 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
170 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
171 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
172 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
173 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
174 .heapIndex = visible_vram_index,
175 };
176 }
177 if (gart_index >= 0) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
182 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
183 .heapIndex = gart_index,
184 };
185 }
186 device->memory_properties.memoryTypeCount = type_count;
187 }
188
189 static void
190 radv_handle_env_var_force_family(struct radv_physical_device *device)
191 {
192 const char *family = getenv("RADV_FORCE_FAMILY");
193 unsigned i;
194
195 if (!family)
196 return;
197
198 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
199 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
200 /* Override family and chip_class. */
201 device->rad_info.family = i;
202
203 if (i >= CHIP_VEGA10)
204 device->rad_info.chip_class = GFX9;
205 else if (i >= CHIP_TONGA)
206 device->rad_info.chip_class = VI;
207 else if (i >= CHIP_BONAIRE)
208 device->rad_info.chip_class = CIK;
209 else
210 device->rad_info.chip_class = SI;
211
212 return;
213 }
214 }
215
216 fprintf(stderr, "radv: Unknown family: %s\n", family);
217 exit(1);
218 }
219
220 static VkResult
221 radv_physical_device_init(struct radv_physical_device *device,
222 struct radv_instance *instance,
223 drmDevicePtr drm_device)
224 {
225 const char *path = drm_device->nodes[DRM_NODE_RENDER];
226 VkResult result;
227 drmVersionPtr version;
228 int fd;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0)
232 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
233
234 version = drmGetVersion(fd);
235 if (!version) {
236 close(fd);
237 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
238 "failed to get version %s: %m", path);
239 }
240
241 if (strcmp(version->name, "amdgpu")) {
242 drmFreeVersion(version);
243 close(fd);
244 return VK_ERROR_INCOMPATIBLE_DRIVER;
245 }
246 drmFreeVersion(version);
247
248 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
249 device->instance = instance;
250 assert(strlen(path) < ARRAY_SIZE(device->path));
251 strncpy(device->path, path, ARRAY_SIZE(device->path));
252
253 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
254 instance->perftest_flags);
255 if (!device->ws) {
256 result = VK_ERROR_INCOMPATIBLE_DRIVER;
257 goto fail;
258 }
259
260 device->local_fd = fd;
261 device->ws->query_info(device->ws, &device->rad_info);
262
263 radv_handle_env_var_force_family(device);
264
265 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
266
267 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
268 device->ws->destroy(device->ws);
269 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
270 "cannot generate UUID");
271 goto fail;
272 }
273
274 /* These flags affect shader compilation. */
275 uint64_t shader_env_flags =
276 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
277 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
278
279 /* The gpu id is already embeded in the uuid so we just pass "radv"
280 * when creating the cache.
281 */
282 char buf[VK_UUID_SIZE * 2 + 1];
283 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
284 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
285
286 if (device->rad_info.chip_class < VI ||
287 device->rad_info.chip_class > GFX9)
288 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
289
290 radv_get_driver_uuid(&device->device_uuid);
291 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
292
293 if (device->rad_info.family == CHIP_STONEY ||
294 device->rad_info.chip_class >= GFX9) {
295 device->has_rbplus = true;
296 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
297 device->rad_info.family == CHIP_VEGA12 ||
298 device->rad_info.family == CHIP_RAVEN;
299 }
300
301 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
302 * on SI.
303 */
304 device->has_clear_state = device->rad_info.chip_class >= CIK;
305
306 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
307
308 /* Vega10/Raven need a special workaround for a hardware bug. */
309 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
310 device->rad_info.family == CHIP_RAVEN;
311
312 /* Out-of-order primitive rasterization. */
313 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
314 device->rad_info.max_se >= 2;
315 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
316 (device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER);
317
318 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
319 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
320
321 radv_physical_device_init_mem_types(device);
322 radv_fill_device_extension_table(device, &device->supported_extensions);
323
324 result = radv_init_wsi(device);
325 if (result != VK_SUCCESS) {
326 device->ws->destroy(device->ws);
327 goto fail;
328 }
329
330 return VK_SUCCESS;
331
332 fail:
333 close(fd);
334 return result;
335 }
336
337 static void
338 radv_physical_device_finish(struct radv_physical_device *device)
339 {
340 radv_finish_wsi(device);
341 device->ws->destroy(device->ws);
342 disk_cache_destroy(device->disk_cache);
343 close(device->local_fd);
344 }
345
346 static void *
347 default_alloc_func(void *pUserData, size_t size, size_t align,
348 VkSystemAllocationScope allocationScope)
349 {
350 return malloc(size);
351 }
352
353 static void *
354 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
355 size_t align, VkSystemAllocationScope allocationScope)
356 {
357 return realloc(pOriginal, size);
358 }
359
360 static void
361 default_free_func(void *pUserData, void *pMemory)
362 {
363 free(pMemory);
364 }
365
366 static const VkAllocationCallbacks default_alloc = {
367 .pUserData = NULL,
368 .pfnAllocation = default_alloc_func,
369 .pfnReallocation = default_realloc_func,
370 .pfnFree = default_free_func,
371 };
372
373 static const struct debug_control radv_debug_options[] = {
374 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
375 {"nodcc", RADV_DEBUG_NO_DCC},
376 {"shaders", RADV_DEBUG_DUMP_SHADERS},
377 {"nocache", RADV_DEBUG_NO_CACHE},
378 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
379 {"nohiz", RADV_DEBUG_NO_HIZ},
380 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
381 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
382 {"allbos", RADV_DEBUG_ALL_BOS},
383 {"noibs", RADV_DEBUG_NO_IBS},
384 {"spirv", RADV_DEBUG_DUMP_SPIRV},
385 {"vmfaults", RADV_DEBUG_VM_FAULTS},
386 {"zerovram", RADV_DEBUG_ZERO_VRAM},
387 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
388 {"nosisched", RADV_DEBUG_NO_SISCHED},
389 {"preoptir", RADV_DEBUG_PREOPTIR},
390 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
391 {NULL, 0}
392 };
393
394 const char *
395 radv_get_debug_option_name(int id)
396 {
397 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
398 return radv_debug_options[id].string;
399 }
400
401 static const struct debug_control radv_perftest_options[] = {
402 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
403 {"sisched", RADV_PERFTEST_SISCHED},
404 {"localbos", RADV_PERFTEST_LOCAL_BOS},
405 {"binning", RADV_PERFTEST_BINNING},
406 {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
407 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
408 {NULL, 0}
409 };
410
411 const char *
412 radv_get_perftest_option_name(int id)
413 {
414 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
415 return radv_perftest_options[id].string;
416 }
417
418 static void
419 radv_handle_per_app_options(struct radv_instance *instance,
420 const VkApplicationInfo *info)
421 {
422 const char *name = info ? info->pApplicationName : NULL;
423
424 if (!name)
425 return;
426
427 if (!strcmp(name, "Talos - Linux - 32bit") ||
428 !strcmp(name, "Talos - Linux - 64bit")) {
429 /* Force enable LLVM sisched for Talos because it looks safe
430 * and it gives few more FPS.
431 */
432 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
433 }
434 }
435
436 static int radv_get_instance_extension_index(const char *name)
437 {
438 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
439 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
440 return i;
441 }
442 return -1;
443 }
444
445
446 VkResult radv_CreateInstance(
447 const VkInstanceCreateInfo* pCreateInfo,
448 const VkAllocationCallbacks* pAllocator,
449 VkInstance* pInstance)
450 {
451 struct radv_instance *instance;
452 VkResult result;
453
454 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
455
456 uint32_t client_version;
457 if (pCreateInfo->pApplicationInfo &&
458 pCreateInfo->pApplicationInfo->apiVersion != 0) {
459 client_version = pCreateInfo->pApplicationInfo->apiVersion;
460 } else {
461 client_version = VK_MAKE_VERSION(1, 0, 0);
462 }
463
464 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
465 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
466 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
467 "Client requested version %d.%d.%d",
468 VK_VERSION_MAJOR(client_version),
469 VK_VERSION_MINOR(client_version),
470 VK_VERSION_PATCH(client_version));
471 }
472
473 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
474 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
475 if (!instance)
476 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
477
478 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
479
480 if (pAllocator)
481 instance->alloc = *pAllocator;
482 else
483 instance->alloc = default_alloc;
484
485 instance->apiVersion = client_version;
486 instance->physicalDeviceCount = -1;
487
488 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
489 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
490 int index = radv_get_instance_extension_index(ext_name);
491
492 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
493 vk_free2(&default_alloc, pAllocator, instance);
494 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
495 }
496
497 instance->enabled_extensions.extensions[index] = true;
498 }
499
500 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
501 if (result != VK_SUCCESS) {
502 vk_free2(&default_alloc, pAllocator, instance);
503 return vk_error(result);
504 }
505
506 _mesa_locale_init();
507
508 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
509
510 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
511 radv_debug_options);
512
513 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
514 radv_perftest_options);
515
516 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
517
518 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
519 /* Disable sisched when the user requests it, this is mostly
520 * useful when the driver force-enable sisched for the given
521 * application.
522 */
523 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
524 }
525
526 *pInstance = radv_instance_to_handle(instance);
527
528 return VK_SUCCESS;
529 }
530
531 void radv_DestroyInstance(
532 VkInstance _instance,
533 const VkAllocationCallbacks* pAllocator)
534 {
535 RADV_FROM_HANDLE(radv_instance, instance, _instance);
536
537 if (!instance)
538 return;
539
540 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
541 radv_physical_device_finish(instance->physicalDevices + i);
542 }
543
544 VG(VALGRIND_DESTROY_MEMPOOL(instance));
545
546 _mesa_locale_fini();
547
548 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
549
550 vk_free(&instance->alloc, instance);
551 }
552
553 static VkResult
554 radv_enumerate_devices(struct radv_instance *instance)
555 {
556 /* TODO: Check for more devices ? */
557 drmDevicePtr devices[8];
558 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
559 int max_devices;
560
561 instance->physicalDeviceCount = 0;
562
563 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
564 if (max_devices < 1)
565 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
566
567 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
568 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
569 devices[i]->bustype == DRM_BUS_PCI &&
570 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
571
572 result = radv_physical_device_init(instance->physicalDevices +
573 instance->physicalDeviceCount,
574 instance,
575 devices[i]);
576 if (result == VK_SUCCESS)
577 ++instance->physicalDeviceCount;
578 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
579 break;
580 }
581 }
582 drmFreeDevices(devices, max_devices);
583
584 return result;
585 }
586
587 VkResult radv_EnumeratePhysicalDevices(
588 VkInstance _instance,
589 uint32_t* pPhysicalDeviceCount,
590 VkPhysicalDevice* pPhysicalDevices)
591 {
592 RADV_FROM_HANDLE(radv_instance, instance, _instance);
593 VkResult result;
594
595 if (instance->physicalDeviceCount < 0) {
596 result = radv_enumerate_devices(instance);
597 if (result != VK_SUCCESS &&
598 result != VK_ERROR_INCOMPATIBLE_DRIVER)
599 return result;
600 }
601
602 if (!pPhysicalDevices) {
603 *pPhysicalDeviceCount = instance->physicalDeviceCount;
604 } else {
605 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
606 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
607 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
608 }
609
610 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
611 : VK_SUCCESS;
612 }
613
614 VkResult radv_EnumeratePhysicalDeviceGroups(
615 VkInstance _instance,
616 uint32_t* pPhysicalDeviceGroupCount,
617 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
618 {
619 RADV_FROM_HANDLE(radv_instance, instance, _instance);
620 VkResult result;
621
622 if (instance->physicalDeviceCount < 0) {
623 result = radv_enumerate_devices(instance);
624 if (result != VK_SUCCESS &&
625 result != VK_ERROR_INCOMPATIBLE_DRIVER)
626 return result;
627 }
628
629 if (!pPhysicalDeviceGroupProperties) {
630 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
631 } else {
632 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
633 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
634 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
635 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
636 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
637 }
638 }
639 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
640 : VK_SUCCESS;
641 }
642
643 void radv_GetPhysicalDeviceFeatures(
644 VkPhysicalDevice physicalDevice,
645 VkPhysicalDeviceFeatures* pFeatures)
646 {
647 memset(pFeatures, 0, sizeof(*pFeatures));
648
649 *pFeatures = (VkPhysicalDeviceFeatures) {
650 .robustBufferAccess = true,
651 .fullDrawIndexUint32 = true,
652 .imageCubeArray = true,
653 .independentBlend = true,
654 .geometryShader = true,
655 .tessellationShader = true,
656 .sampleRateShading = true,
657 .dualSrcBlend = true,
658 .logicOp = true,
659 .multiDrawIndirect = true,
660 .drawIndirectFirstInstance = true,
661 .depthClamp = true,
662 .depthBiasClamp = true,
663 .fillModeNonSolid = true,
664 .depthBounds = true,
665 .wideLines = true,
666 .largePoints = true,
667 .alphaToOne = true,
668 .multiViewport = true,
669 .samplerAnisotropy = true,
670 .textureCompressionETC2 = false,
671 .textureCompressionASTC_LDR = false,
672 .textureCompressionBC = true,
673 .occlusionQueryPrecise = true,
674 .pipelineStatisticsQuery = true,
675 .vertexPipelineStoresAndAtomics = true,
676 .fragmentStoresAndAtomics = true,
677 .shaderTessellationAndGeometryPointSize = true,
678 .shaderImageGatherExtended = true,
679 .shaderStorageImageExtendedFormats = true,
680 .shaderStorageImageMultisample = false,
681 .shaderUniformBufferArrayDynamicIndexing = true,
682 .shaderSampledImageArrayDynamicIndexing = true,
683 .shaderStorageBufferArrayDynamicIndexing = true,
684 .shaderStorageImageArrayDynamicIndexing = true,
685 .shaderStorageImageReadWithoutFormat = true,
686 .shaderStorageImageWriteWithoutFormat = true,
687 .shaderClipDistance = true,
688 .shaderCullDistance = true,
689 .shaderFloat64 = true,
690 .shaderInt64 = true,
691 .shaderInt16 = false,
692 .sparseBinding = true,
693 .variableMultisampleRate = true,
694 .inheritedQueries = true,
695 };
696 }
697
698 void radv_GetPhysicalDeviceFeatures2(
699 VkPhysicalDevice physicalDevice,
700 VkPhysicalDeviceFeatures2KHR *pFeatures)
701 {
702 vk_foreach_struct(ext, pFeatures->pNext) {
703 switch (ext->sType) {
704 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
705 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
706 features->variablePointersStorageBuffer = true;
707 features->variablePointers = false;
708 break;
709 }
710 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
711 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
712 features->multiview = true;
713 features->multiviewGeometryShader = true;
714 features->multiviewTessellationShader = true;
715 break;
716 }
717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
718 VkPhysicalDeviceShaderDrawParameterFeatures *features =
719 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
720 features->shaderDrawParameters = true;
721 break;
722 }
723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
724 VkPhysicalDeviceProtectedMemoryFeatures *features =
725 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
726 features->protectedMemory = false;
727 break;
728 }
729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
730 VkPhysicalDevice16BitStorageFeatures *features =
731 (VkPhysicalDevice16BitStorageFeatures*)ext;
732 features->storageBuffer16BitAccess = false;
733 features->uniformAndStorageBuffer16BitAccess = false;
734 features->storagePushConstant16 = false;
735 features->storageInputOutput16 = false;
736 break;
737 }
738 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
739 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
740 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
741 features->samplerYcbcrConversion = false;
742 break;
743 }
744 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
745 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
746 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)features;
747 features->shaderInputAttachmentArrayDynamicIndexing = true;
748 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
749 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
750 features->shaderUniformBufferArrayNonUniformIndexing = false;
751 features->shaderSampledImageArrayNonUniformIndexing = false;
752 features->shaderStorageBufferArrayNonUniformIndexing = false;
753 features->shaderStorageImageArrayNonUniformIndexing = false;
754 features->shaderInputAttachmentArrayNonUniformIndexing = false;
755 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
756 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
757 features->descriptorBindingUniformBufferUpdateAfterBind = true;
758 features->descriptorBindingSampledImageUpdateAfterBind = true;
759 features->descriptorBindingStorageImageUpdateAfterBind = true;
760 features->descriptorBindingStorageBufferUpdateAfterBind = true;
761 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
762 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
763 features->descriptorBindingUpdateUnusedWhilePending = true;
764 features->descriptorBindingPartiallyBound = true;
765 features->descriptorBindingVariableDescriptorCount = true;
766 features->runtimeDescriptorArray = true;
767 break;
768 }
769 default:
770 break;
771 }
772 }
773 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
774 }
775
776 void radv_GetPhysicalDeviceProperties(
777 VkPhysicalDevice physicalDevice,
778 VkPhysicalDeviceProperties* pProperties)
779 {
780 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
781 VkSampleCountFlags sample_counts = 0xf;
782
783 /* make sure that the entire descriptor set is addressable with a signed
784 * 32-bit int. So the sum of all limits scaled by descriptor size has to
785 * be at most 2 GiB. the combined image & samples object count as one of
786 * both. This limit is for the pipeline layout, not for the set layout, but
787 * there is no set limit, so we just set a pipeline limit. I don't think
788 * any app is going to hit this soon. */
789 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
790 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
791 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
792 32 /* sampler, largest when combined with image */ +
793 64 /* sampled image */ +
794 64 /* storage image */);
795
796 VkPhysicalDeviceLimits limits = {
797 .maxImageDimension1D = (1 << 14),
798 .maxImageDimension2D = (1 << 14),
799 .maxImageDimension3D = (1 << 11),
800 .maxImageDimensionCube = (1 << 14),
801 .maxImageArrayLayers = (1 << 11),
802 .maxTexelBufferElements = 128 * 1024 * 1024,
803 .maxUniformBufferRange = UINT32_MAX,
804 .maxStorageBufferRange = UINT32_MAX,
805 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
806 .maxMemoryAllocationCount = UINT32_MAX,
807 .maxSamplerAllocationCount = 64 * 1024,
808 .bufferImageGranularity = 64, /* A cache line */
809 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
810 .maxBoundDescriptorSets = MAX_SETS,
811 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
812 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
813 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
814 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
815 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
816 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
817 .maxPerStageResources = max_descriptor_set_size,
818 .maxDescriptorSetSamplers = max_descriptor_set_size,
819 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
820 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
821 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
822 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
823 .maxDescriptorSetSampledImages = max_descriptor_set_size,
824 .maxDescriptorSetStorageImages = max_descriptor_set_size,
825 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
826 .maxVertexInputAttributes = 32,
827 .maxVertexInputBindings = 32,
828 .maxVertexInputAttributeOffset = 2047,
829 .maxVertexInputBindingStride = 2048,
830 .maxVertexOutputComponents = 128,
831 .maxTessellationGenerationLevel = 64,
832 .maxTessellationPatchSize = 32,
833 .maxTessellationControlPerVertexInputComponents = 128,
834 .maxTessellationControlPerVertexOutputComponents = 128,
835 .maxTessellationControlPerPatchOutputComponents = 120,
836 .maxTessellationControlTotalOutputComponents = 4096,
837 .maxTessellationEvaluationInputComponents = 128,
838 .maxTessellationEvaluationOutputComponents = 128,
839 .maxGeometryShaderInvocations = 127,
840 .maxGeometryInputComponents = 64,
841 .maxGeometryOutputComponents = 128,
842 .maxGeometryOutputVertices = 256,
843 .maxGeometryTotalOutputComponents = 1024,
844 .maxFragmentInputComponents = 128,
845 .maxFragmentOutputAttachments = 8,
846 .maxFragmentDualSrcAttachments = 1,
847 .maxFragmentCombinedOutputResources = 8,
848 .maxComputeSharedMemorySize = 32768,
849 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
850 .maxComputeWorkGroupInvocations = 2048,
851 .maxComputeWorkGroupSize = {
852 2048,
853 2048,
854 2048
855 },
856 .subPixelPrecisionBits = 4 /* FIXME */,
857 .subTexelPrecisionBits = 4 /* FIXME */,
858 .mipmapPrecisionBits = 4 /* FIXME */,
859 .maxDrawIndexedIndexValue = UINT32_MAX,
860 .maxDrawIndirectCount = UINT32_MAX,
861 .maxSamplerLodBias = 16,
862 .maxSamplerAnisotropy = 16,
863 .maxViewports = MAX_VIEWPORTS,
864 .maxViewportDimensions = { (1 << 14), (1 << 14) },
865 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
866 .viewportSubPixelBits = 13, /* We take a float? */
867 .minMemoryMapAlignment = 4096, /* A page */
868 .minTexelBufferOffsetAlignment = 1,
869 .minUniformBufferOffsetAlignment = 4,
870 .minStorageBufferOffsetAlignment = 4,
871 .minTexelOffset = -32,
872 .maxTexelOffset = 31,
873 .minTexelGatherOffset = -32,
874 .maxTexelGatherOffset = 31,
875 .minInterpolationOffset = -2,
876 .maxInterpolationOffset = 2,
877 .subPixelInterpolationOffsetBits = 8,
878 .maxFramebufferWidth = (1 << 14),
879 .maxFramebufferHeight = (1 << 14),
880 .maxFramebufferLayers = (1 << 10),
881 .framebufferColorSampleCounts = sample_counts,
882 .framebufferDepthSampleCounts = sample_counts,
883 .framebufferStencilSampleCounts = sample_counts,
884 .framebufferNoAttachmentsSampleCounts = sample_counts,
885 .maxColorAttachments = MAX_RTS,
886 .sampledImageColorSampleCounts = sample_counts,
887 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
888 .sampledImageDepthSampleCounts = sample_counts,
889 .sampledImageStencilSampleCounts = sample_counts,
890 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
891 .maxSampleMaskWords = 1,
892 .timestampComputeAndGraphics = true,
893 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
894 .maxClipDistances = 8,
895 .maxCullDistances = 8,
896 .maxCombinedClipAndCullDistances = 8,
897 .discreteQueuePriorities = 1,
898 .pointSizeRange = { 0.125, 255.875 },
899 .lineWidthRange = { 0.0, 7.9921875 },
900 .pointSizeGranularity = (1.0 / 8.0),
901 .lineWidthGranularity = (1.0 / 128.0),
902 .strictLines = false, /* FINISHME */
903 .standardSampleLocations = true,
904 .optimalBufferCopyOffsetAlignment = 128,
905 .optimalBufferCopyRowPitchAlignment = 128,
906 .nonCoherentAtomSize = 64,
907 };
908
909 *pProperties = (VkPhysicalDeviceProperties) {
910 .apiVersion = radv_physical_device_api_version(pdevice),
911 .driverVersion = vk_get_driver_version(),
912 .vendorID = ATI_VENDOR_ID,
913 .deviceID = pdevice->rad_info.pci_id,
914 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
915 .limits = limits,
916 .sparseProperties = {0},
917 };
918
919 strcpy(pProperties->deviceName, pdevice->name);
920 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
921 }
922
923 void radv_GetPhysicalDeviceProperties2(
924 VkPhysicalDevice physicalDevice,
925 VkPhysicalDeviceProperties2KHR *pProperties)
926 {
927 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
928 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
929
930 vk_foreach_struct(ext, pProperties->pNext) {
931 switch (ext->sType) {
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
933 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
934 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
935 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
939 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
940 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
941 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
942 properties->deviceLUIDValid = false;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
946 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
947 properties->maxMultiviewViewCount = MAX_VIEWS;
948 properties->maxMultiviewInstanceIndex = INT_MAX;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
952 VkPhysicalDevicePointClippingPropertiesKHR *properties =
953 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
954 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
958 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
959 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
960 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
964 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
965 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
966 properties->minImportedHostPointerAlignment = 4096;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
970 VkPhysicalDeviceSubgroupProperties *properties =
971 (VkPhysicalDeviceSubgroupProperties*)ext;
972 properties->subgroupSize = 64;
973 properties->supportedStages = VK_SHADER_STAGE_ALL;
974 properties->supportedOperations =
975 VK_SUBGROUP_FEATURE_BASIC_BIT |
976 VK_SUBGROUP_FEATURE_BALLOT_BIT |
977 VK_SUBGROUP_FEATURE_QUAD_BIT |
978 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
979 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
980 VK_SUBGROUP_FEATURE_VOTE_BIT;
981 properties->quadOperationsInAllStages = true;
982 break;
983 }
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
985 VkPhysicalDeviceMaintenance3Properties *properties =
986 (VkPhysicalDeviceMaintenance3Properties*)ext;
987 /* Make sure everything is addressable by a signed 32-bit int, and
988 * our largest descriptors are 96 bytes. */
989 properties->maxPerSetDescriptors = (1ull << 31) / 96;
990 /* Our buffer size fields allow only this much */
991 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
992 break;
993 }
994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
995 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
996 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
997 /* GFX6-8 only support single channel min/max filter. */
998 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
999 properties->filterMinmaxSingleComponentFormats = true;
1000 break;
1001 }
1002 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1003 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1004 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1005
1006 /* Shader engines. */
1007 properties->shaderEngineCount =
1008 pdevice->rad_info.max_se;
1009 properties->shaderArraysPerEngineCount =
1010 pdevice->rad_info.max_sh_per_se;
1011 properties->computeUnitsPerShaderArray =
1012 pdevice->rad_info.num_good_compute_units /
1013 (pdevice->rad_info.max_se *
1014 pdevice->rad_info.max_sh_per_se);
1015 properties->simdPerComputeUnit = 4;
1016 properties->wavefrontsPerSimd =
1017 pdevice->rad_info.family == CHIP_TONGA ||
1018 pdevice->rad_info.family == CHIP_ICELAND ||
1019 pdevice->rad_info.family == CHIP_POLARIS10 ||
1020 pdevice->rad_info.family == CHIP_POLARIS11 ||
1021 pdevice->rad_info.family == CHIP_POLARIS12 ||
1022 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1023 properties->wavefrontSize = 64;
1024
1025 /* SGPR. */
1026 properties->sgprsPerSimd =
1027 radv_get_num_physical_sgprs(pdevice);
1028 properties->minSgprAllocation =
1029 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1030 properties->maxSgprAllocation =
1031 pdevice->rad_info.family == CHIP_TONGA ||
1032 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1033 properties->sgprAllocationGranularity =
1034 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1035
1036 /* VGPR. */
1037 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1038 properties->minVgprAllocation = 4;
1039 properties->maxVgprAllocation = 256;
1040 properties->vgprAllocationGranularity = 4;
1041 break;
1042 }
1043 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1044 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1045 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1046 properties->maxVertexAttribDivisor = UINT32_MAX;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1050 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1051 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1052 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1053 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1054 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1055 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1056 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1057 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1058 properties->robustBufferAccessUpdateAfterBind = false;
1059 properties->quadDivergentImplicitLod = false;
1060
1061 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1062 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1063 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1064 32 /* sampler, largest when combined with image */ +
1065 64 /* sampled image */ +
1066 64 /* storage image */);
1067 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1068 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1069 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1070 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1071 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1072 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1073 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1074 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1075 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1076 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1077 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1078 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1079 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1080 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1081 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1082 break;
1083 }
1084 default:
1085 break;
1086 }
1087 }
1088 }
1089
1090 static void radv_get_physical_device_queue_family_properties(
1091 struct radv_physical_device* pdevice,
1092 uint32_t* pCount,
1093 VkQueueFamilyProperties** pQueueFamilyProperties)
1094 {
1095 int num_queue_families = 1;
1096 int idx;
1097 if (pdevice->rad_info.num_compute_rings > 0 &&
1098 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1099 num_queue_families++;
1100
1101 if (pQueueFamilyProperties == NULL) {
1102 *pCount = num_queue_families;
1103 return;
1104 }
1105
1106 if (!*pCount)
1107 return;
1108
1109 idx = 0;
1110 if (*pCount >= 1) {
1111 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1112 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1113 VK_QUEUE_COMPUTE_BIT |
1114 VK_QUEUE_TRANSFER_BIT |
1115 VK_QUEUE_SPARSE_BINDING_BIT,
1116 .queueCount = 1,
1117 .timestampValidBits = 64,
1118 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1119 };
1120 idx++;
1121 }
1122
1123 if (pdevice->rad_info.num_compute_rings > 0 &&
1124 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1125 if (*pCount > idx) {
1126 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1127 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1128 VK_QUEUE_TRANSFER_BIT |
1129 VK_QUEUE_SPARSE_BINDING_BIT,
1130 .queueCount = pdevice->rad_info.num_compute_rings,
1131 .timestampValidBits = 64,
1132 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1133 };
1134 idx++;
1135 }
1136 }
1137 *pCount = idx;
1138 }
1139
1140 void radv_GetPhysicalDeviceQueueFamilyProperties(
1141 VkPhysicalDevice physicalDevice,
1142 uint32_t* pCount,
1143 VkQueueFamilyProperties* pQueueFamilyProperties)
1144 {
1145 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1146 if (!pQueueFamilyProperties) {
1147 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1148 return;
1149 }
1150 VkQueueFamilyProperties *properties[] = {
1151 pQueueFamilyProperties + 0,
1152 pQueueFamilyProperties + 1,
1153 pQueueFamilyProperties + 2,
1154 };
1155 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1156 assert(*pCount <= 3);
1157 }
1158
1159 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1160 VkPhysicalDevice physicalDevice,
1161 uint32_t* pCount,
1162 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1163 {
1164 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1165 if (!pQueueFamilyProperties) {
1166 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1167 return;
1168 }
1169 VkQueueFamilyProperties *properties[] = {
1170 &pQueueFamilyProperties[0].queueFamilyProperties,
1171 &pQueueFamilyProperties[1].queueFamilyProperties,
1172 &pQueueFamilyProperties[2].queueFamilyProperties,
1173 };
1174 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1175 assert(*pCount <= 3);
1176 }
1177
1178 void radv_GetPhysicalDeviceMemoryProperties(
1179 VkPhysicalDevice physicalDevice,
1180 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1181 {
1182 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1183
1184 *pMemoryProperties = physical_device->memory_properties;
1185 }
1186
1187 void radv_GetPhysicalDeviceMemoryProperties2(
1188 VkPhysicalDevice physicalDevice,
1189 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1190 {
1191 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1192 &pMemoryProperties->memoryProperties);
1193 }
1194
1195 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1196 VkDevice _device,
1197 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1198 const void *pHostPointer,
1199 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1200 {
1201 RADV_FROM_HANDLE(radv_device, device, _device);
1202
1203 switch (handleType)
1204 {
1205 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1206 const struct radv_physical_device *physical_device = device->physical_device;
1207 uint32_t memoryTypeBits = 0;
1208 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1209 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1210 memoryTypeBits = (1 << i);
1211 break;
1212 }
1213 }
1214 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1215 return VK_SUCCESS;
1216 }
1217 default:
1218 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1219 }
1220 }
1221
1222 static enum radeon_ctx_priority
1223 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1224 {
1225 /* Default to MEDIUM when a specific global priority isn't requested */
1226 if (!pObj)
1227 return RADEON_CTX_PRIORITY_MEDIUM;
1228
1229 switch(pObj->globalPriority) {
1230 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1231 return RADEON_CTX_PRIORITY_REALTIME;
1232 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1233 return RADEON_CTX_PRIORITY_HIGH;
1234 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1235 return RADEON_CTX_PRIORITY_MEDIUM;
1236 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1237 return RADEON_CTX_PRIORITY_LOW;
1238 default:
1239 unreachable("Illegal global priority value");
1240 return RADEON_CTX_PRIORITY_INVALID;
1241 }
1242 }
1243
1244 static int
1245 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1246 uint32_t queue_family_index, int idx,
1247 VkDeviceQueueCreateFlags flags,
1248 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1249 {
1250 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1251 queue->device = device;
1252 queue->queue_family_index = queue_family_index;
1253 queue->queue_idx = idx;
1254 queue->priority = radv_get_queue_global_priority(global_priority);
1255 queue->flags = flags;
1256
1257 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1258 if (!queue->hw_ctx)
1259 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1260
1261 return VK_SUCCESS;
1262 }
1263
1264 static void
1265 radv_queue_finish(struct radv_queue *queue)
1266 {
1267 if (queue->hw_ctx)
1268 queue->device->ws->ctx_destroy(queue->hw_ctx);
1269
1270 if (queue->initial_full_flush_preamble_cs)
1271 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1272 if (queue->initial_preamble_cs)
1273 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1274 if (queue->continue_preamble_cs)
1275 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1276 if (queue->descriptor_bo)
1277 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1278 if (queue->scratch_bo)
1279 queue->device->ws->buffer_destroy(queue->scratch_bo);
1280 if (queue->esgs_ring_bo)
1281 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1282 if (queue->gsvs_ring_bo)
1283 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1284 if (queue->tess_rings_bo)
1285 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1286 if (queue->compute_scratch_bo)
1287 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1288 }
1289
1290 static void
1291 radv_bo_list_init(struct radv_bo_list *bo_list)
1292 {
1293 pthread_mutex_init(&bo_list->mutex, NULL);
1294 bo_list->list.count = bo_list->capacity = 0;
1295 bo_list->list.bos = NULL;
1296 }
1297
1298 static void
1299 radv_bo_list_finish(struct radv_bo_list *bo_list)
1300 {
1301 free(bo_list->list.bos);
1302 pthread_mutex_destroy(&bo_list->mutex);
1303 }
1304
1305 static VkResult radv_bo_list_add(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1306 {
1307 pthread_mutex_lock(&bo_list->mutex);
1308 if (bo_list->list.count == bo_list->capacity) {
1309 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1310 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1311
1312 if (!data) {
1313 pthread_mutex_unlock(&bo_list->mutex);
1314 return VK_ERROR_OUT_OF_HOST_MEMORY;
1315 }
1316
1317 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1318 bo_list->capacity = capacity;
1319 }
1320
1321 bo_list->list.bos[bo_list->list.count++] = bo;
1322 pthread_mutex_unlock(&bo_list->mutex);
1323 return VK_SUCCESS;
1324 }
1325
1326 static void radv_bo_list_remove(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1327 {
1328 pthread_mutex_lock(&bo_list->mutex);
1329 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1330 if (bo_list->list.bos[i] == bo) {
1331 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1332 --bo_list->list.count;
1333 break;
1334 }
1335 }
1336 pthread_mutex_unlock(&bo_list->mutex);
1337 }
1338
1339 static void
1340 radv_device_init_gs_info(struct radv_device *device)
1341 {
1342 switch (device->physical_device->rad_info.family) {
1343 case CHIP_OLAND:
1344 case CHIP_HAINAN:
1345 case CHIP_KAVERI:
1346 case CHIP_KABINI:
1347 case CHIP_MULLINS:
1348 case CHIP_ICELAND:
1349 case CHIP_CARRIZO:
1350 case CHIP_STONEY:
1351 device->gs_table_depth = 16;
1352 return;
1353 case CHIP_TAHITI:
1354 case CHIP_PITCAIRN:
1355 case CHIP_VERDE:
1356 case CHIP_BONAIRE:
1357 case CHIP_HAWAII:
1358 case CHIP_TONGA:
1359 case CHIP_FIJI:
1360 case CHIP_POLARIS10:
1361 case CHIP_POLARIS11:
1362 case CHIP_POLARIS12:
1363 case CHIP_VEGAM:
1364 case CHIP_VEGA10:
1365 case CHIP_VEGA12:
1366 case CHIP_RAVEN:
1367 device->gs_table_depth = 32;
1368 return;
1369 default:
1370 unreachable("unknown GPU");
1371 }
1372 }
1373
1374 static int radv_get_device_extension_index(const char *name)
1375 {
1376 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1377 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1378 return i;
1379 }
1380 return -1;
1381 }
1382
1383 VkResult radv_CreateDevice(
1384 VkPhysicalDevice physicalDevice,
1385 const VkDeviceCreateInfo* pCreateInfo,
1386 const VkAllocationCallbacks* pAllocator,
1387 VkDevice* pDevice)
1388 {
1389 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1390 VkResult result;
1391 struct radv_device *device;
1392
1393 bool keep_shader_info = false;
1394
1395 /* Check enabled features */
1396 if (pCreateInfo->pEnabledFeatures) {
1397 VkPhysicalDeviceFeatures supported_features;
1398 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1399 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1400 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1401 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1402 for (uint32_t i = 0; i < num_features; i++) {
1403 if (enabled_feature[i] && !supported_feature[i])
1404 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1405 }
1406 }
1407
1408 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1409 sizeof(*device), 8,
1410 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1411 if (!device)
1412 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1413
1414 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1415 device->instance = physical_device->instance;
1416 device->physical_device = physical_device;
1417
1418 device->ws = physical_device->ws;
1419 if (pAllocator)
1420 device->alloc = *pAllocator;
1421 else
1422 device->alloc = physical_device->instance->alloc;
1423
1424 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1425 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1426 int index = radv_get_device_extension_index(ext_name);
1427 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1428 vk_free(&device->alloc, device);
1429 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1430 }
1431
1432 device->enabled_extensions.extensions[index] = true;
1433 }
1434
1435 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1436
1437 mtx_init(&device->shader_slab_mutex, mtx_plain);
1438 list_inithead(&device->shader_slabs);
1439
1440 radv_bo_list_init(&device->bo_list);
1441
1442 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1443 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1444 uint32_t qfi = queue_create->queueFamilyIndex;
1445 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1446 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1447
1448 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1449
1450 device->queues[qfi] = vk_alloc(&device->alloc,
1451 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1452 if (!device->queues[qfi]) {
1453 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1454 goto fail;
1455 }
1456
1457 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1458
1459 device->queue_count[qfi] = queue_create->queueCount;
1460
1461 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1462 result = radv_queue_init(device, &device->queues[qfi][q],
1463 qfi, q, queue_create->flags,
1464 global_priority);
1465 if (result != VK_SUCCESS)
1466 goto fail;
1467 }
1468 }
1469
1470 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1471 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1472
1473 /* Disabled and not implemented for now. */
1474 device->dfsm_allowed = device->pbb_allowed && false;
1475
1476 #ifdef ANDROID
1477 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1478 #endif
1479
1480 device->llvm_supports_spill = true;
1481
1482 /* The maximum number of scratch waves. Scratch space isn't divided
1483 * evenly between CUs. The number is only a function of the number of CUs.
1484 * We can decrease the constant to decrease the scratch buffer size.
1485 *
1486 * sctx->scratch_waves must be >= the maximum posible size of
1487 * 1 threadgroup, so that the hw doesn't hang from being unable
1488 * to start any.
1489 *
1490 * The recommended value is 4 per CU at most. Higher numbers don't
1491 * bring much benefit, but they still occupy chip resources (think
1492 * async compute). I've seen ~2% performance difference between 4 and 32.
1493 */
1494 uint32_t max_threads_per_block = 2048;
1495 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1496 max_threads_per_block / 64);
1497
1498 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1499
1500 if (device->physical_device->rad_info.chip_class >= CIK) {
1501 /* If the KMD allows it (there is a KMD hw register for it),
1502 * allow launching waves out-of-order.
1503 */
1504 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1505 }
1506
1507 radv_device_init_gs_info(device);
1508
1509 device->tess_offchip_block_dw_size =
1510 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1511 device->has_distributed_tess =
1512 device->physical_device->rad_info.chip_class >= VI &&
1513 device->physical_device->rad_info.max_se >= 2;
1514
1515 if (getenv("RADV_TRACE_FILE")) {
1516 const char *filename = getenv("RADV_TRACE_FILE");
1517
1518 keep_shader_info = true;
1519
1520 if (!radv_init_trace(device))
1521 goto fail;
1522
1523 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1524 radv_dump_enabled_options(device, stderr);
1525 }
1526
1527 device->keep_shader_info = keep_shader_info;
1528
1529 result = radv_device_init_meta(device);
1530 if (result != VK_SUCCESS)
1531 goto fail;
1532
1533 radv_device_init_msaa(device);
1534
1535 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1536 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1537 switch (family) {
1538 case RADV_QUEUE_GENERAL:
1539 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1540 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1541 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1542 break;
1543 case RADV_QUEUE_COMPUTE:
1544 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1545 radeon_emit(device->empty_cs[family], 0);
1546 break;
1547 }
1548 device->ws->cs_finalize(device->empty_cs[family]);
1549 }
1550
1551 if (device->physical_device->rad_info.chip_class >= CIK)
1552 cik_create_gfx_config(device);
1553
1554 VkPipelineCacheCreateInfo ci;
1555 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1556 ci.pNext = NULL;
1557 ci.flags = 0;
1558 ci.pInitialData = NULL;
1559 ci.initialDataSize = 0;
1560 VkPipelineCache pc;
1561 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1562 &ci, NULL, &pc);
1563 if (result != VK_SUCCESS)
1564 goto fail_meta;
1565
1566 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1567
1568 *pDevice = radv_device_to_handle(device);
1569 return VK_SUCCESS;
1570
1571 fail_meta:
1572 radv_device_finish_meta(device);
1573 fail:
1574 radv_bo_list_finish(&device->bo_list);
1575
1576 if (device->trace_bo)
1577 device->ws->buffer_destroy(device->trace_bo);
1578
1579 if (device->gfx_init)
1580 device->ws->buffer_destroy(device->gfx_init);
1581
1582 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1583 for (unsigned q = 0; q < device->queue_count[i]; q++)
1584 radv_queue_finish(&device->queues[i][q]);
1585 if (device->queue_count[i])
1586 vk_free(&device->alloc, device->queues[i]);
1587 }
1588
1589 vk_free(&device->alloc, device);
1590 return result;
1591 }
1592
1593 void radv_DestroyDevice(
1594 VkDevice _device,
1595 const VkAllocationCallbacks* pAllocator)
1596 {
1597 RADV_FROM_HANDLE(radv_device, device, _device);
1598
1599 if (!device)
1600 return;
1601
1602 if (device->trace_bo)
1603 device->ws->buffer_destroy(device->trace_bo);
1604
1605 if (device->gfx_init)
1606 device->ws->buffer_destroy(device->gfx_init);
1607
1608 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1609 for (unsigned q = 0; q < device->queue_count[i]; q++)
1610 radv_queue_finish(&device->queues[i][q]);
1611 if (device->queue_count[i])
1612 vk_free(&device->alloc, device->queues[i]);
1613 if (device->empty_cs[i])
1614 device->ws->cs_destroy(device->empty_cs[i]);
1615 }
1616 radv_device_finish_meta(device);
1617
1618 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1619 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1620
1621 radv_destroy_shader_slabs(device);
1622
1623 radv_bo_list_finish(&device->bo_list);
1624 vk_free(&device->alloc, device);
1625 }
1626
1627 VkResult radv_EnumerateInstanceLayerProperties(
1628 uint32_t* pPropertyCount,
1629 VkLayerProperties* pProperties)
1630 {
1631 if (pProperties == NULL) {
1632 *pPropertyCount = 0;
1633 return VK_SUCCESS;
1634 }
1635
1636 /* None supported at this time */
1637 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1638 }
1639
1640 VkResult radv_EnumerateDeviceLayerProperties(
1641 VkPhysicalDevice physicalDevice,
1642 uint32_t* pPropertyCount,
1643 VkLayerProperties* pProperties)
1644 {
1645 if (pProperties == NULL) {
1646 *pPropertyCount = 0;
1647 return VK_SUCCESS;
1648 }
1649
1650 /* None supported at this time */
1651 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1652 }
1653
1654 void radv_GetDeviceQueue2(
1655 VkDevice _device,
1656 const VkDeviceQueueInfo2* pQueueInfo,
1657 VkQueue* pQueue)
1658 {
1659 RADV_FROM_HANDLE(radv_device, device, _device);
1660 struct radv_queue *queue;
1661
1662 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1663 if (pQueueInfo->flags != queue->flags) {
1664 /* From the Vulkan 1.1.70 spec:
1665 *
1666 * "The queue returned by vkGetDeviceQueue2 must have the same
1667 * flags value from this structure as that used at device
1668 * creation time in a VkDeviceQueueCreateInfo instance. If no
1669 * matching flags were specified at device creation time then
1670 * pQueue will return VK_NULL_HANDLE."
1671 */
1672 *pQueue = VK_NULL_HANDLE;
1673 return;
1674 }
1675
1676 *pQueue = radv_queue_to_handle(queue);
1677 }
1678
1679 void radv_GetDeviceQueue(
1680 VkDevice _device,
1681 uint32_t queueFamilyIndex,
1682 uint32_t queueIndex,
1683 VkQueue* pQueue)
1684 {
1685 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1686 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1687 .queueFamilyIndex = queueFamilyIndex,
1688 .queueIndex = queueIndex
1689 };
1690
1691 radv_GetDeviceQueue2(_device, &info, pQueue);
1692 }
1693
1694 static void
1695 fill_geom_tess_rings(struct radv_queue *queue,
1696 uint32_t *map,
1697 bool add_sample_positions,
1698 uint32_t esgs_ring_size,
1699 struct radeon_winsys_bo *esgs_ring_bo,
1700 uint32_t gsvs_ring_size,
1701 struct radeon_winsys_bo *gsvs_ring_bo,
1702 uint32_t tess_factor_ring_size,
1703 uint32_t tess_offchip_ring_offset,
1704 uint32_t tess_offchip_ring_size,
1705 struct radeon_winsys_bo *tess_rings_bo)
1706 {
1707 uint64_t esgs_va = 0, gsvs_va = 0;
1708 uint64_t tess_va = 0, tess_offchip_va = 0;
1709 uint32_t *desc = &map[4];
1710
1711 if (esgs_ring_bo)
1712 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1713 if (gsvs_ring_bo)
1714 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1715 if (tess_rings_bo) {
1716 tess_va = radv_buffer_get_va(tess_rings_bo);
1717 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1718 }
1719
1720 /* stride 0, num records - size, add tid, swizzle, elsize4,
1721 index stride 64 */
1722 desc[0] = esgs_va;
1723 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1724 S_008F04_STRIDE(0) |
1725 S_008F04_SWIZZLE_ENABLE(true);
1726 desc[2] = esgs_ring_size;
1727 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1728 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1729 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1730 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1731 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1732 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1733 S_008F0C_ELEMENT_SIZE(1) |
1734 S_008F0C_INDEX_STRIDE(3) |
1735 S_008F0C_ADD_TID_ENABLE(true);
1736
1737 desc += 4;
1738 /* GS entry for ES->GS ring */
1739 /* stride 0, num records - size, elsize0,
1740 index stride 0 */
1741 desc[0] = esgs_va;
1742 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1743 S_008F04_STRIDE(0) |
1744 S_008F04_SWIZZLE_ENABLE(false);
1745 desc[2] = esgs_ring_size;
1746 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1747 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1748 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1749 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1750 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1751 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1752 S_008F0C_ELEMENT_SIZE(0) |
1753 S_008F0C_INDEX_STRIDE(0) |
1754 S_008F0C_ADD_TID_ENABLE(false);
1755
1756 desc += 4;
1757 /* VS entry for GS->VS ring */
1758 /* stride 0, num records - size, elsize0,
1759 index stride 0 */
1760 desc[0] = gsvs_va;
1761 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1762 S_008F04_STRIDE(0) |
1763 S_008F04_SWIZZLE_ENABLE(false);
1764 desc[2] = gsvs_ring_size;
1765 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1766 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1767 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1768 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1769 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1770 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1771 S_008F0C_ELEMENT_SIZE(0) |
1772 S_008F0C_INDEX_STRIDE(0) |
1773 S_008F0C_ADD_TID_ENABLE(false);
1774 desc += 4;
1775
1776 /* stride gsvs_itemsize, num records 64
1777 elsize 4, index stride 16 */
1778 /* shader will patch stride and desc[2] */
1779 desc[0] = gsvs_va;
1780 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1781 S_008F04_STRIDE(0) |
1782 S_008F04_SWIZZLE_ENABLE(true);
1783 desc[2] = 0;
1784 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1785 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1786 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1787 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1788 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1789 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1790 S_008F0C_ELEMENT_SIZE(1) |
1791 S_008F0C_INDEX_STRIDE(1) |
1792 S_008F0C_ADD_TID_ENABLE(true);
1793 desc += 4;
1794
1795 desc[0] = tess_va;
1796 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1797 S_008F04_STRIDE(0) |
1798 S_008F04_SWIZZLE_ENABLE(false);
1799 desc[2] = tess_factor_ring_size;
1800 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1801 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1802 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1803 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1804 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1805 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1806 S_008F0C_ELEMENT_SIZE(0) |
1807 S_008F0C_INDEX_STRIDE(0) |
1808 S_008F0C_ADD_TID_ENABLE(false);
1809 desc += 4;
1810
1811 desc[0] = tess_offchip_va;
1812 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1813 S_008F04_STRIDE(0) |
1814 S_008F04_SWIZZLE_ENABLE(false);
1815 desc[2] = tess_offchip_ring_size;
1816 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1817 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1818 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1819 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1820 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1821 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1822 S_008F0C_ELEMENT_SIZE(0) |
1823 S_008F0C_INDEX_STRIDE(0) |
1824 S_008F0C_ADD_TID_ENABLE(false);
1825 desc += 4;
1826
1827 /* add sample positions after all rings */
1828 memcpy(desc, queue->device->sample_locations_1x, 8);
1829 desc += 2;
1830 memcpy(desc, queue->device->sample_locations_2x, 16);
1831 desc += 4;
1832 memcpy(desc, queue->device->sample_locations_4x, 32);
1833 desc += 8;
1834 memcpy(desc, queue->device->sample_locations_8x, 64);
1835 desc += 16;
1836 memcpy(desc, queue->device->sample_locations_16x, 128);
1837 }
1838
1839 static unsigned
1840 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1841 {
1842 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1843 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1844 device->physical_device->rad_info.family != CHIP_STONEY;
1845 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1846 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1847 device->physical_device->rad_info.max_se;
1848 unsigned offchip_granularity;
1849 unsigned hs_offchip_param;
1850 switch (device->tess_offchip_block_dw_size) {
1851 default:
1852 assert(0);
1853 /* fall through */
1854 case 8192:
1855 offchip_granularity = V_03093C_X_8K_DWORDS;
1856 break;
1857 case 4096:
1858 offchip_granularity = V_03093C_X_4K_DWORDS;
1859 break;
1860 }
1861
1862 switch (device->physical_device->rad_info.chip_class) {
1863 case SI:
1864 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1865 break;
1866 case CIK:
1867 case VI:
1868 case GFX9:
1869 default:
1870 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1871 break;
1872 }
1873
1874 *max_offchip_buffers_p = max_offchip_buffers;
1875 if (device->physical_device->rad_info.chip_class >= CIK) {
1876 if (device->physical_device->rad_info.chip_class >= VI)
1877 --max_offchip_buffers;
1878 hs_offchip_param =
1879 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1880 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1881 } else {
1882 hs_offchip_param =
1883 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1884 }
1885 return hs_offchip_param;
1886 }
1887
1888 static VkResult
1889 radv_get_preamble_cs(struct radv_queue *queue,
1890 uint32_t scratch_size,
1891 uint32_t compute_scratch_size,
1892 uint32_t esgs_ring_size,
1893 uint32_t gsvs_ring_size,
1894 bool needs_tess_rings,
1895 bool needs_sample_positions,
1896 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1897 struct radeon_winsys_cs **initial_preamble_cs,
1898 struct radeon_winsys_cs **continue_preamble_cs)
1899 {
1900 struct radeon_winsys_bo *scratch_bo = NULL;
1901 struct radeon_winsys_bo *descriptor_bo = NULL;
1902 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1903 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1904 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1905 struct radeon_winsys_bo *tess_rings_bo = NULL;
1906 struct radeon_winsys_cs *dest_cs[3] = {0};
1907 bool add_tess_rings = false, add_sample_positions = false;
1908 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1909 unsigned max_offchip_buffers;
1910 unsigned hs_offchip_param = 0;
1911 unsigned tess_offchip_ring_offset;
1912 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1913 if (!queue->has_tess_rings) {
1914 if (needs_tess_rings)
1915 add_tess_rings = true;
1916 }
1917 if (!queue->has_sample_positions) {
1918 if (needs_sample_positions)
1919 add_sample_positions = true;
1920 }
1921 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1922 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1923 &max_offchip_buffers);
1924 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1925 tess_offchip_ring_size = max_offchip_buffers *
1926 queue->device->tess_offchip_block_dw_size * 4;
1927
1928 if (scratch_size <= queue->scratch_size &&
1929 compute_scratch_size <= queue->compute_scratch_size &&
1930 esgs_ring_size <= queue->esgs_ring_size &&
1931 gsvs_ring_size <= queue->gsvs_ring_size &&
1932 !add_tess_rings && !add_sample_positions &&
1933 queue->initial_preamble_cs) {
1934 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1935 *initial_preamble_cs = queue->initial_preamble_cs;
1936 *continue_preamble_cs = queue->continue_preamble_cs;
1937 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1938 *continue_preamble_cs = NULL;
1939 return VK_SUCCESS;
1940 }
1941
1942 if (scratch_size > queue->scratch_size) {
1943 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1944 scratch_size,
1945 4096,
1946 RADEON_DOMAIN_VRAM,
1947 ring_bo_flags);
1948 if (!scratch_bo)
1949 goto fail;
1950 } else
1951 scratch_bo = queue->scratch_bo;
1952
1953 if (compute_scratch_size > queue->compute_scratch_size) {
1954 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1955 compute_scratch_size,
1956 4096,
1957 RADEON_DOMAIN_VRAM,
1958 ring_bo_flags);
1959 if (!compute_scratch_bo)
1960 goto fail;
1961
1962 } else
1963 compute_scratch_bo = queue->compute_scratch_bo;
1964
1965 if (esgs_ring_size > queue->esgs_ring_size) {
1966 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1967 esgs_ring_size,
1968 4096,
1969 RADEON_DOMAIN_VRAM,
1970 ring_bo_flags);
1971 if (!esgs_ring_bo)
1972 goto fail;
1973 } else {
1974 esgs_ring_bo = queue->esgs_ring_bo;
1975 esgs_ring_size = queue->esgs_ring_size;
1976 }
1977
1978 if (gsvs_ring_size > queue->gsvs_ring_size) {
1979 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1980 gsvs_ring_size,
1981 4096,
1982 RADEON_DOMAIN_VRAM,
1983 ring_bo_flags);
1984 if (!gsvs_ring_bo)
1985 goto fail;
1986 } else {
1987 gsvs_ring_bo = queue->gsvs_ring_bo;
1988 gsvs_ring_size = queue->gsvs_ring_size;
1989 }
1990
1991 if (add_tess_rings) {
1992 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1993 tess_offchip_ring_offset + tess_offchip_ring_size,
1994 256,
1995 RADEON_DOMAIN_VRAM,
1996 ring_bo_flags);
1997 if (!tess_rings_bo)
1998 goto fail;
1999 } else {
2000 tess_rings_bo = queue->tess_rings_bo;
2001 }
2002
2003 if (scratch_bo != queue->scratch_bo ||
2004 esgs_ring_bo != queue->esgs_ring_bo ||
2005 gsvs_ring_bo != queue->gsvs_ring_bo ||
2006 tess_rings_bo != queue->tess_rings_bo ||
2007 add_sample_positions) {
2008 uint32_t size = 0;
2009 if (gsvs_ring_bo || esgs_ring_bo ||
2010 tess_rings_bo || add_sample_positions) {
2011 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2012 if (add_sample_positions)
2013 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2014 }
2015 else if (scratch_bo)
2016 size = 8; /* 2 dword */
2017
2018 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2019 size,
2020 4096,
2021 RADEON_DOMAIN_VRAM,
2022 RADEON_FLAG_CPU_ACCESS |
2023 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2024 RADEON_FLAG_READ_ONLY);
2025 if (!descriptor_bo)
2026 goto fail;
2027 } else
2028 descriptor_bo = queue->descriptor_bo;
2029
2030 for(int i = 0; i < 3; ++i) {
2031 struct radeon_winsys_cs *cs = NULL;
2032 cs = queue->device->ws->cs_create(queue->device->ws,
2033 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2034 if (!cs)
2035 goto fail;
2036
2037 dest_cs[i] = cs;
2038
2039 if (scratch_bo)
2040 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2041
2042 if (esgs_ring_bo)
2043 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
2044
2045 if (gsvs_ring_bo)
2046 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
2047
2048 if (tess_rings_bo)
2049 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
2050
2051 if (descriptor_bo)
2052 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2053
2054 if (descriptor_bo != queue->descriptor_bo) {
2055 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2056
2057 if (scratch_bo) {
2058 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2059 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2060 S_008F04_SWIZZLE_ENABLE(1);
2061 map[0] = scratch_va;
2062 map[1] = rsrc1;
2063 }
2064
2065 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2066 add_sample_positions)
2067 fill_geom_tess_rings(queue, map, add_sample_positions,
2068 esgs_ring_size, esgs_ring_bo,
2069 gsvs_ring_size, gsvs_ring_bo,
2070 tess_factor_ring_size,
2071 tess_offchip_ring_offset,
2072 tess_offchip_ring_size,
2073 tess_rings_bo);
2074
2075 queue->device->ws->buffer_unmap(descriptor_bo);
2076 }
2077
2078 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2079 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2080 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2081 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2082 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2083 }
2084
2085 if (esgs_ring_bo || gsvs_ring_bo) {
2086 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2087 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2088 radeon_emit(cs, esgs_ring_size >> 8);
2089 radeon_emit(cs, gsvs_ring_size >> 8);
2090 } else {
2091 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2092 radeon_emit(cs, esgs_ring_size >> 8);
2093 radeon_emit(cs, gsvs_ring_size >> 8);
2094 }
2095 }
2096
2097 if (tess_rings_bo) {
2098 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
2099 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2100 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2101 S_030938_SIZE(tess_factor_ring_size / 4));
2102 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2103 tf_va >> 8);
2104 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2105 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2106 S_030944_BASE_HI(tf_va >> 40));
2107 }
2108 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
2109 } else {
2110 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2111 S_008988_SIZE(tess_factor_ring_size / 4));
2112 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2113 tf_va >> 8);
2114 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2115 hs_offchip_param);
2116 }
2117 }
2118
2119 if (descriptor_bo) {
2120 uint64_t va = radv_buffer_get_va(descriptor_bo);
2121 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2122 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2123 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2124 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2125 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2126
2127 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2128 radeon_set_sh_reg_seq(cs, regs[i], 2);
2129 radeon_emit(cs, va);
2130 radeon_emit(cs, va >> 32);
2131 }
2132 } else {
2133 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2134 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2135 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2136 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2137 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2138 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2139
2140 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2141 radeon_set_sh_reg_seq(cs, regs[i], 2);
2142 radeon_emit(cs, va);
2143 radeon_emit(cs, va >> 32);
2144 }
2145 }
2146 }
2147
2148 if (compute_scratch_bo) {
2149 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2150 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2151 S_008F04_SWIZZLE_ENABLE(1);
2152
2153 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2154
2155 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2156 radeon_emit(cs, scratch_va);
2157 radeon_emit(cs, rsrc1);
2158 }
2159
2160 if (i == 0) {
2161 si_cs_emit_cache_flush(cs,
2162 queue->device->physical_device->rad_info.chip_class,
2163 NULL, 0,
2164 queue->queue_family_index == RING_COMPUTE &&
2165 queue->device->physical_device->rad_info.chip_class >= CIK,
2166 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2167 RADV_CMD_FLAG_INV_ICACHE |
2168 RADV_CMD_FLAG_INV_SMEM_L1 |
2169 RADV_CMD_FLAG_INV_VMEM_L1 |
2170 RADV_CMD_FLAG_INV_GLOBAL_L2);
2171 } else if (i == 1) {
2172 si_cs_emit_cache_flush(cs,
2173 queue->device->physical_device->rad_info.chip_class,
2174 NULL, 0,
2175 queue->queue_family_index == RING_COMPUTE &&
2176 queue->device->physical_device->rad_info.chip_class >= CIK,
2177 RADV_CMD_FLAG_INV_ICACHE |
2178 RADV_CMD_FLAG_INV_SMEM_L1 |
2179 RADV_CMD_FLAG_INV_VMEM_L1 |
2180 RADV_CMD_FLAG_INV_GLOBAL_L2);
2181 }
2182
2183 if (!queue->device->ws->cs_finalize(cs))
2184 goto fail;
2185 }
2186
2187 if (queue->initial_full_flush_preamble_cs)
2188 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2189
2190 if (queue->initial_preamble_cs)
2191 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2192
2193 if (queue->continue_preamble_cs)
2194 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2195
2196 queue->initial_full_flush_preamble_cs = dest_cs[0];
2197 queue->initial_preamble_cs = dest_cs[1];
2198 queue->continue_preamble_cs = dest_cs[2];
2199
2200 if (scratch_bo != queue->scratch_bo) {
2201 if (queue->scratch_bo)
2202 queue->device->ws->buffer_destroy(queue->scratch_bo);
2203 queue->scratch_bo = scratch_bo;
2204 queue->scratch_size = scratch_size;
2205 }
2206
2207 if (compute_scratch_bo != queue->compute_scratch_bo) {
2208 if (queue->compute_scratch_bo)
2209 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2210 queue->compute_scratch_bo = compute_scratch_bo;
2211 queue->compute_scratch_size = compute_scratch_size;
2212 }
2213
2214 if (esgs_ring_bo != queue->esgs_ring_bo) {
2215 if (queue->esgs_ring_bo)
2216 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2217 queue->esgs_ring_bo = esgs_ring_bo;
2218 queue->esgs_ring_size = esgs_ring_size;
2219 }
2220
2221 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2222 if (queue->gsvs_ring_bo)
2223 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2224 queue->gsvs_ring_bo = gsvs_ring_bo;
2225 queue->gsvs_ring_size = gsvs_ring_size;
2226 }
2227
2228 if (tess_rings_bo != queue->tess_rings_bo) {
2229 queue->tess_rings_bo = tess_rings_bo;
2230 queue->has_tess_rings = true;
2231 }
2232
2233 if (descriptor_bo != queue->descriptor_bo) {
2234 if (queue->descriptor_bo)
2235 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2236
2237 queue->descriptor_bo = descriptor_bo;
2238 }
2239
2240 if (add_sample_positions)
2241 queue->has_sample_positions = true;
2242
2243 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2244 *initial_preamble_cs = queue->initial_preamble_cs;
2245 *continue_preamble_cs = queue->continue_preamble_cs;
2246 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2247 *continue_preamble_cs = NULL;
2248 return VK_SUCCESS;
2249 fail:
2250 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2251 if (dest_cs[i])
2252 queue->device->ws->cs_destroy(dest_cs[i]);
2253 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2254 queue->device->ws->buffer_destroy(descriptor_bo);
2255 if (scratch_bo && scratch_bo != queue->scratch_bo)
2256 queue->device->ws->buffer_destroy(scratch_bo);
2257 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2258 queue->device->ws->buffer_destroy(compute_scratch_bo);
2259 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2260 queue->device->ws->buffer_destroy(esgs_ring_bo);
2261 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2262 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2263 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2264 queue->device->ws->buffer_destroy(tess_rings_bo);
2265 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2266 }
2267
2268 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2269 int num_sems,
2270 const VkSemaphore *sems,
2271 VkFence _fence,
2272 bool reset_temp)
2273 {
2274 int syncobj_idx = 0, sem_idx = 0;
2275
2276 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2277 return VK_SUCCESS;
2278
2279 for (uint32_t i = 0; i < num_sems; i++) {
2280 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2281
2282 if (sem->temp_syncobj || sem->syncobj)
2283 counts->syncobj_count++;
2284 else
2285 counts->sem_count++;
2286 }
2287
2288 if (_fence != VK_NULL_HANDLE) {
2289 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2290 if (fence->temp_syncobj || fence->syncobj)
2291 counts->syncobj_count++;
2292 }
2293
2294 if (counts->syncobj_count) {
2295 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2296 if (!counts->syncobj)
2297 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2298 }
2299
2300 if (counts->sem_count) {
2301 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2302 if (!counts->sem) {
2303 free(counts->syncobj);
2304 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2305 }
2306 }
2307
2308 for (uint32_t i = 0; i < num_sems; i++) {
2309 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2310
2311 if (sem->temp_syncobj) {
2312 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2313 }
2314 else if (sem->syncobj)
2315 counts->syncobj[syncobj_idx++] = sem->syncobj;
2316 else {
2317 assert(sem->sem);
2318 counts->sem[sem_idx++] = sem->sem;
2319 }
2320 }
2321
2322 if (_fence != VK_NULL_HANDLE) {
2323 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2324 if (fence->temp_syncobj)
2325 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2326 else if (fence->syncobj)
2327 counts->syncobj[syncobj_idx++] = fence->syncobj;
2328 }
2329
2330 return VK_SUCCESS;
2331 }
2332
2333 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2334 {
2335 free(sem_info->wait.syncobj);
2336 free(sem_info->wait.sem);
2337 free(sem_info->signal.syncobj);
2338 free(sem_info->signal.sem);
2339 }
2340
2341
2342 static void radv_free_temp_syncobjs(struct radv_device *device,
2343 int num_sems,
2344 const VkSemaphore *sems)
2345 {
2346 for (uint32_t i = 0; i < num_sems; i++) {
2347 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2348
2349 if (sem->temp_syncobj) {
2350 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2351 sem->temp_syncobj = 0;
2352 }
2353 }
2354 }
2355
2356 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2357 int num_wait_sems,
2358 const VkSemaphore *wait_sems,
2359 int num_signal_sems,
2360 const VkSemaphore *signal_sems,
2361 VkFence fence)
2362 {
2363 VkResult ret;
2364 memset(sem_info, 0, sizeof(*sem_info));
2365
2366 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2367 if (ret)
2368 return ret;
2369 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2370 if (ret)
2371 radv_free_sem_info(sem_info);
2372
2373 /* caller can override these */
2374 sem_info->cs_emit_wait = true;
2375 sem_info->cs_emit_signal = true;
2376 return ret;
2377 }
2378
2379 /* Signals fence as soon as all the work currently put on queue is done. */
2380 static VkResult radv_signal_fence(struct radv_queue *queue,
2381 struct radv_fence *fence)
2382 {
2383 int ret;
2384 VkResult result;
2385 struct radv_winsys_sem_info sem_info;
2386
2387 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2388 radv_fence_to_handle(fence));
2389 if (result != VK_SUCCESS)
2390 return result;
2391
2392 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2393 &queue->device->empty_cs[queue->queue_family_index],
2394 1, NULL, NULL, &sem_info, NULL,
2395 false, fence->fence);
2396 radv_free_sem_info(&sem_info);
2397
2398 /* TODO: find a better error */
2399 if (ret)
2400 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2401
2402 return VK_SUCCESS;
2403 }
2404
2405 VkResult radv_QueueSubmit(
2406 VkQueue _queue,
2407 uint32_t submitCount,
2408 const VkSubmitInfo* pSubmits,
2409 VkFence _fence)
2410 {
2411 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2412 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2413 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2414 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2415 int ret;
2416 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2417 uint32_t scratch_size = 0;
2418 uint32_t compute_scratch_size = 0;
2419 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2420 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2421 VkResult result;
2422 bool fence_emitted = false;
2423 bool tess_rings_needed = false;
2424 bool sample_positions_needed = false;
2425
2426 /* Do this first so failing to allocate scratch buffers can't result in
2427 * partially executed submissions. */
2428 for (uint32_t i = 0; i < submitCount; i++) {
2429 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2430 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2431 pSubmits[i].pCommandBuffers[j]);
2432
2433 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2434 compute_scratch_size = MAX2(compute_scratch_size,
2435 cmd_buffer->compute_scratch_size_needed);
2436 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2437 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2438 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2439 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2440 }
2441 }
2442
2443 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2444 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2445 sample_positions_needed, &initial_flush_preamble_cs,
2446 &initial_preamble_cs, &continue_preamble_cs);
2447 if (result != VK_SUCCESS)
2448 return result;
2449
2450 for (uint32_t i = 0; i < submitCount; i++) {
2451 struct radeon_winsys_cs **cs_array;
2452 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2453 bool can_patch = true;
2454 uint32_t advance;
2455 struct radv_winsys_sem_info sem_info;
2456
2457 result = radv_alloc_sem_info(&sem_info,
2458 pSubmits[i].waitSemaphoreCount,
2459 pSubmits[i].pWaitSemaphores,
2460 pSubmits[i].signalSemaphoreCount,
2461 pSubmits[i].pSignalSemaphores,
2462 _fence);
2463 if (result != VK_SUCCESS)
2464 return result;
2465
2466 if (!pSubmits[i].commandBufferCount) {
2467 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2468 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2469 &queue->device->empty_cs[queue->queue_family_index],
2470 1, NULL, NULL,
2471 &sem_info, NULL,
2472 false, base_fence);
2473 if (ret) {
2474 radv_loge("failed to submit CS %d\n", i);
2475 abort();
2476 }
2477 fence_emitted = true;
2478 }
2479 radv_free_sem_info(&sem_info);
2480 continue;
2481 }
2482
2483 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2484 (pSubmits[i].commandBufferCount));
2485
2486 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2487 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2488 pSubmits[i].pCommandBuffers[j]);
2489 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2490
2491 cs_array[j] = cmd_buffer->cs;
2492 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2493 can_patch = false;
2494
2495 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2496 }
2497
2498 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2499 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2500 advance = MIN2(max_cs_submission,
2501 pSubmits[i].commandBufferCount - j);
2502
2503 if (queue->device->trace_bo)
2504 *queue->device->trace_id_ptr = 0;
2505
2506 sem_info.cs_emit_wait = j == 0;
2507 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2508
2509 pthread_mutex_lock(&queue->device->bo_list.mutex);
2510
2511 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2512 advance, initial_preamble, continue_preamble_cs,
2513 &sem_info, &queue->device->bo_list.list,
2514 can_patch, base_fence);
2515
2516 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2517
2518 if (ret) {
2519 radv_loge("failed to submit CS %d\n", i);
2520 abort();
2521 }
2522 fence_emitted = true;
2523 if (queue->device->trace_bo) {
2524 radv_check_gpu_hangs(queue, cs_array[j]);
2525 }
2526 }
2527
2528 radv_free_temp_syncobjs(queue->device,
2529 pSubmits[i].waitSemaphoreCount,
2530 pSubmits[i].pWaitSemaphores);
2531 radv_free_sem_info(&sem_info);
2532 free(cs_array);
2533 }
2534
2535 if (fence) {
2536 if (!fence_emitted) {
2537 radv_signal_fence(queue, fence);
2538 }
2539 fence->submitted = true;
2540 }
2541
2542 return VK_SUCCESS;
2543 }
2544
2545 VkResult radv_QueueWaitIdle(
2546 VkQueue _queue)
2547 {
2548 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2549
2550 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2551 radv_queue_family_to_ring(queue->queue_family_index),
2552 queue->queue_idx);
2553 return VK_SUCCESS;
2554 }
2555
2556 VkResult radv_DeviceWaitIdle(
2557 VkDevice _device)
2558 {
2559 RADV_FROM_HANDLE(radv_device, device, _device);
2560
2561 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2562 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2563 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2564 }
2565 }
2566 return VK_SUCCESS;
2567 }
2568
2569 VkResult radv_EnumerateInstanceExtensionProperties(
2570 const char* pLayerName,
2571 uint32_t* pPropertyCount,
2572 VkExtensionProperties* pProperties)
2573 {
2574 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2575
2576 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2577 if (radv_supported_instance_extensions.extensions[i]) {
2578 vk_outarray_append(&out, prop) {
2579 *prop = radv_instance_extensions[i];
2580 }
2581 }
2582 }
2583
2584 return vk_outarray_status(&out);
2585 }
2586
2587 VkResult radv_EnumerateDeviceExtensionProperties(
2588 VkPhysicalDevice physicalDevice,
2589 const char* pLayerName,
2590 uint32_t* pPropertyCount,
2591 VkExtensionProperties* pProperties)
2592 {
2593 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2594 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2595
2596 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2597 if (device->supported_extensions.extensions[i]) {
2598 vk_outarray_append(&out, prop) {
2599 *prop = radv_device_extensions[i];
2600 }
2601 }
2602 }
2603
2604 return vk_outarray_status(&out);
2605 }
2606
2607 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2608 VkInstance _instance,
2609 const char* pName)
2610 {
2611 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2612
2613 return radv_lookup_entrypoint_checked(pName,
2614 instance ? instance->apiVersion : 0,
2615 instance ? &instance->enabled_extensions : NULL,
2616 NULL);
2617 }
2618
2619 /* The loader wants us to expose a second GetInstanceProcAddr function
2620 * to work around certain LD_PRELOAD issues seen in apps.
2621 */
2622 PUBLIC
2623 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2624 VkInstance instance,
2625 const char* pName);
2626
2627 PUBLIC
2628 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2629 VkInstance instance,
2630 const char* pName)
2631 {
2632 return radv_GetInstanceProcAddr(instance, pName);
2633 }
2634
2635 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2636 VkDevice _device,
2637 const char* pName)
2638 {
2639 RADV_FROM_HANDLE(radv_device, device, _device);
2640
2641 return radv_lookup_entrypoint_checked(pName,
2642 device->instance->apiVersion,
2643 &device->instance->enabled_extensions,
2644 &device->enabled_extensions);
2645 }
2646
2647 bool radv_get_memory_fd(struct radv_device *device,
2648 struct radv_device_memory *memory,
2649 int *pFD)
2650 {
2651 struct radeon_bo_metadata metadata;
2652
2653 if (memory->image) {
2654 radv_init_metadata(device, memory->image, &metadata);
2655 device->ws->buffer_set_metadata(memory->bo, &metadata);
2656 }
2657
2658 return device->ws->buffer_get_fd(device->ws, memory->bo,
2659 pFD);
2660 }
2661
2662 static VkResult radv_alloc_memory(struct radv_device *device,
2663 const VkMemoryAllocateInfo* pAllocateInfo,
2664 const VkAllocationCallbacks* pAllocator,
2665 VkDeviceMemory* pMem)
2666 {
2667 struct radv_device_memory *mem;
2668 VkResult result;
2669 enum radeon_bo_domain domain;
2670 uint32_t flags = 0;
2671 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2672
2673 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2674
2675 if (pAllocateInfo->allocationSize == 0) {
2676 /* Apparently, this is allowed */
2677 *pMem = VK_NULL_HANDLE;
2678 return VK_SUCCESS;
2679 }
2680
2681 const VkImportMemoryFdInfoKHR *import_info =
2682 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2683 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2684 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2685 const VkExportMemoryAllocateInfoKHR *export_info =
2686 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2687 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2688 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2689
2690 const struct wsi_memory_allocate_info *wsi_info =
2691 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2692
2693 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2694 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2695 if (mem == NULL)
2696 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2697
2698 if (wsi_info && wsi_info->implicit_sync)
2699 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2700
2701 if (dedicate_info) {
2702 mem->image = radv_image_from_handle(dedicate_info->image);
2703 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2704 } else {
2705 mem->image = NULL;
2706 mem->buffer = NULL;
2707 }
2708
2709 mem->user_ptr = NULL;
2710
2711 if (import_info) {
2712 assert(import_info->handleType ==
2713 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2714 import_info->handleType ==
2715 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2716 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2717 NULL, NULL);
2718 if (!mem->bo) {
2719 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2720 goto fail;
2721 } else {
2722 close(import_info->fd);
2723 }
2724 } else if (host_ptr_info) {
2725 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2726 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2727 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2728 pAllocateInfo->allocationSize);
2729 if (!mem->bo) {
2730 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2731 goto fail;
2732 } else {
2733 mem->user_ptr = host_ptr_info->pHostPointer;
2734 }
2735 } else {
2736 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2737 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2738 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2739 domain = RADEON_DOMAIN_GTT;
2740 else
2741 domain = RADEON_DOMAIN_VRAM;
2742
2743 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2744 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2745 else
2746 flags |= RADEON_FLAG_CPU_ACCESS;
2747
2748 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2749 flags |= RADEON_FLAG_GTT_WC;
2750
2751 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2752 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2753
2754 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2755 domain, flags);
2756
2757 if (!mem->bo) {
2758 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2759 goto fail;
2760 }
2761 mem->type_index = mem_type_index;
2762 }
2763
2764 result = radv_bo_list_add(&device->bo_list, mem->bo);
2765 if (result != VK_SUCCESS)
2766 goto fail_bo;
2767
2768 *pMem = radv_device_memory_to_handle(mem);
2769
2770 return VK_SUCCESS;
2771
2772 fail_bo:
2773 device->ws->buffer_destroy(mem->bo);
2774 fail:
2775 vk_free2(&device->alloc, pAllocator, mem);
2776
2777 return result;
2778 }
2779
2780 VkResult radv_AllocateMemory(
2781 VkDevice _device,
2782 const VkMemoryAllocateInfo* pAllocateInfo,
2783 const VkAllocationCallbacks* pAllocator,
2784 VkDeviceMemory* pMem)
2785 {
2786 RADV_FROM_HANDLE(radv_device, device, _device);
2787 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2788 }
2789
2790 void radv_FreeMemory(
2791 VkDevice _device,
2792 VkDeviceMemory _mem,
2793 const VkAllocationCallbacks* pAllocator)
2794 {
2795 RADV_FROM_HANDLE(radv_device, device, _device);
2796 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2797
2798 if (mem == NULL)
2799 return;
2800
2801 radv_bo_list_remove(&device->bo_list, mem->bo);
2802 device->ws->buffer_destroy(mem->bo);
2803 mem->bo = NULL;
2804
2805 vk_free2(&device->alloc, pAllocator, mem);
2806 }
2807
2808 VkResult radv_MapMemory(
2809 VkDevice _device,
2810 VkDeviceMemory _memory,
2811 VkDeviceSize offset,
2812 VkDeviceSize size,
2813 VkMemoryMapFlags flags,
2814 void** ppData)
2815 {
2816 RADV_FROM_HANDLE(radv_device, device, _device);
2817 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2818
2819 if (mem == NULL) {
2820 *ppData = NULL;
2821 return VK_SUCCESS;
2822 }
2823
2824 if (mem->user_ptr)
2825 *ppData = mem->user_ptr;
2826 else
2827 *ppData = device->ws->buffer_map(mem->bo);
2828
2829 if (*ppData) {
2830 *ppData += offset;
2831 return VK_SUCCESS;
2832 }
2833
2834 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2835 }
2836
2837 void radv_UnmapMemory(
2838 VkDevice _device,
2839 VkDeviceMemory _memory)
2840 {
2841 RADV_FROM_HANDLE(radv_device, device, _device);
2842 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2843
2844 if (mem == NULL)
2845 return;
2846
2847 if (mem->user_ptr == NULL)
2848 device->ws->buffer_unmap(mem->bo);
2849 }
2850
2851 VkResult radv_FlushMappedMemoryRanges(
2852 VkDevice _device,
2853 uint32_t memoryRangeCount,
2854 const VkMappedMemoryRange* pMemoryRanges)
2855 {
2856 return VK_SUCCESS;
2857 }
2858
2859 VkResult radv_InvalidateMappedMemoryRanges(
2860 VkDevice _device,
2861 uint32_t memoryRangeCount,
2862 const VkMappedMemoryRange* pMemoryRanges)
2863 {
2864 return VK_SUCCESS;
2865 }
2866
2867 void radv_GetBufferMemoryRequirements(
2868 VkDevice _device,
2869 VkBuffer _buffer,
2870 VkMemoryRequirements* pMemoryRequirements)
2871 {
2872 RADV_FROM_HANDLE(radv_device, device, _device);
2873 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2874
2875 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2876
2877 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2878 pMemoryRequirements->alignment = 4096;
2879 else
2880 pMemoryRequirements->alignment = 16;
2881
2882 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2883 }
2884
2885 void radv_GetBufferMemoryRequirements2(
2886 VkDevice device,
2887 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2888 VkMemoryRequirements2KHR* pMemoryRequirements)
2889 {
2890 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2891 &pMemoryRequirements->memoryRequirements);
2892 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2893 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2894 switch (ext->sType) {
2895 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2896 VkMemoryDedicatedRequirementsKHR *req =
2897 (VkMemoryDedicatedRequirementsKHR *) ext;
2898 req->requiresDedicatedAllocation = buffer->shareable;
2899 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2900 break;
2901 }
2902 default:
2903 break;
2904 }
2905 }
2906 }
2907
2908 void radv_GetImageMemoryRequirements(
2909 VkDevice _device,
2910 VkImage _image,
2911 VkMemoryRequirements* pMemoryRequirements)
2912 {
2913 RADV_FROM_HANDLE(radv_device, device, _device);
2914 RADV_FROM_HANDLE(radv_image, image, _image);
2915
2916 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2917
2918 pMemoryRequirements->size = image->size;
2919 pMemoryRequirements->alignment = image->alignment;
2920 }
2921
2922 void radv_GetImageMemoryRequirements2(
2923 VkDevice device,
2924 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2925 VkMemoryRequirements2KHR* pMemoryRequirements)
2926 {
2927 radv_GetImageMemoryRequirements(device, pInfo->image,
2928 &pMemoryRequirements->memoryRequirements);
2929
2930 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2931
2932 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2933 switch (ext->sType) {
2934 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2935 VkMemoryDedicatedRequirementsKHR *req =
2936 (VkMemoryDedicatedRequirementsKHR *) ext;
2937 req->requiresDedicatedAllocation = image->shareable;
2938 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2939 break;
2940 }
2941 default:
2942 break;
2943 }
2944 }
2945 }
2946
2947 void radv_GetImageSparseMemoryRequirements(
2948 VkDevice device,
2949 VkImage image,
2950 uint32_t* pSparseMemoryRequirementCount,
2951 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2952 {
2953 stub();
2954 }
2955
2956 void radv_GetImageSparseMemoryRequirements2(
2957 VkDevice device,
2958 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2959 uint32_t* pSparseMemoryRequirementCount,
2960 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2961 {
2962 stub();
2963 }
2964
2965 void radv_GetDeviceMemoryCommitment(
2966 VkDevice device,
2967 VkDeviceMemory memory,
2968 VkDeviceSize* pCommittedMemoryInBytes)
2969 {
2970 *pCommittedMemoryInBytes = 0;
2971 }
2972
2973 VkResult radv_BindBufferMemory2(VkDevice device,
2974 uint32_t bindInfoCount,
2975 const VkBindBufferMemoryInfoKHR *pBindInfos)
2976 {
2977 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2978 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2979 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2980
2981 if (mem) {
2982 buffer->bo = mem->bo;
2983 buffer->offset = pBindInfos[i].memoryOffset;
2984 } else {
2985 buffer->bo = NULL;
2986 }
2987 }
2988 return VK_SUCCESS;
2989 }
2990
2991 VkResult radv_BindBufferMemory(
2992 VkDevice device,
2993 VkBuffer buffer,
2994 VkDeviceMemory memory,
2995 VkDeviceSize memoryOffset)
2996 {
2997 const VkBindBufferMemoryInfoKHR info = {
2998 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2999 .buffer = buffer,
3000 .memory = memory,
3001 .memoryOffset = memoryOffset
3002 };
3003
3004 return radv_BindBufferMemory2(device, 1, &info);
3005 }
3006
3007 VkResult radv_BindImageMemory2(VkDevice device,
3008 uint32_t bindInfoCount,
3009 const VkBindImageMemoryInfoKHR *pBindInfos)
3010 {
3011 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3012 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3013 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3014
3015 if (mem) {
3016 image->bo = mem->bo;
3017 image->offset = pBindInfos[i].memoryOffset;
3018 } else {
3019 image->bo = NULL;
3020 image->offset = 0;
3021 }
3022 }
3023 return VK_SUCCESS;
3024 }
3025
3026
3027 VkResult radv_BindImageMemory(
3028 VkDevice device,
3029 VkImage image,
3030 VkDeviceMemory memory,
3031 VkDeviceSize memoryOffset)
3032 {
3033 const VkBindImageMemoryInfoKHR info = {
3034 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3035 .image = image,
3036 .memory = memory,
3037 .memoryOffset = memoryOffset
3038 };
3039
3040 return radv_BindImageMemory2(device, 1, &info);
3041 }
3042
3043
3044 static void
3045 radv_sparse_buffer_bind_memory(struct radv_device *device,
3046 const VkSparseBufferMemoryBindInfo *bind)
3047 {
3048 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3049
3050 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3051 struct radv_device_memory *mem = NULL;
3052
3053 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3054 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3055
3056 device->ws->buffer_virtual_bind(buffer->bo,
3057 bind->pBinds[i].resourceOffset,
3058 bind->pBinds[i].size,
3059 mem ? mem->bo : NULL,
3060 bind->pBinds[i].memoryOffset);
3061 }
3062 }
3063
3064 static void
3065 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3066 const VkSparseImageOpaqueMemoryBindInfo *bind)
3067 {
3068 RADV_FROM_HANDLE(radv_image, image, bind->image);
3069
3070 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3071 struct radv_device_memory *mem = NULL;
3072
3073 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3074 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3075
3076 device->ws->buffer_virtual_bind(image->bo,
3077 bind->pBinds[i].resourceOffset,
3078 bind->pBinds[i].size,
3079 mem ? mem->bo : NULL,
3080 bind->pBinds[i].memoryOffset);
3081 }
3082 }
3083
3084 VkResult radv_QueueBindSparse(
3085 VkQueue _queue,
3086 uint32_t bindInfoCount,
3087 const VkBindSparseInfo* pBindInfo,
3088 VkFence _fence)
3089 {
3090 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3091 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3092 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3093 bool fence_emitted = false;
3094
3095 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3096 struct radv_winsys_sem_info sem_info;
3097 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3098 radv_sparse_buffer_bind_memory(queue->device,
3099 pBindInfo[i].pBufferBinds + j);
3100 }
3101
3102 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3103 radv_sparse_image_opaque_bind_memory(queue->device,
3104 pBindInfo[i].pImageOpaqueBinds + j);
3105 }
3106
3107 VkResult result;
3108 result = radv_alloc_sem_info(&sem_info,
3109 pBindInfo[i].waitSemaphoreCount,
3110 pBindInfo[i].pWaitSemaphores,
3111 pBindInfo[i].signalSemaphoreCount,
3112 pBindInfo[i].pSignalSemaphores,
3113 _fence);
3114 if (result != VK_SUCCESS)
3115 return result;
3116
3117 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3118 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3119 &queue->device->empty_cs[queue->queue_family_index],
3120 1, NULL, NULL,
3121 &sem_info, NULL,
3122 false, base_fence);
3123 fence_emitted = true;
3124 if (fence)
3125 fence->submitted = true;
3126 }
3127
3128 radv_free_sem_info(&sem_info);
3129
3130 }
3131
3132 if (fence) {
3133 if (!fence_emitted) {
3134 radv_signal_fence(queue, fence);
3135 }
3136 fence->submitted = true;
3137 }
3138
3139 return VK_SUCCESS;
3140 }
3141
3142 VkResult radv_CreateFence(
3143 VkDevice _device,
3144 const VkFenceCreateInfo* pCreateInfo,
3145 const VkAllocationCallbacks* pAllocator,
3146 VkFence* pFence)
3147 {
3148 RADV_FROM_HANDLE(radv_device, device, _device);
3149 const VkExportFenceCreateInfoKHR *export =
3150 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3151 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3152 export ? export->handleTypes : 0;
3153
3154 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3155 sizeof(*fence), 8,
3156 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3157
3158 if (!fence)
3159 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3160
3161 fence->submitted = false;
3162 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3163 fence->temp_syncobj = 0;
3164 if (device->always_use_syncobj || handleTypes) {
3165 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3166 if (ret) {
3167 vk_free2(&device->alloc, pAllocator, fence);
3168 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3169 }
3170 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3171 device->ws->signal_syncobj(device->ws, fence->syncobj);
3172 }
3173 fence->fence = NULL;
3174 } else {
3175 fence->fence = device->ws->create_fence();
3176 if (!fence->fence) {
3177 vk_free2(&device->alloc, pAllocator, fence);
3178 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3179 }
3180 fence->syncobj = 0;
3181 }
3182
3183 *pFence = radv_fence_to_handle(fence);
3184
3185 return VK_SUCCESS;
3186 }
3187
3188 void radv_DestroyFence(
3189 VkDevice _device,
3190 VkFence _fence,
3191 const VkAllocationCallbacks* pAllocator)
3192 {
3193 RADV_FROM_HANDLE(radv_device, device, _device);
3194 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3195
3196 if (!fence)
3197 return;
3198
3199 if (fence->temp_syncobj)
3200 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3201 if (fence->syncobj)
3202 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3203 if (fence->fence)
3204 device->ws->destroy_fence(fence->fence);
3205 vk_free2(&device->alloc, pAllocator, fence);
3206 }
3207
3208
3209 static uint64_t radv_get_current_time()
3210 {
3211 struct timespec tv;
3212 clock_gettime(CLOCK_MONOTONIC, &tv);
3213 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3214 }
3215
3216 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3217 {
3218 uint64_t current_time = radv_get_current_time();
3219
3220 timeout = MIN2(UINT64_MAX - current_time, timeout);
3221
3222 return current_time + timeout;
3223 }
3224
3225
3226 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3227 {
3228 for (uint32_t i = 0; i < fenceCount; ++i) {
3229 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3230 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3231 return false;
3232 }
3233 return true;
3234 }
3235
3236 VkResult radv_WaitForFences(
3237 VkDevice _device,
3238 uint32_t fenceCount,
3239 const VkFence* pFences,
3240 VkBool32 waitAll,
3241 uint64_t timeout)
3242 {
3243 RADV_FROM_HANDLE(radv_device, device, _device);
3244 timeout = radv_get_absolute_timeout(timeout);
3245
3246 if (device->always_use_syncobj) {
3247 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3248 if (!handles)
3249 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3250
3251 for (uint32_t i = 0; i < fenceCount; ++i) {
3252 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3253 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3254 }
3255
3256 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3257
3258 free(handles);
3259 return success ? VK_SUCCESS : VK_TIMEOUT;
3260 }
3261
3262 if (!waitAll && fenceCount > 1) {
3263 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3264 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3265 uint32_t wait_count = 0;
3266 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3267 if (!fences)
3268 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3269
3270 for (uint32_t i = 0; i < fenceCount; ++i) {
3271 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3272
3273 if (fence->signalled) {
3274 free(fences);
3275 return VK_SUCCESS;
3276 }
3277
3278 fences[wait_count++] = fence->fence;
3279 }
3280
3281 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3282 waitAll, timeout - radv_get_current_time());
3283
3284 free(fences);
3285 return success ? VK_SUCCESS : VK_TIMEOUT;
3286 }
3287
3288 while(radv_get_current_time() <= timeout) {
3289 for (uint32_t i = 0; i < fenceCount; ++i) {
3290 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3291 return VK_SUCCESS;
3292 }
3293 }
3294 return VK_TIMEOUT;
3295 }
3296
3297 for (uint32_t i = 0; i < fenceCount; ++i) {
3298 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3299 bool expired = false;
3300
3301 if (fence->temp_syncobj) {
3302 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3303 return VK_TIMEOUT;
3304 continue;
3305 }
3306
3307 if (fence->syncobj) {
3308 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3309 return VK_TIMEOUT;
3310 continue;
3311 }
3312
3313 if (fence->signalled)
3314 continue;
3315
3316 if (!fence->submitted) {
3317 while(radv_get_current_time() <= timeout && !fence->submitted)
3318 /* Do nothing */;
3319
3320 if (!fence->submitted)
3321 return VK_TIMEOUT;
3322
3323 /* Recheck as it may have been set by submitting operations. */
3324 if (fence->signalled)
3325 continue;
3326 }
3327
3328 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3329 if (!expired)
3330 return VK_TIMEOUT;
3331
3332 fence->signalled = true;
3333 }
3334
3335 return VK_SUCCESS;
3336 }
3337
3338 VkResult radv_ResetFences(VkDevice _device,
3339 uint32_t fenceCount,
3340 const VkFence *pFences)
3341 {
3342 RADV_FROM_HANDLE(radv_device, device, _device);
3343
3344 for (unsigned i = 0; i < fenceCount; ++i) {
3345 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3346 fence->submitted = fence->signalled = false;
3347
3348 /* Per spec, we first restore the permanent payload, and then reset, so
3349 * having a temp syncobj should not skip resetting the permanent syncobj. */
3350 if (fence->temp_syncobj) {
3351 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3352 fence->temp_syncobj = 0;
3353 }
3354
3355 if (fence->syncobj) {
3356 device->ws->reset_syncobj(device->ws, fence->syncobj);
3357 }
3358 }
3359
3360 return VK_SUCCESS;
3361 }
3362
3363 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3364 {
3365 RADV_FROM_HANDLE(radv_device, device, _device);
3366 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3367
3368 if (fence->temp_syncobj) {
3369 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3370 return success ? VK_SUCCESS : VK_NOT_READY;
3371 }
3372
3373 if (fence->syncobj) {
3374 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3375 return success ? VK_SUCCESS : VK_NOT_READY;
3376 }
3377
3378 if (fence->signalled)
3379 return VK_SUCCESS;
3380 if (!fence->submitted)
3381 return VK_NOT_READY;
3382 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3383 return VK_NOT_READY;
3384
3385 return VK_SUCCESS;
3386 }
3387
3388
3389 // Queue semaphore functions
3390
3391 VkResult radv_CreateSemaphore(
3392 VkDevice _device,
3393 const VkSemaphoreCreateInfo* pCreateInfo,
3394 const VkAllocationCallbacks* pAllocator,
3395 VkSemaphore* pSemaphore)
3396 {
3397 RADV_FROM_HANDLE(radv_device, device, _device);
3398 const VkExportSemaphoreCreateInfoKHR *export =
3399 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3400 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3401 export ? export->handleTypes : 0;
3402
3403 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3404 sizeof(*sem), 8,
3405 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3406 if (!sem)
3407 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3408
3409 sem->temp_syncobj = 0;
3410 /* create a syncobject if we are going to export this semaphore */
3411 if (device->always_use_syncobj || handleTypes) {
3412 assert (device->physical_device->rad_info.has_syncobj);
3413 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3414 if (ret) {
3415 vk_free2(&device->alloc, pAllocator, sem);
3416 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3417 }
3418 sem->sem = NULL;
3419 } else {
3420 sem->sem = device->ws->create_sem(device->ws);
3421 if (!sem->sem) {
3422 vk_free2(&device->alloc, pAllocator, sem);
3423 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3424 }
3425 sem->syncobj = 0;
3426 }
3427
3428 *pSemaphore = radv_semaphore_to_handle(sem);
3429 return VK_SUCCESS;
3430 }
3431
3432 void radv_DestroySemaphore(
3433 VkDevice _device,
3434 VkSemaphore _semaphore,
3435 const VkAllocationCallbacks* pAllocator)
3436 {
3437 RADV_FROM_HANDLE(radv_device, device, _device);
3438 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3439 if (!_semaphore)
3440 return;
3441
3442 if (sem->syncobj)
3443 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3444 else
3445 device->ws->destroy_sem(sem->sem);
3446 vk_free2(&device->alloc, pAllocator, sem);
3447 }
3448
3449 VkResult radv_CreateEvent(
3450 VkDevice _device,
3451 const VkEventCreateInfo* pCreateInfo,
3452 const VkAllocationCallbacks* pAllocator,
3453 VkEvent* pEvent)
3454 {
3455 RADV_FROM_HANDLE(radv_device, device, _device);
3456 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3457 sizeof(*event), 8,
3458 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3459
3460 if (!event)
3461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3462
3463 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3464 RADEON_DOMAIN_GTT,
3465 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3466 if (!event->bo) {
3467 vk_free2(&device->alloc, pAllocator, event);
3468 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3469 }
3470
3471 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3472
3473 *pEvent = radv_event_to_handle(event);
3474
3475 return VK_SUCCESS;
3476 }
3477
3478 void radv_DestroyEvent(
3479 VkDevice _device,
3480 VkEvent _event,
3481 const VkAllocationCallbacks* pAllocator)
3482 {
3483 RADV_FROM_HANDLE(radv_device, device, _device);
3484 RADV_FROM_HANDLE(radv_event, event, _event);
3485
3486 if (!event)
3487 return;
3488 device->ws->buffer_destroy(event->bo);
3489 vk_free2(&device->alloc, pAllocator, event);
3490 }
3491
3492 VkResult radv_GetEventStatus(
3493 VkDevice _device,
3494 VkEvent _event)
3495 {
3496 RADV_FROM_HANDLE(radv_event, event, _event);
3497
3498 if (*event->map == 1)
3499 return VK_EVENT_SET;
3500 return VK_EVENT_RESET;
3501 }
3502
3503 VkResult radv_SetEvent(
3504 VkDevice _device,
3505 VkEvent _event)
3506 {
3507 RADV_FROM_HANDLE(radv_event, event, _event);
3508 *event->map = 1;
3509
3510 return VK_SUCCESS;
3511 }
3512
3513 VkResult radv_ResetEvent(
3514 VkDevice _device,
3515 VkEvent _event)
3516 {
3517 RADV_FROM_HANDLE(radv_event, event, _event);
3518 *event->map = 0;
3519
3520 return VK_SUCCESS;
3521 }
3522
3523 VkResult radv_CreateBuffer(
3524 VkDevice _device,
3525 const VkBufferCreateInfo* pCreateInfo,
3526 const VkAllocationCallbacks* pAllocator,
3527 VkBuffer* pBuffer)
3528 {
3529 RADV_FROM_HANDLE(radv_device, device, _device);
3530 struct radv_buffer *buffer;
3531
3532 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3533
3534 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3535 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3536 if (buffer == NULL)
3537 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3538
3539 buffer->size = pCreateInfo->size;
3540 buffer->usage = pCreateInfo->usage;
3541 buffer->bo = NULL;
3542 buffer->offset = 0;
3543 buffer->flags = pCreateInfo->flags;
3544
3545 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3546 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3547
3548 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3549 buffer->bo = device->ws->buffer_create(device->ws,
3550 align64(buffer->size, 4096),
3551 4096, 0, RADEON_FLAG_VIRTUAL);
3552 if (!buffer->bo) {
3553 vk_free2(&device->alloc, pAllocator, buffer);
3554 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3555 }
3556 }
3557
3558 *pBuffer = radv_buffer_to_handle(buffer);
3559
3560 return VK_SUCCESS;
3561 }
3562
3563 void radv_DestroyBuffer(
3564 VkDevice _device,
3565 VkBuffer _buffer,
3566 const VkAllocationCallbacks* pAllocator)
3567 {
3568 RADV_FROM_HANDLE(radv_device, device, _device);
3569 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3570
3571 if (!buffer)
3572 return;
3573
3574 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3575 device->ws->buffer_destroy(buffer->bo);
3576
3577 vk_free2(&device->alloc, pAllocator, buffer);
3578 }
3579
3580 static inline unsigned
3581 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3582 {
3583 if (stencil)
3584 return image->surface.u.legacy.stencil_tiling_index[level];
3585 else
3586 return image->surface.u.legacy.tiling_index[level];
3587 }
3588
3589 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3590 {
3591 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3592 }
3593
3594 static uint32_t
3595 radv_init_dcc_control_reg(struct radv_device *device,
3596 struct radv_image_view *iview)
3597 {
3598 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3599 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3600 unsigned max_compressed_block_size;
3601 unsigned independent_64b_blocks;
3602
3603 if (device->physical_device->rad_info.chip_class < VI)
3604 return 0;
3605
3606 if (iview->image->info.samples > 1) {
3607 if (iview->image->surface.bpe == 1)
3608 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3609 else if (iview->image->surface.bpe == 2)
3610 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3611 }
3612
3613 if (!device->physical_device->rad_info.has_dedicated_vram) {
3614 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3615 * dGPU and 64 for APU because all of our APUs to date use
3616 * DIMMs which have a request granularity size of 64B while all
3617 * other chips have a 32B request size.
3618 */
3619 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3620 }
3621
3622 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3623 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3624 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3625 /* If this DCC image is potentially going to be used in texture
3626 * fetches, we need some special settings.
3627 */
3628 independent_64b_blocks = 1;
3629 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3630 } else {
3631 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3632 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3633 * big as possible for better compression state.
3634 */
3635 independent_64b_blocks = 0;
3636 max_compressed_block_size = max_uncompressed_block_size;
3637 }
3638
3639 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3640 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3641 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3642 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3643 }
3644
3645 static void
3646 radv_initialise_color_surface(struct radv_device *device,
3647 struct radv_color_buffer_info *cb,
3648 struct radv_image_view *iview)
3649 {
3650 const struct vk_format_description *desc;
3651 unsigned ntype, format, swap, endian;
3652 unsigned blend_clamp = 0, blend_bypass = 0;
3653 uint64_t va;
3654 const struct radeon_surf *surf = &iview->image->surface;
3655
3656 desc = vk_format_description(iview->vk_format);
3657
3658 memset(cb, 0, sizeof(*cb));
3659
3660 /* Intensity is implemented as Red, so treat it that way. */
3661 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3662
3663 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3664
3665 cb->cb_color_base = va >> 8;
3666
3667 if (device->physical_device->rad_info.chip_class >= GFX9) {
3668 struct gfx9_surf_meta_flags meta;
3669 if (iview->image->dcc_offset)
3670 meta = iview->image->surface.u.gfx9.dcc;
3671 else
3672 meta = iview->image->surface.u.gfx9.cmask;
3673
3674 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3675 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3676 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3677 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3678
3679 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3680 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3681 } else {
3682 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3683 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3684
3685 cb->cb_color_base += level_info->offset >> 8;
3686 if (level_info->mode == RADEON_SURF_MODE_2D)
3687 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3688
3689 pitch_tile_max = level_info->nblk_x / 8 - 1;
3690 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3691 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3692
3693 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3694 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3695 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3696
3697 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3698
3699 if (radv_image_has_fmask(iview->image)) {
3700 if (device->physical_device->rad_info.chip_class >= CIK)
3701 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3702 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3703 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3704 } else {
3705 /* This must be set for fast clear to work without FMASK. */
3706 if (device->physical_device->rad_info.chip_class >= CIK)
3707 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3708 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3709 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3710 }
3711 }
3712
3713 /* CMASK variables */
3714 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3715 va += iview->image->cmask.offset;
3716 cb->cb_color_cmask = va >> 8;
3717
3718 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3719 va += iview->image->dcc_offset;
3720 cb->cb_dcc_base = va >> 8;
3721 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3722
3723 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3724 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3725 S_028C6C_SLICE_MAX(max_slice);
3726
3727 if (iview->image->info.samples > 1) {
3728 unsigned log_samples = util_logbase2(iview->image->info.samples);
3729
3730 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3731 S_028C74_NUM_FRAGMENTS(log_samples);
3732 }
3733
3734 if (radv_image_has_fmask(iview->image)) {
3735 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3736 cb->cb_color_fmask = va >> 8;
3737 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3738 } else {
3739 cb->cb_color_fmask = cb->cb_color_base;
3740 }
3741
3742 ntype = radv_translate_color_numformat(iview->vk_format,
3743 desc,
3744 vk_format_get_first_non_void_channel(iview->vk_format));
3745 format = radv_translate_colorformat(iview->vk_format);
3746 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3747 radv_finishme("Illegal color\n");
3748 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3749 endian = radv_colorformat_endian_swap(format);
3750
3751 /* blend clamp should be set for all NORM/SRGB types */
3752 if (ntype == V_028C70_NUMBER_UNORM ||
3753 ntype == V_028C70_NUMBER_SNORM ||
3754 ntype == V_028C70_NUMBER_SRGB)
3755 blend_clamp = 1;
3756
3757 /* set blend bypass according to docs if SINT/UINT or
3758 8/24 COLOR variants */
3759 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3760 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3761 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3762 blend_clamp = 0;
3763 blend_bypass = 1;
3764 }
3765 #if 0
3766 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3767 (format == V_028C70_COLOR_8 ||
3768 format == V_028C70_COLOR_8_8 ||
3769 format == V_028C70_COLOR_8_8_8_8))
3770 ->color_is_int8 = true;
3771 #endif
3772 cb->cb_color_info = S_028C70_FORMAT(format) |
3773 S_028C70_COMP_SWAP(swap) |
3774 S_028C70_BLEND_CLAMP(blend_clamp) |
3775 S_028C70_BLEND_BYPASS(blend_bypass) |
3776 S_028C70_SIMPLE_FLOAT(1) |
3777 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3778 ntype != V_028C70_NUMBER_SNORM &&
3779 ntype != V_028C70_NUMBER_SRGB &&
3780 format != V_028C70_COLOR_8_24 &&
3781 format != V_028C70_COLOR_24_8) |
3782 S_028C70_NUMBER_TYPE(ntype) |
3783 S_028C70_ENDIAN(endian);
3784 if (radv_image_has_fmask(iview->image)) {
3785 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3786 if (device->physical_device->rad_info.chip_class == SI) {
3787 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3788 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3789 }
3790 }
3791
3792 if (radv_image_has_cmask(iview->image) &&
3793 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3794 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3795
3796 if (radv_dcc_enabled(iview->image, iview->base_mip))
3797 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3798
3799 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3800
3801 /* This must be set for fast clear to work without FMASK. */
3802 if (!radv_image_has_fmask(iview->image) &&
3803 device->physical_device->rad_info.chip_class == SI) {
3804 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3805 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3806 }
3807
3808 if (device->physical_device->rad_info.chip_class >= GFX9) {
3809 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3810 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3811
3812 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3813 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3814 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3815 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3816 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3817 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3818 }
3819 }
3820
3821 static unsigned
3822 radv_calc_decompress_on_z_planes(struct radv_device *device,
3823 struct radv_image_view *iview)
3824 {
3825 unsigned max_zplanes = 0;
3826
3827 assert(radv_image_is_tc_compat_htile(iview->image));
3828
3829 if (device->physical_device->rad_info.chip_class >= GFX9) {
3830 /* Default value for 32-bit depth surfaces. */
3831 max_zplanes = 4;
3832
3833 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3834 iview->image->info.samples > 1)
3835 max_zplanes = 2;
3836
3837 max_zplanes = max_zplanes + 1;
3838 } else {
3839 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3840 /* Do not enable Z plane compression for 16-bit depth
3841 * surfaces because isn't supported on GFX8. Only
3842 * 32-bit depth surfaces are supported by the hardware.
3843 * This allows to maintain shader compatibility and to
3844 * reduce the number of depth decompressions.
3845 */
3846 max_zplanes = 1;
3847 } else {
3848 if (iview->image->info.samples <= 1)
3849 max_zplanes = 5;
3850 else if (iview->image->info.samples <= 4)
3851 max_zplanes = 3;
3852 else
3853 max_zplanes = 2;
3854 }
3855 }
3856
3857 return max_zplanes;
3858 }
3859
3860 static void
3861 radv_initialise_ds_surface(struct radv_device *device,
3862 struct radv_ds_buffer_info *ds,
3863 struct radv_image_view *iview)
3864 {
3865 unsigned level = iview->base_mip;
3866 unsigned format, stencil_format;
3867 uint64_t va, s_offs, z_offs;
3868 bool stencil_only = false;
3869 memset(ds, 0, sizeof(*ds));
3870 switch (iview->image->vk_format) {
3871 case VK_FORMAT_D24_UNORM_S8_UINT:
3872 case VK_FORMAT_X8_D24_UNORM_PACK32:
3873 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3874 ds->offset_scale = 2.0f;
3875 break;
3876 case VK_FORMAT_D16_UNORM:
3877 case VK_FORMAT_D16_UNORM_S8_UINT:
3878 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3879 ds->offset_scale = 4.0f;
3880 break;
3881 case VK_FORMAT_D32_SFLOAT:
3882 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3883 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3884 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3885 ds->offset_scale = 1.0f;
3886 break;
3887 case VK_FORMAT_S8_UINT:
3888 stencil_only = true;
3889 break;
3890 default:
3891 break;
3892 }
3893
3894 format = radv_translate_dbformat(iview->image->vk_format);
3895 stencil_format = iview->image->surface.has_stencil ?
3896 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3897
3898 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3899 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3900 S_028008_SLICE_MAX(max_slice);
3901
3902 ds->db_htile_data_base = 0;
3903 ds->db_htile_surface = 0;
3904
3905 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3906 s_offs = z_offs = va;
3907
3908 if (device->physical_device->rad_info.chip_class >= GFX9) {
3909 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3910 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3911
3912 ds->db_z_info = S_028038_FORMAT(format) |
3913 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3914 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3915 S_028038_MAXMIP(iview->image->info.levels - 1);
3916 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3917 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3918
3919 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3920 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3921 ds->db_depth_view |= S_028008_MIPID(level);
3922
3923 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3924 S_02801C_Y_MAX(iview->image->info.height - 1);
3925
3926 if (radv_htile_enabled(iview->image, level)) {
3927 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3928
3929 if (radv_image_is_tc_compat_htile(iview->image)) {
3930 unsigned max_zplanes =
3931 radv_calc_decompress_on_z_planes(device, iview);
3932
3933 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3934 S_028038_ITERATE_FLUSH(1);
3935 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3936 }
3937
3938 if (!iview->image->surface.has_stencil)
3939 /* Use all of the htile_buffer for depth if there's no stencil. */
3940 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3941 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3942 iview->image->htile_offset;
3943 ds->db_htile_data_base = va >> 8;
3944 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3945 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3946 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3947 }
3948 } else {
3949 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3950
3951 if (stencil_only)
3952 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3953
3954 z_offs += iview->image->surface.u.legacy.level[level].offset;
3955 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3956
3957 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3958 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3959 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3960
3961 if (iview->image->info.samples > 1)
3962 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3963
3964 if (device->physical_device->rad_info.chip_class >= CIK) {
3965 struct radeon_info *info = &device->physical_device->rad_info;
3966 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3967 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3968 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3969 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3970 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3971 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3972
3973 if (stencil_only)
3974 tile_mode = stencil_tile_mode;
3975
3976 ds->db_depth_info |=
3977 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3978 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3979 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3980 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3981 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3982 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3983 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3984 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3985 } else {
3986 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3987 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3988 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3989 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3990 if (stencil_only)
3991 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3992 }
3993
3994 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3995 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3996 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3997
3998 if (radv_htile_enabled(iview->image, level)) {
3999 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4000
4001 if (!iview->image->surface.has_stencil &&
4002 !radv_image_is_tc_compat_htile(iview->image))
4003 /* Use all of the htile_buffer for depth if there's no stencil. */
4004 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4005
4006 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4007 iview->image->htile_offset;
4008 ds->db_htile_data_base = va >> 8;
4009 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4010
4011 if (radv_image_is_tc_compat_htile(iview->image)) {
4012 unsigned max_zplanes =
4013 radv_calc_decompress_on_z_planes(device, iview);
4014
4015 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4016 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4017 }
4018 }
4019 }
4020
4021 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4022 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4023 }
4024
4025 VkResult radv_CreateFramebuffer(
4026 VkDevice _device,
4027 const VkFramebufferCreateInfo* pCreateInfo,
4028 const VkAllocationCallbacks* pAllocator,
4029 VkFramebuffer* pFramebuffer)
4030 {
4031 RADV_FROM_HANDLE(radv_device, device, _device);
4032 struct radv_framebuffer *framebuffer;
4033
4034 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4035
4036 size_t size = sizeof(*framebuffer) +
4037 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4038 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4039 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4040 if (framebuffer == NULL)
4041 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4042
4043 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4044 framebuffer->width = pCreateInfo->width;
4045 framebuffer->height = pCreateInfo->height;
4046 framebuffer->layers = pCreateInfo->layers;
4047 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4048 VkImageView _iview = pCreateInfo->pAttachments[i];
4049 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4050 framebuffer->attachments[i].attachment = iview;
4051 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4052 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4053 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4054 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4055 }
4056 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4057 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4058 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4059 }
4060
4061 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4062 return VK_SUCCESS;
4063 }
4064
4065 void radv_DestroyFramebuffer(
4066 VkDevice _device,
4067 VkFramebuffer _fb,
4068 const VkAllocationCallbacks* pAllocator)
4069 {
4070 RADV_FROM_HANDLE(radv_device, device, _device);
4071 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4072
4073 if (!fb)
4074 return;
4075 vk_free2(&device->alloc, pAllocator, fb);
4076 }
4077
4078 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4079 {
4080 switch (address_mode) {
4081 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4082 return V_008F30_SQ_TEX_WRAP;
4083 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4084 return V_008F30_SQ_TEX_MIRROR;
4085 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4086 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4087 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4088 return V_008F30_SQ_TEX_CLAMP_BORDER;
4089 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4090 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4091 default:
4092 unreachable("illegal tex wrap mode");
4093 break;
4094 }
4095 }
4096
4097 static unsigned
4098 radv_tex_compare(VkCompareOp op)
4099 {
4100 switch (op) {
4101 case VK_COMPARE_OP_NEVER:
4102 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4103 case VK_COMPARE_OP_LESS:
4104 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4105 case VK_COMPARE_OP_EQUAL:
4106 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4107 case VK_COMPARE_OP_LESS_OR_EQUAL:
4108 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4109 case VK_COMPARE_OP_GREATER:
4110 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4111 case VK_COMPARE_OP_NOT_EQUAL:
4112 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4113 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4114 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4115 case VK_COMPARE_OP_ALWAYS:
4116 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4117 default:
4118 unreachable("illegal compare mode");
4119 break;
4120 }
4121 }
4122
4123 static unsigned
4124 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4125 {
4126 switch (filter) {
4127 case VK_FILTER_NEAREST:
4128 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4129 V_008F38_SQ_TEX_XY_FILTER_POINT);
4130 case VK_FILTER_LINEAR:
4131 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4132 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4133 case VK_FILTER_CUBIC_IMG:
4134 default:
4135 fprintf(stderr, "illegal texture filter");
4136 return 0;
4137 }
4138 }
4139
4140 static unsigned
4141 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4142 {
4143 switch (mode) {
4144 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4145 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4146 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4147 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4148 default:
4149 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4150 }
4151 }
4152
4153 static unsigned
4154 radv_tex_bordercolor(VkBorderColor bcolor)
4155 {
4156 switch (bcolor) {
4157 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4158 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4159 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4160 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4161 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4162 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4163 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4164 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4165 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4166 default:
4167 break;
4168 }
4169 return 0;
4170 }
4171
4172 static unsigned
4173 radv_tex_aniso_filter(unsigned filter)
4174 {
4175 if (filter < 2)
4176 return 0;
4177 if (filter < 4)
4178 return 1;
4179 if (filter < 8)
4180 return 2;
4181 if (filter < 16)
4182 return 3;
4183 return 4;
4184 }
4185
4186 static unsigned
4187 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4188 {
4189 switch (mode) {
4190 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4191 return SQ_IMG_FILTER_MODE_BLEND;
4192 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4193 return SQ_IMG_FILTER_MODE_MIN;
4194 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4195 return SQ_IMG_FILTER_MODE_MAX;
4196 default:
4197 break;
4198 }
4199 return 0;
4200 }
4201
4202 static void
4203 radv_init_sampler(struct radv_device *device,
4204 struct radv_sampler *sampler,
4205 const VkSamplerCreateInfo *pCreateInfo)
4206 {
4207 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4208 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4209 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4210 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4211 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4212
4213 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4214 vk_find_struct_const(pCreateInfo->pNext,
4215 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4216 if (sampler_reduction)
4217 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4218
4219 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4220 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4221 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4222 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4223 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4224 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4225 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4226 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4227 S_008F30_DISABLE_CUBE_WRAP(0) |
4228 S_008F30_COMPAT_MODE(is_vi) |
4229 S_008F30_FILTER_MODE(filter_mode));
4230 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4231 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4232 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4233 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4234 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4235 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4236 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4237 S_008F38_MIP_POINT_PRECLAMP(0) |
4238 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4239 S_008F38_FILTER_PREC_FIX(1) |
4240 S_008F38_ANISO_OVERRIDE(is_vi));
4241 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4242 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4243 }
4244
4245 VkResult radv_CreateSampler(
4246 VkDevice _device,
4247 const VkSamplerCreateInfo* pCreateInfo,
4248 const VkAllocationCallbacks* pAllocator,
4249 VkSampler* pSampler)
4250 {
4251 RADV_FROM_HANDLE(radv_device, device, _device);
4252 struct radv_sampler *sampler;
4253
4254 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4255
4256 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4257 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4258 if (!sampler)
4259 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4260
4261 radv_init_sampler(device, sampler, pCreateInfo);
4262 *pSampler = radv_sampler_to_handle(sampler);
4263
4264 return VK_SUCCESS;
4265 }
4266
4267 void radv_DestroySampler(
4268 VkDevice _device,
4269 VkSampler _sampler,
4270 const VkAllocationCallbacks* pAllocator)
4271 {
4272 RADV_FROM_HANDLE(radv_device, device, _device);
4273 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4274
4275 if (!sampler)
4276 return;
4277 vk_free2(&device->alloc, pAllocator, sampler);
4278 }
4279
4280 /* vk_icd.h does not declare this function, so we declare it here to
4281 * suppress Wmissing-prototypes.
4282 */
4283 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4284 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4285
4286 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4287 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4288 {
4289 /* For the full details on loader interface versioning, see
4290 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4291 * What follows is a condensed summary, to help you navigate the large and
4292 * confusing official doc.
4293 *
4294 * - Loader interface v0 is incompatible with later versions. We don't
4295 * support it.
4296 *
4297 * - In loader interface v1:
4298 * - The first ICD entrypoint called by the loader is
4299 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4300 * entrypoint.
4301 * - The ICD must statically expose no other Vulkan symbol unless it is
4302 * linked with -Bsymbolic.
4303 * - Each dispatchable Vulkan handle created by the ICD must be
4304 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4305 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4306 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4307 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4308 * such loader-managed surfaces.
4309 *
4310 * - Loader interface v2 differs from v1 in:
4311 * - The first ICD entrypoint called by the loader is
4312 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4313 * statically expose this entrypoint.
4314 *
4315 * - Loader interface v3 differs from v2 in:
4316 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4317 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4318 * because the loader no longer does so.
4319 */
4320 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4321 return VK_SUCCESS;
4322 }
4323
4324 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4325 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4326 int *pFD)
4327 {
4328 RADV_FROM_HANDLE(radv_device, device, _device);
4329 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4330
4331 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4332
4333 /* At the moment, we support only the below handle types. */
4334 assert(pGetFdInfo->handleType ==
4335 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4336 pGetFdInfo->handleType ==
4337 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4338
4339 bool ret = radv_get_memory_fd(device, memory, pFD);
4340 if (ret == false)
4341 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4342 return VK_SUCCESS;
4343 }
4344
4345 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4346 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4347 int fd,
4348 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4349 {
4350 switch (handleType) {
4351 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4352 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4353 return VK_SUCCESS;
4354
4355 default:
4356 /* The valid usage section for this function says:
4357 *
4358 * "handleType must not be one of the handle types defined as
4359 * opaque."
4360 *
4361 * So opaque handle types fall into the default "unsupported" case.
4362 */
4363 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4364 }
4365 }
4366
4367 static VkResult radv_import_opaque_fd(struct radv_device *device,
4368 int fd,
4369 uint32_t *syncobj)
4370 {
4371 uint32_t syncobj_handle = 0;
4372 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4373 if (ret != 0)
4374 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4375
4376 if (*syncobj)
4377 device->ws->destroy_syncobj(device->ws, *syncobj);
4378
4379 *syncobj = syncobj_handle;
4380 close(fd);
4381
4382 return VK_SUCCESS;
4383 }
4384
4385 static VkResult radv_import_sync_fd(struct radv_device *device,
4386 int fd,
4387 uint32_t *syncobj)
4388 {
4389 /* If we create a syncobj we do it locally so that if we have an error, we don't
4390 * leave a syncobj in an undetermined state in the fence. */
4391 uint32_t syncobj_handle = *syncobj;
4392 if (!syncobj_handle) {
4393 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4394 if (ret) {
4395 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4396 }
4397 }
4398
4399 if (fd == -1) {
4400 device->ws->signal_syncobj(device->ws, syncobj_handle);
4401 } else {
4402 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4403 if (ret != 0)
4404 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4405 }
4406
4407 *syncobj = syncobj_handle;
4408 if (fd != -1)
4409 close(fd);
4410
4411 return VK_SUCCESS;
4412 }
4413
4414 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4415 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4416 {
4417 RADV_FROM_HANDLE(radv_device, device, _device);
4418 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4419 uint32_t *syncobj_dst = NULL;
4420
4421 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4422 syncobj_dst = &sem->temp_syncobj;
4423 } else {
4424 syncobj_dst = &sem->syncobj;
4425 }
4426
4427 switch(pImportSemaphoreFdInfo->handleType) {
4428 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4429 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4430 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4431 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4432 default:
4433 unreachable("Unhandled semaphore handle type");
4434 }
4435 }
4436
4437 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4438 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4439 int *pFd)
4440 {
4441 RADV_FROM_HANDLE(radv_device, device, _device);
4442 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4443 int ret;
4444 uint32_t syncobj_handle;
4445
4446 if (sem->temp_syncobj)
4447 syncobj_handle = sem->temp_syncobj;
4448 else
4449 syncobj_handle = sem->syncobj;
4450
4451 switch(pGetFdInfo->handleType) {
4452 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4453 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4454 break;
4455 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4456 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4457 if (!ret) {
4458 if (sem->temp_syncobj) {
4459 close (sem->temp_syncobj);
4460 sem->temp_syncobj = 0;
4461 } else {
4462 device->ws->reset_syncobj(device->ws, syncobj_handle);
4463 }
4464 }
4465 break;
4466 default:
4467 unreachable("Unhandled semaphore handle type");
4468 }
4469
4470 if (ret)
4471 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4472 return VK_SUCCESS;
4473 }
4474
4475 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4476 VkPhysicalDevice physicalDevice,
4477 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4478 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4479 {
4480 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4481
4482 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4483 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4484 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4485 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4486 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4487 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4488 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4489 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4490 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4491 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4492 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4493 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4494 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4495 } else {
4496 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4497 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4498 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4499 }
4500 }
4501
4502 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4503 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4504 {
4505 RADV_FROM_HANDLE(radv_device, device, _device);
4506 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4507 uint32_t *syncobj_dst = NULL;
4508
4509
4510 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4511 syncobj_dst = &fence->temp_syncobj;
4512 } else {
4513 syncobj_dst = &fence->syncobj;
4514 }
4515
4516 switch(pImportFenceFdInfo->handleType) {
4517 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4518 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4519 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4520 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4521 default:
4522 unreachable("Unhandled fence handle type");
4523 }
4524 }
4525
4526 VkResult radv_GetFenceFdKHR(VkDevice _device,
4527 const VkFenceGetFdInfoKHR *pGetFdInfo,
4528 int *pFd)
4529 {
4530 RADV_FROM_HANDLE(radv_device, device, _device);
4531 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4532 int ret;
4533 uint32_t syncobj_handle;
4534
4535 if (fence->temp_syncobj)
4536 syncobj_handle = fence->temp_syncobj;
4537 else
4538 syncobj_handle = fence->syncobj;
4539
4540 switch(pGetFdInfo->handleType) {
4541 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4542 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4543 break;
4544 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4545 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4546 if (!ret) {
4547 if (fence->temp_syncobj) {
4548 close (fence->temp_syncobj);
4549 fence->temp_syncobj = 0;
4550 } else {
4551 device->ws->reset_syncobj(device->ws, syncobj_handle);
4552 }
4553 }
4554 break;
4555 default:
4556 unreachable("Unhandled fence handle type");
4557 }
4558
4559 if (ret)
4560 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4561 return VK_SUCCESS;
4562 }
4563
4564 void radv_GetPhysicalDeviceExternalFenceProperties(
4565 VkPhysicalDevice physicalDevice,
4566 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4567 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4568 {
4569 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4570
4571 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4572 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4573 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4574 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4575 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4576 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4577 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4578 } else {
4579 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4580 pExternalFenceProperties->compatibleHandleTypes = 0;
4581 pExternalFenceProperties->externalFenceFeatures = 0;
4582 }
4583 }
4584
4585 VkResult
4586 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4587 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4588 const VkAllocationCallbacks* pAllocator,
4589 VkDebugReportCallbackEXT* pCallback)
4590 {
4591 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4592 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4593 pCreateInfo, pAllocator, &instance->alloc,
4594 pCallback);
4595 }
4596
4597 void
4598 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4599 VkDebugReportCallbackEXT _callback,
4600 const VkAllocationCallbacks* pAllocator)
4601 {
4602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4603 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4604 _callback, pAllocator, &instance->alloc);
4605 }
4606
4607 void
4608 radv_DebugReportMessageEXT(VkInstance _instance,
4609 VkDebugReportFlagsEXT flags,
4610 VkDebugReportObjectTypeEXT objectType,
4611 uint64_t object,
4612 size_t location,
4613 int32_t messageCode,
4614 const char* pLayerPrefix,
4615 const char* pMessage)
4616 {
4617 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4618 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4619 object, location, messageCode, pLayerPrefix, pMessage);
4620 }
4621
4622 void
4623 radv_GetDeviceGroupPeerMemoryFeatures(
4624 VkDevice device,
4625 uint32_t heapIndex,
4626 uint32_t localDeviceIndex,
4627 uint32_t remoteDeviceIndex,
4628 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4629 {
4630 assert(localDeviceIndex == remoteDeviceIndex);
4631
4632 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4633 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4634 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4635 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4636 }