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radv: add support for VK_EXT_conditional_rendering
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 memset(pFeatures, 0, sizeof(*pFeatures));
689
690 *pFeatures = (VkPhysicalDeviceFeatures) {
691 .robustBufferAccess = true,
692 .fullDrawIndexUint32 = true,
693 .imageCubeArray = true,
694 .independentBlend = true,
695 .geometryShader = true,
696 .tessellationShader = true,
697 .sampleRateShading = true,
698 .dualSrcBlend = true,
699 .logicOp = true,
700 .multiDrawIndirect = true,
701 .drawIndirectFirstInstance = true,
702 .depthClamp = true,
703 .depthBiasClamp = true,
704 .fillModeNonSolid = true,
705 .depthBounds = true,
706 .wideLines = true,
707 .largePoints = true,
708 .alphaToOne = true,
709 .multiViewport = true,
710 .samplerAnisotropy = true,
711 .textureCompressionETC2 = false,
712 .textureCompressionASTC_LDR = false,
713 .textureCompressionBC = true,
714 .occlusionQueryPrecise = true,
715 .pipelineStatisticsQuery = true,
716 .vertexPipelineStoresAndAtomics = true,
717 .fragmentStoresAndAtomics = true,
718 .shaderTessellationAndGeometryPointSize = true,
719 .shaderImageGatherExtended = true,
720 .shaderStorageImageExtendedFormats = true,
721 .shaderStorageImageMultisample = false,
722 .shaderUniformBufferArrayDynamicIndexing = true,
723 .shaderSampledImageArrayDynamicIndexing = true,
724 .shaderStorageBufferArrayDynamicIndexing = true,
725 .shaderStorageImageArrayDynamicIndexing = true,
726 .shaderStorageImageReadWithoutFormat = true,
727 .shaderStorageImageWriteWithoutFormat = true,
728 .shaderClipDistance = true,
729 .shaderCullDistance = true,
730 .shaderFloat64 = true,
731 .shaderInt64 = true,
732 .shaderInt16 = false,
733 .sparseBinding = true,
734 .variableMultisampleRate = true,
735 .inheritedQueries = true,
736 };
737 }
738
739 void radv_GetPhysicalDeviceFeatures2(
740 VkPhysicalDevice physicalDevice,
741 VkPhysicalDeviceFeatures2KHR *pFeatures)
742 {
743 vk_foreach_struct(ext, pFeatures->pNext) {
744 switch (ext->sType) {
745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
746 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
747 features->variablePointersStorageBuffer = true;
748 features->variablePointers = false;
749 break;
750 }
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
752 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
753 features->multiview = true;
754 features->multiviewGeometryShader = true;
755 features->multiviewTessellationShader = true;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
759 VkPhysicalDeviceShaderDrawParameterFeatures *features =
760 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
761 features->shaderDrawParameters = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
765 VkPhysicalDeviceProtectedMemoryFeatures *features =
766 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
767 features->protectedMemory = false;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
771 VkPhysicalDevice16BitStorageFeatures *features =
772 (VkPhysicalDevice16BitStorageFeatures*)ext;
773 features->storageBuffer16BitAccess = false;
774 features->uniformAndStorageBuffer16BitAccess = false;
775 features->storagePushConstant16 = false;
776 features->storageInputOutput16 = false;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
780 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
781 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
782 features->samplerYcbcrConversion = false;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
786 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
787 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
788 features->shaderInputAttachmentArrayDynamicIndexing = true;
789 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
790 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
791 features->shaderUniformBufferArrayNonUniformIndexing = false;
792 features->shaderSampledImageArrayNonUniformIndexing = false;
793 features->shaderStorageBufferArrayNonUniformIndexing = false;
794 features->shaderStorageImageArrayNonUniformIndexing = false;
795 features->shaderInputAttachmentArrayNonUniformIndexing = false;
796 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
797 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
798 features->descriptorBindingUniformBufferUpdateAfterBind = true;
799 features->descriptorBindingSampledImageUpdateAfterBind = true;
800 features->descriptorBindingStorageImageUpdateAfterBind = true;
801 features->descriptorBindingStorageBufferUpdateAfterBind = true;
802 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
803 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
804 features->descriptorBindingUpdateUnusedWhilePending = true;
805 features->descriptorBindingPartiallyBound = true;
806 features->descriptorBindingVariableDescriptorCount = true;
807 features->runtimeDescriptorArray = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
811 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
812 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
813 features->conditionalRendering = true;
814 features->inheritedConditionalRendering = false;
815 break;
816 }
817 default:
818 break;
819 }
820 }
821 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
822 }
823
824 void radv_GetPhysicalDeviceProperties(
825 VkPhysicalDevice physicalDevice,
826 VkPhysicalDeviceProperties* pProperties)
827 {
828 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
829 VkSampleCountFlags sample_counts = 0xf;
830
831 /* make sure that the entire descriptor set is addressable with a signed
832 * 32-bit int. So the sum of all limits scaled by descriptor size has to
833 * be at most 2 GiB. the combined image & samples object count as one of
834 * both. This limit is for the pipeline layout, not for the set layout, but
835 * there is no set limit, so we just set a pipeline limit. I don't think
836 * any app is going to hit this soon. */
837 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
838 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
839 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
840 32 /* sampler, largest when combined with image */ +
841 64 /* sampled image */ +
842 64 /* storage image */);
843
844 VkPhysicalDeviceLimits limits = {
845 .maxImageDimension1D = (1 << 14),
846 .maxImageDimension2D = (1 << 14),
847 .maxImageDimension3D = (1 << 11),
848 .maxImageDimensionCube = (1 << 14),
849 .maxImageArrayLayers = (1 << 11),
850 .maxTexelBufferElements = 128 * 1024 * 1024,
851 .maxUniformBufferRange = UINT32_MAX,
852 .maxStorageBufferRange = UINT32_MAX,
853 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
854 .maxMemoryAllocationCount = UINT32_MAX,
855 .maxSamplerAllocationCount = 64 * 1024,
856 .bufferImageGranularity = 64, /* A cache line */
857 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
858 .maxBoundDescriptorSets = MAX_SETS,
859 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
860 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
861 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
862 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
863 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
864 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
865 .maxPerStageResources = max_descriptor_set_size,
866 .maxDescriptorSetSamplers = max_descriptor_set_size,
867 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
868 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
869 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
870 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
871 .maxDescriptorSetSampledImages = max_descriptor_set_size,
872 .maxDescriptorSetStorageImages = max_descriptor_set_size,
873 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
874 .maxVertexInputAttributes = 32,
875 .maxVertexInputBindings = 32,
876 .maxVertexInputAttributeOffset = 2047,
877 .maxVertexInputBindingStride = 2048,
878 .maxVertexOutputComponents = 128,
879 .maxTessellationGenerationLevel = 64,
880 .maxTessellationPatchSize = 32,
881 .maxTessellationControlPerVertexInputComponents = 128,
882 .maxTessellationControlPerVertexOutputComponents = 128,
883 .maxTessellationControlPerPatchOutputComponents = 120,
884 .maxTessellationControlTotalOutputComponents = 4096,
885 .maxTessellationEvaluationInputComponents = 128,
886 .maxTessellationEvaluationOutputComponents = 128,
887 .maxGeometryShaderInvocations = 127,
888 .maxGeometryInputComponents = 64,
889 .maxGeometryOutputComponents = 128,
890 .maxGeometryOutputVertices = 256,
891 .maxGeometryTotalOutputComponents = 1024,
892 .maxFragmentInputComponents = 128,
893 .maxFragmentOutputAttachments = 8,
894 .maxFragmentDualSrcAttachments = 1,
895 .maxFragmentCombinedOutputResources = 8,
896 .maxComputeSharedMemorySize = 32768,
897 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
898 .maxComputeWorkGroupInvocations = 2048,
899 .maxComputeWorkGroupSize = {
900 2048,
901 2048,
902 2048
903 },
904 .subPixelPrecisionBits = 4 /* FIXME */,
905 .subTexelPrecisionBits = 4 /* FIXME */,
906 .mipmapPrecisionBits = 4 /* FIXME */,
907 .maxDrawIndexedIndexValue = UINT32_MAX,
908 .maxDrawIndirectCount = UINT32_MAX,
909 .maxSamplerLodBias = 16,
910 .maxSamplerAnisotropy = 16,
911 .maxViewports = MAX_VIEWPORTS,
912 .maxViewportDimensions = { (1 << 14), (1 << 14) },
913 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
914 .viewportSubPixelBits = 8,
915 .minMemoryMapAlignment = 4096, /* A page */
916 .minTexelBufferOffsetAlignment = 1,
917 .minUniformBufferOffsetAlignment = 4,
918 .minStorageBufferOffsetAlignment = 4,
919 .minTexelOffset = -32,
920 .maxTexelOffset = 31,
921 .minTexelGatherOffset = -32,
922 .maxTexelGatherOffset = 31,
923 .minInterpolationOffset = -2,
924 .maxInterpolationOffset = 2,
925 .subPixelInterpolationOffsetBits = 8,
926 .maxFramebufferWidth = (1 << 14),
927 .maxFramebufferHeight = (1 << 14),
928 .maxFramebufferLayers = (1 << 10),
929 .framebufferColorSampleCounts = sample_counts,
930 .framebufferDepthSampleCounts = sample_counts,
931 .framebufferStencilSampleCounts = sample_counts,
932 .framebufferNoAttachmentsSampleCounts = sample_counts,
933 .maxColorAttachments = MAX_RTS,
934 .sampledImageColorSampleCounts = sample_counts,
935 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
936 .sampledImageDepthSampleCounts = sample_counts,
937 .sampledImageStencilSampleCounts = sample_counts,
938 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
939 .maxSampleMaskWords = 1,
940 .timestampComputeAndGraphics = true,
941 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
942 .maxClipDistances = 8,
943 .maxCullDistances = 8,
944 .maxCombinedClipAndCullDistances = 8,
945 .discreteQueuePriorities = 1,
946 .pointSizeRange = { 0.125, 255.875 },
947 .lineWidthRange = { 0.0, 7.9921875 },
948 .pointSizeGranularity = (1.0 / 8.0),
949 .lineWidthGranularity = (1.0 / 128.0),
950 .strictLines = false, /* FINISHME */
951 .standardSampleLocations = true,
952 .optimalBufferCopyOffsetAlignment = 128,
953 .optimalBufferCopyRowPitchAlignment = 128,
954 .nonCoherentAtomSize = 64,
955 };
956
957 *pProperties = (VkPhysicalDeviceProperties) {
958 .apiVersion = radv_physical_device_api_version(pdevice),
959 .driverVersion = vk_get_driver_version(),
960 .vendorID = ATI_VENDOR_ID,
961 .deviceID = pdevice->rad_info.pci_id,
962 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
963 .limits = limits,
964 .sparseProperties = {0},
965 };
966
967 strcpy(pProperties->deviceName, pdevice->name);
968 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
969 }
970
971 void radv_GetPhysicalDeviceProperties2(
972 VkPhysicalDevice physicalDevice,
973 VkPhysicalDeviceProperties2KHR *pProperties)
974 {
975 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
976 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
977
978 vk_foreach_struct(ext, pProperties->pNext) {
979 switch (ext->sType) {
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
981 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
982 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
983 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
987 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
988 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
989 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
990 properties->deviceLUIDValid = false;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
994 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
995 properties->maxMultiviewViewCount = MAX_VIEWS;
996 properties->maxMultiviewInstanceIndex = INT_MAX;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1000 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1001 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1002 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1003 break;
1004 }
1005 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1006 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1007 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1008 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1012 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1013 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1014 properties->minImportedHostPointerAlignment = 4096;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1018 VkPhysicalDeviceSubgroupProperties *properties =
1019 (VkPhysicalDeviceSubgroupProperties*)ext;
1020 properties->subgroupSize = 64;
1021 properties->supportedStages = VK_SHADER_STAGE_ALL;
1022 properties->supportedOperations =
1023 VK_SUBGROUP_FEATURE_BASIC_BIT |
1024 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1025 VK_SUBGROUP_FEATURE_QUAD_BIT |
1026 VK_SUBGROUP_FEATURE_VOTE_BIT;
1027 if (pdevice->rad_info.chip_class >= VI) {
1028 properties->supportedOperations |=
1029 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1030 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1031 }
1032 properties->quadOperationsInAllStages = true;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1036 VkPhysicalDeviceMaintenance3Properties *properties =
1037 (VkPhysicalDeviceMaintenance3Properties*)ext;
1038 /* Make sure everything is addressable by a signed 32-bit int, and
1039 * our largest descriptors are 96 bytes. */
1040 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1041 /* Our buffer size fields allow only this much */
1042 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1046 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1047 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1048 /* GFX6-8 only support single channel min/max filter. */
1049 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1050 properties->filterMinmaxSingleComponentFormats = true;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1054 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1055 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1056
1057 /* Shader engines. */
1058 properties->shaderEngineCount =
1059 pdevice->rad_info.max_se;
1060 properties->shaderArraysPerEngineCount =
1061 pdevice->rad_info.max_sh_per_se;
1062 properties->computeUnitsPerShaderArray =
1063 pdevice->rad_info.num_good_compute_units /
1064 (pdevice->rad_info.max_se *
1065 pdevice->rad_info.max_sh_per_se);
1066 properties->simdPerComputeUnit = 4;
1067 properties->wavefrontsPerSimd =
1068 pdevice->rad_info.family == CHIP_TONGA ||
1069 pdevice->rad_info.family == CHIP_ICELAND ||
1070 pdevice->rad_info.family == CHIP_POLARIS10 ||
1071 pdevice->rad_info.family == CHIP_POLARIS11 ||
1072 pdevice->rad_info.family == CHIP_POLARIS12 ||
1073 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1074 properties->wavefrontSize = 64;
1075
1076 /* SGPR. */
1077 properties->sgprsPerSimd =
1078 radv_get_num_physical_sgprs(pdevice);
1079 properties->minSgprAllocation =
1080 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1081 properties->maxSgprAllocation =
1082 pdevice->rad_info.family == CHIP_TONGA ||
1083 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1084 properties->sgprAllocationGranularity =
1085 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1086
1087 /* VGPR. */
1088 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1089 properties->minVgprAllocation = 4;
1090 properties->maxVgprAllocation = 256;
1091 properties->vgprAllocationGranularity = 4;
1092 break;
1093 }
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1095 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1096 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1097 properties->maxVertexAttribDivisor = UINT32_MAX;
1098 break;
1099 }
1100 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1101 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1102 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1103 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1104 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1105 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1106 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1107 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1108 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1109 properties->robustBufferAccessUpdateAfterBind = false;
1110 properties->quadDivergentImplicitLod = false;
1111
1112 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1113 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1114 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1115 32 /* sampler, largest when combined with image */ +
1116 64 /* sampled image */ +
1117 64 /* storage image */);
1118 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1119 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1120 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1121 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1122 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1123 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1124 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1125 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1126 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1127 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1128 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1129 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1130 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1131 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1132 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1133 break;
1134 }
1135 default:
1136 break;
1137 }
1138 }
1139 }
1140
1141 static void radv_get_physical_device_queue_family_properties(
1142 struct radv_physical_device* pdevice,
1143 uint32_t* pCount,
1144 VkQueueFamilyProperties** pQueueFamilyProperties)
1145 {
1146 int num_queue_families = 1;
1147 int idx;
1148 if (pdevice->rad_info.num_compute_rings > 0 &&
1149 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1150 num_queue_families++;
1151
1152 if (pQueueFamilyProperties == NULL) {
1153 *pCount = num_queue_families;
1154 return;
1155 }
1156
1157 if (!*pCount)
1158 return;
1159
1160 idx = 0;
1161 if (*pCount >= 1) {
1162 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1163 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1164 VK_QUEUE_COMPUTE_BIT |
1165 VK_QUEUE_TRANSFER_BIT |
1166 VK_QUEUE_SPARSE_BINDING_BIT,
1167 .queueCount = 1,
1168 .timestampValidBits = 64,
1169 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1170 };
1171 idx++;
1172 }
1173
1174 if (pdevice->rad_info.num_compute_rings > 0 &&
1175 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1176 if (*pCount > idx) {
1177 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1178 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1179 VK_QUEUE_TRANSFER_BIT |
1180 VK_QUEUE_SPARSE_BINDING_BIT,
1181 .queueCount = pdevice->rad_info.num_compute_rings,
1182 .timestampValidBits = 64,
1183 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1184 };
1185 idx++;
1186 }
1187 }
1188 *pCount = idx;
1189 }
1190
1191 void radv_GetPhysicalDeviceQueueFamilyProperties(
1192 VkPhysicalDevice physicalDevice,
1193 uint32_t* pCount,
1194 VkQueueFamilyProperties* pQueueFamilyProperties)
1195 {
1196 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1197 if (!pQueueFamilyProperties) {
1198 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1199 return;
1200 }
1201 VkQueueFamilyProperties *properties[] = {
1202 pQueueFamilyProperties + 0,
1203 pQueueFamilyProperties + 1,
1204 pQueueFamilyProperties + 2,
1205 };
1206 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1207 assert(*pCount <= 3);
1208 }
1209
1210 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1211 VkPhysicalDevice physicalDevice,
1212 uint32_t* pCount,
1213 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1214 {
1215 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1216 if (!pQueueFamilyProperties) {
1217 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1218 return;
1219 }
1220 VkQueueFamilyProperties *properties[] = {
1221 &pQueueFamilyProperties[0].queueFamilyProperties,
1222 &pQueueFamilyProperties[1].queueFamilyProperties,
1223 &pQueueFamilyProperties[2].queueFamilyProperties,
1224 };
1225 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1226 assert(*pCount <= 3);
1227 }
1228
1229 void radv_GetPhysicalDeviceMemoryProperties(
1230 VkPhysicalDevice physicalDevice,
1231 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1232 {
1233 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1234
1235 *pMemoryProperties = physical_device->memory_properties;
1236 }
1237
1238 void radv_GetPhysicalDeviceMemoryProperties2(
1239 VkPhysicalDevice physicalDevice,
1240 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1241 {
1242 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1243 &pMemoryProperties->memoryProperties);
1244 }
1245
1246 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1247 VkDevice _device,
1248 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1249 const void *pHostPointer,
1250 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1251 {
1252 RADV_FROM_HANDLE(radv_device, device, _device);
1253
1254 switch (handleType)
1255 {
1256 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1257 const struct radv_physical_device *physical_device = device->physical_device;
1258 uint32_t memoryTypeBits = 0;
1259 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1260 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1261 memoryTypeBits = (1 << i);
1262 break;
1263 }
1264 }
1265 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1266 return VK_SUCCESS;
1267 }
1268 default:
1269 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1270 }
1271 }
1272
1273 static enum radeon_ctx_priority
1274 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1275 {
1276 /* Default to MEDIUM when a specific global priority isn't requested */
1277 if (!pObj)
1278 return RADEON_CTX_PRIORITY_MEDIUM;
1279
1280 switch(pObj->globalPriority) {
1281 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1282 return RADEON_CTX_PRIORITY_REALTIME;
1283 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1284 return RADEON_CTX_PRIORITY_HIGH;
1285 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1286 return RADEON_CTX_PRIORITY_MEDIUM;
1287 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1288 return RADEON_CTX_PRIORITY_LOW;
1289 default:
1290 unreachable("Illegal global priority value");
1291 return RADEON_CTX_PRIORITY_INVALID;
1292 }
1293 }
1294
1295 static int
1296 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1297 uint32_t queue_family_index, int idx,
1298 VkDeviceQueueCreateFlags flags,
1299 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1300 {
1301 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1302 queue->device = device;
1303 queue->queue_family_index = queue_family_index;
1304 queue->queue_idx = idx;
1305 queue->priority = radv_get_queue_global_priority(global_priority);
1306 queue->flags = flags;
1307
1308 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1309 if (!queue->hw_ctx)
1310 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1311
1312 return VK_SUCCESS;
1313 }
1314
1315 static void
1316 radv_queue_finish(struct radv_queue *queue)
1317 {
1318 if (queue->hw_ctx)
1319 queue->device->ws->ctx_destroy(queue->hw_ctx);
1320
1321 if (queue->initial_full_flush_preamble_cs)
1322 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1323 if (queue->initial_preamble_cs)
1324 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1325 if (queue->continue_preamble_cs)
1326 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1327 if (queue->descriptor_bo)
1328 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1329 if (queue->scratch_bo)
1330 queue->device->ws->buffer_destroy(queue->scratch_bo);
1331 if (queue->esgs_ring_bo)
1332 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1333 if (queue->gsvs_ring_bo)
1334 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1335 if (queue->tess_rings_bo)
1336 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1337 if (queue->compute_scratch_bo)
1338 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1339 }
1340
1341 static void
1342 radv_bo_list_init(struct radv_bo_list *bo_list)
1343 {
1344 pthread_mutex_init(&bo_list->mutex, NULL);
1345 bo_list->list.count = bo_list->capacity = 0;
1346 bo_list->list.bos = NULL;
1347 }
1348
1349 static void
1350 radv_bo_list_finish(struct radv_bo_list *bo_list)
1351 {
1352 free(bo_list->list.bos);
1353 pthread_mutex_destroy(&bo_list->mutex);
1354 }
1355
1356 static VkResult radv_bo_list_add(struct radv_device *device,
1357 struct radeon_winsys_bo *bo)
1358 {
1359 struct radv_bo_list *bo_list = &device->bo_list;
1360
1361 if (unlikely(!device->use_global_bo_list))
1362 return VK_SUCCESS;
1363
1364 pthread_mutex_lock(&bo_list->mutex);
1365 if (bo_list->list.count == bo_list->capacity) {
1366 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1367 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1368
1369 if (!data) {
1370 pthread_mutex_unlock(&bo_list->mutex);
1371 return VK_ERROR_OUT_OF_HOST_MEMORY;
1372 }
1373
1374 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1375 bo_list->capacity = capacity;
1376 }
1377
1378 bo_list->list.bos[bo_list->list.count++] = bo;
1379 pthread_mutex_unlock(&bo_list->mutex);
1380 return VK_SUCCESS;
1381 }
1382
1383 static void radv_bo_list_remove(struct radv_device *device,
1384 struct radeon_winsys_bo *bo)
1385 {
1386 struct radv_bo_list *bo_list = &device->bo_list;
1387
1388 if (unlikely(!device->use_global_bo_list))
1389 return;
1390
1391 pthread_mutex_lock(&bo_list->mutex);
1392 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1393 if (bo_list->list.bos[i] == bo) {
1394 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1395 --bo_list->list.count;
1396 break;
1397 }
1398 }
1399 pthread_mutex_unlock(&bo_list->mutex);
1400 }
1401
1402 static void
1403 radv_device_init_gs_info(struct radv_device *device)
1404 {
1405 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1406 device->physical_device->rad_info.family);
1407 }
1408
1409 static int radv_get_device_extension_index(const char *name)
1410 {
1411 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1412 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1413 return i;
1414 }
1415 return -1;
1416 }
1417
1418 VkResult radv_CreateDevice(
1419 VkPhysicalDevice physicalDevice,
1420 const VkDeviceCreateInfo* pCreateInfo,
1421 const VkAllocationCallbacks* pAllocator,
1422 VkDevice* pDevice)
1423 {
1424 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1425 VkResult result;
1426 struct radv_device *device;
1427
1428 bool keep_shader_info = false;
1429
1430 /* Check enabled features */
1431 if (pCreateInfo->pEnabledFeatures) {
1432 VkPhysicalDeviceFeatures supported_features;
1433 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1434 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1435 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1436 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1437 for (uint32_t i = 0; i < num_features; i++) {
1438 if (enabled_feature[i] && !supported_feature[i])
1439 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1440 }
1441 }
1442
1443 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1444 sizeof(*device), 8,
1445 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1446 if (!device)
1447 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1448
1449 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1450 device->instance = physical_device->instance;
1451 device->physical_device = physical_device;
1452
1453 device->ws = physical_device->ws;
1454 if (pAllocator)
1455 device->alloc = *pAllocator;
1456 else
1457 device->alloc = physical_device->instance->alloc;
1458
1459 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1460 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1461 int index = radv_get_device_extension_index(ext_name);
1462 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1463 vk_free(&device->alloc, device);
1464 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1465 }
1466
1467 device->enabled_extensions.extensions[index] = true;
1468 }
1469
1470 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1471
1472 /* With update after bind we can't attach bo's to the command buffer
1473 * from the descriptor set anymore, so we have to use a global BO list.
1474 */
1475 device->use_global_bo_list =
1476 device->enabled_extensions.EXT_descriptor_indexing;
1477
1478 mtx_init(&device->shader_slab_mutex, mtx_plain);
1479 list_inithead(&device->shader_slabs);
1480
1481 radv_bo_list_init(&device->bo_list);
1482
1483 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1484 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1485 uint32_t qfi = queue_create->queueFamilyIndex;
1486 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1487 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1488
1489 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1490
1491 device->queues[qfi] = vk_alloc(&device->alloc,
1492 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1493 if (!device->queues[qfi]) {
1494 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1495 goto fail;
1496 }
1497
1498 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1499
1500 device->queue_count[qfi] = queue_create->queueCount;
1501
1502 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1503 result = radv_queue_init(device, &device->queues[qfi][q],
1504 qfi, q, queue_create->flags,
1505 global_priority);
1506 if (result != VK_SUCCESS)
1507 goto fail;
1508 }
1509 }
1510
1511 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1512 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1513
1514 /* Disabled and not implemented for now. */
1515 device->dfsm_allowed = device->pbb_allowed && false;
1516
1517 #ifdef ANDROID
1518 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1519 #endif
1520
1521 /* The maximum number of scratch waves. Scratch space isn't divided
1522 * evenly between CUs. The number is only a function of the number of CUs.
1523 * We can decrease the constant to decrease the scratch buffer size.
1524 *
1525 * sctx->scratch_waves must be >= the maximum possible size of
1526 * 1 threadgroup, so that the hw doesn't hang from being unable
1527 * to start any.
1528 *
1529 * The recommended value is 4 per CU at most. Higher numbers don't
1530 * bring much benefit, but they still occupy chip resources (think
1531 * async compute). I've seen ~2% performance difference between 4 and 32.
1532 */
1533 uint32_t max_threads_per_block = 2048;
1534 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1535 max_threads_per_block / 64);
1536
1537 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1538
1539 if (device->physical_device->rad_info.chip_class >= CIK) {
1540 /* If the KMD allows it (there is a KMD hw register for it),
1541 * allow launching waves out-of-order.
1542 */
1543 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1544 }
1545
1546 radv_device_init_gs_info(device);
1547
1548 device->tess_offchip_block_dw_size =
1549 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1550 device->has_distributed_tess =
1551 device->physical_device->rad_info.chip_class >= VI &&
1552 device->physical_device->rad_info.max_se >= 2;
1553
1554 if (getenv("RADV_TRACE_FILE")) {
1555 const char *filename = getenv("RADV_TRACE_FILE");
1556
1557 keep_shader_info = true;
1558
1559 if (!radv_init_trace(device))
1560 goto fail;
1561
1562 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1563 radv_dump_enabled_options(device, stderr);
1564 }
1565
1566 device->keep_shader_info = keep_shader_info;
1567
1568 result = radv_device_init_meta(device);
1569 if (result != VK_SUCCESS)
1570 goto fail;
1571
1572 radv_device_init_msaa(device);
1573
1574 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1575 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1576 switch (family) {
1577 case RADV_QUEUE_GENERAL:
1578 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1579 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1580 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1581 break;
1582 case RADV_QUEUE_COMPUTE:
1583 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1584 radeon_emit(device->empty_cs[family], 0);
1585 break;
1586 }
1587 device->ws->cs_finalize(device->empty_cs[family]);
1588 }
1589
1590 if (device->physical_device->rad_info.chip_class >= CIK)
1591 cik_create_gfx_config(device);
1592
1593 VkPipelineCacheCreateInfo ci;
1594 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1595 ci.pNext = NULL;
1596 ci.flags = 0;
1597 ci.pInitialData = NULL;
1598 ci.initialDataSize = 0;
1599 VkPipelineCache pc;
1600 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1601 &ci, NULL, &pc);
1602 if (result != VK_SUCCESS)
1603 goto fail_meta;
1604
1605 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1606
1607 *pDevice = radv_device_to_handle(device);
1608 return VK_SUCCESS;
1609
1610 fail_meta:
1611 radv_device_finish_meta(device);
1612 fail:
1613 radv_bo_list_finish(&device->bo_list);
1614
1615 if (device->trace_bo)
1616 device->ws->buffer_destroy(device->trace_bo);
1617
1618 if (device->gfx_init)
1619 device->ws->buffer_destroy(device->gfx_init);
1620
1621 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1622 for (unsigned q = 0; q < device->queue_count[i]; q++)
1623 radv_queue_finish(&device->queues[i][q]);
1624 if (device->queue_count[i])
1625 vk_free(&device->alloc, device->queues[i]);
1626 }
1627
1628 vk_free(&device->alloc, device);
1629 return result;
1630 }
1631
1632 void radv_DestroyDevice(
1633 VkDevice _device,
1634 const VkAllocationCallbacks* pAllocator)
1635 {
1636 RADV_FROM_HANDLE(radv_device, device, _device);
1637
1638 if (!device)
1639 return;
1640
1641 if (device->trace_bo)
1642 device->ws->buffer_destroy(device->trace_bo);
1643
1644 if (device->gfx_init)
1645 device->ws->buffer_destroy(device->gfx_init);
1646
1647 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1648 for (unsigned q = 0; q < device->queue_count[i]; q++)
1649 radv_queue_finish(&device->queues[i][q]);
1650 if (device->queue_count[i])
1651 vk_free(&device->alloc, device->queues[i]);
1652 if (device->empty_cs[i])
1653 device->ws->cs_destroy(device->empty_cs[i]);
1654 }
1655 radv_device_finish_meta(device);
1656
1657 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1658 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1659
1660 radv_destroy_shader_slabs(device);
1661
1662 radv_bo_list_finish(&device->bo_list);
1663 vk_free(&device->alloc, device);
1664 }
1665
1666 VkResult radv_EnumerateInstanceLayerProperties(
1667 uint32_t* pPropertyCount,
1668 VkLayerProperties* pProperties)
1669 {
1670 if (pProperties == NULL) {
1671 *pPropertyCount = 0;
1672 return VK_SUCCESS;
1673 }
1674
1675 /* None supported at this time */
1676 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1677 }
1678
1679 VkResult radv_EnumerateDeviceLayerProperties(
1680 VkPhysicalDevice physicalDevice,
1681 uint32_t* pPropertyCount,
1682 VkLayerProperties* pProperties)
1683 {
1684 if (pProperties == NULL) {
1685 *pPropertyCount = 0;
1686 return VK_SUCCESS;
1687 }
1688
1689 /* None supported at this time */
1690 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1691 }
1692
1693 void radv_GetDeviceQueue2(
1694 VkDevice _device,
1695 const VkDeviceQueueInfo2* pQueueInfo,
1696 VkQueue* pQueue)
1697 {
1698 RADV_FROM_HANDLE(radv_device, device, _device);
1699 struct radv_queue *queue;
1700
1701 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1702 if (pQueueInfo->flags != queue->flags) {
1703 /* From the Vulkan 1.1.70 spec:
1704 *
1705 * "The queue returned by vkGetDeviceQueue2 must have the same
1706 * flags value from this structure as that used at device
1707 * creation time in a VkDeviceQueueCreateInfo instance. If no
1708 * matching flags were specified at device creation time then
1709 * pQueue will return VK_NULL_HANDLE."
1710 */
1711 *pQueue = VK_NULL_HANDLE;
1712 return;
1713 }
1714
1715 *pQueue = radv_queue_to_handle(queue);
1716 }
1717
1718 void radv_GetDeviceQueue(
1719 VkDevice _device,
1720 uint32_t queueFamilyIndex,
1721 uint32_t queueIndex,
1722 VkQueue* pQueue)
1723 {
1724 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1725 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1726 .queueFamilyIndex = queueFamilyIndex,
1727 .queueIndex = queueIndex
1728 };
1729
1730 radv_GetDeviceQueue2(_device, &info, pQueue);
1731 }
1732
1733 static void
1734 fill_geom_tess_rings(struct radv_queue *queue,
1735 uint32_t *map,
1736 bool add_sample_positions,
1737 uint32_t esgs_ring_size,
1738 struct radeon_winsys_bo *esgs_ring_bo,
1739 uint32_t gsvs_ring_size,
1740 struct radeon_winsys_bo *gsvs_ring_bo,
1741 uint32_t tess_factor_ring_size,
1742 uint32_t tess_offchip_ring_offset,
1743 uint32_t tess_offchip_ring_size,
1744 struct radeon_winsys_bo *tess_rings_bo)
1745 {
1746 uint64_t esgs_va = 0, gsvs_va = 0;
1747 uint64_t tess_va = 0, tess_offchip_va = 0;
1748 uint32_t *desc = &map[4];
1749
1750 if (esgs_ring_bo)
1751 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1752 if (gsvs_ring_bo)
1753 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1754 if (tess_rings_bo) {
1755 tess_va = radv_buffer_get_va(tess_rings_bo);
1756 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1757 }
1758
1759 /* stride 0, num records - size, add tid, swizzle, elsize4,
1760 index stride 64 */
1761 desc[0] = esgs_va;
1762 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1763 S_008F04_STRIDE(0) |
1764 S_008F04_SWIZZLE_ENABLE(true);
1765 desc[2] = esgs_ring_size;
1766 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1767 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1768 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1769 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1770 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1771 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1772 S_008F0C_ELEMENT_SIZE(1) |
1773 S_008F0C_INDEX_STRIDE(3) |
1774 S_008F0C_ADD_TID_ENABLE(true);
1775
1776 desc += 4;
1777 /* GS entry for ES->GS ring */
1778 /* stride 0, num records - size, elsize0,
1779 index stride 0 */
1780 desc[0] = esgs_va;
1781 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1782 S_008F04_STRIDE(0) |
1783 S_008F04_SWIZZLE_ENABLE(false);
1784 desc[2] = esgs_ring_size;
1785 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1786 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1787 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1788 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1789 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1790 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1791 S_008F0C_ELEMENT_SIZE(0) |
1792 S_008F0C_INDEX_STRIDE(0) |
1793 S_008F0C_ADD_TID_ENABLE(false);
1794
1795 desc += 4;
1796 /* VS entry for GS->VS ring */
1797 /* stride 0, num records - size, elsize0,
1798 index stride 0 */
1799 desc[0] = gsvs_va;
1800 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1801 S_008F04_STRIDE(0) |
1802 S_008F04_SWIZZLE_ENABLE(false);
1803 desc[2] = gsvs_ring_size;
1804 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1805 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1806 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1807 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1808 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1809 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1810 S_008F0C_ELEMENT_SIZE(0) |
1811 S_008F0C_INDEX_STRIDE(0) |
1812 S_008F0C_ADD_TID_ENABLE(false);
1813 desc += 4;
1814
1815 /* stride gsvs_itemsize, num records 64
1816 elsize 4, index stride 16 */
1817 /* shader will patch stride and desc[2] */
1818 desc[0] = gsvs_va;
1819 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1820 S_008F04_STRIDE(0) |
1821 S_008F04_SWIZZLE_ENABLE(true);
1822 desc[2] = 0;
1823 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1824 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1825 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1826 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1827 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1828 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1829 S_008F0C_ELEMENT_SIZE(1) |
1830 S_008F0C_INDEX_STRIDE(1) |
1831 S_008F0C_ADD_TID_ENABLE(true);
1832 desc += 4;
1833
1834 desc[0] = tess_va;
1835 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1836 S_008F04_STRIDE(0) |
1837 S_008F04_SWIZZLE_ENABLE(false);
1838 desc[2] = tess_factor_ring_size;
1839 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1840 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1841 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1842 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1843 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1844 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1845 S_008F0C_ELEMENT_SIZE(0) |
1846 S_008F0C_INDEX_STRIDE(0) |
1847 S_008F0C_ADD_TID_ENABLE(false);
1848 desc += 4;
1849
1850 desc[0] = tess_offchip_va;
1851 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1852 S_008F04_STRIDE(0) |
1853 S_008F04_SWIZZLE_ENABLE(false);
1854 desc[2] = tess_offchip_ring_size;
1855 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1856 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1857 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1858 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1859 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1860 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1861 S_008F0C_ELEMENT_SIZE(0) |
1862 S_008F0C_INDEX_STRIDE(0) |
1863 S_008F0C_ADD_TID_ENABLE(false);
1864 desc += 4;
1865
1866 /* add sample positions after all rings */
1867 memcpy(desc, queue->device->sample_locations_1x, 8);
1868 desc += 2;
1869 memcpy(desc, queue->device->sample_locations_2x, 16);
1870 desc += 4;
1871 memcpy(desc, queue->device->sample_locations_4x, 32);
1872 desc += 8;
1873 memcpy(desc, queue->device->sample_locations_8x, 64);
1874 desc += 16;
1875 memcpy(desc, queue->device->sample_locations_16x, 128);
1876 }
1877
1878 static unsigned
1879 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1880 {
1881 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1882 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1883 device->physical_device->rad_info.family != CHIP_STONEY;
1884 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1885 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1886 device->physical_device->rad_info.max_se;
1887 unsigned offchip_granularity;
1888 unsigned hs_offchip_param;
1889 switch (device->tess_offchip_block_dw_size) {
1890 default:
1891 assert(0);
1892 /* fall through */
1893 case 8192:
1894 offchip_granularity = V_03093C_X_8K_DWORDS;
1895 break;
1896 case 4096:
1897 offchip_granularity = V_03093C_X_4K_DWORDS;
1898 break;
1899 }
1900
1901 switch (device->physical_device->rad_info.chip_class) {
1902 case SI:
1903 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1904 break;
1905 case CIK:
1906 case VI:
1907 case GFX9:
1908 default:
1909 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1910 break;
1911 }
1912
1913 *max_offchip_buffers_p = max_offchip_buffers;
1914 if (device->physical_device->rad_info.chip_class >= CIK) {
1915 if (device->physical_device->rad_info.chip_class >= VI)
1916 --max_offchip_buffers;
1917 hs_offchip_param =
1918 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1919 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1920 } else {
1921 hs_offchip_param =
1922 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1923 }
1924 return hs_offchip_param;
1925 }
1926
1927 static void
1928 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1929 struct radeon_winsys_bo *esgs_ring_bo,
1930 uint32_t esgs_ring_size,
1931 struct radeon_winsys_bo *gsvs_ring_bo,
1932 uint32_t gsvs_ring_size)
1933 {
1934 if (!esgs_ring_bo && !gsvs_ring_bo)
1935 return;
1936
1937 if (esgs_ring_bo)
1938 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1939
1940 if (gsvs_ring_bo)
1941 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1942
1943 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1944 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1945 radeon_emit(cs, esgs_ring_size >> 8);
1946 radeon_emit(cs, gsvs_ring_size >> 8);
1947 } else {
1948 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1949 radeon_emit(cs, esgs_ring_size >> 8);
1950 radeon_emit(cs, gsvs_ring_size >> 8);
1951 }
1952 }
1953
1954 static void
1955 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1956 unsigned hs_offchip_param, unsigned tf_ring_size,
1957 struct radeon_winsys_bo *tess_rings_bo)
1958 {
1959 uint64_t tf_va;
1960
1961 if (!tess_rings_bo)
1962 return;
1963
1964 tf_va = radv_buffer_get_va(tess_rings_bo);
1965
1966 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1967
1968 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1969 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1970 S_030938_SIZE(tf_ring_size / 4));
1971 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1972 tf_va >> 8);
1973 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1974 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1975 S_030944_BASE_HI(tf_va >> 40));
1976 }
1977 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1978 hs_offchip_param);
1979 } else {
1980 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1981 S_008988_SIZE(tf_ring_size / 4));
1982 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1983 tf_va >> 8);
1984 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1985 hs_offchip_param);
1986 }
1987 }
1988
1989 static void
1990 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1991 struct radeon_winsys_bo *compute_scratch_bo)
1992 {
1993 uint64_t scratch_va;
1994
1995 if (!compute_scratch_bo)
1996 return;
1997
1998 scratch_va = radv_buffer_get_va(compute_scratch_bo);
1999
2000 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2001
2002 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2003 radeon_emit(cs, scratch_va);
2004 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2005 S_008F04_SWIZZLE_ENABLE(1));
2006 }
2007
2008 static void
2009 radv_emit_global_shader_pointers(struct radv_queue *queue,
2010 struct radeon_cmdbuf *cs,
2011 struct radeon_winsys_bo *descriptor_bo)
2012 {
2013 uint64_t va;
2014
2015 if (!descriptor_bo)
2016 return;
2017
2018 va = radv_buffer_get_va(descriptor_bo);
2019
2020 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2021
2022 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2023 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2024 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2025 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2026 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2027
2028 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2029 radv_emit_shader_pointer(queue->device, cs, regs[i],
2030 va, true);
2031 }
2032 } else {
2033 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2034 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2035 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2036 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2037 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2038 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2039
2040 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2041 radv_emit_shader_pointer(queue->device, cs, regs[i],
2042 va, true);
2043 }
2044 }
2045 }
2046
2047 static VkResult
2048 radv_get_preamble_cs(struct radv_queue *queue,
2049 uint32_t scratch_size,
2050 uint32_t compute_scratch_size,
2051 uint32_t esgs_ring_size,
2052 uint32_t gsvs_ring_size,
2053 bool needs_tess_rings,
2054 bool needs_sample_positions,
2055 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2056 struct radeon_cmdbuf **initial_preamble_cs,
2057 struct radeon_cmdbuf **continue_preamble_cs)
2058 {
2059 struct radeon_winsys_bo *scratch_bo = NULL;
2060 struct radeon_winsys_bo *descriptor_bo = NULL;
2061 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2062 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2063 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2064 struct radeon_winsys_bo *tess_rings_bo = NULL;
2065 struct radeon_cmdbuf *dest_cs[3] = {0};
2066 bool add_tess_rings = false, add_sample_positions = false;
2067 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2068 unsigned max_offchip_buffers;
2069 unsigned hs_offchip_param = 0;
2070 unsigned tess_offchip_ring_offset;
2071 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2072 if (!queue->has_tess_rings) {
2073 if (needs_tess_rings)
2074 add_tess_rings = true;
2075 }
2076 if (!queue->has_sample_positions) {
2077 if (needs_sample_positions)
2078 add_sample_positions = true;
2079 }
2080 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2081 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2082 &max_offchip_buffers);
2083 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2084 tess_offchip_ring_size = max_offchip_buffers *
2085 queue->device->tess_offchip_block_dw_size * 4;
2086
2087 if (scratch_size <= queue->scratch_size &&
2088 compute_scratch_size <= queue->compute_scratch_size &&
2089 esgs_ring_size <= queue->esgs_ring_size &&
2090 gsvs_ring_size <= queue->gsvs_ring_size &&
2091 !add_tess_rings && !add_sample_positions &&
2092 queue->initial_preamble_cs) {
2093 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2094 *initial_preamble_cs = queue->initial_preamble_cs;
2095 *continue_preamble_cs = queue->continue_preamble_cs;
2096 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2097 *continue_preamble_cs = NULL;
2098 return VK_SUCCESS;
2099 }
2100
2101 if (scratch_size > queue->scratch_size) {
2102 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2103 scratch_size,
2104 4096,
2105 RADEON_DOMAIN_VRAM,
2106 ring_bo_flags);
2107 if (!scratch_bo)
2108 goto fail;
2109 } else
2110 scratch_bo = queue->scratch_bo;
2111
2112 if (compute_scratch_size > queue->compute_scratch_size) {
2113 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2114 compute_scratch_size,
2115 4096,
2116 RADEON_DOMAIN_VRAM,
2117 ring_bo_flags);
2118 if (!compute_scratch_bo)
2119 goto fail;
2120
2121 } else
2122 compute_scratch_bo = queue->compute_scratch_bo;
2123
2124 if (esgs_ring_size > queue->esgs_ring_size) {
2125 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2126 esgs_ring_size,
2127 4096,
2128 RADEON_DOMAIN_VRAM,
2129 ring_bo_flags);
2130 if (!esgs_ring_bo)
2131 goto fail;
2132 } else {
2133 esgs_ring_bo = queue->esgs_ring_bo;
2134 esgs_ring_size = queue->esgs_ring_size;
2135 }
2136
2137 if (gsvs_ring_size > queue->gsvs_ring_size) {
2138 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2139 gsvs_ring_size,
2140 4096,
2141 RADEON_DOMAIN_VRAM,
2142 ring_bo_flags);
2143 if (!gsvs_ring_bo)
2144 goto fail;
2145 } else {
2146 gsvs_ring_bo = queue->gsvs_ring_bo;
2147 gsvs_ring_size = queue->gsvs_ring_size;
2148 }
2149
2150 if (add_tess_rings) {
2151 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2152 tess_offchip_ring_offset + tess_offchip_ring_size,
2153 256,
2154 RADEON_DOMAIN_VRAM,
2155 ring_bo_flags);
2156 if (!tess_rings_bo)
2157 goto fail;
2158 } else {
2159 tess_rings_bo = queue->tess_rings_bo;
2160 }
2161
2162 if (scratch_bo != queue->scratch_bo ||
2163 esgs_ring_bo != queue->esgs_ring_bo ||
2164 gsvs_ring_bo != queue->gsvs_ring_bo ||
2165 tess_rings_bo != queue->tess_rings_bo ||
2166 add_sample_positions) {
2167 uint32_t size = 0;
2168 if (gsvs_ring_bo || esgs_ring_bo ||
2169 tess_rings_bo || add_sample_positions) {
2170 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2171 if (add_sample_positions)
2172 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2173 }
2174 else if (scratch_bo)
2175 size = 8; /* 2 dword */
2176
2177 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2178 size,
2179 4096,
2180 RADEON_DOMAIN_VRAM,
2181 RADEON_FLAG_CPU_ACCESS |
2182 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2183 RADEON_FLAG_READ_ONLY);
2184 if (!descriptor_bo)
2185 goto fail;
2186 } else
2187 descriptor_bo = queue->descriptor_bo;
2188
2189 for(int i = 0; i < 3; ++i) {
2190 struct radeon_cmdbuf *cs = NULL;
2191 cs = queue->device->ws->cs_create(queue->device->ws,
2192 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2193 if (!cs)
2194 goto fail;
2195
2196 dest_cs[i] = cs;
2197
2198 if (scratch_bo)
2199 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2200
2201 if (descriptor_bo != queue->descriptor_bo) {
2202 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2203
2204 if (scratch_bo) {
2205 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2206 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2207 S_008F04_SWIZZLE_ENABLE(1);
2208 map[0] = scratch_va;
2209 map[1] = rsrc1;
2210 }
2211
2212 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2213 add_sample_positions)
2214 fill_geom_tess_rings(queue, map, add_sample_positions,
2215 esgs_ring_size, esgs_ring_bo,
2216 gsvs_ring_size, gsvs_ring_bo,
2217 tess_factor_ring_size,
2218 tess_offchip_ring_offset,
2219 tess_offchip_ring_size,
2220 tess_rings_bo);
2221
2222 queue->device->ws->buffer_unmap(descriptor_bo);
2223 }
2224
2225 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2226 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2227 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2228 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2229 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2230 }
2231
2232 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2233 gsvs_ring_bo, gsvs_ring_size);
2234 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2235 tess_factor_ring_size, tess_rings_bo);
2236 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2237 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2238
2239 if (i == 0) {
2240 si_cs_emit_cache_flush(cs,
2241 queue->device->physical_device->rad_info.chip_class,
2242 NULL, 0,
2243 queue->queue_family_index == RING_COMPUTE &&
2244 queue->device->physical_device->rad_info.chip_class >= CIK,
2245 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2246 RADV_CMD_FLAG_INV_ICACHE |
2247 RADV_CMD_FLAG_INV_SMEM_L1 |
2248 RADV_CMD_FLAG_INV_VMEM_L1 |
2249 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2250 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2251 } else if (i == 1) {
2252 si_cs_emit_cache_flush(cs,
2253 queue->device->physical_device->rad_info.chip_class,
2254 NULL, 0,
2255 queue->queue_family_index == RING_COMPUTE &&
2256 queue->device->physical_device->rad_info.chip_class >= CIK,
2257 RADV_CMD_FLAG_INV_ICACHE |
2258 RADV_CMD_FLAG_INV_SMEM_L1 |
2259 RADV_CMD_FLAG_INV_VMEM_L1 |
2260 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2261 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2262 }
2263
2264 if (!queue->device->ws->cs_finalize(cs))
2265 goto fail;
2266 }
2267
2268 if (queue->initial_full_flush_preamble_cs)
2269 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2270
2271 if (queue->initial_preamble_cs)
2272 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2273
2274 if (queue->continue_preamble_cs)
2275 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2276
2277 queue->initial_full_flush_preamble_cs = dest_cs[0];
2278 queue->initial_preamble_cs = dest_cs[1];
2279 queue->continue_preamble_cs = dest_cs[2];
2280
2281 if (scratch_bo != queue->scratch_bo) {
2282 if (queue->scratch_bo)
2283 queue->device->ws->buffer_destroy(queue->scratch_bo);
2284 queue->scratch_bo = scratch_bo;
2285 queue->scratch_size = scratch_size;
2286 }
2287
2288 if (compute_scratch_bo != queue->compute_scratch_bo) {
2289 if (queue->compute_scratch_bo)
2290 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2291 queue->compute_scratch_bo = compute_scratch_bo;
2292 queue->compute_scratch_size = compute_scratch_size;
2293 }
2294
2295 if (esgs_ring_bo != queue->esgs_ring_bo) {
2296 if (queue->esgs_ring_bo)
2297 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2298 queue->esgs_ring_bo = esgs_ring_bo;
2299 queue->esgs_ring_size = esgs_ring_size;
2300 }
2301
2302 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2303 if (queue->gsvs_ring_bo)
2304 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2305 queue->gsvs_ring_bo = gsvs_ring_bo;
2306 queue->gsvs_ring_size = gsvs_ring_size;
2307 }
2308
2309 if (tess_rings_bo != queue->tess_rings_bo) {
2310 queue->tess_rings_bo = tess_rings_bo;
2311 queue->has_tess_rings = true;
2312 }
2313
2314 if (descriptor_bo != queue->descriptor_bo) {
2315 if (queue->descriptor_bo)
2316 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2317
2318 queue->descriptor_bo = descriptor_bo;
2319 }
2320
2321 if (add_sample_positions)
2322 queue->has_sample_positions = true;
2323
2324 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2325 *initial_preamble_cs = queue->initial_preamble_cs;
2326 *continue_preamble_cs = queue->continue_preamble_cs;
2327 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2328 *continue_preamble_cs = NULL;
2329 return VK_SUCCESS;
2330 fail:
2331 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2332 if (dest_cs[i])
2333 queue->device->ws->cs_destroy(dest_cs[i]);
2334 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2335 queue->device->ws->buffer_destroy(descriptor_bo);
2336 if (scratch_bo && scratch_bo != queue->scratch_bo)
2337 queue->device->ws->buffer_destroy(scratch_bo);
2338 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2339 queue->device->ws->buffer_destroy(compute_scratch_bo);
2340 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2341 queue->device->ws->buffer_destroy(esgs_ring_bo);
2342 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2343 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2344 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2345 queue->device->ws->buffer_destroy(tess_rings_bo);
2346 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2347 }
2348
2349 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2350 struct radv_winsys_sem_counts *counts,
2351 int num_sems,
2352 const VkSemaphore *sems,
2353 VkFence _fence,
2354 bool reset_temp)
2355 {
2356 int syncobj_idx = 0, sem_idx = 0;
2357
2358 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2359 return VK_SUCCESS;
2360
2361 for (uint32_t i = 0; i < num_sems; i++) {
2362 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2363
2364 if (sem->temp_syncobj || sem->syncobj)
2365 counts->syncobj_count++;
2366 else
2367 counts->sem_count++;
2368 }
2369
2370 if (_fence != VK_NULL_HANDLE) {
2371 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2372 if (fence->temp_syncobj || fence->syncobj)
2373 counts->syncobj_count++;
2374 }
2375
2376 if (counts->syncobj_count) {
2377 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2378 if (!counts->syncobj)
2379 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2380 }
2381
2382 if (counts->sem_count) {
2383 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2384 if (!counts->sem) {
2385 free(counts->syncobj);
2386 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2387 }
2388 }
2389
2390 for (uint32_t i = 0; i < num_sems; i++) {
2391 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2392
2393 if (sem->temp_syncobj) {
2394 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2395 }
2396 else if (sem->syncobj)
2397 counts->syncobj[syncobj_idx++] = sem->syncobj;
2398 else {
2399 assert(sem->sem);
2400 counts->sem[sem_idx++] = sem->sem;
2401 }
2402 }
2403
2404 if (_fence != VK_NULL_HANDLE) {
2405 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2406 if (fence->temp_syncobj)
2407 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2408 else if (fence->syncobj)
2409 counts->syncobj[syncobj_idx++] = fence->syncobj;
2410 }
2411
2412 return VK_SUCCESS;
2413 }
2414
2415 static void
2416 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2417 {
2418 free(sem_info->wait.syncobj);
2419 free(sem_info->wait.sem);
2420 free(sem_info->signal.syncobj);
2421 free(sem_info->signal.sem);
2422 }
2423
2424
2425 static void radv_free_temp_syncobjs(struct radv_device *device,
2426 int num_sems,
2427 const VkSemaphore *sems)
2428 {
2429 for (uint32_t i = 0; i < num_sems; i++) {
2430 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2431
2432 if (sem->temp_syncobj) {
2433 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2434 sem->temp_syncobj = 0;
2435 }
2436 }
2437 }
2438
2439 static VkResult
2440 radv_alloc_sem_info(struct radv_instance *instance,
2441 struct radv_winsys_sem_info *sem_info,
2442 int num_wait_sems,
2443 const VkSemaphore *wait_sems,
2444 int num_signal_sems,
2445 const VkSemaphore *signal_sems,
2446 VkFence fence)
2447 {
2448 VkResult ret;
2449 memset(sem_info, 0, sizeof(*sem_info));
2450
2451 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2452 if (ret)
2453 return ret;
2454 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2455 if (ret)
2456 radv_free_sem_info(sem_info);
2457
2458 /* caller can override these */
2459 sem_info->cs_emit_wait = true;
2460 sem_info->cs_emit_signal = true;
2461 return ret;
2462 }
2463
2464 /* Signals fence as soon as all the work currently put on queue is done. */
2465 static VkResult radv_signal_fence(struct radv_queue *queue,
2466 struct radv_fence *fence)
2467 {
2468 int ret;
2469 VkResult result;
2470 struct radv_winsys_sem_info sem_info;
2471
2472 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2473 radv_fence_to_handle(fence));
2474 if (result != VK_SUCCESS)
2475 return result;
2476
2477 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2478 &queue->device->empty_cs[queue->queue_family_index],
2479 1, NULL, NULL, &sem_info, NULL,
2480 false, fence->fence);
2481 radv_free_sem_info(&sem_info);
2482
2483 if (ret)
2484 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2485
2486 return VK_SUCCESS;
2487 }
2488
2489 VkResult radv_QueueSubmit(
2490 VkQueue _queue,
2491 uint32_t submitCount,
2492 const VkSubmitInfo* pSubmits,
2493 VkFence _fence)
2494 {
2495 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2496 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2497 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2498 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2499 int ret;
2500 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2501 uint32_t scratch_size = 0;
2502 uint32_t compute_scratch_size = 0;
2503 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2504 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2505 VkResult result;
2506 bool fence_emitted = false;
2507 bool tess_rings_needed = false;
2508 bool sample_positions_needed = false;
2509
2510 /* Do this first so failing to allocate scratch buffers can't result in
2511 * partially executed submissions. */
2512 for (uint32_t i = 0; i < submitCount; i++) {
2513 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2514 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2515 pSubmits[i].pCommandBuffers[j]);
2516
2517 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2518 compute_scratch_size = MAX2(compute_scratch_size,
2519 cmd_buffer->compute_scratch_size_needed);
2520 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2521 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2522 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2523 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2524 }
2525 }
2526
2527 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2528 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2529 sample_positions_needed, &initial_flush_preamble_cs,
2530 &initial_preamble_cs, &continue_preamble_cs);
2531 if (result != VK_SUCCESS)
2532 return result;
2533
2534 for (uint32_t i = 0; i < submitCount; i++) {
2535 struct radeon_cmdbuf **cs_array;
2536 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2537 bool can_patch = true;
2538 uint32_t advance;
2539 struct radv_winsys_sem_info sem_info;
2540
2541 result = radv_alloc_sem_info(queue->device->instance,
2542 &sem_info,
2543 pSubmits[i].waitSemaphoreCount,
2544 pSubmits[i].pWaitSemaphores,
2545 pSubmits[i].signalSemaphoreCount,
2546 pSubmits[i].pSignalSemaphores,
2547 _fence);
2548 if (result != VK_SUCCESS)
2549 return result;
2550
2551 if (!pSubmits[i].commandBufferCount) {
2552 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2553 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2554 &queue->device->empty_cs[queue->queue_family_index],
2555 1, NULL, NULL,
2556 &sem_info, NULL,
2557 false, base_fence);
2558 if (ret) {
2559 radv_loge("failed to submit CS %d\n", i);
2560 abort();
2561 }
2562 fence_emitted = true;
2563 }
2564 radv_free_sem_info(&sem_info);
2565 continue;
2566 }
2567
2568 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2569 (pSubmits[i].commandBufferCount));
2570
2571 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2572 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2573 pSubmits[i].pCommandBuffers[j]);
2574 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2575
2576 cs_array[j] = cmd_buffer->cs;
2577 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2578 can_patch = false;
2579
2580 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2581 }
2582
2583 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2584 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2585 const struct radv_winsys_bo_list *bo_list = NULL;
2586
2587 advance = MIN2(max_cs_submission,
2588 pSubmits[i].commandBufferCount - j);
2589
2590 if (queue->device->trace_bo)
2591 *queue->device->trace_id_ptr = 0;
2592
2593 sem_info.cs_emit_wait = j == 0;
2594 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2595
2596 if (unlikely(queue->device->use_global_bo_list)) {
2597 pthread_mutex_lock(&queue->device->bo_list.mutex);
2598 bo_list = &queue->device->bo_list.list;
2599 }
2600
2601 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2602 advance, initial_preamble, continue_preamble_cs,
2603 &sem_info, bo_list,
2604 can_patch, base_fence);
2605
2606 if (unlikely(queue->device->use_global_bo_list))
2607 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2608
2609 if (ret) {
2610 radv_loge("failed to submit CS %d\n", i);
2611 abort();
2612 }
2613 fence_emitted = true;
2614 if (queue->device->trace_bo) {
2615 radv_check_gpu_hangs(queue, cs_array[j]);
2616 }
2617 }
2618
2619 radv_free_temp_syncobjs(queue->device,
2620 pSubmits[i].waitSemaphoreCount,
2621 pSubmits[i].pWaitSemaphores);
2622 radv_free_sem_info(&sem_info);
2623 free(cs_array);
2624 }
2625
2626 if (fence) {
2627 if (!fence_emitted) {
2628 result = radv_signal_fence(queue, fence);
2629 if (result != VK_SUCCESS)
2630 return result;
2631 }
2632 fence->submitted = true;
2633 }
2634
2635 return VK_SUCCESS;
2636 }
2637
2638 VkResult radv_QueueWaitIdle(
2639 VkQueue _queue)
2640 {
2641 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2642
2643 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2644 radv_queue_family_to_ring(queue->queue_family_index),
2645 queue->queue_idx);
2646 return VK_SUCCESS;
2647 }
2648
2649 VkResult radv_DeviceWaitIdle(
2650 VkDevice _device)
2651 {
2652 RADV_FROM_HANDLE(radv_device, device, _device);
2653
2654 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2655 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2656 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2657 }
2658 }
2659 return VK_SUCCESS;
2660 }
2661
2662 VkResult radv_EnumerateInstanceExtensionProperties(
2663 const char* pLayerName,
2664 uint32_t* pPropertyCount,
2665 VkExtensionProperties* pProperties)
2666 {
2667 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2668
2669 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2670 if (radv_supported_instance_extensions.extensions[i]) {
2671 vk_outarray_append(&out, prop) {
2672 *prop = radv_instance_extensions[i];
2673 }
2674 }
2675 }
2676
2677 return vk_outarray_status(&out);
2678 }
2679
2680 VkResult radv_EnumerateDeviceExtensionProperties(
2681 VkPhysicalDevice physicalDevice,
2682 const char* pLayerName,
2683 uint32_t* pPropertyCount,
2684 VkExtensionProperties* pProperties)
2685 {
2686 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2687 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2688
2689 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2690 if (device->supported_extensions.extensions[i]) {
2691 vk_outarray_append(&out, prop) {
2692 *prop = radv_device_extensions[i];
2693 }
2694 }
2695 }
2696
2697 return vk_outarray_status(&out);
2698 }
2699
2700 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2701 VkInstance _instance,
2702 const char* pName)
2703 {
2704 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2705
2706 return radv_lookup_entrypoint_checked(pName,
2707 instance ? instance->apiVersion : 0,
2708 instance ? &instance->enabled_extensions : NULL,
2709 NULL);
2710 }
2711
2712 /* The loader wants us to expose a second GetInstanceProcAddr function
2713 * to work around certain LD_PRELOAD issues seen in apps.
2714 */
2715 PUBLIC
2716 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2717 VkInstance instance,
2718 const char* pName);
2719
2720 PUBLIC
2721 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2722 VkInstance instance,
2723 const char* pName)
2724 {
2725 return radv_GetInstanceProcAddr(instance, pName);
2726 }
2727
2728 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2729 VkDevice _device,
2730 const char* pName)
2731 {
2732 RADV_FROM_HANDLE(radv_device, device, _device);
2733
2734 return radv_lookup_entrypoint_checked(pName,
2735 device->instance->apiVersion,
2736 &device->instance->enabled_extensions,
2737 &device->enabled_extensions);
2738 }
2739
2740 bool radv_get_memory_fd(struct radv_device *device,
2741 struct radv_device_memory *memory,
2742 int *pFD)
2743 {
2744 struct radeon_bo_metadata metadata;
2745
2746 if (memory->image) {
2747 radv_init_metadata(device, memory->image, &metadata);
2748 device->ws->buffer_set_metadata(memory->bo, &metadata);
2749 }
2750
2751 return device->ws->buffer_get_fd(device->ws, memory->bo,
2752 pFD);
2753 }
2754
2755 static VkResult radv_alloc_memory(struct radv_device *device,
2756 const VkMemoryAllocateInfo* pAllocateInfo,
2757 const VkAllocationCallbacks* pAllocator,
2758 VkDeviceMemory* pMem)
2759 {
2760 struct radv_device_memory *mem;
2761 VkResult result;
2762 enum radeon_bo_domain domain;
2763 uint32_t flags = 0;
2764 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2765
2766 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2767
2768 if (pAllocateInfo->allocationSize == 0) {
2769 /* Apparently, this is allowed */
2770 *pMem = VK_NULL_HANDLE;
2771 return VK_SUCCESS;
2772 }
2773
2774 const VkImportMemoryFdInfoKHR *import_info =
2775 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2776 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2777 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2778 const VkExportMemoryAllocateInfoKHR *export_info =
2779 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2780 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2781 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2782
2783 const struct wsi_memory_allocate_info *wsi_info =
2784 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2785
2786 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2787 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2788 if (mem == NULL)
2789 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2790
2791 if (wsi_info && wsi_info->implicit_sync)
2792 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2793
2794 if (dedicate_info) {
2795 mem->image = radv_image_from_handle(dedicate_info->image);
2796 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2797 } else {
2798 mem->image = NULL;
2799 mem->buffer = NULL;
2800 }
2801
2802 mem->user_ptr = NULL;
2803
2804 if (import_info) {
2805 assert(import_info->handleType ==
2806 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2807 import_info->handleType ==
2808 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2809 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2810 NULL, NULL);
2811 if (!mem->bo) {
2812 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2813 goto fail;
2814 } else {
2815 close(import_info->fd);
2816 }
2817 } else if (host_ptr_info) {
2818 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2819 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2820 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2821 pAllocateInfo->allocationSize);
2822 if (!mem->bo) {
2823 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2824 goto fail;
2825 } else {
2826 mem->user_ptr = host_ptr_info->pHostPointer;
2827 }
2828 } else {
2829 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2830 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2831 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2832 domain = RADEON_DOMAIN_GTT;
2833 else
2834 domain = RADEON_DOMAIN_VRAM;
2835
2836 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2837 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2838 else
2839 flags |= RADEON_FLAG_CPU_ACCESS;
2840
2841 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2842 flags |= RADEON_FLAG_GTT_WC;
2843
2844 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2845 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2846
2847 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2848 domain, flags);
2849
2850 if (!mem->bo) {
2851 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2852 goto fail;
2853 }
2854 mem->type_index = mem_type_index;
2855 }
2856
2857 result = radv_bo_list_add(device, mem->bo);
2858 if (result != VK_SUCCESS)
2859 goto fail_bo;
2860
2861 *pMem = radv_device_memory_to_handle(mem);
2862
2863 return VK_SUCCESS;
2864
2865 fail_bo:
2866 device->ws->buffer_destroy(mem->bo);
2867 fail:
2868 vk_free2(&device->alloc, pAllocator, mem);
2869
2870 return result;
2871 }
2872
2873 VkResult radv_AllocateMemory(
2874 VkDevice _device,
2875 const VkMemoryAllocateInfo* pAllocateInfo,
2876 const VkAllocationCallbacks* pAllocator,
2877 VkDeviceMemory* pMem)
2878 {
2879 RADV_FROM_HANDLE(radv_device, device, _device);
2880 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2881 }
2882
2883 void radv_FreeMemory(
2884 VkDevice _device,
2885 VkDeviceMemory _mem,
2886 const VkAllocationCallbacks* pAllocator)
2887 {
2888 RADV_FROM_HANDLE(radv_device, device, _device);
2889 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2890
2891 if (mem == NULL)
2892 return;
2893
2894 radv_bo_list_remove(device, mem->bo);
2895 device->ws->buffer_destroy(mem->bo);
2896 mem->bo = NULL;
2897
2898 vk_free2(&device->alloc, pAllocator, mem);
2899 }
2900
2901 VkResult radv_MapMemory(
2902 VkDevice _device,
2903 VkDeviceMemory _memory,
2904 VkDeviceSize offset,
2905 VkDeviceSize size,
2906 VkMemoryMapFlags flags,
2907 void** ppData)
2908 {
2909 RADV_FROM_HANDLE(radv_device, device, _device);
2910 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2911
2912 if (mem == NULL) {
2913 *ppData = NULL;
2914 return VK_SUCCESS;
2915 }
2916
2917 if (mem->user_ptr)
2918 *ppData = mem->user_ptr;
2919 else
2920 *ppData = device->ws->buffer_map(mem->bo);
2921
2922 if (*ppData) {
2923 *ppData += offset;
2924 return VK_SUCCESS;
2925 }
2926
2927 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2928 }
2929
2930 void radv_UnmapMemory(
2931 VkDevice _device,
2932 VkDeviceMemory _memory)
2933 {
2934 RADV_FROM_HANDLE(radv_device, device, _device);
2935 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2936
2937 if (mem == NULL)
2938 return;
2939
2940 if (mem->user_ptr == NULL)
2941 device->ws->buffer_unmap(mem->bo);
2942 }
2943
2944 VkResult radv_FlushMappedMemoryRanges(
2945 VkDevice _device,
2946 uint32_t memoryRangeCount,
2947 const VkMappedMemoryRange* pMemoryRanges)
2948 {
2949 return VK_SUCCESS;
2950 }
2951
2952 VkResult radv_InvalidateMappedMemoryRanges(
2953 VkDevice _device,
2954 uint32_t memoryRangeCount,
2955 const VkMappedMemoryRange* pMemoryRanges)
2956 {
2957 return VK_SUCCESS;
2958 }
2959
2960 void radv_GetBufferMemoryRequirements(
2961 VkDevice _device,
2962 VkBuffer _buffer,
2963 VkMemoryRequirements* pMemoryRequirements)
2964 {
2965 RADV_FROM_HANDLE(radv_device, device, _device);
2966 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2967
2968 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2969
2970 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2971 pMemoryRequirements->alignment = 4096;
2972 else
2973 pMemoryRequirements->alignment = 16;
2974
2975 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2976 }
2977
2978 void radv_GetBufferMemoryRequirements2(
2979 VkDevice device,
2980 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2981 VkMemoryRequirements2KHR* pMemoryRequirements)
2982 {
2983 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2984 &pMemoryRequirements->memoryRequirements);
2985 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2986 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2987 switch (ext->sType) {
2988 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2989 VkMemoryDedicatedRequirementsKHR *req =
2990 (VkMemoryDedicatedRequirementsKHR *) ext;
2991 req->requiresDedicatedAllocation = buffer->shareable;
2992 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2993 break;
2994 }
2995 default:
2996 break;
2997 }
2998 }
2999 }
3000
3001 void radv_GetImageMemoryRequirements(
3002 VkDevice _device,
3003 VkImage _image,
3004 VkMemoryRequirements* pMemoryRequirements)
3005 {
3006 RADV_FROM_HANDLE(radv_device, device, _device);
3007 RADV_FROM_HANDLE(radv_image, image, _image);
3008
3009 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3010
3011 pMemoryRequirements->size = image->size;
3012 pMemoryRequirements->alignment = image->alignment;
3013 }
3014
3015 void radv_GetImageMemoryRequirements2(
3016 VkDevice device,
3017 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3018 VkMemoryRequirements2KHR* pMemoryRequirements)
3019 {
3020 radv_GetImageMemoryRequirements(device, pInfo->image,
3021 &pMemoryRequirements->memoryRequirements);
3022
3023 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3024
3025 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3026 switch (ext->sType) {
3027 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3028 VkMemoryDedicatedRequirementsKHR *req =
3029 (VkMemoryDedicatedRequirementsKHR *) ext;
3030 req->requiresDedicatedAllocation = image->shareable;
3031 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3032 break;
3033 }
3034 default:
3035 break;
3036 }
3037 }
3038 }
3039
3040 void radv_GetImageSparseMemoryRequirements(
3041 VkDevice device,
3042 VkImage image,
3043 uint32_t* pSparseMemoryRequirementCount,
3044 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3045 {
3046 stub();
3047 }
3048
3049 void radv_GetImageSparseMemoryRequirements2(
3050 VkDevice device,
3051 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3052 uint32_t* pSparseMemoryRequirementCount,
3053 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3054 {
3055 stub();
3056 }
3057
3058 void radv_GetDeviceMemoryCommitment(
3059 VkDevice device,
3060 VkDeviceMemory memory,
3061 VkDeviceSize* pCommittedMemoryInBytes)
3062 {
3063 *pCommittedMemoryInBytes = 0;
3064 }
3065
3066 VkResult radv_BindBufferMemory2(VkDevice device,
3067 uint32_t bindInfoCount,
3068 const VkBindBufferMemoryInfoKHR *pBindInfos)
3069 {
3070 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3071 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3072 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3073
3074 if (mem) {
3075 buffer->bo = mem->bo;
3076 buffer->offset = pBindInfos[i].memoryOffset;
3077 } else {
3078 buffer->bo = NULL;
3079 }
3080 }
3081 return VK_SUCCESS;
3082 }
3083
3084 VkResult radv_BindBufferMemory(
3085 VkDevice device,
3086 VkBuffer buffer,
3087 VkDeviceMemory memory,
3088 VkDeviceSize memoryOffset)
3089 {
3090 const VkBindBufferMemoryInfoKHR info = {
3091 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3092 .buffer = buffer,
3093 .memory = memory,
3094 .memoryOffset = memoryOffset
3095 };
3096
3097 return radv_BindBufferMemory2(device, 1, &info);
3098 }
3099
3100 VkResult radv_BindImageMemory2(VkDevice device,
3101 uint32_t bindInfoCount,
3102 const VkBindImageMemoryInfoKHR *pBindInfos)
3103 {
3104 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3105 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3106 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3107
3108 if (mem) {
3109 image->bo = mem->bo;
3110 image->offset = pBindInfos[i].memoryOffset;
3111 } else {
3112 image->bo = NULL;
3113 image->offset = 0;
3114 }
3115 }
3116 return VK_SUCCESS;
3117 }
3118
3119
3120 VkResult radv_BindImageMemory(
3121 VkDevice device,
3122 VkImage image,
3123 VkDeviceMemory memory,
3124 VkDeviceSize memoryOffset)
3125 {
3126 const VkBindImageMemoryInfoKHR info = {
3127 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3128 .image = image,
3129 .memory = memory,
3130 .memoryOffset = memoryOffset
3131 };
3132
3133 return radv_BindImageMemory2(device, 1, &info);
3134 }
3135
3136
3137 static void
3138 radv_sparse_buffer_bind_memory(struct radv_device *device,
3139 const VkSparseBufferMemoryBindInfo *bind)
3140 {
3141 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3142
3143 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3144 struct radv_device_memory *mem = NULL;
3145
3146 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3147 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3148
3149 device->ws->buffer_virtual_bind(buffer->bo,
3150 bind->pBinds[i].resourceOffset,
3151 bind->pBinds[i].size,
3152 mem ? mem->bo : NULL,
3153 bind->pBinds[i].memoryOffset);
3154 }
3155 }
3156
3157 static void
3158 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3159 const VkSparseImageOpaqueMemoryBindInfo *bind)
3160 {
3161 RADV_FROM_HANDLE(radv_image, image, bind->image);
3162
3163 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3164 struct radv_device_memory *mem = NULL;
3165
3166 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3167 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3168
3169 device->ws->buffer_virtual_bind(image->bo,
3170 bind->pBinds[i].resourceOffset,
3171 bind->pBinds[i].size,
3172 mem ? mem->bo : NULL,
3173 bind->pBinds[i].memoryOffset);
3174 }
3175 }
3176
3177 VkResult radv_QueueBindSparse(
3178 VkQueue _queue,
3179 uint32_t bindInfoCount,
3180 const VkBindSparseInfo* pBindInfo,
3181 VkFence _fence)
3182 {
3183 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3184 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3185 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3186 bool fence_emitted = false;
3187 VkResult result;
3188 int ret;
3189
3190 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3191 struct radv_winsys_sem_info sem_info;
3192 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3193 radv_sparse_buffer_bind_memory(queue->device,
3194 pBindInfo[i].pBufferBinds + j);
3195 }
3196
3197 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3198 radv_sparse_image_opaque_bind_memory(queue->device,
3199 pBindInfo[i].pImageOpaqueBinds + j);
3200 }
3201
3202 VkResult result;
3203 result = radv_alloc_sem_info(queue->device->instance,
3204 &sem_info,
3205 pBindInfo[i].waitSemaphoreCount,
3206 pBindInfo[i].pWaitSemaphores,
3207 pBindInfo[i].signalSemaphoreCount,
3208 pBindInfo[i].pSignalSemaphores,
3209 _fence);
3210 if (result != VK_SUCCESS)
3211 return result;
3212
3213 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3214 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3215 &queue->device->empty_cs[queue->queue_family_index],
3216 1, NULL, NULL,
3217 &sem_info, NULL,
3218 false, base_fence);
3219 if (ret) {
3220 radv_loge("failed to submit CS %d\n", i);
3221 abort();
3222 }
3223
3224 fence_emitted = true;
3225 if (fence)
3226 fence->submitted = true;
3227 }
3228
3229 radv_free_sem_info(&sem_info);
3230
3231 }
3232
3233 if (fence) {
3234 if (!fence_emitted) {
3235 result = radv_signal_fence(queue, fence);
3236 if (result != VK_SUCCESS)
3237 return result;
3238 }
3239 fence->submitted = true;
3240 }
3241
3242 return VK_SUCCESS;
3243 }
3244
3245 VkResult radv_CreateFence(
3246 VkDevice _device,
3247 const VkFenceCreateInfo* pCreateInfo,
3248 const VkAllocationCallbacks* pAllocator,
3249 VkFence* pFence)
3250 {
3251 RADV_FROM_HANDLE(radv_device, device, _device);
3252 const VkExportFenceCreateInfoKHR *export =
3253 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3254 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3255 export ? export->handleTypes : 0;
3256
3257 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3258 sizeof(*fence), 8,
3259 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3260
3261 if (!fence)
3262 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3263
3264 fence->fence_wsi = NULL;
3265 fence->submitted = false;
3266 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3267 fence->temp_syncobj = 0;
3268 if (device->always_use_syncobj || handleTypes) {
3269 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3270 if (ret) {
3271 vk_free2(&device->alloc, pAllocator, fence);
3272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3273 }
3274 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3275 device->ws->signal_syncobj(device->ws, fence->syncobj);
3276 }
3277 fence->fence = NULL;
3278 } else {
3279 fence->fence = device->ws->create_fence();
3280 if (!fence->fence) {
3281 vk_free2(&device->alloc, pAllocator, fence);
3282 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3283 }
3284 fence->syncobj = 0;
3285 }
3286
3287 *pFence = radv_fence_to_handle(fence);
3288
3289 return VK_SUCCESS;
3290 }
3291
3292 void radv_DestroyFence(
3293 VkDevice _device,
3294 VkFence _fence,
3295 const VkAllocationCallbacks* pAllocator)
3296 {
3297 RADV_FROM_HANDLE(radv_device, device, _device);
3298 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3299
3300 if (!fence)
3301 return;
3302
3303 if (fence->temp_syncobj)
3304 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3305 if (fence->syncobj)
3306 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3307 if (fence->fence)
3308 device->ws->destroy_fence(fence->fence);
3309 if (fence->fence_wsi)
3310 fence->fence_wsi->destroy(fence->fence_wsi);
3311 vk_free2(&device->alloc, pAllocator, fence);
3312 }
3313
3314
3315 static uint64_t radv_get_current_time()
3316 {
3317 struct timespec tv;
3318 clock_gettime(CLOCK_MONOTONIC, &tv);
3319 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3320 }
3321
3322 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3323 {
3324 uint64_t current_time = radv_get_current_time();
3325
3326 timeout = MIN2(UINT64_MAX - current_time, timeout);
3327
3328 return current_time + timeout;
3329 }
3330
3331
3332 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3333 {
3334 for (uint32_t i = 0; i < fenceCount; ++i) {
3335 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3336 if (fence->fence == NULL || fence->syncobj ||
3337 fence->temp_syncobj ||
3338 (!fence->signalled && !fence->submitted))
3339 return false;
3340 }
3341 return true;
3342 }
3343
3344 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3345 {
3346 for (uint32_t i = 0; i < fenceCount; ++i) {
3347 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3348 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3349 return false;
3350 }
3351 return true;
3352 }
3353
3354 VkResult radv_WaitForFences(
3355 VkDevice _device,
3356 uint32_t fenceCount,
3357 const VkFence* pFences,
3358 VkBool32 waitAll,
3359 uint64_t timeout)
3360 {
3361 RADV_FROM_HANDLE(radv_device, device, _device);
3362 timeout = radv_get_absolute_timeout(timeout);
3363
3364 if (device->always_use_syncobj &&
3365 radv_all_fences_syncobj(fenceCount, pFences))
3366 {
3367 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3368 if (!handles)
3369 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3370
3371 for (uint32_t i = 0; i < fenceCount; ++i) {
3372 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3373 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3374 }
3375
3376 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3377
3378 free(handles);
3379 return success ? VK_SUCCESS : VK_TIMEOUT;
3380 }
3381
3382 if (!waitAll && fenceCount > 1) {
3383 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3384 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3385 uint32_t wait_count = 0;
3386 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3387 if (!fences)
3388 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3389
3390 for (uint32_t i = 0; i < fenceCount; ++i) {
3391 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3392
3393 if (fence->signalled) {
3394 free(fences);
3395 return VK_SUCCESS;
3396 }
3397
3398 fences[wait_count++] = fence->fence;
3399 }
3400
3401 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3402 waitAll, timeout - radv_get_current_time());
3403
3404 free(fences);
3405 return success ? VK_SUCCESS : VK_TIMEOUT;
3406 }
3407
3408 while(radv_get_current_time() <= timeout) {
3409 for (uint32_t i = 0; i < fenceCount; ++i) {
3410 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3411 return VK_SUCCESS;
3412 }
3413 }
3414 return VK_TIMEOUT;
3415 }
3416
3417 for (uint32_t i = 0; i < fenceCount; ++i) {
3418 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3419 bool expired = false;
3420
3421 if (fence->temp_syncobj) {
3422 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3423 return VK_TIMEOUT;
3424 continue;
3425 }
3426
3427 if (fence->syncobj) {
3428 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3429 return VK_TIMEOUT;
3430 continue;
3431 }
3432
3433 if (fence->signalled)
3434 continue;
3435
3436 if (fence->fence) {
3437 if (!fence->submitted) {
3438 while(radv_get_current_time() <= timeout &&
3439 !fence->submitted)
3440 /* Do nothing */;
3441
3442 if (!fence->submitted)
3443 return VK_TIMEOUT;
3444
3445 /* Recheck as it may have been set by
3446 * submitting operations. */
3447
3448 if (fence->signalled)
3449 continue;
3450 }
3451
3452 expired = device->ws->fence_wait(device->ws,
3453 fence->fence,
3454 true, timeout);
3455 if (!expired)
3456 return VK_TIMEOUT;
3457 }
3458
3459 if (fence->fence_wsi) {
3460 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3461 if (result != VK_SUCCESS)
3462 return result;
3463 }
3464
3465 fence->signalled = true;
3466 }
3467
3468 return VK_SUCCESS;
3469 }
3470
3471 VkResult radv_ResetFences(VkDevice _device,
3472 uint32_t fenceCount,
3473 const VkFence *pFences)
3474 {
3475 RADV_FROM_HANDLE(radv_device, device, _device);
3476
3477 for (unsigned i = 0; i < fenceCount; ++i) {
3478 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3479 fence->submitted = fence->signalled = false;
3480
3481 /* Per spec, we first restore the permanent payload, and then reset, so
3482 * having a temp syncobj should not skip resetting the permanent syncobj. */
3483 if (fence->temp_syncobj) {
3484 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3485 fence->temp_syncobj = 0;
3486 }
3487
3488 if (fence->syncobj) {
3489 device->ws->reset_syncobj(device->ws, fence->syncobj);
3490 }
3491 }
3492
3493 return VK_SUCCESS;
3494 }
3495
3496 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3497 {
3498 RADV_FROM_HANDLE(radv_device, device, _device);
3499 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3500
3501 if (fence->temp_syncobj) {
3502 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3503 return success ? VK_SUCCESS : VK_NOT_READY;
3504 }
3505
3506 if (fence->syncobj) {
3507 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3508 return success ? VK_SUCCESS : VK_NOT_READY;
3509 }
3510
3511 if (fence->signalled)
3512 return VK_SUCCESS;
3513 if (!fence->submitted)
3514 return VK_NOT_READY;
3515 if (fence->fence) {
3516 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3517 return VK_NOT_READY;
3518 }
3519 if (fence->fence_wsi) {
3520 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3521
3522 if (result != VK_SUCCESS) {
3523 if (result == VK_TIMEOUT)
3524 return VK_NOT_READY;
3525 return result;
3526 }
3527 }
3528 return VK_SUCCESS;
3529 }
3530
3531
3532 // Queue semaphore functions
3533
3534 VkResult radv_CreateSemaphore(
3535 VkDevice _device,
3536 const VkSemaphoreCreateInfo* pCreateInfo,
3537 const VkAllocationCallbacks* pAllocator,
3538 VkSemaphore* pSemaphore)
3539 {
3540 RADV_FROM_HANDLE(radv_device, device, _device);
3541 const VkExportSemaphoreCreateInfoKHR *export =
3542 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3543 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3544 export ? export->handleTypes : 0;
3545
3546 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3547 sizeof(*sem), 8,
3548 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3549 if (!sem)
3550 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3551
3552 sem->temp_syncobj = 0;
3553 /* create a syncobject if we are going to export this semaphore */
3554 if (device->always_use_syncobj || handleTypes) {
3555 assert (device->physical_device->rad_info.has_syncobj);
3556 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3557 if (ret) {
3558 vk_free2(&device->alloc, pAllocator, sem);
3559 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3560 }
3561 sem->sem = NULL;
3562 } else {
3563 sem->sem = device->ws->create_sem(device->ws);
3564 if (!sem->sem) {
3565 vk_free2(&device->alloc, pAllocator, sem);
3566 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3567 }
3568 sem->syncobj = 0;
3569 }
3570
3571 *pSemaphore = radv_semaphore_to_handle(sem);
3572 return VK_SUCCESS;
3573 }
3574
3575 void radv_DestroySemaphore(
3576 VkDevice _device,
3577 VkSemaphore _semaphore,
3578 const VkAllocationCallbacks* pAllocator)
3579 {
3580 RADV_FROM_HANDLE(radv_device, device, _device);
3581 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3582 if (!_semaphore)
3583 return;
3584
3585 if (sem->syncobj)
3586 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3587 else
3588 device->ws->destroy_sem(sem->sem);
3589 vk_free2(&device->alloc, pAllocator, sem);
3590 }
3591
3592 VkResult radv_CreateEvent(
3593 VkDevice _device,
3594 const VkEventCreateInfo* pCreateInfo,
3595 const VkAllocationCallbacks* pAllocator,
3596 VkEvent* pEvent)
3597 {
3598 RADV_FROM_HANDLE(radv_device, device, _device);
3599 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3600 sizeof(*event), 8,
3601 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3602
3603 if (!event)
3604 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3605
3606 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3607 RADEON_DOMAIN_GTT,
3608 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3609 if (!event->bo) {
3610 vk_free2(&device->alloc, pAllocator, event);
3611 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3612 }
3613
3614 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3615
3616 *pEvent = radv_event_to_handle(event);
3617
3618 return VK_SUCCESS;
3619 }
3620
3621 void radv_DestroyEvent(
3622 VkDevice _device,
3623 VkEvent _event,
3624 const VkAllocationCallbacks* pAllocator)
3625 {
3626 RADV_FROM_HANDLE(radv_device, device, _device);
3627 RADV_FROM_HANDLE(radv_event, event, _event);
3628
3629 if (!event)
3630 return;
3631 device->ws->buffer_destroy(event->bo);
3632 vk_free2(&device->alloc, pAllocator, event);
3633 }
3634
3635 VkResult radv_GetEventStatus(
3636 VkDevice _device,
3637 VkEvent _event)
3638 {
3639 RADV_FROM_HANDLE(radv_event, event, _event);
3640
3641 if (*event->map == 1)
3642 return VK_EVENT_SET;
3643 return VK_EVENT_RESET;
3644 }
3645
3646 VkResult radv_SetEvent(
3647 VkDevice _device,
3648 VkEvent _event)
3649 {
3650 RADV_FROM_HANDLE(radv_event, event, _event);
3651 *event->map = 1;
3652
3653 return VK_SUCCESS;
3654 }
3655
3656 VkResult radv_ResetEvent(
3657 VkDevice _device,
3658 VkEvent _event)
3659 {
3660 RADV_FROM_HANDLE(radv_event, event, _event);
3661 *event->map = 0;
3662
3663 return VK_SUCCESS;
3664 }
3665
3666 VkResult radv_CreateBuffer(
3667 VkDevice _device,
3668 const VkBufferCreateInfo* pCreateInfo,
3669 const VkAllocationCallbacks* pAllocator,
3670 VkBuffer* pBuffer)
3671 {
3672 RADV_FROM_HANDLE(radv_device, device, _device);
3673 struct radv_buffer *buffer;
3674
3675 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3676
3677 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3678 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3679 if (buffer == NULL)
3680 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3681
3682 buffer->size = pCreateInfo->size;
3683 buffer->usage = pCreateInfo->usage;
3684 buffer->bo = NULL;
3685 buffer->offset = 0;
3686 buffer->flags = pCreateInfo->flags;
3687
3688 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3689 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3690
3691 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3692 buffer->bo = device->ws->buffer_create(device->ws,
3693 align64(buffer->size, 4096),
3694 4096, 0, RADEON_FLAG_VIRTUAL);
3695 if (!buffer->bo) {
3696 vk_free2(&device->alloc, pAllocator, buffer);
3697 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3698 }
3699 }
3700
3701 *pBuffer = radv_buffer_to_handle(buffer);
3702
3703 return VK_SUCCESS;
3704 }
3705
3706 void radv_DestroyBuffer(
3707 VkDevice _device,
3708 VkBuffer _buffer,
3709 const VkAllocationCallbacks* pAllocator)
3710 {
3711 RADV_FROM_HANDLE(radv_device, device, _device);
3712 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3713
3714 if (!buffer)
3715 return;
3716
3717 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3718 device->ws->buffer_destroy(buffer->bo);
3719
3720 vk_free2(&device->alloc, pAllocator, buffer);
3721 }
3722
3723 static inline unsigned
3724 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3725 {
3726 if (stencil)
3727 return image->surface.u.legacy.stencil_tiling_index[level];
3728 else
3729 return image->surface.u.legacy.tiling_index[level];
3730 }
3731
3732 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3733 {
3734 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3735 }
3736
3737 static uint32_t
3738 radv_init_dcc_control_reg(struct radv_device *device,
3739 struct radv_image_view *iview)
3740 {
3741 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3742 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3743 unsigned max_compressed_block_size;
3744 unsigned independent_64b_blocks;
3745
3746 if (device->physical_device->rad_info.chip_class < VI)
3747 return 0;
3748
3749 if (iview->image->info.samples > 1) {
3750 if (iview->image->surface.bpe == 1)
3751 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3752 else if (iview->image->surface.bpe == 2)
3753 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3754 }
3755
3756 if (!device->physical_device->rad_info.has_dedicated_vram) {
3757 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3758 * dGPU and 64 for APU because all of our APUs to date use
3759 * DIMMs which have a request granularity size of 64B while all
3760 * other chips have a 32B request size.
3761 */
3762 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3763 }
3764
3765 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3766 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3767 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3768 /* If this DCC image is potentially going to be used in texture
3769 * fetches, we need some special settings.
3770 */
3771 independent_64b_blocks = 1;
3772 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3773 } else {
3774 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3775 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3776 * big as possible for better compression state.
3777 */
3778 independent_64b_blocks = 0;
3779 max_compressed_block_size = max_uncompressed_block_size;
3780 }
3781
3782 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3783 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3784 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3785 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3786 }
3787
3788 static void
3789 radv_initialise_color_surface(struct radv_device *device,
3790 struct radv_color_buffer_info *cb,
3791 struct radv_image_view *iview)
3792 {
3793 const struct vk_format_description *desc;
3794 unsigned ntype, format, swap, endian;
3795 unsigned blend_clamp = 0, blend_bypass = 0;
3796 uint64_t va;
3797 const struct radeon_surf *surf = &iview->image->surface;
3798
3799 desc = vk_format_description(iview->vk_format);
3800
3801 memset(cb, 0, sizeof(*cb));
3802
3803 /* Intensity is implemented as Red, so treat it that way. */
3804 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3805
3806 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3807
3808 cb->cb_color_base = va >> 8;
3809
3810 if (device->physical_device->rad_info.chip_class >= GFX9) {
3811 struct gfx9_surf_meta_flags meta;
3812 if (iview->image->dcc_offset)
3813 meta = iview->image->surface.u.gfx9.dcc;
3814 else
3815 meta = iview->image->surface.u.gfx9.cmask;
3816
3817 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3818 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3819 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3820 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3821
3822 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3823 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3824 } else {
3825 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3826 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3827
3828 cb->cb_color_base += level_info->offset >> 8;
3829 if (level_info->mode == RADEON_SURF_MODE_2D)
3830 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3831
3832 pitch_tile_max = level_info->nblk_x / 8 - 1;
3833 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3834 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3835
3836 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3837 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3838 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3839
3840 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3841
3842 if (radv_image_has_fmask(iview->image)) {
3843 if (device->physical_device->rad_info.chip_class >= CIK)
3844 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3845 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3846 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3847 } else {
3848 /* This must be set for fast clear to work without FMASK. */
3849 if (device->physical_device->rad_info.chip_class >= CIK)
3850 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3851 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3852 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3853 }
3854 }
3855
3856 /* CMASK variables */
3857 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3858 va += iview->image->cmask.offset;
3859 cb->cb_color_cmask = va >> 8;
3860
3861 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3862 va += iview->image->dcc_offset;
3863 cb->cb_dcc_base = va >> 8;
3864 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3865
3866 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3867 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3868 S_028C6C_SLICE_MAX(max_slice);
3869
3870 if (iview->image->info.samples > 1) {
3871 unsigned log_samples = util_logbase2(iview->image->info.samples);
3872
3873 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3874 S_028C74_NUM_FRAGMENTS(log_samples);
3875 }
3876
3877 if (radv_image_has_fmask(iview->image)) {
3878 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3879 cb->cb_color_fmask = va >> 8;
3880 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3881 } else {
3882 cb->cb_color_fmask = cb->cb_color_base;
3883 }
3884
3885 ntype = radv_translate_color_numformat(iview->vk_format,
3886 desc,
3887 vk_format_get_first_non_void_channel(iview->vk_format));
3888 format = radv_translate_colorformat(iview->vk_format);
3889 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3890 radv_finishme("Illegal color\n");
3891 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3892 endian = radv_colorformat_endian_swap(format);
3893
3894 /* blend clamp should be set for all NORM/SRGB types */
3895 if (ntype == V_028C70_NUMBER_UNORM ||
3896 ntype == V_028C70_NUMBER_SNORM ||
3897 ntype == V_028C70_NUMBER_SRGB)
3898 blend_clamp = 1;
3899
3900 /* set blend bypass according to docs if SINT/UINT or
3901 8/24 COLOR variants */
3902 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3903 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3904 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3905 blend_clamp = 0;
3906 blend_bypass = 1;
3907 }
3908 #if 0
3909 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3910 (format == V_028C70_COLOR_8 ||
3911 format == V_028C70_COLOR_8_8 ||
3912 format == V_028C70_COLOR_8_8_8_8))
3913 ->color_is_int8 = true;
3914 #endif
3915 cb->cb_color_info = S_028C70_FORMAT(format) |
3916 S_028C70_COMP_SWAP(swap) |
3917 S_028C70_BLEND_CLAMP(blend_clamp) |
3918 S_028C70_BLEND_BYPASS(blend_bypass) |
3919 S_028C70_SIMPLE_FLOAT(1) |
3920 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3921 ntype != V_028C70_NUMBER_SNORM &&
3922 ntype != V_028C70_NUMBER_SRGB &&
3923 format != V_028C70_COLOR_8_24 &&
3924 format != V_028C70_COLOR_24_8) |
3925 S_028C70_NUMBER_TYPE(ntype) |
3926 S_028C70_ENDIAN(endian);
3927 if (radv_image_has_fmask(iview->image)) {
3928 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3929 if (device->physical_device->rad_info.chip_class == SI) {
3930 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3931 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3932 }
3933 }
3934
3935 if (radv_image_has_cmask(iview->image) &&
3936 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3937 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3938
3939 if (radv_dcc_enabled(iview->image, iview->base_mip))
3940 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3941
3942 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3943
3944 /* This must be set for fast clear to work without FMASK. */
3945 if (!radv_image_has_fmask(iview->image) &&
3946 device->physical_device->rad_info.chip_class == SI) {
3947 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3948 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3949 }
3950
3951 if (device->physical_device->rad_info.chip_class >= GFX9) {
3952 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3953 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3954
3955 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3956 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3957 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3958 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3959 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3960 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3961 }
3962 }
3963
3964 static unsigned
3965 radv_calc_decompress_on_z_planes(struct radv_device *device,
3966 struct radv_image_view *iview)
3967 {
3968 unsigned max_zplanes = 0;
3969
3970 assert(radv_image_is_tc_compat_htile(iview->image));
3971
3972 if (device->physical_device->rad_info.chip_class >= GFX9) {
3973 /* Default value for 32-bit depth surfaces. */
3974 max_zplanes = 4;
3975
3976 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3977 iview->image->info.samples > 1)
3978 max_zplanes = 2;
3979
3980 max_zplanes = max_zplanes + 1;
3981 } else {
3982 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3983 /* Do not enable Z plane compression for 16-bit depth
3984 * surfaces because isn't supported on GFX8. Only
3985 * 32-bit depth surfaces are supported by the hardware.
3986 * This allows to maintain shader compatibility and to
3987 * reduce the number of depth decompressions.
3988 */
3989 max_zplanes = 1;
3990 } else {
3991 if (iview->image->info.samples <= 1)
3992 max_zplanes = 5;
3993 else if (iview->image->info.samples <= 4)
3994 max_zplanes = 3;
3995 else
3996 max_zplanes = 2;
3997 }
3998 }
3999
4000 return max_zplanes;
4001 }
4002
4003 static void
4004 radv_initialise_ds_surface(struct radv_device *device,
4005 struct radv_ds_buffer_info *ds,
4006 struct radv_image_view *iview)
4007 {
4008 unsigned level = iview->base_mip;
4009 unsigned format, stencil_format;
4010 uint64_t va, s_offs, z_offs;
4011 bool stencil_only = false;
4012 memset(ds, 0, sizeof(*ds));
4013 switch (iview->image->vk_format) {
4014 case VK_FORMAT_D24_UNORM_S8_UINT:
4015 case VK_FORMAT_X8_D24_UNORM_PACK32:
4016 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4017 ds->offset_scale = 2.0f;
4018 break;
4019 case VK_FORMAT_D16_UNORM:
4020 case VK_FORMAT_D16_UNORM_S8_UINT:
4021 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4022 ds->offset_scale = 4.0f;
4023 break;
4024 case VK_FORMAT_D32_SFLOAT:
4025 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4026 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4027 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4028 ds->offset_scale = 1.0f;
4029 break;
4030 case VK_FORMAT_S8_UINT:
4031 stencil_only = true;
4032 break;
4033 default:
4034 break;
4035 }
4036
4037 format = radv_translate_dbformat(iview->image->vk_format);
4038 stencil_format = iview->image->surface.has_stencil ?
4039 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4040
4041 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4042 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4043 S_028008_SLICE_MAX(max_slice);
4044
4045 ds->db_htile_data_base = 0;
4046 ds->db_htile_surface = 0;
4047
4048 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4049 s_offs = z_offs = va;
4050
4051 if (device->physical_device->rad_info.chip_class >= GFX9) {
4052 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4053 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4054
4055 ds->db_z_info = S_028038_FORMAT(format) |
4056 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4057 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4058 S_028038_MAXMIP(iview->image->info.levels - 1) |
4059 S_028038_ZRANGE_PRECISION(1);
4060 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4061 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4062
4063 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4064 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4065 ds->db_depth_view |= S_028008_MIPID(level);
4066
4067 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4068 S_02801C_Y_MAX(iview->image->info.height - 1);
4069
4070 if (radv_htile_enabled(iview->image, level)) {
4071 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4072
4073 if (radv_image_is_tc_compat_htile(iview->image)) {
4074 unsigned max_zplanes =
4075 radv_calc_decompress_on_z_planes(device, iview);
4076
4077 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4078 S_028038_ITERATE_FLUSH(1);
4079 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4080 }
4081
4082 if (!iview->image->surface.has_stencil)
4083 /* Use all of the htile_buffer for depth if there's no stencil. */
4084 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4085 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4086 iview->image->htile_offset;
4087 ds->db_htile_data_base = va >> 8;
4088 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4089 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4090 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4091 }
4092 } else {
4093 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4094
4095 if (stencil_only)
4096 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4097
4098 z_offs += iview->image->surface.u.legacy.level[level].offset;
4099 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4100
4101 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4102 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4103 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4104
4105 if (iview->image->info.samples > 1)
4106 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4107
4108 if (device->physical_device->rad_info.chip_class >= CIK) {
4109 struct radeon_info *info = &device->physical_device->rad_info;
4110 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4111 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4112 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4113 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4114 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4115 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4116
4117 if (stencil_only)
4118 tile_mode = stencil_tile_mode;
4119
4120 ds->db_depth_info |=
4121 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4122 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4123 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4124 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4125 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4126 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4127 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4128 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4129 } else {
4130 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4131 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4132 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4133 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4134 if (stencil_only)
4135 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4136 }
4137
4138 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4139 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4140 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4141
4142 if (radv_htile_enabled(iview->image, level)) {
4143 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4144
4145 if (!iview->image->surface.has_stencil &&
4146 !radv_image_is_tc_compat_htile(iview->image))
4147 /* Use all of the htile_buffer for depth if there's no stencil. */
4148 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4149
4150 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4151 iview->image->htile_offset;
4152 ds->db_htile_data_base = va >> 8;
4153 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4154
4155 if (radv_image_is_tc_compat_htile(iview->image)) {
4156 unsigned max_zplanes =
4157 radv_calc_decompress_on_z_planes(device, iview);
4158
4159 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4160 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4161 }
4162 }
4163 }
4164
4165 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4166 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4167 }
4168
4169 VkResult radv_CreateFramebuffer(
4170 VkDevice _device,
4171 const VkFramebufferCreateInfo* pCreateInfo,
4172 const VkAllocationCallbacks* pAllocator,
4173 VkFramebuffer* pFramebuffer)
4174 {
4175 RADV_FROM_HANDLE(radv_device, device, _device);
4176 struct radv_framebuffer *framebuffer;
4177
4178 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4179
4180 size_t size = sizeof(*framebuffer) +
4181 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4182 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4183 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4184 if (framebuffer == NULL)
4185 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4186
4187 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4188 framebuffer->width = pCreateInfo->width;
4189 framebuffer->height = pCreateInfo->height;
4190 framebuffer->layers = pCreateInfo->layers;
4191 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4192 VkImageView _iview = pCreateInfo->pAttachments[i];
4193 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4194 framebuffer->attachments[i].attachment = iview;
4195 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4196 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4197 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4198 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4199 }
4200 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4201 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4202 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4203 }
4204
4205 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4206 return VK_SUCCESS;
4207 }
4208
4209 void radv_DestroyFramebuffer(
4210 VkDevice _device,
4211 VkFramebuffer _fb,
4212 const VkAllocationCallbacks* pAllocator)
4213 {
4214 RADV_FROM_HANDLE(radv_device, device, _device);
4215 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4216
4217 if (!fb)
4218 return;
4219 vk_free2(&device->alloc, pAllocator, fb);
4220 }
4221
4222 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4223 {
4224 switch (address_mode) {
4225 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4226 return V_008F30_SQ_TEX_WRAP;
4227 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4228 return V_008F30_SQ_TEX_MIRROR;
4229 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4230 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4231 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4232 return V_008F30_SQ_TEX_CLAMP_BORDER;
4233 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4234 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4235 default:
4236 unreachable("illegal tex wrap mode");
4237 break;
4238 }
4239 }
4240
4241 static unsigned
4242 radv_tex_compare(VkCompareOp op)
4243 {
4244 switch (op) {
4245 case VK_COMPARE_OP_NEVER:
4246 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4247 case VK_COMPARE_OP_LESS:
4248 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4249 case VK_COMPARE_OP_EQUAL:
4250 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4251 case VK_COMPARE_OP_LESS_OR_EQUAL:
4252 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4253 case VK_COMPARE_OP_GREATER:
4254 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4255 case VK_COMPARE_OP_NOT_EQUAL:
4256 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4257 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4258 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4259 case VK_COMPARE_OP_ALWAYS:
4260 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4261 default:
4262 unreachable("illegal compare mode");
4263 break;
4264 }
4265 }
4266
4267 static unsigned
4268 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4269 {
4270 switch (filter) {
4271 case VK_FILTER_NEAREST:
4272 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4273 V_008F38_SQ_TEX_XY_FILTER_POINT);
4274 case VK_FILTER_LINEAR:
4275 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4276 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4277 case VK_FILTER_CUBIC_IMG:
4278 default:
4279 fprintf(stderr, "illegal texture filter");
4280 return 0;
4281 }
4282 }
4283
4284 static unsigned
4285 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4286 {
4287 switch (mode) {
4288 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4289 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4290 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4291 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4292 default:
4293 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4294 }
4295 }
4296
4297 static unsigned
4298 radv_tex_bordercolor(VkBorderColor bcolor)
4299 {
4300 switch (bcolor) {
4301 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4302 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4303 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4304 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4305 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4306 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4307 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4308 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4309 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4310 default:
4311 break;
4312 }
4313 return 0;
4314 }
4315
4316 static unsigned
4317 radv_tex_aniso_filter(unsigned filter)
4318 {
4319 if (filter < 2)
4320 return 0;
4321 if (filter < 4)
4322 return 1;
4323 if (filter < 8)
4324 return 2;
4325 if (filter < 16)
4326 return 3;
4327 return 4;
4328 }
4329
4330 static unsigned
4331 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4332 {
4333 switch (mode) {
4334 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4335 return SQ_IMG_FILTER_MODE_BLEND;
4336 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4337 return SQ_IMG_FILTER_MODE_MIN;
4338 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4339 return SQ_IMG_FILTER_MODE_MAX;
4340 default:
4341 break;
4342 }
4343 return 0;
4344 }
4345
4346 static void
4347 radv_init_sampler(struct radv_device *device,
4348 struct radv_sampler *sampler,
4349 const VkSamplerCreateInfo *pCreateInfo)
4350 {
4351 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4352 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4353 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4354 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4355 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4356
4357 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4358 vk_find_struct_const(pCreateInfo->pNext,
4359 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4360 if (sampler_reduction)
4361 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4362
4363 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4364 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4365 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4366 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4367 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4368 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4369 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4370 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4371 S_008F30_DISABLE_CUBE_WRAP(0) |
4372 S_008F30_COMPAT_MODE(is_vi) |
4373 S_008F30_FILTER_MODE(filter_mode));
4374 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4375 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4376 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4377 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4378 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4379 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4380 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4381 S_008F38_MIP_POINT_PRECLAMP(0) |
4382 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4383 S_008F38_FILTER_PREC_FIX(1) |
4384 S_008F38_ANISO_OVERRIDE(is_vi));
4385 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4386 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4387 }
4388
4389 VkResult radv_CreateSampler(
4390 VkDevice _device,
4391 const VkSamplerCreateInfo* pCreateInfo,
4392 const VkAllocationCallbacks* pAllocator,
4393 VkSampler* pSampler)
4394 {
4395 RADV_FROM_HANDLE(radv_device, device, _device);
4396 struct radv_sampler *sampler;
4397
4398 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4399
4400 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4401 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4402 if (!sampler)
4403 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4404
4405 radv_init_sampler(device, sampler, pCreateInfo);
4406 *pSampler = radv_sampler_to_handle(sampler);
4407
4408 return VK_SUCCESS;
4409 }
4410
4411 void radv_DestroySampler(
4412 VkDevice _device,
4413 VkSampler _sampler,
4414 const VkAllocationCallbacks* pAllocator)
4415 {
4416 RADV_FROM_HANDLE(radv_device, device, _device);
4417 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4418
4419 if (!sampler)
4420 return;
4421 vk_free2(&device->alloc, pAllocator, sampler);
4422 }
4423
4424 /* vk_icd.h does not declare this function, so we declare it here to
4425 * suppress Wmissing-prototypes.
4426 */
4427 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4428 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4429
4430 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4431 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4432 {
4433 /* For the full details on loader interface versioning, see
4434 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4435 * What follows is a condensed summary, to help you navigate the large and
4436 * confusing official doc.
4437 *
4438 * - Loader interface v0 is incompatible with later versions. We don't
4439 * support it.
4440 *
4441 * - In loader interface v1:
4442 * - The first ICD entrypoint called by the loader is
4443 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4444 * entrypoint.
4445 * - The ICD must statically expose no other Vulkan symbol unless it is
4446 * linked with -Bsymbolic.
4447 * - Each dispatchable Vulkan handle created by the ICD must be
4448 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4449 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4450 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4451 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4452 * such loader-managed surfaces.
4453 *
4454 * - Loader interface v2 differs from v1 in:
4455 * - The first ICD entrypoint called by the loader is
4456 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4457 * statically expose this entrypoint.
4458 *
4459 * - Loader interface v3 differs from v2 in:
4460 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4461 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4462 * because the loader no longer does so.
4463 */
4464 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4465 return VK_SUCCESS;
4466 }
4467
4468 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4469 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4470 int *pFD)
4471 {
4472 RADV_FROM_HANDLE(radv_device, device, _device);
4473 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4474
4475 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4476
4477 /* At the moment, we support only the below handle types. */
4478 assert(pGetFdInfo->handleType ==
4479 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4480 pGetFdInfo->handleType ==
4481 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4482
4483 bool ret = radv_get_memory_fd(device, memory, pFD);
4484 if (ret == false)
4485 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4486 return VK_SUCCESS;
4487 }
4488
4489 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4490 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4491 int fd,
4492 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4493 {
4494 RADV_FROM_HANDLE(radv_device, device, _device);
4495
4496 switch (handleType) {
4497 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4498 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4499 return VK_SUCCESS;
4500
4501 default:
4502 /* The valid usage section for this function says:
4503 *
4504 * "handleType must not be one of the handle types defined as
4505 * opaque."
4506 *
4507 * So opaque handle types fall into the default "unsupported" case.
4508 */
4509 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4510 }
4511 }
4512
4513 static VkResult radv_import_opaque_fd(struct radv_device *device,
4514 int fd,
4515 uint32_t *syncobj)
4516 {
4517 uint32_t syncobj_handle = 0;
4518 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4519 if (ret != 0)
4520 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4521
4522 if (*syncobj)
4523 device->ws->destroy_syncobj(device->ws, *syncobj);
4524
4525 *syncobj = syncobj_handle;
4526 close(fd);
4527
4528 return VK_SUCCESS;
4529 }
4530
4531 static VkResult radv_import_sync_fd(struct radv_device *device,
4532 int fd,
4533 uint32_t *syncobj)
4534 {
4535 /* If we create a syncobj we do it locally so that if we have an error, we don't
4536 * leave a syncobj in an undetermined state in the fence. */
4537 uint32_t syncobj_handle = *syncobj;
4538 if (!syncobj_handle) {
4539 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4540 if (ret) {
4541 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4542 }
4543 }
4544
4545 if (fd == -1) {
4546 device->ws->signal_syncobj(device->ws, syncobj_handle);
4547 } else {
4548 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4549 if (ret != 0)
4550 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4551 }
4552
4553 *syncobj = syncobj_handle;
4554 if (fd != -1)
4555 close(fd);
4556
4557 return VK_SUCCESS;
4558 }
4559
4560 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4561 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4562 {
4563 RADV_FROM_HANDLE(radv_device, device, _device);
4564 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4565 uint32_t *syncobj_dst = NULL;
4566
4567 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4568 syncobj_dst = &sem->temp_syncobj;
4569 } else {
4570 syncobj_dst = &sem->syncobj;
4571 }
4572
4573 switch(pImportSemaphoreFdInfo->handleType) {
4574 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4575 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4576 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4577 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4578 default:
4579 unreachable("Unhandled semaphore handle type");
4580 }
4581 }
4582
4583 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4584 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4585 int *pFd)
4586 {
4587 RADV_FROM_HANDLE(radv_device, device, _device);
4588 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4589 int ret;
4590 uint32_t syncobj_handle;
4591
4592 if (sem->temp_syncobj)
4593 syncobj_handle = sem->temp_syncobj;
4594 else
4595 syncobj_handle = sem->syncobj;
4596
4597 switch(pGetFdInfo->handleType) {
4598 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4599 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4600 break;
4601 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4602 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4603 if (!ret) {
4604 if (sem->temp_syncobj) {
4605 close (sem->temp_syncobj);
4606 sem->temp_syncobj = 0;
4607 } else {
4608 device->ws->reset_syncobj(device->ws, syncobj_handle);
4609 }
4610 }
4611 break;
4612 default:
4613 unreachable("Unhandled semaphore handle type");
4614 }
4615
4616 if (ret)
4617 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4618 return VK_SUCCESS;
4619 }
4620
4621 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4622 VkPhysicalDevice physicalDevice,
4623 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4624 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4625 {
4626 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4627
4628 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4629 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4630 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4631 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4632 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4633 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4634 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4635 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4636 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4637 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4638 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4639 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4640 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4641 } else {
4642 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4643 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4644 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4645 }
4646 }
4647
4648 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4649 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4650 {
4651 RADV_FROM_HANDLE(radv_device, device, _device);
4652 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4653 uint32_t *syncobj_dst = NULL;
4654
4655
4656 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4657 syncobj_dst = &fence->temp_syncobj;
4658 } else {
4659 syncobj_dst = &fence->syncobj;
4660 }
4661
4662 switch(pImportFenceFdInfo->handleType) {
4663 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4664 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4665 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4666 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4667 default:
4668 unreachable("Unhandled fence handle type");
4669 }
4670 }
4671
4672 VkResult radv_GetFenceFdKHR(VkDevice _device,
4673 const VkFenceGetFdInfoKHR *pGetFdInfo,
4674 int *pFd)
4675 {
4676 RADV_FROM_HANDLE(radv_device, device, _device);
4677 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4678 int ret;
4679 uint32_t syncobj_handle;
4680
4681 if (fence->temp_syncobj)
4682 syncobj_handle = fence->temp_syncobj;
4683 else
4684 syncobj_handle = fence->syncobj;
4685
4686 switch(pGetFdInfo->handleType) {
4687 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4688 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4689 break;
4690 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4691 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4692 if (!ret) {
4693 if (fence->temp_syncobj) {
4694 close (fence->temp_syncobj);
4695 fence->temp_syncobj = 0;
4696 } else {
4697 device->ws->reset_syncobj(device->ws, syncobj_handle);
4698 }
4699 }
4700 break;
4701 default:
4702 unreachable("Unhandled fence handle type");
4703 }
4704
4705 if (ret)
4706 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4707 return VK_SUCCESS;
4708 }
4709
4710 void radv_GetPhysicalDeviceExternalFenceProperties(
4711 VkPhysicalDevice physicalDevice,
4712 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4713 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4714 {
4715 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4716
4717 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4718 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4719 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4720 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4721 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4722 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4723 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4724 } else {
4725 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4726 pExternalFenceProperties->compatibleHandleTypes = 0;
4727 pExternalFenceProperties->externalFenceFeatures = 0;
4728 }
4729 }
4730
4731 VkResult
4732 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4733 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4734 const VkAllocationCallbacks* pAllocator,
4735 VkDebugReportCallbackEXT* pCallback)
4736 {
4737 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4738 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4739 pCreateInfo, pAllocator, &instance->alloc,
4740 pCallback);
4741 }
4742
4743 void
4744 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4745 VkDebugReportCallbackEXT _callback,
4746 const VkAllocationCallbacks* pAllocator)
4747 {
4748 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4749 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4750 _callback, pAllocator, &instance->alloc);
4751 }
4752
4753 void
4754 radv_DebugReportMessageEXT(VkInstance _instance,
4755 VkDebugReportFlagsEXT flags,
4756 VkDebugReportObjectTypeEXT objectType,
4757 uint64_t object,
4758 size_t location,
4759 int32_t messageCode,
4760 const char* pLayerPrefix,
4761 const char* pMessage)
4762 {
4763 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4764 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4765 object, location, messageCode, pLayerPrefix, pMessage);
4766 }
4767
4768 void
4769 radv_GetDeviceGroupPeerMemoryFeatures(
4770 VkDevice device,
4771 uint32_t heapIndex,
4772 uint32_t localDeviceIndex,
4773 uint32_t remoteDeviceIndex,
4774 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4775 {
4776 assert(localDeviceIndex == remoteDeviceIndex);
4777
4778 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4779 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4780 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4781 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4782 }