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radv/gfx10: Enable binning.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 radv_physical_device_init_mem_types(device);
387 radv_fill_device_extension_table(device, &device->supported_extensions);
388
389 device->bus_info = *drm_device->businfo.pci;
390
391 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
392 ac_print_gpu_info(&device->rad_info);
393
394 /* The WSI is structured as a layer on top of the driver, so this has
395 * to be the last part of initialization (at least until we get other
396 * semi-layers).
397 */
398 result = radv_init_wsi(device);
399 if (result != VK_SUCCESS) {
400 device->ws->destroy(device->ws);
401 vk_error(instance, result);
402 goto fail;
403 }
404
405 return VK_SUCCESS;
406
407 fail:
408 close(fd);
409 if (master_fd != -1)
410 close(master_fd);
411 return result;
412 }
413
414 static void
415 radv_physical_device_finish(struct radv_physical_device *device)
416 {
417 radv_finish_wsi(device);
418 device->ws->destroy(device->ws);
419 disk_cache_destroy(device->disk_cache);
420 close(device->local_fd);
421 if (device->master_fd != -1)
422 close(device->master_fd);
423 }
424
425 static void *
426 default_alloc_func(void *pUserData, size_t size, size_t align,
427 VkSystemAllocationScope allocationScope)
428 {
429 return malloc(size);
430 }
431
432 static void *
433 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
434 size_t align, VkSystemAllocationScope allocationScope)
435 {
436 return realloc(pOriginal, size);
437 }
438
439 static void
440 default_free_func(void *pUserData, void *pMemory)
441 {
442 free(pMemory);
443 }
444
445 static const VkAllocationCallbacks default_alloc = {
446 .pUserData = NULL,
447 .pfnAllocation = default_alloc_func,
448 .pfnReallocation = default_realloc_func,
449 .pfnFree = default_free_func,
450 };
451
452 static const struct debug_control radv_debug_options[] = {
453 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
454 {"nodcc", RADV_DEBUG_NO_DCC},
455 {"shaders", RADV_DEBUG_DUMP_SHADERS},
456 {"nocache", RADV_DEBUG_NO_CACHE},
457 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
458 {"nohiz", RADV_DEBUG_NO_HIZ},
459 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
460 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
461 {"allbos", RADV_DEBUG_ALL_BOS},
462 {"noibs", RADV_DEBUG_NO_IBS},
463 {"spirv", RADV_DEBUG_DUMP_SPIRV},
464 {"vmfaults", RADV_DEBUG_VM_FAULTS},
465 {"zerovram", RADV_DEBUG_ZERO_VRAM},
466 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
467 {"nosisched", RADV_DEBUG_NO_SISCHED},
468 {"preoptir", RADV_DEBUG_PREOPTIR},
469 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
470 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
471 {"info", RADV_DEBUG_INFO},
472 {"errors", RADV_DEBUG_ERRORS},
473 {"startup", RADV_DEBUG_STARTUP},
474 {"checkir", RADV_DEBUG_CHECKIR},
475 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
476 {"nobinning", RADV_DEBUG_NOBINNING},
477 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
478 {"nongg", RADV_DEBUG_NO_NGG},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_debug_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
486 return radv_debug_options[id].string;
487 }
488
489 static const struct debug_control radv_perftest_options[] = {
490 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
491 {"sisched", RADV_PERFTEST_SISCHED},
492 {"localbos", RADV_PERFTEST_LOCAL_BOS},
493 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
494 {"bolist", RADV_PERFTEST_BO_LIST},
495 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
496 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
497 {NULL, 0}
498 };
499
500 const char *
501 radv_get_perftest_option_name(int id)
502 {
503 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
504 return radv_perftest_options[id].string;
505 }
506
507 static void
508 radv_handle_per_app_options(struct radv_instance *instance,
509 const VkApplicationInfo *info)
510 {
511 const char *name = info ? info->pApplicationName : NULL;
512
513 if (!name)
514 return;
515
516 if (!strcmp(name, "Talos - Linux - 32bit") ||
517 !strcmp(name, "Talos - Linux - 64bit")) {
518 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
519 /* Force enable LLVM sisched for Talos because it looks
520 * safe and it gives few more FPS.
521 */
522 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
523 }
524 } else if (!strcmp(name, "DOOM_VFR")) {
525 /* Work around a Doom VFR game bug */
526 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
527 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
528 /* Workaround for a WaW hazard when LLVM moves/merges
529 * load/store memory operations.
530 * See https://reviews.llvm.org/D61313
531 */
532 if (HAVE_LLVM < 0x900)
533 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
534 }
535 }
536
537 static int radv_get_instance_extension_index(const char *name)
538 {
539 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
540 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
541 return i;
542 }
543 return -1;
544 }
545
546 static const char radv_dri_options_xml[] =
547 DRI_CONF_BEGIN
548 DRI_CONF_SECTION_QUALITY
549 DRI_CONF_ADAPTIVE_SYNC("true")
550 DRI_CONF_SECTION_END
551 DRI_CONF_END;
552
553 static void radv_init_dri_options(struct radv_instance *instance)
554 {
555 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
556 driParseConfigFiles(&instance->dri_options,
557 &instance->available_dri_options,
558 0, "radv", NULL);
559 }
560
561 VkResult radv_CreateInstance(
562 const VkInstanceCreateInfo* pCreateInfo,
563 const VkAllocationCallbacks* pAllocator,
564 VkInstance* pInstance)
565 {
566 struct radv_instance *instance;
567 VkResult result;
568
569 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
570
571 uint32_t client_version;
572 if (pCreateInfo->pApplicationInfo &&
573 pCreateInfo->pApplicationInfo->apiVersion != 0) {
574 client_version = pCreateInfo->pApplicationInfo->apiVersion;
575 } else {
576 client_version = VK_API_VERSION_1_0;
577 }
578
579 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
580 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
581 if (!instance)
582 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
583
584 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
585
586 if (pAllocator)
587 instance->alloc = *pAllocator;
588 else
589 instance->alloc = default_alloc;
590
591 instance->apiVersion = client_version;
592 instance->physicalDeviceCount = -1;
593
594 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
595 radv_debug_options);
596
597 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
598 radv_perftest_options);
599
600
601 if (instance->debug_flags & RADV_DEBUG_STARTUP)
602 radv_logi("Created an instance");
603
604 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
605 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
606 int index = radv_get_instance_extension_index(ext_name);
607
608 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
609 vk_free2(&default_alloc, pAllocator, instance);
610 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
611 }
612
613 instance->enabled_extensions.extensions[index] = true;
614 }
615
616 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
617 if (result != VK_SUCCESS) {
618 vk_free2(&default_alloc, pAllocator, instance);
619 return vk_error(instance, result);
620 }
621
622 _mesa_locale_init();
623 glsl_type_singleton_init_or_ref();
624
625 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
626
627 radv_init_dri_options(instance);
628 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
629
630 *pInstance = radv_instance_to_handle(instance);
631
632 return VK_SUCCESS;
633 }
634
635 void radv_DestroyInstance(
636 VkInstance _instance,
637 const VkAllocationCallbacks* pAllocator)
638 {
639 RADV_FROM_HANDLE(radv_instance, instance, _instance);
640
641 if (!instance)
642 return;
643
644 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
645 radv_physical_device_finish(instance->physicalDevices + i);
646 }
647
648 VG(VALGRIND_DESTROY_MEMPOOL(instance));
649
650 glsl_type_singleton_decref();
651 _mesa_locale_fini();
652
653 driDestroyOptionCache(&instance->dri_options);
654 driDestroyOptionInfo(&instance->available_dri_options);
655
656 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
657
658 vk_free(&instance->alloc, instance);
659 }
660
661 static VkResult
662 radv_enumerate_devices(struct radv_instance *instance)
663 {
664 /* TODO: Check for more devices ? */
665 drmDevicePtr devices[8];
666 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
667 int max_devices;
668
669 instance->physicalDeviceCount = 0;
670
671 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
672
673 if (instance->debug_flags & RADV_DEBUG_STARTUP)
674 radv_logi("Found %d drm nodes", max_devices);
675
676 if (max_devices < 1)
677 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
678
679 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
680 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
681 devices[i]->bustype == DRM_BUS_PCI &&
682 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
683
684 result = radv_physical_device_init(instance->physicalDevices +
685 instance->physicalDeviceCount,
686 instance,
687 devices[i]);
688 if (result == VK_SUCCESS)
689 ++instance->physicalDeviceCount;
690 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
691 break;
692 }
693 }
694 drmFreeDevices(devices, max_devices);
695
696 return result;
697 }
698
699 VkResult radv_EnumeratePhysicalDevices(
700 VkInstance _instance,
701 uint32_t* pPhysicalDeviceCount,
702 VkPhysicalDevice* pPhysicalDevices)
703 {
704 RADV_FROM_HANDLE(radv_instance, instance, _instance);
705 VkResult result;
706
707 if (instance->physicalDeviceCount < 0) {
708 result = radv_enumerate_devices(instance);
709 if (result != VK_SUCCESS &&
710 result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 return result;
712 }
713
714 if (!pPhysicalDevices) {
715 *pPhysicalDeviceCount = instance->physicalDeviceCount;
716 } else {
717 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
718 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
719 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
720 }
721
722 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
723 : VK_SUCCESS;
724 }
725
726 VkResult radv_EnumeratePhysicalDeviceGroups(
727 VkInstance _instance,
728 uint32_t* pPhysicalDeviceGroupCount,
729 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
730 {
731 RADV_FROM_HANDLE(radv_instance, instance, _instance);
732 VkResult result;
733
734 if (instance->physicalDeviceCount < 0) {
735 result = radv_enumerate_devices(instance);
736 if (result != VK_SUCCESS &&
737 result != VK_ERROR_INCOMPATIBLE_DRIVER)
738 return result;
739 }
740
741 if (!pPhysicalDeviceGroupProperties) {
742 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
743 } else {
744 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
745 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
746 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
747 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
748 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
749 }
750 }
751 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
752 : VK_SUCCESS;
753 }
754
755 void radv_GetPhysicalDeviceFeatures(
756 VkPhysicalDevice physicalDevice,
757 VkPhysicalDeviceFeatures* pFeatures)
758 {
759 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
760 memset(pFeatures, 0, sizeof(*pFeatures));
761
762 *pFeatures = (VkPhysicalDeviceFeatures) {
763 .robustBufferAccess = true,
764 .fullDrawIndexUint32 = true,
765 .imageCubeArray = true,
766 .independentBlend = true,
767 .geometryShader = true,
768 .tessellationShader = true,
769 .sampleRateShading = true,
770 .dualSrcBlend = true,
771 .logicOp = true,
772 .multiDrawIndirect = true,
773 .drawIndirectFirstInstance = true,
774 .depthClamp = true,
775 .depthBiasClamp = true,
776 .fillModeNonSolid = true,
777 .depthBounds = true,
778 .wideLines = true,
779 .largePoints = true,
780 .alphaToOne = true,
781 .multiViewport = true,
782 .samplerAnisotropy = true,
783 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
784 .textureCompressionASTC_LDR = false,
785 .textureCompressionBC = true,
786 .occlusionQueryPrecise = true,
787 .pipelineStatisticsQuery = true,
788 .vertexPipelineStoresAndAtomics = true,
789 .fragmentStoresAndAtomics = true,
790 .shaderTessellationAndGeometryPointSize = true,
791 .shaderImageGatherExtended = true,
792 .shaderStorageImageExtendedFormats = true,
793 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
794 .shaderUniformBufferArrayDynamicIndexing = true,
795 .shaderSampledImageArrayDynamicIndexing = true,
796 .shaderStorageBufferArrayDynamicIndexing = true,
797 .shaderStorageImageArrayDynamicIndexing = true,
798 .shaderStorageImageReadWithoutFormat = true,
799 .shaderStorageImageWriteWithoutFormat = true,
800 .shaderClipDistance = true,
801 .shaderCullDistance = true,
802 .shaderFloat64 = true,
803 .shaderInt64 = true,
804 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
805 .sparseBinding = true,
806 .variableMultisampleRate = true,
807 .inheritedQueries = true,
808 };
809 }
810
811 void radv_GetPhysicalDeviceFeatures2(
812 VkPhysicalDevice physicalDevice,
813 VkPhysicalDeviceFeatures2 *pFeatures)
814 {
815 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
816 vk_foreach_struct(ext, pFeatures->pNext) {
817 switch (ext->sType) {
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
819 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
820 features->variablePointersStorageBuffer = true;
821 features->variablePointers = true;
822 break;
823 }
824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
825 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
826 features->multiview = true;
827 features->multiviewGeometryShader = true;
828 features->multiviewTessellationShader = true;
829 break;
830 }
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
832 VkPhysicalDeviceShaderDrawParametersFeatures *features =
833 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
834 features->shaderDrawParameters = true;
835 break;
836 }
837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
838 VkPhysicalDeviceProtectedMemoryFeatures *features =
839 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
840 features->protectedMemory = false;
841 break;
842 }
843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
844 VkPhysicalDevice16BitStorageFeatures *features =
845 (VkPhysicalDevice16BitStorageFeatures*)ext;
846 bool enabled = pdevice->rad_info.chip_class >= GFX8;
847 features->storageBuffer16BitAccess = enabled;
848 features->uniformAndStorageBuffer16BitAccess = enabled;
849 features->storagePushConstant16 = enabled;
850 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
854 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
855 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
856 features->samplerYcbcrConversion = true;
857 break;
858 }
859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
860 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
861 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
862 features->shaderInputAttachmentArrayDynamicIndexing = true;
863 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
864 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
865 features->shaderUniformBufferArrayNonUniformIndexing = true;
866 features->shaderSampledImageArrayNonUniformIndexing = true;
867 features->shaderStorageBufferArrayNonUniformIndexing = true;
868 features->shaderStorageImageArrayNonUniformIndexing = true;
869 features->shaderInputAttachmentArrayNonUniformIndexing = true;
870 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
871 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
872 features->descriptorBindingUniformBufferUpdateAfterBind = true;
873 features->descriptorBindingSampledImageUpdateAfterBind = true;
874 features->descriptorBindingStorageImageUpdateAfterBind = true;
875 features->descriptorBindingStorageBufferUpdateAfterBind = true;
876 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
877 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
878 features->descriptorBindingUpdateUnusedWhilePending = true;
879 features->descriptorBindingPartiallyBound = true;
880 features->descriptorBindingVariableDescriptorCount = true;
881 features->runtimeDescriptorArray = true;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
885 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
886 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
887 features->conditionalRendering = true;
888 features->inheritedConditionalRendering = false;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
892 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
893 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
894 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
895 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
896 break;
897 }
898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
899 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
900 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
901 features->transformFeedback = true;
902 features->geometryStreams = true;
903 break;
904 }
905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
906 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
907 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
908 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
912 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
913 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
914 features->memoryPriority = VK_TRUE;
915 break;
916 }
917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
918 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
919 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
920 features->bufferDeviceAddress = true;
921 features->bufferDeviceAddressCaptureReplay = false;
922 features->bufferDeviceAddressMultiDevice = false;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
926 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
927 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
928 features->depthClipEnable = true;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
932 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
933 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
934 features->hostQueryReset = true;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
938 VkPhysicalDevice8BitStorageFeaturesKHR *features =
939 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
940 bool enabled = pdevice->rad_info.chip_class >= GFX8;
941 features->storageBuffer8BitAccess = enabled;
942 features->uniformAndStorageBuffer8BitAccess = enabled;
943 features->storagePushConstant8 = enabled;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
947 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
948 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
949 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
950 features->shaderInt8 = true;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
954 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
955 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
956 /* TODO: Enable this once the driver supports 64-bit
957 * compare&swap atomic operations.
958 */
959 features->shaderBufferInt64Atomics = false;
960 features->shaderSharedInt64Atomics = false;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
964 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
965 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
966
967 features->inlineUniformBlock = true;
968 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
972 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
973 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
974 features->computeDerivativeGroupQuads = false;
975 features->computeDerivativeGroupLinear = true;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
979 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
980 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
981 features->ycbcrImageArrays = true;
982 break;
983 }
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
985 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
986 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
987 features->uniformBufferStandardLayout = true;
988 break;
989 }
990 default:
991 break;
992 }
993 }
994 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
995 }
996
997 void radv_GetPhysicalDeviceProperties(
998 VkPhysicalDevice physicalDevice,
999 VkPhysicalDeviceProperties* pProperties)
1000 {
1001 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1002 VkSampleCountFlags sample_counts = 0xf;
1003
1004 /* make sure that the entire descriptor set is addressable with a signed
1005 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1006 * be at most 2 GiB. the combined image & samples object count as one of
1007 * both. This limit is for the pipeline layout, not for the set layout, but
1008 * there is no set limit, so we just set a pipeline limit. I don't think
1009 * any app is going to hit this soon. */
1010 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1011 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1012 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1013 32 /* sampler, largest when combined with image */ +
1014 64 /* sampled image */ +
1015 64 /* storage image */);
1016
1017 VkPhysicalDeviceLimits limits = {
1018 .maxImageDimension1D = (1 << 14),
1019 .maxImageDimension2D = (1 << 14),
1020 .maxImageDimension3D = (1 << 11),
1021 .maxImageDimensionCube = (1 << 14),
1022 .maxImageArrayLayers = (1 << 11),
1023 .maxTexelBufferElements = 128 * 1024 * 1024,
1024 .maxUniformBufferRange = UINT32_MAX,
1025 .maxStorageBufferRange = UINT32_MAX,
1026 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1027 .maxMemoryAllocationCount = UINT32_MAX,
1028 .maxSamplerAllocationCount = 64 * 1024,
1029 .bufferImageGranularity = 64, /* A cache line */
1030 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1031 .maxBoundDescriptorSets = MAX_SETS,
1032 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1033 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1034 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1035 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1036 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1037 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1038 .maxPerStageResources = max_descriptor_set_size,
1039 .maxDescriptorSetSamplers = max_descriptor_set_size,
1040 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1041 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1042 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1043 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1044 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1045 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1046 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1047 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1048 .maxVertexInputBindings = MAX_VBS,
1049 .maxVertexInputAttributeOffset = 2047,
1050 .maxVertexInputBindingStride = 2048,
1051 .maxVertexOutputComponents = 128,
1052 .maxTessellationGenerationLevel = 64,
1053 .maxTessellationPatchSize = 32,
1054 .maxTessellationControlPerVertexInputComponents = 128,
1055 .maxTessellationControlPerVertexOutputComponents = 128,
1056 .maxTessellationControlPerPatchOutputComponents = 120,
1057 .maxTessellationControlTotalOutputComponents = 4096,
1058 .maxTessellationEvaluationInputComponents = 128,
1059 .maxTessellationEvaluationOutputComponents = 128,
1060 .maxGeometryShaderInvocations = 127,
1061 .maxGeometryInputComponents = 64,
1062 .maxGeometryOutputComponents = 128,
1063 .maxGeometryOutputVertices = 256,
1064 .maxGeometryTotalOutputComponents = 1024,
1065 .maxFragmentInputComponents = 128,
1066 .maxFragmentOutputAttachments = 8,
1067 .maxFragmentDualSrcAttachments = 1,
1068 .maxFragmentCombinedOutputResources = 8,
1069 .maxComputeSharedMemorySize = 32768,
1070 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1071 .maxComputeWorkGroupInvocations = 2048,
1072 .maxComputeWorkGroupSize = {
1073 2048,
1074 2048,
1075 2048
1076 },
1077 .subPixelPrecisionBits = 8,
1078 .subTexelPrecisionBits = 8,
1079 .mipmapPrecisionBits = 8,
1080 .maxDrawIndexedIndexValue = UINT32_MAX,
1081 .maxDrawIndirectCount = UINT32_MAX,
1082 .maxSamplerLodBias = 16,
1083 .maxSamplerAnisotropy = 16,
1084 .maxViewports = MAX_VIEWPORTS,
1085 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1086 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1087 .viewportSubPixelBits = 8,
1088 .minMemoryMapAlignment = 4096, /* A page */
1089 .minTexelBufferOffsetAlignment = 1,
1090 .minUniformBufferOffsetAlignment = 4,
1091 .minStorageBufferOffsetAlignment = 4,
1092 .minTexelOffset = -32,
1093 .maxTexelOffset = 31,
1094 .minTexelGatherOffset = -32,
1095 .maxTexelGatherOffset = 31,
1096 .minInterpolationOffset = -2,
1097 .maxInterpolationOffset = 2,
1098 .subPixelInterpolationOffsetBits = 8,
1099 .maxFramebufferWidth = (1 << 14),
1100 .maxFramebufferHeight = (1 << 14),
1101 .maxFramebufferLayers = (1 << 10),
1102 .framebufferColorSampleCounts = sample_counts,
1103 .framebufferDepthSampleCounts = sample_counts,
1104 .framebufferStencilSampleCounts = sample_counts,
1105 .framebufferNoAttachmentsSampleCounts = sample_counts,
1106 .maxColorAttachments = MAX_RTS,
1107 .sampledImageColorSampleCounts = sample_counts,
1108 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1109 .sampledImageDepthSampleCounts = sample_counts,
1110 .sampledImageStencilSampleCounts = sample_counts,
1111 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1112 .maxSampleMaskWords = 1,
1113 .timestampComputeAndGraphics = true,
1114 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1115 .maxClipDistances = 8,
1116 .maxCullDistances = 8,
1117 .maxCombinedClipAndCullDistances = 8,
1118 .discreteQueuePriorities = 2,
1119 .pointSizeRange = { 0.0, 8192.0 },
1120 .lineWidthRange = { 0.0, 7.9921875 },
1121 .pointSizeGranularity = (1.0 / 8.0),
1122 .lineWidthGranularity = (1.0 / 128.0),
1123 .strictLines = false, /* FINISHME */
1124 .standardSampleLocations = true,
1125 .optimalBufferCopyOffsetAlignment = 128,
1126 .optimalBufferCopyRowPitchAlignment = 128,
1127 .nonCoherentAtomSize = 64,
1128 };
1129
1130 *pProperties = (VkPhysicalDeviceProperties) {
1131 .apiVersion = radv_physical_device_api_version(pdevice),
1132 .driverVersion = vk_get_driver_version(),
1133 .vendorID = ATI_VENDOR_ID,
1134 .deviceID = pdevice->rad_info.pci_id,
1135 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1136 .limits = limits,
1137 .sparseProperties = {0},
1138 };
1139
1140 strcpy(pProperties->deviceName, pdevice->name);
1141 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1142 }
1143
1144 void radv_GetPhysicalDeviceProperties2(
1145 VkPhysicalDevice physicalDevice,
1146 VkPhysicalDeviceProperties2 *pProperties)
1147 {
1148 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1149 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1150
1151 vk_foreach_struct(ext, pProperties->pNext) {
1152 switch (ext->sType) {
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1154 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1155 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1156 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1157 break;
1158 }
1159 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1160 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1161 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1162 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1163 properties->deviceLUIDValid = false;
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1167 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1168 properties->maxMultiviewViewCount = MAX_VIEWS;
1169 properties->maxMultiviewInstanceIndex = INT_MAX;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1173 VkPhysicalDevicePointClippingProperties *properties =
1174 (VkPhysicalDevicePointClippingProperties*)ext;
1175 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1176 break;
1177 }
1178 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1179 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1180 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1181 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1185 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1186 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1187 properties->minImportedHostPointerAlignment = 4096;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1191 VkPhysicalDeviceSubgroupProperties *properties =
1192 (VkPhysicalDeviceSubgroupProperties*)ext;
1193 properties->subgroupSize = 64;
1194 properties->supportedStages = VK_SHADER_STAGE_ALL;
1195 properties->supportedOperations =
1196 VK_SUBGROUP_FEATURE_BASIC_BIT |
1197 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1198 VK_SUBGROUP_FEATURE_QUAD_BIT |
1199 VK_SUBGROUP_FEATURE_VOTE_BIT;
1200 if (pdevice->rad_info.chip_class >= GFX8) {
1201 properties->supportedOperations |=
1202 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1203 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1204 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1205 }
1206 properties->quadOperationsInAllStages = true;
1207 break;
1208 }
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1210 VkPhysicalDeviceMaintenance3Properties *properties =
1211 (VkPhysicalDeviceMaintenance3Properties*)ext;
1212 /* Make sure everything is addressable by a signed 32-bit int, and
1213 * our largest descriptors are 96 bytes. */
1214 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1215 /* Our buffer size fields allow only this much */
1216 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1220 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1221 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1222 /* GFX6-8 only support single channel min/max filter. */
1223 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1224 properties->filterMinmaxSingleComponentFormats = true;
1225 break;
1226 }
1227 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1228 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1229 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1230
1231 /* Shader engines. */
1232 properties->shaderEngineCount =
1233 pdevice->rad_info.max_se;
1234 properties->shaderArraysPerEngineCount =
1235 pdevice->rad_info.max_sh_per_se;
1236 properties->computeUnitsPerShaderArray =
1237 pdevice->rad_info.num_good_cu_per_sh;
1238 properties->simdPerComputeUnit = 4;
1239 properties->wavefrontsPerSimd =
1240 pdevice->rad_info.family == CHIP_TONGA ||
1241 pdevice->rad_info.family == CHIP_ICELAND ||
1242 pdevice->rad_info.family == CHIP_POLARIS10 ||
1243 pdevice->rad_info.family == CHIP_POLARIS11 ||
1244 pdevice->rad_info.family == CHIP_POLARIS12 ||
1245 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1246 properties->wavefrontSize = 64;
1247
1248 /* SGPR. */
1249 properties->sgprsPerSimd =
1250 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1251 properties->minSgprAllocation =
1252 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1253 properties->maxSgprAllocation =
1254 pdevice->rad_info.family == CHIP_TONGA ||
1255 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1256 properties->sgprAllocationGranularity =
1257 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1258
1259 /* VGPR. */
1260 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1261 properties->minVgprAllocation = 4;
1262 properties->maxVgprAllocation = 256;
1263 properties->vgprAllocationGranularity = 4;
1264 break;
1265 }
1266 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1267 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1268 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1269 properties->maxVertexAttribDivisor = UINT32_MAX;
1270 break;
1271 }
1272 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1273 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1274 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1275 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1276 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1277 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1278 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1279 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1280 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1281 properties->robustBufferAccessUpdateAfterBind = false;
1282 properties->quadDivergentImplicitLod = false;
1283
1284 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1285 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1286 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1287 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* sampler, largest when combined with image */ +
1289 64 /* sampled image */ +
1290 64 /* storage image */);
1291 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1292 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1295 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1296 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1297 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1299 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1301 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1302 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1303 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1304 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1305 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1306 break;
1307 }
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1309 VkPhysicalDeviceProtectedMemoryProperties *properties =
1310 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1311 properties->protectedNoFault = false;
1312 break;
1313 }
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1315 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1316 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1317 properties->primitiveOverestimationSize = 0;
1318 properties->maxExtraPrimitiveOverestimationSize = 0;
1319 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1320 properties->primitiveUnderestimation = VK_FALSE;
1321 properties->conservativePointAndLineRasterization = VK_FALSE;
1322 properties->degenerateTrianglesRasterized = VK_FALSE;
1323 properties->degenerateLinesRasterized = VK_FALSE;
1324 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1325 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1326 break;
1327 }
1328 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1329 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1330 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1331 properties->pciDomain = pdevice->bus_info.domain;
1332 properties->pciBus = pdevice->bus_info.bus;
1333 properties->pciDevice = pdevice->bus_info.dev;
1334 properties->pciFunction = pdevice->bus_info.func;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1338 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1339 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1340
1341 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1342 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1343 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1344 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1345 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1346
1347 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1348 .major = 1,
1349 .minor = 1,
1350 .subminor = 2,
1351 .patch = 0,
1352 };
1353 break;
1354 }
1355 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1356 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1357 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1358 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1359 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1360 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1361 properties->maxTransformFeedbackStreamDataSize = 512;
1362 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1363 properties->maxTransformFeedbackBufferDataStride = 512;
1364 properties->transformFeedbackQueries = true;
1365 properties->transformFeedbackStreamsLinesTriangles = true;
1366 properties->transformFeedbackRasterizationStreamSelect = false;
1367 properties->transformFeedbackDraw = true;
1368 break;
1369 }
1370 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1371 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1372 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1373
1374 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1375 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1376 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1377 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1378 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1379 break;
1380 }
1381 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1382 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1383 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1384 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1385 VK_SAMPLE_COUNT_4_BIT |
1386 VK_SAMPLE_COUNT_8_BIT;
1387 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1388 properties->sampleLocationCoordinateRange[0] = 0.0f;
1389 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1390 properties->sampleLocationSubPixelBits = 4;
1391 properties->variableSampleLocations = VK_FALSE;
1392 break;
1393 }
1394 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1395 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1396 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1397
1398 /* We support all of the depth resolve modes */
1399 properties->supportedDepthResolveModes =
1400 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1401 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1402 VK_RESOLVE_MODE_MIN_BIT_KHR |
1403 VK_RESOLVE_MODE_MAX_BIT_KHR;
1404
1405 /* Average doesn't make sense for stencil so we don't support that */
1406 properties->supportedStencilResolveModes =
1407 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1408 VK_RESOLVE_MODE_MIN_BIT_KHR |
1409 VK_RESOLVE_MODE_MAX_BIT_KHR;
1410
1411 properties->independentResolveNone = VK_TRUE;
1412 properties->independentResolve = VK_TRUE;
1413 break;
1414 }
1415 default:
1416 break;
1417 }
1418 }
1419 }
1420
1421 static void radv_get_physical_device_queue_family_properties(
1422 struct radv_physical_device* pdevice,
1423 uint32_t* pCount,
1424 VkQueueFamilyProperties** pQueueFamilyProperties)
1425 {
1426 int num_queue_families = 1;
1427 int idx;
1428 if (pdevice->rad_info.num_compute_rings > 0 &&
1429 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1430 num_queue_families++;
1431
1432 if (pQueueFamilyProperties == NULL) {
1433 *pCount = num_queue_families;
1434 return;
1435 }
1436
1437 if (!*pCount)
1438 return;
1439
1440 idx = 0;
1441 if (*pCount >= 1) {
1442 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1443 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1444 VK_QUEUE_COMPUTE_BIT |
1445 VK_QUEUE_TRANSFER_BIT |
1446 VK_QUEUE_SPARSE_BINDING_BIT,
1447 .queueCount = 1,
1448 .timestampValidBits = 64,
1449 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1450 };
1451 idx++;
1452 }
1453
1454 if (pdevice->rad_info.num_compute_rings > 0 &&
1455 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1456 if (*pCount > idx) {
1457 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1458 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1459 VK_QUEUE_TRANSFER_BIT |
1460 VK_QUEUE_SPARSE_BINDING_BIT,
1461 .queueCount = pdevice->rad_info.num_compute_rings,
1462 .timestampValidBits = 64,
1463 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1464 };
1465 idx++;
1466 }
1467 }
1468 *pCount = idx;
1469 }
1470
1471 void radv_GetPhysicalDeviceQueueFamilyProperties(
1472 VkPhysicalDevice physicalDevice,
1473 uint32_t* pCount,
1474 VkQueueFamilyProperties* pQueueFamilyProperties)
1475 {
1476 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1477 if (!pQueueFamilyProperties) {
1478 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1479 return;
1480 }
1481 VkQueueFamilyProperties *properties[] = {
1482 pQueueFamilyProperties + 0,
1483 pQueueFamilyProperties + 1,
1484 pQueueFamilyProperties + 2,
1485 };
1486 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1487 assert(*pCount <= 3);
1488 }
1489
1490 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1491 VkPhysicalDevice physicalDevice,
1492 uint32_t* pCount,
1493 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1494 {
1495 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1496 if (!pQueueFamilyProperties) {
1497 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1498 return;
1499 }
1500 VkQueueFamilyProperties *properties[] = {
1501 &pQueueFamilyProperties[0].queueFamilyProperties,
1502 &pQueueFamilyProperties[1].queueFamilyProperties,
1503 &pQueueFamilyProperties[2].queueFamilyProperties,
1504 };
1505 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1506 assert(*pCount <= 3);
1507 }
1508
1509 void radv_GetPhysicalDeviceMemoryProperties(
1510 VkPhysicalDevice physicalDevice,
1511 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1512 {
1513 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1514
1515 *pMemoryProperties = physical_device->memory_properties;
1516 }
1517
1518 static void
1519 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1520 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1521 {
1522 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1523 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1524 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1525 uint64_t vram_size = radv_get_vram_size(device);
1526 uint64_t gtt_size = device->rad_info.gart_size;
1527 uint64_t heap_budget, heap_usage;
1528
1529 /* For all memory heaps, the computation of budget is as follow:
1530 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1531 *
1532 * The Vulkan spec 1.1.97 says that the budget should include any
1533 * currently allocated device memory.
1534 *
1535 * Note that the application heap usages are not really accurate (eg.
1536 * in presence of shared buffers).
1537 */
1538 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1539 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1540
1541 switch (device->mem_type_indices[i]) {
1542 case RADV_MEM_TYPE_VRAM:
1543 heap_usage = device->ws->query_value(device->ws,
1544 RADEON_ALLOCATED_VRAM);
1545
1546 heap_budget = vram_size -
1547 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1548 heap_usage;
1549
1550 memoryBudget->heapBudget[heap_index] = heap_budget;
1551 memoryBudget->heapUsage[heap_index] = heap_usage;
1552 break;
1553 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1554 heap_usage = device->ws->query_value(device->ws,
1555 RADEON_ALLOCATED_VRAM_VIS);
1556
1557 heap_budget = visible_vram_size -
1558 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1559 heap_usage;
1560
1561 memoryBudget->heapBudget[heap_index] = heap_budget;
1562 memoryBudget->heapUsage[heap_index] = heap_usage;
1563 break;
1564 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1565 heap_usage = device->ws->query_value(device->ws,
1566 RADEON_ALLOCATED_GTT);
1567
1568 heap_budget = gtt_size -
1569 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1570 heap_usage;
1571
1572 memoryBudget->heapBudget[heap_index] = heap_budget;
1573 memoryBudget->heapUsage[heap_index] = heap_usage;
1574 break;
1575 default:
1576 break;
1577 }
1578 }
1579
1580 /* The heapBudget and heapUsage values must be zero for array elements
1581 * greater than or equal to
1582 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1583 */
1584 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1585 memoryBudget->heapBudget[i] = 0;
1586 memoryBudget->heapUsage[i] = 0;
1587 }
1588 }
1589
1590 void radv_GetPhysicalDeviceMemoryProperties2(
1591 VkPhysicalDevice physicalDevice,
1592 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1593 {
1594 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1595 &pMemoryProperties->memoryProperties);
1596
1597 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1598 vk_find_struct(pMemoryProperties->pNext,
1599 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1600 if (memory_budget)
1601 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1602 }
1603
1604 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1605 VkDevice _device,
1606 VkExternalMemoryHandleTypeFlagBits handleType,
1607 const void *pHostPointer,
1608 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1609 {
1610 RADV_FROM_HANDLE(radv_device, device, _device);
1611
1612 switch (handleType)
1613 {
1614 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1615 const struct radv_physical_device *physical_device = device->physical_device;
1616 uint32_t memoryTypeBits = 0;
1617 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1618 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1619 memoryTypeBits = (1 << i);
1620 break;
1621 }
1622 }
1623 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1624 return VK_SUCCESS;
1625 }
1626 default:
1627 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1628 }
1629 }
1630
1631 static enum radeon_ctx_priority
1632 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1633 {
1634 /* Default to MEDIUM when a specific global priority isn't requested */
1635 if (!pObj)
1636 return RADEON_CTX_PRIORITY_MEDIUM;
1637
1638 switch(pObj->globalPriority) {
1639 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1640 return RADEON_CTX_PRIORITY_REALTIME;
1641 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1642 return RADEON_CTX_PRIORITY_HIGH;
1643 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1644 return RADEON_CTX_PRIORITY_MEDIUM;
1645 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1646 return RADEON_CTX_PRIORITY_LOW;
1647 default:
1648 unreachable("Illegal global priority value");
1649 return RADEON_CTX_PRIORITY_INVALID;
1650 }
1651 }
1652
1653 static int
1654 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1655 uint32_t queue_family_index, int idx,
1656 VkDeviceQueueCreateFlags flags,
1657 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1658 {
1659 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1660 queue->device = device;
1661 queue->queue_family_index = queue_family_index;
1662 queue->queue_idx = idx;
1663 queue->priority = radv_get_queue_global_priority(global_priority);
1664 queue->flags = flags;
1665
1666 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1667 if (!queue->hw_ctx)
1668 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1669
1670 return VK_SUCCESS;
1671 }
1672
1673 static void
1674 radv_queue_finish(struct radv_queue *queue)
1675 {
1676 if (queue->hw_ctx)
1677 queue->device->ws->ctx_destroy(queue->hw_ctx);
1678
1679 if (queue->initial_full_flush_preamble_cs)
1680 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1681 if (queue->initial_preamble_cs)
1682 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1683 if (queue->continue_preamble_cs)
1684 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1685 if (queue->descriptor_bo)
1686 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1687 if (queue->scratch_bo)
1688 queue->device->ws->buffer_destroy(queue->scratch_bo);
1689 if (queue->esgs_ring_bo)
1690 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1691 if (queue->gsvs_ring_bo)
1692 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1693 if (queue->tess_rings_bo)
1694 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1695 if (queue->compute_scratch_bo)
1696 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1697 }
1698
1699 static void
1700 radv_bo_list_init(struct radv_bo_list *bo_list)
1701 {
1702 pthread_mutex_init(&bo_list->mutex, NULL);
1703 bo_list->list.count = bo_list->capacity = 0;
1704 bo_list->list.bos = NULL;
1705 }
1706
1707 static void
1708 radv_bo_list_finish(struct radv_bo_list *bo_list)
1709 {
1710 free(bo_list->list.bos);
1711 pthread_mutex_destroy(&bo_list->mutex);
1712 }
1713
1714 static VkResult radv_bo_list_add(struct radv_device *device,
1715 struct radeon_winsys_bo *bo)
1716 {
1717 struct radv_bo_list *bo_list = &device->bo_list;
1718
1719 if (bo->is_local)
1720 return VK_SUCCESS;
1721
1722 if (unlikely(!device->use_global_bo_list))
1723 return VK_SUCCESS;
1724
1725 pthread_mutex_lock(&bo_list->mutex);
1726 if (bo_list->list.count == bo_list->capacity) {
1727 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1728 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1729
1730 if (!data) {
1731 pthread_mutex_unlock(&bo_list->mutex);
1732 return VK_ERROR_OUT_OF_HOST_MEMORY;
1733 }
1734
1735 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1736 bo_list->capacity = capacity;
1737 }
1738
1739 bo_list->list.bos[bo_list->list.count++] = bo;
1740 pthread_mutex_unlock(&bo_list->mutex);
1741 return VK_SUCCESS;
1742 }
1743
1744 static void radv_bo_list_remove(struct radv_device *device,
1745 struct radeon_winsys_bo *bo)
1746 {
1747 struct radv_bo_list *bo_list = &device->bo_list;
1748
1749 if (bo->is_local)
1750 return;
1751
1752 if (unlikely(!device->use_global_bo_list))
1753 return;
1754
1755 pthread_mutex_lock(&bo_list->mutex);
1756 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1757 if (bo_list->list.bos[i] == bo) {
1758 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1759 --bo_list->list.count;
1760 break;
1761 }
1762 }
1763 pthread_mutex_unlock(&bo_list->mutex);
1764 }
1765
1766 static void
1767 radv_device_init_gs_info(struct radv_device *device)
1768 {
1769 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1770 device->physical_device->rad_info.family);
1771 }
1772
1773 static int radv_get_device_extension_index(const char *name)
1774 {
1775 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1776 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1777 return i;
1778 }
1779 return -1;
1780 }
1781
1782 static int
1783 radv_get_int_debug_option(const char *name, int default_value)
1784 {
1785 const char *str;
1786 int result;
1787
1788 str = getenv(name);
1789 if (!str) {
1790 result = default_value;
1791 } else {
1792 char *endptr;
1793
1794 result = strtol(str, &endptr, 0);
1795 if (str == endptr) {
1796 /* No digits founs. */
1797 result = default_value;
1798 }
1799 }
1800
1801 return result;
1802 }
1803
1804 VkResult radv_CreateDevice(
1805 VkPhysicalDevice physicalDevice,
1806 const VkDeviceCreateInfo* pCreateInfo,
1807 const VkAllocationCallbacks* pAllocator,
1808 VkDevice* pDevice)
1809 {
1810 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1811 VkResult result;
1812 struct radv_device *device;
1813
1814 bool keep_shader_info = false;
1815
1816 /* Check enabled features */
1817 if (pCreateInfo->pEnabledFeatures) {
1818 VkPhysicalDeviceFeatures supported_features;
1819 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1820 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1821 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1822 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1823 for (uint32_t i = 0; i < num_features; i++) {
1824 if (enabled_feature[i] && !supported_feature[i])
1825 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1826 }
1827 }
1828
1829 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1830 sizeof(*device), 8,
1831 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1832 if (!device)
1833 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1834
1835 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1836 device->instance = physical_device->instance;
1837 device->physical_device = physical_device;
1838
1839 device->ws = physical_device->ws;
1840 if (pAllocator)
1841 device->alloc = *pAllocator;
1842 else
1843 device->alloc = physical_device->instance->alloc;
1844
1845 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1846 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1847 int index = radv_get_device_extension_index(ext_name);
1848 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1849 vk_free(&device->alloc, device);
1850 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1851 }
1852
1853 device->enabled_extensions.extensions[index] = true;
1854 }
1855
1856 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1857
1858 /* With update after bind we can't attach bo's to the command buffer
1859 * from the descriptor set anymore, so we have to use a global BO list.
1860 */
1861 device->use_global_bo_list =
1862 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1863 device->enabled_extensions.EXT_descriptor_indexing ||
1864 device->enabled_extensions.EXT_buffer_device_address;
1865
1866 mtx_init(&device->shader_slab_mutex, mtx_plain);
1867 list_inithead(&device->shader_slabs);
1868
1869 radv_bo_list_init(&device->bo_list);
1870
1871 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1872 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1873 uint32_t qfi = queue_create->queueFamilyIndex;
1874 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1875 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1876
1877 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1878
1879 device->queues[qfi] = vk_alloc(&device->alloc,
1880 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1881 if (!device->queues[qfi]) {
1882 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1883 goto fail;
1884 }
1885
1886 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1887
1888 device->queue_count[qfi] = queue_create->queueCount;
1889
1890 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1891 result = radv_queue_init(device, &device->queues[qfi][q],
1892 qfi, q, queue_create->flags,
1893 global_priority);
1894 if (result != VK_SUCCESS)
1895 goto fail;
1896 }
1897 }
1898
1899 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1900 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1901
1902 /* Disabled and not implemented for now. */
1903 device->dfsm_allowed = device->pbb_allowed &&
1904 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1905 device->physical_device->rad_info.family == CHIP_RAVEN2);
1906
1907 #ifdef ANDROID
1908 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1909 #endif
1910
1911 /* The maximum number of scratch waves. Scratch space isn't divided
1912 * evenly between CUs. The number is only a function of the number of CUs.
1913 * We can decrease the constant to decrease the scratch buffer size.
1914 *
1915 * sctx->scratch_waves must be >= the maximum possible size of
1916 * 1 threadgroup, so that the hw doesn't hang from being unable
1917 * to start any.
1918 *
1919 * The recommended value is 4 per CU at most. Higher numbers don't
1920 * bring much benefit, but they still occupy chip resources (think
1921 * async compute). I've seen ~2% performance difference between 4 and 32.
1922 */
1923 uint32_t max_threads_per_block = 2048;
1924 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1925 max_threads_per_block / 64);
1926
1927 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1928
1929 if (device->physical_device->rad_info.chip_class >= GFX7) {
1930 /* If the KMD allows it (there is a KMD hw register for it),
1931 * allow launching waves out-of-order.
1932 */
1933 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1934 }
1935
1936 radv_device_init_gs_info(device);
1937
1938 device->tess_offchip_block_dw_size =
1939 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1940 device->has_distributed_tess =
1941 device->physical_device->rad_info.chip_class >= GFX8 &&
1942 device->physical_device->rad_info.max_se >= 2;
1943
1944 if (getenv("RADV_TRACE_FILE")) {
1945 const char *filename = getenv("RADV_TRACE_FILE");
1946
1947 keep_shader_info = true;
1948
1949 if (!radv_init_trace(device))
1950 goto fail;
1951
1952 fprintf(stderr, "*****************************************************************************\n");
1953 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1954 fprintf(stderr, "*****************************************************************************\n");
1955
1956 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1957 radv_dump_enabled_options(device, stderr);
1958 }
1959
1960 device->keep_shader_info = keep_shader_info;
1961
1962 result = radv_device_init_meta(device);
1963 if (result != VK_SUCCESS)
1964 goto fail;
1965
1966 radv_device_init_msaa(device);
1967
1968 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1969 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1970 switch (family) {
1971 case RADV_QUEUE_GENERAL:
1972 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1973 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1974 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1975 break;
1976 case RADV_QUEUE_COMPUTE:
1977 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1978 radeon_emit(device->empty_cs[family], 0);
1979 break;
1980 }
1981 device->ws->cs_finalize(device->empty_cs[family]);
1982 }
1983
1984 if (device->physical_device->rad_info.chip_class >= GFX7)
1985 cik_create_gfx_config(device);
1986
1987 VkPipelineCacheCreateInfo ci;
1988 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1989 ci.pNext = NULL;
1990 ci.flags = 0;
1991 ci.pInitialData = NULL;
1992 ci.initialDataSize = 0;
1993 VkPipelineCache pc;
1994 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1995 &ci, NULL, &pc);
1996 if (result != VK_SUCCESS)
1997 goto fail_meta;
1998
1999 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2000
2001 device->force_aniso =
2002 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2003 if (device->force_aniso >= 0) {
2004 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2005 1 << util_logbase2(device->force_aniso));
2006 }
2007
2008 *pDevice = radv_device_to_handle(device);
2009 return VK_SUCCESS;
2010
2011 fail_meta:
2012 radv_device_finish_meta(device);
2013 fail:
2014 radv_bo_list_finish(&device->bo_list);
2015
2016 if (device->trace_bo)
2017 device->ws->buffer_destroy(device->trace_bo);
2018
2019 if (device->gfx_init)
2020 device->ws->buffer_destroy(device->gfx_init);
2021
2022 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2023 for (unsigned q = 0; q < device->queue_count[i]; q++)
2024 radv_queue_finish(&device->queues[i][q]);
2025 if (device->queue_count[i])
2026 vk_free(&device->alloc, device->queues[i]);
2027 }
2028
2029 vk_free(&device->alloc, device);
2030 return result;
2031 }
2032
2033 void radv_DestroyDevice(
2034 VkDevice _device,
2035 const VkAllocationCallbacks* pAllocator)
2036 {
2037 RADV_FROM_HANDLE(radv_device, device, _device);
2038
2039 if (!device)
2040 return;
2041
2042 if (device->trace_bo)
2043 device->ws->buffer_destroy(device->trace_bo);
2044
2045 if (device->gfx_init)
2046 device->ws->buffer_destroy(device->gfx_init);
2047
2048 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2049 for (unsigned q = 0; q < device->queue_count[i]; q++)
2050 radv_queue_finish(&device->queues[i][q]);
2051 if (device->queue_count[i])
2052 vk_free(&device->alloc, device->queues[i]);
2053 if (device->empty_cs[i])
2054 device->ws->cs_destroy(device->empty_cs[i]);
2055 }
2056 radv_device_finish_meta(device);
2057
2058 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2059 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2060
2061 radv_destroy_shader_slabs(device);
2062
2063 radv_bo_list_finish(&device->bo_list);
2064 vk_free(&device->alloc, device);
2065 }
2066
2067 VkResult radv_EnumerateInstanceLayerProperties(
2068 uint32_t* pPropertyCount,
2069 VkLayerProperties* pProperties)
2070 {
2071 if (pProperties == NULL) {
2072 *pPropertyCount = 0;
2073 return VK_SUCCESS;
2074 }
2075
2076 /* None supported at this time */
2077 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2078 }
2079
2080 VkResult radv_EnumerateDeviceLayerProperties(
2081 VkPhysicalDevice physicalDevice,
2082 uint32_t* pPropertyCount,
2083 VkLayerProperties* pProperties)
2084 {
2085 if (pProperties == NULL) {
2086 *pPropertyCount = 0;
2087 return VK_SUCCESS;
2088 }
2089
2090 /* None supported at this time */
2091 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2092 }
2093
2094 void radv_GetDeviceQueue2(
2095 VkDevice _device,
2096 const VkDeviceQueueInfo2* pQueueInfo,
2097 VkQueue* pQueue)
2098 {
2099 RADV_FROM_HANDLE(radv_device, device, _device);
2100 struct radv_queue *queue;
2101
2102 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2103 if (pQueueInfo->flags != queue->flags) {
2104 /* From the Vulkan 1.1.70 spec:
2105 *
2106 * "The queue returned by vkGetDeviceQueue2 must have the same
2107 * flags value from this structure as that used at device
2108 * creation time in a VkDeviceQueueCreateInfo instance. If no
2109 * matching flags were specified at device creation time then
2110 * pQueue will return VK_NULL_HANDLE."
2111 */
2112 *pQueue = VK_NULL_HANDLE;
2113 return;
2114 }
2115
2116 *pQueue = radv_queue_to_handle(queue);
2117 }
2118
2119 void radv_GetDeviceQueue(
2120 VkDevice _device,
2121 uint32_t queueFamilyIndex,
2122 uint32_t queueIndex,
2123 VkQueue* pQueue)
2124 {
2125 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2126 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2127 .queueFamilyIndex = queueFamilyIndex,
2128 .queueIndex = queueIndex
2129 };
2130
2131 radv_GetDeviceQueue2(_device, &info, pQueue);
2132 }
2133
2134 static void
2135 fill_geom_tess_rings(struct radv_queue *queue,
2136 uint32_t *map,
2137 bool add_sample_positions,
2138 uint32_t esgs_ring_size,
2139 struct radeon_winsys_bo *esgs_ring_bo,
2140 uint32_t gsvs_ring_size,
2141 struct radeon_winsys_bo *gsvs_ring_bo,
2142 uint32_t tess_factor_ring_size,
2143 uint32_t tess_offchip_ring_offset,
2144 uint32_t tess_offchip_ring_size,
2145 struct radeon_winsys_bo *tess_rings_bo)
2146 {
2147 uint32_t *desc = &map[4];
2148
2149 if (esgs_ring_bo) {
2150 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2151
2152 /* stride 0, num records - size, add tid, swizzle, elsize4,
2153 index stride 64 */
2154 desc[0] = esgs_va;
2155 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2156 S_008F04_SWIZZLE_ENABLE(true);
2157 desc[2] = esgs_ring_size;
2158 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2159 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2160 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2161 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2162 S_008F0C_INDEX_STRIDE(3) |
2163 S_008F0C_ADD_TID_ENABLE(1);
2164
2165 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2166 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2167 S_008F0C_OOB_SELECT(2) |
2168 S_008F0C_RESOURCE_LEVEL(1);
2169 } else {
2170 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2172 S_008F0C_ELEMENT_SIZE(1);
2173 }
2174
2175 /* GS entry for ES->GS ring */
2176 /* stride 0, num records - size, elsize0,
2177 index stride 0 */
2178 desc[4] = esgs_va;
2179 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2180 desc[6] = esgs_ring_size;
2181 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2182 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2183 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2184 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2185
2186 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2187 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2188 S_008F0C_OOB_SELECT(2) |
2189 S_008F0C_RESOURCE_LEVEL(1);
2190 } else {
2191 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2193 }
2194 }
2195
2196 desc += 8;
2197
2198 if (gsvs_ring_bo) {
2199 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2200
2201 /* VS entry for GS->VS ring */
2202 /* stride 0, num records - size, elsize0,
2203 index stride 0 */
2204 desc[0] = gsvs_va;
2205 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2206 desc[2] = gsvs_ring_size;
2207 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2208 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2209 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2210 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2211
2212 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2213 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2214 S_008F0C_OOB_SELECT(2) |
2215 S_008F0C_RESOURCE_LEVEL(1);
2216 } else {
2217 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2218 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2219 }
2220
2221 /* stride gsvs_itemsize, num records 64
2222 elsize 4, index stride 16 */
2223 /* shader will patch stride and desc[2] */
2224 desc[4] = gsvs_va;
2225 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2226 S_008F04_SWIZZLE_ENABLE(1);
2227 desc[6] = 0;
2228 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2229 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2230 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2231 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2232 S_008F0C_INDEX_STRIDE(1) |
2233 S_008F0C_ADD_TID_ENABLE(true);
2234
2235 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2236 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2237 S_008F0C_OOB_SELECT(2) |
2238 S_008F0C_RESOURCE_LEVEL(1);
2239 } else {
2240 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2241 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2242 S_008F0C_ELEMENT_SIZE(1);
2243 }
2244
2245 }
2246
2247 desc += 8;
2248
2249 if (tess_rings_bo) {
2250 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2251 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2252
2253 desc[0] = tess_va;
2254 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2255 desc[2] = tess_factor_ring_size;
2256 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2257 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2258 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2259 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2260
2261 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2262 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2263 S_008F0C_OOB_SELECT(3) |
2264 S_008F0C_RESOURCE_LEVEL(1);
2265 } else {
2266 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2267 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2268 }
2269
2270 desc[4] = tess_offchip_va;
2271 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2272 desc[6] = tess_offchip_ring_size;
2273 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2274 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2275 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2276 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2277
2278 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2279 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2280 S_008F0C_OOB_SELECT(3) |
2281 S_008F0C_RESOURCE_LEVEL(1);
2282 } else {
2283 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2284 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2285 }
2286 }
2287
2288 desc += 8;
2289
2290 if (add_sample_positions) {
2291 /* add sample positions after all rings */
2292 memcpy(desc, queue->device->sample_locations_1x, 8);
2293 desc += 2;
2294 memcpy(desc, queue->device->sample_locations_2x, 16);
2295 desc += 4;
2296 memcpy(desc, queue->device->sample_locations_4x, 32);
2297 desc += 8;
2298 memcpy(desc, queue->device->sample_locations_8x, 64);
2299 }
2300 }
2301
2302 static unsigned
2303 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2304 {
2305 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2306 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2307 device->physical_device->rad_info.family != CHIP_STONEY;
2308 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2309 unsigned max_offchip_buffers;
2310 unsigned offchip_granularity;
2311 unsigned hs_offchip_param;
2312
2313 /*
2314 * Per RadeonSI:
2315 * This must be one less than the maximum number due to a hw limitation.
2316 * Various hardware bugs need thGFX7
2317 *
2318 * Per AMDVLK:
2319 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2320 * Gfx7 should limit max_offchip_buffers to 508
2321 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2322 *
2323 * Follow AMDVLK here.
2324 */
2325 if (device->physical_device->rad_info.chip_class >= GFX10) {
2326 max_offchip_buffers_per_se = 256;
2327 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2328 device->physical_device->rad_info.chip_class == GFX7 ||
2329 device->physical_device->rad_info.chip_class == GFX6)
2330 --max_offchip_buffers_per_se;
2331
2332 max_offchip_buffers = max_offchip_buffers_per_se *
2333 device->physical_device->rad_info.max_se;
2334
2335 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2336 * around by setting 4K granularity.
2337 */
2338 if (device->tess_offchip_block_dw_size == 4096) {
2339 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2340 offchip_granularity = V_03093C_X_4K_DWORDS;
2341 } else {
2342 assert(device->tess_offchip_block_dw_size == 8192);
2343 offchip_granularity = V_03093C_X_8K_DWORDS;
2344 }
2345
2346 switch (device->physical_device->rad_info.chip_class) {
2347 case GFX6:
2348 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2349 break;
2350 case GFX7:
2351 case GFX8:
2352 case GFX9:
2353 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2354 break;
2355 case GFX10:
2356 break;
2357 default:
2358 break;
2359 }
2360
2361 *max_offchip_buffers_p = max_offchip_buffers;
2362 if (device->physical_device->rad_info.chip_class >= GFX7) {
2363 if (device->physical_device->rad_info.chip_class >= GFX8)
2364 --max_offchip_buffers;
2365 hs_offchip_param =
2366 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2367 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2368 } else {
2369 hs_offchip_param =
2370 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2371 }
2372 return hs_offchip_param;
2373 }
2374
2375 static void
2376 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2377 struct radeon_winsys_bo *esgs_ring_bo,
2378 uint32_t esgs_ring_size,
2379 struct radeon_winsys_bo *gsvs_ring_bo,
2380 uint32_t gsvs_ring_size)
2381 {
2382 if (!esgs_ring_bo && !gsvs_ring_bo)
2383 return;
2384
2385 if (esgs_ring_bo)
2386 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2387
2388 if (gsvs_ring_bo)
2389 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2390
2391 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2392 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2393 radeon_emit(cs, esgs_ring_size >> 8);
2394 radeon_emit(cs, gsvs_ring_size >> 8);
2395 } else {
2396 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2397 radeon_emit(cs, esgs_ring_size >> 8);
2398 radeon_emit(cs, gsvs_ring_size >> 8);
2399 }
2400 }
2401
2402 static void
2403 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2404 unsigned hs_offchip_param, unsigned tf_ring_size,
2405 struct radeon_winsys_bo *tess_rings_bo)
2406 {
2407 uint64_t tf_va;
2408
2409 if (!tess_rings_bo)
2410 return;
2411
2412 tf_va = radv_buffer_get_va(tess_rings_bo);
2413
2414 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2415
2416 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2417 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2418 S_030938_SIZE(tf_ring_size / 4));
2419 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2420 tf_va >> 8);
2421
2422 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2423 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2424 S_030984_BASE_HI(tf_va >> 40));
2425 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2426 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2427 S_030944_BASE_HI(tf_va >> 40));
2428 }
2429 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2430 hs_offchip_param);
2431 } else {
2432 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2433 S_008988_SIZE(tf_ring_size / 4));
2434 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2435 tf_va >> 8);
2436 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2437 hs_offchip_param);
2438 }
2439 }
2440
2441 static void
2442 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2443 struct radeon_winsys_bo *compute_scratch_bo)
2444 {
2445 uint64_t scratch_va;
2446
2447 if (!compute_scratch_bo)
2448 return;
2449
2450 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2451
2452 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2453
2454 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2455 radeon_emit(cs, scratch_va);
2456 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2457 S_008F04_SWIZZLE_ENABLE(1));
2458 }
2459
2460 static void
2461 radv_emit_global_shader_pointers(struct radv_queue *queue,
2462 struct radeon_cmdbuf *cs,
2463 struct radeon_winsys_bo *descriptor_bo)
2464 {
2465 uint64_t va;
2466
2467 if (!descriptor_bo)
2468 return;
2469
2470 va = radv_buffer_get_va(descriptor_bo);
2471
2472 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2473
2474 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2475 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2476 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2477 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2478 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2479
2480 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2481 radv_emit_shader_pointer(queue->device, cs, regs[i],
2482 va, true);
2483 }
2484 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2485 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2486 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2487 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2488 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2489
2490 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2491 radv_emit_shader_pointer(queue->device, cs, regs[i],
2492 va, true);
2493 }
2494 } else {
2495 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2496 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2497 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2498 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2499 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2500 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2501
2502 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2503 radv_emit_shader_pointer(queue->device, cs, regs[i],
2504 va, true);
2505 }
2506 }
2507 }
2508
2509 static void
2510 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2511 {
2512 struct radv_device *device = queue->device;
2513
2514 if (device->gfx_init) {
2515 uint64_t va = radv_buffer_get_va(device->gfx_init);
2516
2517 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2518 radeon_emit(cs, va);
2519 radeon_emit(cs, va >> 32);
2520 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2521
2522 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2523 } else {
2524 struct radv_physical_device *physical_device = device->physical_device;
2525 si_emit_graphics(physical_device, cs);
2526 }
2527 }
2528
2529 static void
2530 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2531 {
2532 struct radv_physical_device *physical_device = queue->device->physical_device;
2533 si_emit_compute(physical_device, cs);
2534 }
2535
2536 static VkResult
2537 radv_get_preamble_cs(struct radv_queue *queue,
2538 uint32_t scratch_size,
2539 uint32_t compute_scratch_size,
2540 uint32_t esgs_ring_size,
2541 uint32_t gsvs_ring_size,
2542 bool needs_tess_rings,
2543 bool needs_sample_positions,
2544 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2545 struct radeon_cmdbuf **initial_preamble_cs,
2546 struct radeon_cmdbuf **continue_preamble_cs)
2547 {
2548 struct radeon_winsys_bo *scratch_bo = NULL;
2549 struct radeon_winsys_bo *descriptor_bo = NULL;
2550 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2551 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2552 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2553 struct radeon_winsys_bo *tess_rings_bo = NULL;
2554 struct radeon_cmdbuf *dest_cs[3] = {0};
2555 bool add_tess_rings = false, add_sample_positions = false;
2556 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2557 unsigned max_offchip_buffers;
2558 unsigned hs_offchip_param = 0;
2559 unsigned tess_offchip_ring_offset;
2560 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2561 if (!queue->has_tess_rings) {
2562 if (needs_tess_rings)
2563 add_tess_rings = true;
2564 }
2565 if (!queue->has_sample_positions) {
2566 if (needs_sample_positions)
2567 add_sample_positions = true;
2568 }
2569 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2570 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2571 &max_offchip_buffers);
2572 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2573 tess_offchip_ring_size = max_offchip_buffers *
2574 queue->device->tess_offchip_block_dw_size * 4;
2575
2576 if (scratch_size <= queue->scratch_size &&
2577 compute_scratch_size <= queue->compute_scratch_size &&
2578 esgs_ring_size <= queue->esgs_ring_size &&
2579 gsvs_ring_size <= queue->gsvs_ring_size &&
2580 !add_tess_rings && !add_sample_positions &&
2581 queue->initial_preamble_cs) {
2582 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2583 *initial_preamble_cs = queue->initial_preamble_cs;
2584 *continue_preamble_cs = queue->continue_preamble_cs;
2585 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2586 *continue_preamble_cs = NULL;
2587 return VK_SUCCESS;
2588 }
2589
2590 if (scratch_size > queue->scratch_size) {
2591 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2592 scratch_size,
2593 4096,
2594 RADEON_DOMAIN_VRAM,
2595 ring_bo_flags,
2596 RADV_BO_PRIORITY_SCRATCH);
2597 if (!scratch_bo)
2598 goto fail;
2599 } else
2600 scratch_bo = queue->scratch_bo;
2601
2602 if (compute_scratch_size > queue->compute_scratch_size) {
2603 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2604 compute_scratch_size,
2605 4096,
2606 RADEON_DOMAIN_VRAM,
2607 ring_bo_flags,
2608 RADV_BO_PRIORITY_SCRATCH);
2609 if (!compute_scratch_bo)
2610 goto fail;
2611
2612 } else
2613 compute_scratch_bo = queue->compute_scratch_bo;
2614
2615 if (esgs_ring_size > queue->esgs_ring_size) {
2616 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2617 esgs_ring_size,
2618 4096,
2619 RADEON_DOMAIN_VRAM,
2620 ring_bo_flags,
2621 RADV_BO_PRIORITY_SCRATCH);
2622 if (!esgs_ring_bo)
2623 goto fail;
2624 } else {
2625 esgs_ring_bo = queue->esgs_ring_bo;
2626 esgs_ring_size = queue->esgs_ring_size;
2627 }
2628
2629 if (gsvs_ring_size > queue->gsvs_ring_size) {
2630 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2631 gsvs_ring_size,
2632 4096,
2633 RADEON_DOMAIN_VRAM,
2634 ring_bo_flags,
2635 RADV_BO_PRIORITY_SCRATCH);
2636 if (!gsvs_ring_bo)
2637 goto fail;
2638 } else {
2639 gsvs_ring_bo = queue->gsvs_ring_bo;
2640 gsvs_ring_size = queue->gsvs_ring_size;
2641 }
2642
2643 if (add_tess_rings) {
2644 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2645 tess_offchip_ring_offset + tess_offchip_ring_size,
2646 256,
2647 RADEON_DOMAIN_VRAM,
2648 ring_bo_flags,
2649 RADV_BO_PRIORITY_SCRATCH);
2650 if (!tess_rings_bo)
2651 goto fail;
2652 } else {
2653 tess_rings_bo = queue->tess_rings_bo;
2654 }
2655
2656 if (scratch_bo != queue->scratch_bo ||
2657 esgs_ring_bo != queue->esgs_ring_bo ||
2658 gsvs_ring_bo != queue->gsvs_ring_bo ||
2659 tess_rings_bo != queue->tess_rings_bo ||
2660 add_sample_positions) {
2661 uint32_t size = 0;
2662 if (gsvs_ring_bo || esgs_ring_bo ||
2663 tess_rings_bo || add_sample_positions) {
2664 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2665 if (add_sample_positions)
2666 size += 128; /* 64+32+16+8 = 120 bytes */
2667 }
2668 else if (scratch_bo)
2669 size = 8; /* 2 dword */
2670
2671 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2672 size,
2673 4096,
2674 RADEON_DOMAIN_VRAM,
2675 RADEON_FLAG_CPU_ACCESS |
2676 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2677 RADEON_FLAG_READ_ONLY,
2678 RADV_BO_PRIORITY_DESCRIPTOR);
2679 if (!descriptor_bo)
2680 goto fail;
2681 } else
2682 descriptor_bo = queue->descriptor_bo;
2683
2684 if (descriptor_bo != queue->descriptor_bo) {
2685 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2686
2687 if (scratch_bo) {
2688 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2689 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2690 S_008F04_SWIZZLE_ENABLE(1);
2691 map[0] = scratch_va;
2692 map[1] = rsrc1;
2693 }
2694
2695 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2696 fill_geom_tess_rings(queue, map, add_sample_positions,
2697 esgs_ring_size, esgs_ring_bo,
2698 gsvs_ring_size, gsvs_ring_bo,
2699 tess_factor_ring_size,
2700 tess_offchip_ring_offset,
2701 tess_offchip_ring_size,
2702 tess_rings_bo);
2703
2704 queue->device->ws->buffer_unmap(descriptor_bo);
2705 }
2706
2707 for(int i = 0; i < 3; ++i) {
2708 struct radeon_cmdbuf *cs = NULL;
2709 cs = queue->device->ws->cs_create(queue->device->ws,
2710 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2711 if (!cs)
2712 goto fail;
2713
2714 dest_cs[i] = cs;
2715
2716 if (scratch_bo)
2717 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2718
2719 /* Emit initial configuration. */
2720 switch (queue->queue_family_index) {
2721 case RADV_QUEUE_GENERAL:
2722 radv_init_graphics_state(cs, queue);
2723 break;
2724 case RADV_QUEUE_COMPUTE:
2725 radv_init_compute_state(cs, queue);
2726 break;
2727 case RADV_QUEUE_TRANSFER:
2728 break;
2729 }
2730
2731 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2732 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2733 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2734
2735 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2736 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2737 }
2738
2739 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2740 gsvs_ring_bo, gsvs_ring_size);
2741 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2742 tess_factor_ring_size, tess_rings_bo);
2743 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2744 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2745
2746 if (i == 0) {
2747 si_cs_emit_cache_flush(cs,
2748 queue->device->physical_device->rad_info.chip_class,
2749 NULL, 0,
2750 queue->queue_family_index == RING_COMPUTE &&
2751 queue->device->physical_device->rad_info.chip_class >= GFX7,
2752 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2753 RADV_CMD_FLAG_INV_ICACHE |
2754 RADV_CMD_FLAG_INV_SCACHE |
2755 RADV_CMD_FLAG_INV_VCACHE |
2756 RADV_CMD_FLAG_INV_L2 |
2757 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2758 } else if (i == 1) {
2759 si_cs_emit_cache_flush(cs,
2760 queue->device->physical_device->rad_info.chip_class,
2761 NULL, 0,
2762 queue->queue_family_index == RING_COMPUTE &&
2763 queue->device->physical_device->rad_info.chip_class >= GFX7,
2764 RADV_CMD_FLAG_INV_ICACHE |
2765 RADV_CMD_FLAG_INV_SCACHE |
2766 RADV_CMD_FLAG_INV_VCACHE |
2767 RADV_CMD_FLAG_INV_L2 |
2768 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2769 }
2770
2771 if (!queue->device->ws->cs_finalize(cs))
2772 goto fail;
2773 }
2774
2775 if (queue->initial_full_flush_preamble_cs)
2776 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2777
2778 if (queue->initial_preamble_cs)
2779 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2780
2781 if (queue->continue_preamble_cs)
2782 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2783
2784 queue->initial_full_flush_preamble_cs = dest_cs[0];
2785 queue->initial_preamble_cs = dest_cs[1];
2786 queue->continue_preamble_cs = dest_cs[2];
2787
2788 if (scratch_bo != queue->scratch_bo) {
2789 if (queue->scratch_bo)
2790 queue->device->ws->buffer_destroy(queue->scratch_bo);
2791 queue->scratch_bo = scratch_bo;
2792 queue->scratch_size = scratch_size;
2793 }
2794
2795 if (compute_scratch_bo != queue->compute_scratch_bo) {
2796 if (queue->compute_scratch_bo)
2797 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2798 queue->compute_scratch_bo = compute_scratch_bo;
2799 queue->compute_scratch_size = compute_scratch_size;
2800 }
2801
2802 if (esgs_ring_bo != queue->esgs_ring_bo) {
2803 if (queue->esgs_ring_bo)
2804 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2805 queue->esgs_ring_bo = esgs_ring_bo;
2806 queue->esgs_ring_size = esgs_ring_size;
2807 }
2808
2809 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2810 if (queue->gsvs_ring_bo)
2811 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2812 queue->gsvs_ring_bo = gsvs_ring_bo;
2813 queue->gsvs_ring_size = gsvs_ring_size;
2814 }
2815
2816 if (tess_rings_bo != queue->tess_rings_bo) {
2817 queue->tess_rings_bo = tess_rings_bo;
2818 queue->has_tess_rings = true;
2819 }
2820
2821 if (descriptor_bo != queue->descriptor_bo) {
2822 if (queue->descriptor_bo)
2823 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2824
2825 queue->descriptor_bo = descriptor_bo;
2826 }
2827
2828 if (add_sample_positions)
2829 queue->has_sample_positions = true;
2830
2831 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2832 *initial_preamble_cs = queue->initial_preamble_cs;
2833 *continue_preamble_cs = queue->continue_preamble_cs;
2834 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2835 *continue_preamble_cs = NULL;
2836 return VK_SUCCESS;
2837 fail:
2838 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2839 if (dest_cs[i])
2840 queue->device->ws->cs_destroy(dest_cs[i]);
2841 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2842 queue->device->ws->buffer_destroy(descriptor_bo);
2843 if (scratch_bo && scratch_bo != queue->scratch_bo)
2844 queue->device->ws->buffer_destroy(scratch_bo);
2845 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2846 queue->device->ws->buffer_destroy(compute_scratch_bo);
2847 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2848 queue->device->ws->buffer_destroy(esgs_ring_bo);
2849 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2850 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2851 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2852 queue->device->ws->buffer_destroy(tess_rings_bo);
2853 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2854 }
2855
2856 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2857 struct radv_winsys_sem_counts *counts,
2858 int num_sems,
2859 const VkSemaphore *sems,
2860 VkFence _fence,
2861 bool reset_temp)
2862 {
2863 int syncobj_idx = 0, sem_idx = 0;
2864
2865 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2866 return VK_SUCCESS;
2867
2868 for (uint32_t i = 0; i < num_sems; i++) {
2869 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2870
2871 if (sem->temp_syncobj || sem->syncobj)
2872 counts->syncobj_count++;
2873 else
2874 counts->sem_count++;
2875 }
2876
2877 if (_fence != VK_NULL_HANDLE) {
2878 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2879 if (fence->temp_syncobj || fence->syncobj)
2880 counts->syncobj_count++;
2881 }
2882
2883 if (counts->syncobj_count) {
2884 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2885 if (!counts->syncobj)
2886 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2887 }
2888
2889 if (counts->sem_count) {
2890 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2891 if (!counts->sem) {
2892 free(counts->syncobj);
2893 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2894 }
2895 }
2896
2897 for (uint32_t i = 0; i < num_sems; i++) {
2898 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2899
2900 if (sem->temp_syncobj) {
2901 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2902 }
2903 else if (sem->syncobj)
2904 counts->syncobj[syncobj_idx++] = sem->syncobj;
2905 else {
2906 assert(sem->sem);
2907 counts->sem[sem_idx++] = sem->sem;
2908 }
2909 }
2910
2911 if (_fence != VK_NULL_HANDLE) {
2912 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2913 if (fence->temp_syncobj)
2914 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2915 else if (fence->syncobj)
2916 counts->syncobj[syncobj_idx++] = fence->syncobj;
2917 }
2918
2919 return VK_SUCCESS;
2920 }
2921
2922 static void
2923 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2924 {
2925 free(sem_info->wait.syncobj);
2926 free(sem_info->wait.sem);
2927 free(sem_info->signal.syncobj);
2928 free(sem_info->signal.sem);
2929 }
2930
2931
2932 static void radv_free_temp_syncobjs(struct radv_device *device,
2933 int num_sems,
2934 const VkSemaphore *sems)
2935 {
2936 for (uint32_t i = 0; i < num_sems; i++) {
2937 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2938
2939 if (sem->temp_syncobj) {
2940 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2941 sem->temp_syncobj = 0;
2942 }
2943 }
2944 }
2945
2946 static VkResult
2947 radv_alloc_sem_info(struct radv_instance *instance,
2948 struct radv_winsys_sem_info *sem_info,
2949 int num_wait_sems,
2950 const VkSemaphore *wait_sems,
2951 int num_signal_sems,
2952 const VkSemaphore *signal_sems,
2953 VkFence fence)
2954 {
2955 VkResult ret;
2956 memset(sem_info, 0, sizeof(*sem_info));
2957
2958 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2959 if (ret)
2960 return ret;
2961 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2962 if (ret)
2963 radv_free_sem_info(sem_info);
2964
2965 /* caller can override these */
2966 sem_info->cs_emit_wait = true;
2967 sem_info->cs_emit_signal = true;
2968 return ret;
2969 }
2970
2971 /* Signals fence as soon as all the work currently put on queue is done. */
2972 static VkResult radv_signal_fence(struct radv_queue *queue,
2973 struct radv_fence *fence)
2974 {
2975 int ret;
2976 VkResult result;
2977 struct radv_winsys_sem_info sem_info;
2978
2979 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2980 radv_fence_to_handle(fence));
2981 if (result != VK_SUCCESS)
2982 return result;
2983
2984 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2985 &queue->device->empty_cs[queue->queue_family_index],
2986 1, NULL, NULL, &sem_info, NULL,
2987 false, fence->fence);
2988 radv_free_sem_info(&sem_info);
2989
2990 if (ret)
2991 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2992
2993 return VK_SUCCESS;
2994 }
2995
2996 VkResult radv_QueueSubmit(
2997 VkQueue _queue,
2998 uint32_t submitCount,
2999 const VkSubmitInfo* pSubmits,
3000 VkFence _fence)
3001 {
3002 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3003 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3004 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3005 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3006 int ret;
3007 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3008 uint32_t scratch_size = 0;
3009 uint32_t compute_scratch_size = 0;
3010 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3011 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3012 VkResult result;
3013 bool fence_emitted = false;
3014 bool tess_rings_needed = false;
3015 bool sample_positions_needed = false;
3016
3017 /* Do this first so failing to allocate scratch buffers can't result in
3018 * partially executed submissions. */
3019 for (uint32_t i = 0; i < submitCount; i++) {
3020 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3021 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3022 pSubmits[i].pCommandBuffers[j]);
3023
3024 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3025 compute_scratch_size = MAX2(compute_scratch_size,
3026 cmd_buffer->compute_scratch_size_needed);
3027 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3028 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3029 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3030 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3031 }
3032 }
3033
3034 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3035 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3036 sample_positions_needed, &initial_flush_preamble_cs,
3037 &initial_preamble_cs, &continue_preamble_cs);
3038 if (result != VK_SUCCESS)
3039 return result;
3040
3041 for (uint32_t i = 0; i < submitCount; i++) {
3042 struct radeon_cmdbuf **cs_array;
3043 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3044 bool can_patch = true;
3045 uint32_t advance;
3046 struct radv_winsys_sem_info sem_info;
3047
3048 result = radv_alloc_sem_info(queue->device->instance,
3049 &sem_info,
3050 pSubmits[i].waitSemaphoreCount,
3051 pSubmits[i].pWaitSemaphores,
3052 pSubmits[i].signalSemaphoreCount,
3053 pSubmits[i].pSignalSemaphores,
3054 _fence);
3055 if (result != VK_SUCCESS)
3056 return result;
3057
3058 if (!pSubmits[i].commandBufferCount) {
3059 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3060 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3061 &queue->device->empty_cs[queue->queue_family_index],
3062 1, NULL, NULL,
3063 &sem_info, NULL,
3064 false, base_fence);
3065 if (ret) {
3066 radv_loge("failed to submit CS %d\n", i);
3067 abort();
3068 }
3069 fence_emitted = true;
3070 }
3071 radv_free_sem_info(&sem_info);
3072 continue;
3073 }
3074
3075 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3076 (pSubmits[i].commandBufferCount));
3077
3078 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3079 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3080 pSubmits[i].pCommandBuffers[j]);
3081 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3082
3083 cs_array[j] = cmd_buffer->cs;
3084 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3085 can_patch = false;
3086
3087 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3088 }
3089
3090 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3091 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3092 const struct radv_winsys_bo_list *bo_list = NULL;
3093
3094 advance = MIN2(max_cs_submission,
3095 pSubmits[i].commandBufferCount - j);
3096
3097 if (queue->device->trace_bo)
3098 *queue->device->trace_id_ptr = 0;
3099
3100 sem_info.cs_emit_wait = j == 0;
3101 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3102
3103 if (unlikely(queue->device->use_global_bo_list)) {
3104 pthread_mutex_lock(&queue->device->bo_list.mutex);
3105 bo_list = &queue->device->bo_list.list;
3106 }
3107
3108 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3109 advance, initial_preamble, continue_preamble_cs,
3110 &sem_info, bo_list,
3111 can_patch, base_fence);
3112
3113 if (unlikely(queue->device->use_global_bo_list))
3114 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3115
3116 if (ret) {
3117 radv_loge("failed to submit CS %d\n", i);
3118 abort();
3119 }
3120 fence_emitted = true;
3121 if (queue->device->trace_bo) {
3122 radv_check_gpu_hangs(queue, cs_array[j]);
3123 }
3124 }
3125
3126 radv_free_temp_syncobjs(queue->device,
3127 pSubmits[i].waitSemaphoreCount,
3128 pSubmits[i].pWaitSemaphores);
3129 radv_free_sem_info(&sem_info);
3130 free(cs_array);
3131 }
3132
3133 if (fence) {
3134 if (!fence_emitted) {
3135 result = radv_signal_fence(queue, fence);
3136 if (result != VK_SUCCESS)
3137 return result;
3138 }
3139 }
3140
3141 return VK_SUCCESS;
3142 }
3143
3144 VkResult radv_QueueWaitIdle(
3145 VkQueue _queue)
3146 {
3147 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3148
3149 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3150 radv_queue_family_to_ring(queue->queue_family_index),
3151 queue->queue_idx);
3152 return VK_SUCCESS;
3153 }
3154
3155 VkResult radv_DeviceWaitIdle(
3156 VkDevice _device)
3157 {
3158 RADV_FROM_HANDLE(radv_device, device, _device);
3159
3160 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3161 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3162 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3163 }
3164 }
3165 return VK_SUCCESS;
3166 }
3167
3168 VkResult radv_EnumerateInstanceExtensionProperties(
3169 const char* pLayerName,
3170 uint32_t* pPropertyCount,
3171 VkExtensionProperties* pProperties)
3172 {
3173 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3174
3175 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3176 if (radv_supported_instance_extensions.extensions[i]) {
3177 vk_outarray_append(&out, prop) {
3178 *prop = radv_instance_extensions[i];
3179 }
3180 }
3181 }
3182
3183 return vk_outarray_status(&out);
3184 }
3185
3186 VkResult radv_EnumerateDeviceExtensionProperties(
3187 VkPhysicalDevice physicalDevice,
3188 const char* pLayerName,
3189 uint32_t* pPropertyCount,
3190 VkExtensionProperties* pProperties)
3191 {
3192 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3193 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3194
3195 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3196 if (device->supported_extensions.extensions[i]) {
3197 vk_outarray_append(&out, prop) {
3198 *prop = radv_device_extensions[i];
3199 }
3200 }
3201 }
3202
3203 return vk_outarray_status(&out);
3204 }
3205
3206 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3207 VkInstance _instance,
3208 const char* pName)
3209 {
3210 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3211
3212 return radv_lookup_entrypoint_checked(pName,
3213 instance ? instance->apiVersion : 0,
3214 instance ? &instance->enabled_extensions : NULL,
3215 NULL);
3216 }
3217
3218 /* The loader wants us to expose a second GetInstanceProcAddr function
3219 * to work around certain LD_PRELOAD issues seen in apps.
3220 */
3221 PUBLIC
3222 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3223 VkInstance instance,
3224 const char* pName);
3225
3226 PUBLIC
3227 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3228 VkInstance instance,
3229 const char* pName)
3230 {
3231 return radv_GetInstanceProcAddr(instance, pName);
3232 }
3233
3234 PUBLIC
3235 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3236 VkInstance _instance,
3237 const char* pName);
3238
3239 PUBLIC
3240 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3241 VkInstance _instance,
3242 const char* pName)
3243 {
3244 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3245
3246 return radv_lookup_physical_device_entrypoint_checked(pName,
3247 instance ? instance->apiVersion : 0,
3248 instance ? &instance->enabled_extensions : NULL);
3249 }
3250
3251 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3252 VkDevice _device,
3253 const char* pName)
3254 {
3255 RADV_FROM_HANDLE(radv_device, device, _device);
3256
3257 return radv_lookup_entrypoint_checked(pName,
3258 device->instance->apiVersion,
3259 &device->instance->enabled_extensions,
3260 &device->enabled_extensions);
3261 }
3262
3263 bool radv_get_memory_fd(struct radv_device *device,
3264 struct radv_device_memory *memory,
3265 int *pFD)
3266 {
3267 struct radeon_bo_metadata metadata;
3268
3269 if (memory->image) {
3270 radv_init_metadata(device, memory->image, &metadata);
3271 device->ws->buffer_set_metadata(memory->bo, &metadata);
3272 }
3273
3274 return device->ws->buffer_get_fd(device->ws, memory->bo,
3275 pFD);
3276 }
3277
3278 static VkResult radv_alloc_memory(struct radv_device *device,
3279 const VkMemoryAllocateInfo* pAllocateInfo,
3280 const VkAllocationCallbacks* pAllocator,
3281 VkDeviceMemory* pMem)
3282 {
3283 struct radv_device_memory *mem;
3284 VkResult result;
3285 enum radeon_bo_domain domain;
3286 uint32_t flags = 0;
3287 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3288
3289 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3290
3291 if (pAllocateInfo->allocationSize == 0) {
3292 /* Apparently, this is allowed */
3293 *pMem = VK_NULL_HANDLE;
3294 return VK_SUCCESS;
3295 }
3296
3297 const VkImportMemoryFdInfoKHR *import_info =
3298 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3299 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3300 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3301 const VkExportMemoryAllocateInfo *export_info =
3302 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3303 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3304 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3305
3306 const struct wsi_memory_allocate_info *wsi_info =
3307 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3308
3309 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3310 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3311 if (mem == NULL)
3312 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3313
3314 if (wsi_info && wsi_info->implicit_sync)
3315 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3316
3317 if (dedicate_info) {
3318 mem->image = radv_image_from_handle(dedicate_info->image);
3319 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3320 } else {
3321 mem->image = NULL;
3322 mem->buffer = NULL;
3323 }
3324
3325 float priority_float = 0.5;
3326 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3327 vk_find_struct_const(pAllocateInfo->pNext,
3328 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3329 if (priority_ext)
3330 priority_float = priority_ext->priority;
3331
3332 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3333 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3334
3335 mem->user_ptr = NULL;
3336
3337 if (import_info) {
3338 assert(import_info->handleType ==
3339 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3340 import_info->handleType ==
3341 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3342 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3343 priority, NULL, NULL);
3344 if (!mem->bo) {
3345 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3346 goto fail;
3347 } else {
3348 close(import_info->fd);
3349 }
3350 } else if (host_ptr_info) {
3351 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3352 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3353 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3354 pAllocateInfo->allocationSize,
3355 priority);
3356 if (!mem->bo) {
3357 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3358 goto fail;
3359 } else {
3360 mem->user_ptr = host_ptr_info->pHostPointer;
3361 }
3362 } else {
3363 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3364 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3365 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3366 domain = RADEON_DOMAIN_GTT;
3367 else
3368 domain = RADEON_DOMAIN_VRAM;
3369
3370 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3371 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3372 else
3373 flags |= RADEON_FLAG_CPU_ACCESS;
3374
3375 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3376 flags |= RADEON_FLAG_GTT_WC;
3377
3378 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3379 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3380 if (device->use_global_bo_list) {
3381 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3382 }
3383 }
3384
3385 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3386 domain, flags, priority);
3387
3388 if (!mem->bo) {
3389 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3390 goto fail;
3391 }
3392 mem->type_index = mem_type_index;
3393 }
3394
3395 result = radv_bo_list_add(device, mem->bo);
3396 if (result != VK_SUCCESS)
3397 goto fail_bo;
3398
3399 *pMem = radv_device_memory_to_handle(mem);
3400
3401 return VK_SUCCESS;
3402
3403 fail_bo:
3404 device->ws->buffer_destroy(mem->bo);
3405 fail:
3406 vk_free2(&device->alloc, pAllocator, mem);
3407
3408 return result;
3409 }
3410
3411 VkResult radv_AllocateMemory(
3412 VkDevice _device,
3413 const VkMemoryAllocateInfo* pAllocateInfo,
3414 const VkAllocationCallbacks* pAllocator,
3415 VkDeviceMemory* pMem)
3416 {
3417 RADV_FROM_HANDLE(radv_device, device, _device);
3418 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3419 }
3420
3421 void radv_FreeMemory(
3422 VkDevice _device,
3423 VkDeviceMemory _mem,
3424 const VkAllocationCallbacks* pAllocator)
3425 {
3426 RADV_FROM_HANDLE(radv_device, device, _device);
3427 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3428
3429 if (mem == NULL)
3430 return;
3431
3432 radv_bo_list_remove(device, mem->bo);
3433 device->ws->buffer_destroy(mem->bo);
3434 mem->bo = NULL;
3435
3436 vk_free2(&device->alloc, pAllocator, mem);
3437 }
3438
3439 VkResult radv_MapMemory(
3440 VkDevice _device,
3441 VkDeviceMemory _memory,
3442 VkDeviceSize offset,
3443 VkDeviceSize size,
3444 VkMemoryMapFlags flags,
3445 void** ppData)
3446 {
3447 RADV_FROM_HANDLE(radv_device, device, _device);
3448 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3449
3450 if (mem == NULL) {
3451 *ppData = NULL;
3452 return VK_SUCCESS;
3453 }
3454
3455 if (mem->user_ptr)
3456 *ppData = mem->user_ptr;
3457 else
3458 *ppData = device->ws->buffer_map(mem->bo);
3459
3460 if (*ppData) {
3461 *ppData += offset;
3462 return VK_SUCCESS;
3463 }
3464
3465 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3466 }
3467
3468 void radv_UnmapMemory(
3469 VkDevice _device,
3470 VkDeviceMemory _memory)
3471 {
3472 RADV_FROM_HANDLE(radv_device, device, _device);
3473 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3474
3475 if (mem == NULL)
3476 return;
3477
3478 if (mem->user_ptr == NULL)
3479 device->ws->buffer_unmap(mem->bo);
3480 }
3481
3482 VkResult radv_FlushMappedMemoryRanges(
3483 VkDevice _device,
3484 uint32_t memoryRangeCount,
3485 const VkMappedMemoryRange* pMemoryRanges)
3486 {
3487 return VK_SUCCESS;
3488 }
3489
3490 VkResult radv_InvalidateMappedMemoryRanges(
3491 VkDevice _device,
3492 uint32_t memoryRangeCount,
3493 const VkMappedMemoryRange* pMemoryRanges)
3494 {
3495 return VK_SUCCESS;
3496 }
3497
3498 void radv_GetBufferMemoryRequirements(
3499 VkDevice _device,
3500 VkBuffer _buffer,
3501 VkMemoryRequirements* pMemoryRequirements)
3502 {
3503 RADV_FROM_HANDLE(radv_device, device, _device);
3504 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3505
3506 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3507
3508 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3509 pMemoryRequirements->alignment = 4096;
3510 else
3511 pMemoryRequirements->alignment = 16;
3512
3513 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3514 }
3515
3516 void radv_GetBufferMemoryRequirements2(
3517 VkDevice device,
3518 const VkBufferMemoryRequirementsInfo2 *pInfo,
3519 VkMemoryRequirements2 *pMemoryRequirements)
3520 {
3521 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3522 &pMemoryRequirements->memoryRequirements);
3523 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3524 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3525 switch (ext->sType) {
3526 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3527 VkMemoryDedicatedRequirements *req =
3528 (VkMemoryDedicatedRequirements *) ext;
3529 req->requiresDedicatedAllocation = buffer->shareable;
3530 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3531 break;
3532 }
3533 default:
3534 break;
3535 }
3536 }
3537 }
3538
3539 void radv_GetImageMemoryRequirements(
3540 VkDevice _device,
3541 VkImage _image,
3542 VkMemoryRequirements* pMemoryRequirements)
3543 {
3544 RADV_FROM_HANDLE(radv_device, device, _device);
3545 RADV_FROM_HANDLE(radv_image, image, _image);
3546
3547 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3548
3549 pMemoryRequirements->size = image->size;
3550 pMemoryRequirements->alignment = image->alignment;
3551 }
3552
3553 void radv_GetImageMemoryRequirements2(
3554 VkDevice device,
3555 const VkImageMemoryRequirementsInfo2 *pInfo,
3556 VkMemoryRequirements2 *pMemoryRequirements)
3557 {
3558 radv_GetImageMemoryRequirements(device, pInfo->image,
3559 &pMemoryRequirements->memoryRequirements);
3560
3561 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3562
3563 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3564 switch (ext->sType) {
3565 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3566 VkMemoryDedicatedRequirements *req =
3567 (VkMemoryDedicatedRequirements *) ext;
3568 req->requiresDedicatedAllocation = image->shareable;
3569 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3570 break;
3571 }
3572 default:
3573 break;
3574 }
3575 }
3576 }
3577
3578 void radv_GetImageSparseMemoryRequirements(
3579 VkDevice device,
3580 VkImage image,
3581 uint32_t* pSparseMemoryRequirementCount,
3582 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3583 {
3584 stub();
3585 }
3586
3587 void radv_GetImageSparseMemoryRequirements2(
3588 VkDevice device,
3589 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3590 uint32_t* pSparseMemoryRequirementCount,
3591 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3592 {
3593 stub();
3594 }
3595
3596 void radv_GetDeviceMemoryCommitment(
3597 VkDevice device,
3598 VkDeviceMemory memory,
3599 VkDeviceSize* pCommittedMemoryInBytes)
3600 {
3601 *pCommittedMemoryInBytes = 0;
3602 }
3603
3604 VkResult radv_BindBufferMemory2(VkDevice device,
3605 uint32_t bindInfoCount,
3606 const VkBindBufferMemoryInfo *pBindInfos)
3607 {
3608 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3609 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3610 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3611
3612 if (mem) {
3613 buffer->bo = mem->bo;
3614 buffer->offset = pBindInfos[i].memoryOffset;
3615 } else {
3616 buffer->bo = NULL;
3617 }
3618 }
3619 return VK_SUCCESS;
3620 }
3621
3622 VkResult radv_BindBufferMemory(
3623 VkDevice device,
3624 VkBuffer buffer,
3625 VkDeviceMemory memory,
3626 VkDeviceSize memoryOffset)
3627 {
3628 const VkBindBufferMemoryInfo info = {
3629 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3630 .buffer = buffer,
3631 .memory = memory,
3632 .memoryOffset = memoryOffset
3633 };
3634
3635 return radv_BindBufferMemory2(device, 1, &info);
3636 }
3637
3638 VkResult radv_BindImageMemory2(VkDevice device,
3639 uint32_t bindInfoCount,
3640 const VkBindImageMemoryInfo *pBindInfos)
3641 {
3642 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3643 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3644 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3645
3646 if (mem) {
3647 image->bo = mem->bo;
3648 image->offset = pBindInfos[i].memoryOffset;
3649 } else {
3650 image->bo = NULL;
3651 image->offset = 0;
3652 }
3653 }
3654 return VK_SUCCESS;
3655 }
3656
3657
3658 VkResult radv_BindImageMemory(
3659 VkDevice device,
3660 VkImage image,
3661 VkDeviceMemory memory,
3662 VkDeviceSize memoryOffset)
3663 {
3664 const VkBindImageMemoryInfo info = {
3665 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3666 .image = image,
3667 .memory = memory,
3668 .memoryOffset = memoryOffset
3669 };
3670
3671 return radv_BindImageMemory2(device, 1, &info);
3672 }
3673
3674
3675 static void
3676 radv_sparse_buffer_bind_memory(struct radv_device *device,
3677 const VkSparseBufferMemoryBindInfo *bind)
3678 {
3679 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3680
3681 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3682 struct radv_device_memory *mem = NULL;
3683
3684 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3685 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3686
3687 device->ws->buffer_virtual_bind(buffer->bo,
3688 bind->pBinds[i].resourceOffset,
3689 bind->pBinds[i].size,
3690 mem ? mem->bo : NULL,
3691 bind->pBinds[i].memoryOffset);
3692 }
3693 }
3694
3695 static void
3696 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3697 const VkSparseImageOpaqueMemoryBindInfo *bind)
3698 {
3699 RADV_FROM_HANDLE(radv_image, image, bind->image);
3700
3701 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3702 struct radv_device_memory *mem = NULL;
3703
3704 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3705 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3706
3707 device->ws->buffer_virtual_bind(image->bo,
3708 bind->pBinds[i].resourceOffset,
3709 bind->pBinds[i].size,
3710 mem ? mem->bo : NULL,
3711 bind->pBinds[i].memoryOffset);
3712 }
3713 }
3714
3715 VkResult radv_QueueBindSparse(
3716 VkQueue _queue,
3717 uint32_t bindInfoCount,
3718 const VkBindSparseInfo* pBindInfo,
3719 VkFence _fence)
3720 {
3721 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3722 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3723 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3724 bool fence_emitted = false;
3725 VkResult result;
3726 int ret;
3727
3728 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3729 struct radv_winsys_sem_info sem_info;
3730 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3731 radv_sparse_buffer_bind_memory(queue->device,
3732 pBindInfo[i].pBufferBinds + j);
3733 }
3734
3735 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3736 radv_sparse_image_opaque_bind_memory(queue->device,
3737 pBindInfo[i].pImageOpaqueBinds + j);
3738 }
3739
3740 VkResult result;
3741 result = radv_alloc_sem_info(queue->device->instance,
3742 &sem_info,
3743 pBindInfo[i].waitSemaphoreCount,
3744 pBindInfo[i].pWaitSemaphores,
3745 pBindInfo[i].signalSemaphoreCount,
3746 pBindInfo[i].pSignalSemaphores,
3747 _fence);
3748 if (result != VK_SUCCESS)
3749 return result;
3750
3751 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3752 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3753 &queue->device->empty_cs[queue->queue_family_index],
3754 1, NULL, NULL,
3755 &sem_info, NULL,
3756 false, base_fence);
3757 if (ret) {
3758 radv_loge("failed to submit CS %d\n", i);
3759 abort();
3760 }
3761
3762 fence_emitted = true;
3763 }
3764
3765 radv_free_sem_info(&sem_info);
3766
3767 }
3768
3769 if (fence) {
3770 if (!fence_emitted) {
3771 result = radv_signal_fence(queue, fence);
3772 if (result != VK_SUCCESS)
3773 return result;
3774 }
3775 }
3776
3777 return VK_SUCCESS;
3778 }
3779
3780 VkResult radv_CreateFence(
3781 VkDevice _device,
3782 const VkFenceCreateInfo* pCreateInfo,
3783 const VkAllocationCallbacks* pAllocator,
3784 VkFence* pFence)
3785 {
3786 RADV_FROM_HANDLE(radv_device, device, _device);
3787 const VkExportFenceCreateInfo *export =
3788 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3789 VkExternalFenceHandleTypeFlags handleTypes =
3790 export ? export->handleTypes : 0;
3791
3792 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3793 sizeof(*fence), 8,
3794 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3795
3796 if (!fence)
3797 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3798
3799 fence->fence_wsi = NULL;
3800 fence->temp_syncobj = 0;
3801 if (device->always_use_syncobj || handleTypes) {
3802 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3803 if (ret) {
3804 vk_free2(&device->alloc, pAllocator, fence);
3805 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3806 }
3807 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3808 device->ws->signal_syncobj(device->ws, fence->syncobj);
3809 }
3810 fence->fence = NULL;
3811 } else {
3812 fence->fence = device->ws->create_fence();
3813 if (!fence->fence) {
3814 vk_free2(&device->alloc, pAllocator, fence);
3815 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3816 }
3817 fence->syncobj = 0;
3818 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3819 device->ws->signal_fence(fence->fence);
3820 }
3821
3822 *pFence = radv_fence_to_handle(fence);
3823
3824 return VK_SUCCESS;
3825 }
3826
3827 void radv_DestroyFence(
3828 VkDevice _device,
3829 VkFence _fence,
3830 const VkAllocationCallbacks* pAllocator)
3831 {
3832 RADV_FROM_HANDLE(radv_device, device, _device);
3833 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3834
3835 if (!fence)
3836 return;
3837
3838 if (fence->temp_syncobj)
3839 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3840 if (fence->syncobj)
3841 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3842 if (fence->fence)
3843 device->ws->destroy_fence(fence->fence);
3844 if (fence->fence_wsi)
3845 fence->fence_wsi->destroy(fence->fence_wsi);
3846 vk_free2(&device->alloc, pAllocator, fence);
3847 }
3848
3849
3850 uint64_t radv_get_current_time(void)
3851 {
3852 struct timespec tv;
3853 clock_gettime(CLOCK_MONOTONIC, &tv);
3854 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3855 }
3856
3857 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3858 {
3859 uint64_t current_time = radv_get_current_time();
3860
3861 timeout = MIN2(UINT64_MAX - current_time, timeout);
3862
3863 return current_time + timeout;
3864 }
3865
3866
3867 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3868 uint32_t fenceCount, const VkFence *pFences)
3869 {
3870 for (uint32_t i = 0; i < fenceCount; ++i) {
3871 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3872 if (fence->fence == NULL || fence->syncobj ||
3873 fence->temp_syncobj || fence->fence_wsi ||
3874 (!device->ws->is_fence_waitable(fence->fence)))
3875 return false;
3876 }
3877 return true;
3878 }
3879
3880 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3881 {
3882 for (uint32_t i = 0; i < fenceCount; ++i) {
3883 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3884 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3885 return false;
3886 }
3887 return true;
3888 }
3889
3890 VkResult radv_WaitForFences(
3891 VkDevice _device,
3892 uint32_t fenceCount,
3893 const VkFence* pFences,
3894 VkBool32 waitAll,
3895 uint64_t timeout)
3896 {
3897 RADV_FROM_HANDLE(radv_device, device, _device);
3898 timeout = radv_get_absolute_timeout(timeout);
3899
3900 if (device->always_use_syncobj &&
3901 radv_all_fences_syncobj(fenceCount, pFences))
3902 {
3903 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3904 if (!handles)
3905 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3906
3907 for (uint32_t i = 0; i < fenceCount; ++i) {
3908 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3909 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3910 }
3911
3912 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3913
3914 free(handles);
3915 return success ? VK_SUCCESS : VK_TIMEOUT;
3916 }
3917
3918 if (!waitAll && fenceCount > 1) {
3919 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3920 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3921 uint32_t wait_count = 0;
3922 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3923 if (!fences)
3924 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3925
3926 for (uint32_t i = 0; i < fenceCount; ++i) {
3927 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3928
3929 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3930 free(fences);
3931 return VK_SUCCESS;
3932 }
3933
3934 fences[wait_count++] = fence->fence;
3935 }
3936
3937 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3938 waitAll, timeout - radv_get_current_time());
3939
3940 free(fences);
3941 return success ? VK_SUCCESS : VK_TIMEOUT;
3942 }
3943
3944 while(radv_get_current_time() <= timeout) {
3945 for (uint32_t i = 0; i < fenceCount; ++i) {
3946 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3947 return VK_SUCCESS;
3948 }
3949 }
3950 return VK_TIMEOUT;
3951 }
3952
3953 for (uint32_t i = 0; i < fenceCount; ++i) {
3954 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3955 bool expired = false;
3956
3957 if (fence->temp_syncobj) {
3958 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3959 return VK_TIMEOUT;
3960 continue;
3961 }
3962
3963 if (fence->syncobj) {
3964 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3965 return VK_TIMEOUT;
3966 continue;
3967 }
3968
3969 if (fence->fence) {
3970 if (!device->ws->is_fence_waitable(fence->fence)) {
3971 while(!device->ws->is_fence_waitable(fence->fence) &&
3972 radv_get_current_time() <= timeout)
3973 /* Do nothing */;
3974 }
3975
3976 expired = device->ws->fence_wait(device->ws,
3977 fence->fence,
3978 true, timeout);
3979 if (!expired)
3980 return VK_TIMEOUT;
3981 }
3982
3983 if (fence->fence_wsi) {
3984 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3985 if (result != VK_SUCCESS)
3986 return result;
3987 }
3988 }
3989
3990 return VK_SUCCESS;
3991 }
3992
3993 VkResult radv_ResetFences(VkDevice _device,
3994 uint32_t fenceCount,
3995 const VkFence *pFences)
3996 {
3997 RADV_FROM_HANDLE(radv_device, device, _device);
3998
3999 for (unsigned i = 0; i < fenceCount; ++i) {
4000 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4001 if (fence->fence)
4002 device->ws->reset_fence(fence->fence);
4003
4004 /* Per spec, we first restore the permanent payload, and then reset, so
4005 * having a temp syncobj should not skip resetting the permanent syncobj. */
4006 if (fence->temp_syncobj) {
4007 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4008 fence->temp_syncobj = 0;
4009 }
4010
4011 if (fence->syncobj) {
4012 device->ws->reset_syncobj(device->ws, fence->syncobj);
4013 }
4014 }
4015
4016 return VK_SUCCESS;
4017 }
4018
4019 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4020 {
4021 RADV_FROM_HANDLE(radv_device, device, _device);
4022 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4023
4024 if (fence->temp_syncobj) {
4025 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4026 return success ? VK_SUCCESS : VK_NOT_READY;
4027 }
4028
4029 if (fence->syncobj) {
4030 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4031 return success ? VK_SUCCESS : VK_NOT_READY;
4032 }
4033
4034 if (fence->fence) {
4035 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4036 return VK_NOT_READY;
4037 }
4038 if (fence->fence_wsi) {
4039 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4040
4041 if (result != VK_SUCCESS) {
4042 if (result == VK_TIMEOUT)
4043 return VK_NOT_READY;
4044 return result;
4045 }
4046 }
4047 return VK_SUCCESS;
4048 }
4049
4050
4051 // Queue semaphore functions
4052
4053 VkResult radv_CreateSemaphore(
4054 VkDevice _device,
4055 const VkSemaphoreCreateInfo* pCreateInfo,
4056 const VkAllocationCallbacks* pAllocator,
4057 VkSemaphore* pSemaphore)
4058 {
4059 RADV_FROM_HANDLE(radv_device, device, _device);
4060 const VkExportSemaphoreCreateInfo *export =
4061 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4062 VkExternalSemaphoreHandleTypeFlags handleTypes =
4063 export ? export->handleTypes : 0;
4064
4065 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4066 sizeof(*sem), 8,
4067 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4068 if (!sem)
4069 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4070
4071 sem->temp_syncobj = 0;
4072 /* create a syncobject if we are going to export this semaphore */
4073 if (device->always_use_syncobj || handleTypes) {
4074 assert (device->physical_device->rad_info.has_syncobj);
4075 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4076 if (ret) {
4077 vk_free2(&device->alloc, pAllocator, sem);
4078 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4079 }
4080 sem->sem = NULL;
4081 } else {
4082 sem->sem = device->ws->create_sem(device->ws);
4083 if (!sem->sem) {
4084 vk_free2(&device->alloc, pAllocator, sem);
4085 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4086 }
4087 sem->syncobj = 0;
4088 }
4089
4090 *pSemaphore = radv_semaphore_to_handle(sem);
4091 return VK_SUCCESS;
4092 }
4093
4094 void radv_DestroySemaphore(
4095 VkDevice _device,
4096 VkSemaphore _semaphore,
4097 const VkAllocationCallbacks* pAllocator)
4098 {
4099 RADV_FROM_HANDLE(radv_device, device, _device);
4100 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4101 if (!_semaphore)
4102 return;
4103
4104 if (sem->syncobj)
4105 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4106 else
4107 device->ws->destroy_sem(sem->sem);
4108 vk_free2(&device->alloc, pAllocator, sem);
4109 }
4110
4111 VkResult radv_CreateEvent(
4112 VkDevice _device,
4113 const VkEventCreateInfo* pCreateInfo,
4114 const VkAllocationCallbacks* pAllocator,
4115 VkEvent* pEvent)
4116 {
4117 RADV_FROM_HANDLE(radv_device, device, _device);
4118 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4119 sizeof(*event), 8,
4120 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4121
4122 if (!event)
4123 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4124
4125 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4126 RADEON_DOMAIN_GTT,
4127 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4128 RADV_BO_PRIORITY_FENCE);
4129 if (!event->bo) {
4130 vk_free2(&device->alloc, pAllocator, event);
4131 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4132 }
4133
4134 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4135
4136 *pEvent = radv_event_to_handle(event);
4137
4138 return VK_SUCCESS;
4139 }
4140
4141 void radv_DestroyEvent(
4142 VkDevice _device,
4143 VkEvent _event,
4144 const VkAllocationCallbacks* pAllocator)
4145 {
4146 RADV_FROM_HANDLE(radv_device, device, _device);
4147 RADV_FROM_HANDLE(radv_event, event, _event);
4148
4149 if (!event)
4150 return;
4151 device->ws->buffer_destroy(event->bo);
4152 vk_free2(&device->alloc, pAllocator, event);
4153 }
4154
4155 VkResult radv_GetEventStatus(
4156 VkDevice _device,
4157 VkEvent _event)
4158 {
4159 RADV_FROM_HANDLE(radv_event, event, _event);
4160
4161 if (*event->map == 1)
4162 return VK_EVENT_SET;
4163 return VK_EVENT_RESET;
4164 }
4165
4166 VkResult radv_SetEvent(
4167 VkDevice _device,
4168 VkEvent _event)
4169 {
4170 RADV_FROM_HANDLE(radv_event, event, _event);
4171 *event->map = 1;
4172
4173 return VK_SUCCESS;
4174 }
4175
4176 VkResult radv_ResetEvent(
4177 VkDevice _device,
4178 VkEvent _event)
4179 {
4180 RADV_FROM_HANDLE(radv_event, event, _event);
4181 *event->map = 0;
4182
4183 return VK_SUCCESS;
4184 }
4185
4186 VkResult radv_CreateBuffer(
4187 VkDevice _device,
4188 const VkBufferCreateInfo* pCreateInfo,
4189 const VkAllocationCallbacks* pAllocator,
4190 VkBuffer* pBuffer)
4191 {
4192 RADV_FROM_HANDLE(radv_device, device, _device);
4193 struct radv_buffer *buffer;
4194
4195 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4196
4197 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4198 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4199 if (buffer == NULL)
4200 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4201
4202 buffer->size = pCreateInfo->size;
4203 buffer->usage = pCreateInfo->usage;
4204 buffer->bo = NULL;
4205 buffer->offset = 0;
4206 buffer->flags = pCreateInfo->flags;
4207
4208 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4209 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4210
4211 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4212 buffer->bo = device->ws->buffer_create(device->ws,
4213 align64(buffer->size, 4096),
4214 4096, 0, RADEON_FLAG_VIRTUAL,
4215 RADV_BO_PRIORITY_VIRTUAL);
4216 if (!buffer->bo) {
4217 vk_free2(&device->alloc, pAllocator, buffer);
4218 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4219 }
4220 }
4221
4222 *pBuffer = radv_buffer_to_handle(buffer);
4223
4224 return VK_SUCCESS;
4225 }
4226
4227 void radv_DestroyBuffer(
4228 VkDevice _device,
4229 VkBuffer _buffer,
4230 const VkAllocationCallbacks* pAllocator)
4231 {
4232 RADV_FROM_HANDLE(radv_device, device, _device);
4233 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4234
4235 if (!buffer)
4236 return;
4237
4238 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4239 device->ws->buffer_destroy(buffer->bo);
4240
4241 vk_free2(&device->alloc, pAllocator, buffer);
4242 }
4243
4244 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4245 VkDevice device,
4246 const VkBufferDeviceAddressInfoEXT* pInfo)
4247 {
4248 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4249 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4250 }
4251
4252
4253 static inline unsigned
4254 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4255 {
4256 if (stencil)
4257 return plane->surface.u.legacy.stencil_tiling_index[level];
4258 else
4259 return plane->surface.u.legacy.tiling_index[level];
4260 }
4261
4262 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4263 {
4264 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4265 }
4266
4267 static uint32_t
4268 radv_init_dcc_control_reg(struct radv_device *device,
4269 struct radv_image_view *iview)
4270 {
4271 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4272 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4273 unsigned max_compressed_block_size;
4274 unsigned independent_128b_blocks;
4275 unsigned independent_64b_blocks;
4276
4277 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4278 return 0;
4279
4280 if (!device->physical_device->rad_info.has_dedicated_vram) {
4281 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4282 * dGPU and 64 for APU because all of our APUs to date use
4283 * DIMMs which have a request granularity size of 64B while all
4284 * other chips have a 32B request size.
4285 */
4286 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4287 }
4288
4289 if (device->physical_device->rad_info.chip_class >= GFX10) {
4290 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4291 independent_64b_blocks = 0;
4292 independent_128b_blocks = 1;
4293 } else {
4294 independent_128b_blocks = 0;
4295
4296 if (iview->image->info.samples > 1) {
4297 if (iview->image->planes[0].surface.bpe == 1)
4298 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4299 else if (iview->image->planes[0].surface.bpe == 2)
4300 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4301 }
4302
4303 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4304 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4305 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4306 /* If this DCC image is potentially going to be used in texture
4307 * fetches, we need some special settings.
4308 */
4309 independent_64b_blocks = 1;
4310 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4311 } else {
4312 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4313 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4314 * big as possible for better compression state.
4315 */
4316 independent_64b_blocks = 0;
4317 max_compressed_block_size = max_uncompressed_block_size;
4318 }
4319 }
4320
4321 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4322 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4323 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4324 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4325 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4326 }
4327
4328 static void
4329 radv_initialise_color_surface(struct radv_device *device,
4330 struct radv_color_buffer_info *cb,
4331 struct radv_image_view *iview)
4332 {
4333 const struct vk_format_description *desc;
4334 unsigned ntype, format, swap, endian;
4335 unsigned blend_clamp = 0, blend_bypass = 0;
4336 uint64_t va;
4337 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4338 const struct radeon_surf *surf = &plane->surface;
4339
4340 desc = vk_format_description(iview->vk_format);
4341
4342 memset(cb, 0, sizeof(*cb));
4343
4344 /* Intensity is implemented as Red, so treat it that way. */
4345 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4346
4347 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4348
4349 cb->cb_color_base = va >> 8;
4350
4351 if (device->physical_device->rad_info.chip_class >= GFX9) {
4352 struct gfx9_surf_meta_flags meta;
4353 if (iview->image->dcc_offset)
4354 meta = surf->u.gfx9.dcc;
4355 else
4356 meta = surf->u.gfx9.cmask;
4357
4358 if (device->physical_device->rad_info.chip_class >= GFX10) {
4359 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4360 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4361 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4362 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4363 } else {
4364 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4365 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4366 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4367 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4368 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4369 }
4370
4371 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4372 cb->cb_color_base |= surf->tile_swizzle;
4373 } else {
4374 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4375 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4376
4377 cb->cb_color_base += level_info->offset >> 8;
4378 if (level_info->mode == RADEON_SURF_MODE_2D)
4379 cb->cb_color_base |= surf->tile_swizzle;
4380
4381 pitch_tile_max = level_info->nblk_x / 8 - 1;
4382 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4383 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4384
4385 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4386 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4387 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4388
4389 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4390
4391 if (radv_image_has_fmask(iview->image)) {
4392 if (device->physical_device->rad_info.chip_class >= GFX7)
4393 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4394 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4395 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4396 } else {
4397 /* This must be set for fast clear to work without FMASK. */
4398 if (device->physical_device->rad_info.chip_class >= GFX7)
4399 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4400 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4401 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4402 }
4403 }
4404
4405 /* CMASK variables */
4406 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4407 va += iview->image->cmask.offset;
4408 cb->cb_color_cmask = va >> 8;
4409
4410 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4411 va += iview->image->dcc_offset;
4412
4413 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4414 device->physical_device->rad_info.chip_class <= GFX8)
4415 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4416
4417 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4418 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4419
4420 cb->cb_dcc_base = va >> 8;
4421 cb->cb_dcc_base |= dcc_tile_swizzle;
4422
4423 /* GFX10 field has the same base shift as the GFX6 field. */
4424 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4425 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4426 S_028C6C_SLICE_MAX_GFX10(max_slice);
4427
4428 if (iview->image->info.samples > 1) {
4429 unsigned log_samples = util_logbase2(iview->image->info.samples);
4430
4431 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4432 S_028C74_NUM_FRAGMENTS(log_samples);
4433 }
4434
4435 if (radv_image_has_fmask(iview->image)) {
4436 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4437 cb->cb_color_fmask = va >> 8;
4438 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4439 } else {
4440 cb->cb_color_fmask = cb->cb_color_base;
4441 }
4442
4443 ntype = radv_translate_color_numformat(iview->vk_format,
4444 desc,
4445 vk_format_get_first_non_void_channel(iview->vk_format));
4446 format = radv_translate_colorformat(iview->vk_format);
4447 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4448 radv_finishme("Illegal color\n");
4449 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4450 endian = radv_colorformat_endian_swap(format);
4451
4452 /* blend clamp should be set for all NORM/SRGB types */
4453 if (ntype == V_028C70_NUMBER_UNORM ||
4454 ntype == V_028C70_NUMBER_SNORM ||
4455 ntype == V_028C70_NUMBER_SRGB)
4456 blend_clamp = 1;
4457
4458 /* set blend bypass according to docs if SINT/UINT or
4459 8/24 COLOR variants */
4460 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4461 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4462 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4463 blend_clamp = 0;
4464 blend_bypass = 1;
4465 }
4466 #if 0
4467 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4468 (format == V_028C70_COLOR_8 ||
4469 format == V_028C70_COLOR_8_8 ||
4470 format == V_028C70_COLOR_8_8_8_8))
4471 ->color_is_int8 = true;
4472 #endif
4473 cb->cb_color_info = S_028C70_FORMAT(format) |
4474 S_028C70_COMP_SWAP(swap) |
4475 S_028C70_BLEND_CLAMP(blend_clamp) |
4476 S_028C70_BLEND_BYPASS(blend_bypass) |
4477 S_028C70_SIMPLE_FLOAT(1) |
4478 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4479 ntype != V_028C70_NUMBER_SNORM &&
4480 ntype != V_028C70_NUMBER_SRGB &&
4481 format != V_028C70_COLOR_8_24 &&
4482 format != V_028C70_COLOR_24_8) |
4483 S_028C70_NUMBER_TYPE(ntype) |
4484 S_028C70_ENDIAN(endian);
4485 if (radv_image_has_fmask(iview->image)) {
4486 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4487 if (device->physical_device->rad_info.chip_class == GFX6) {
4488 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4489 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4490 }
4491
4492 if (radv_image_is_tc_compat_cmask(iview->image)) {
4493 /* Allow the texture block to read FMASK directly
4494 * without decompressing it. This bit must be cleared
4495 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4496 * otherwise the operation doesn't happen.
4497 */
4498 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4499
4500 /* Set CMASK into a tiling format that allows the
4501 * texture block to read it.
4502 */
4503 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4504 }
4505 }
4506
4507 if (radv_image_has_cmask(iview->image) &&
4508 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4509 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4510
4511 if (radv_dcc_enabled(iview->image, iview->base_mip))
4512 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4513
4514 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4515
4516 /* This must be set for fast clear to work without FMASK. */
4517 if (!radv_image_has_fmask(iview->image) &&
4518 device->physical_device->rad_info.chip_class == GFX6) {
4519 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4520 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4521 }
4522
4523 if (device->physical_device->rad_info.chip_class >= GFX9) {
4524 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4525
4526 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4527 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4528 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4529 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4530
4531 if (device->physical_device->rad_info.chip_class >= GFX10) {
4532 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4533
4534 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4535 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4536 S_028EE0_RESOURCE_LEVEL(1);
4537 } else {
4538 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4539 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4540 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4541 }
4542
4543 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4544 S_028C68_MIP0_HEIGHT(height - 1) |
4545 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4546 }
4547 }
4548
4549 static unsigned
4550 radv_calc_decompress_on_z_planes(struct radv_device *device,
4551 struct radv_image_view *iview)
4552 {
4553 unsigned max_zplanes = 0;
4554
4555 assert(radv_image_is_tc_compat_htile(iview->image));
4556
4557 if (device->physical_device->rad_info.chip_class >= GFX9) {
4558 /* Default value for 32-bit depth surfaces. */
4559 max_zplanes = 4;
4560
4561 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4562 iview->image->info.samples > 1)
4563 max_zplanes = 2;
4564
4565 max_zplanes = max_zplanes + 1;
4566 } else {
4567 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4568 /* Do not enable Z plane compression for 16-bit depth
4569 * surfaces because isn't supported on GFX8. Only
4570 * 32-bit depth surfaces are supported by the hardware.
4571 * This allows to maintain shader compatibility and to
4572 * reduce the number of depth decompressions.
4573 */
4574 max_zplanes = 1;
4575 } else {
4576 if (iview->image->info.samples <= 1)
4577 max_zplanes = 5;
4578 else if (iview->image->info.samples <= 4)
4579 max_zplanes = 3;
4580 else
4581 max_zplanes = 2;
4582 }
4583 }
4584
4585 return max_zplanes;
4586 }
4587
4588 static void
4589 radv_initialise_ds_surface(struct radv_device *device,
4590 struct radv_ds_buffer_info *ds,
4591 struct radv_image_view *iview)
4592 {
4593 unsigned level = iview->base_mip;
4594 unsigned format, stencil_format;
4595 uint64_t va, s_offs, z_offs;
4596 bool stencil_only = false;
4597 const struct radv_image_plane *plane = &iview->image->planes[0];
4598 const struct radeon_surf *surf = &plane->surface;
4599
4600 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4601
4602 memset(ds, 0, sizeof(*ds));
4603 switch (iview->image->vk_format) {
4604 case VK_FORMAT_D24_UNORM_S8_UINT:
4605 case VK_FORMAT_X8_D24_UNORM_PACK32:
4606 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4607 ds->offset_scale = 2.0f;
4608 break;
4609 case VK_FORMAT_D16_UNORM:
4610 case VK_FORMAT_D16_UNORM_S8_UINT:
4611 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4612 ds->offset_scale = 4.0f;
4613 break;
4614 case VK_FORMAT_D32_SFLOAT:
4615 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4616 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4617 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4618 ds->offset_scale = 1.0f;
4619 break;
4620 case VK_FORMAT_S8_UINT:
4621 stencil_only = true;
4622 break;
4623 default:
4624 break;
4625 }
4626
4627 format = radv_translate_dbformat(iview->image->vk_format);
4628 stencil_format = surf->has_stencil ?
4629 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4630
4631 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4632 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4633 S_028008_SLICE_MAX(max_slice);
4634 if (device->physical_device->rad_info.chip_class >= GFX10) {
4635 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4636 S_028008_SLICE_MAX_HI(max_slice >> 11);
4637 }
4638
4639 ds->db_htile_data_base = 0;
4640 ds->db_htile_surface = 0;
4641
4642 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4643 s_offs = z_offs = va;
4644
4645 if (device->physical_device->rad_info.chip_class >= GFX9) {
4646 assert(surf->u.gfx9.surf_offset == 0);
4647 s_offs += surf->u.gfx9.stencil_offset;
4648
4649 ds->db_z_info = S_028038_FORMAT(format) |
4650 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4651 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4652 S_028038_MAXMIP(iview->image->info.levels - 1) |
4653 S_028038_ZRANGE_PRECISION(1);
4654 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4655 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4656
4657 if (device->physical_device->rad_info.chip_class == GFX9) {
4658 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4659 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4660 }
4661
4662 ds->db_depth_view |= S_028008_MIPID(level);
4663 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4664 S_02801C_Y_MAX(iview->image->info.height - 1);
4665
4666 if (radv_htile_enabled(iview->image, level)) {
4667 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4668
4669 if (radv_image_is_tc_compat_htile(iview->image)) {
4670 unsigned max_zplanes =
4671 radv_calc_decompress_on_z_planes(device, iview);
4672
4673 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4674
4675 if (device->physical_device->rad_info.chip_class >= GFX10) {
4676 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4677 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4678 } else {
4679 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4680 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4681 }
4682 }
4683
4684 if (!surf->has_stencil)
4685 /* Use all of the htile_buffer for depth if there's no stencil. */
4686 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4687 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4688 iview->image->htile_offset;
4689 ds->db_htile_data_base = va >> 8;
4690 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4691 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4692
4693 if (device->physical_device->rad_info.chip_class == GFX9) {
4694 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4695 }
4696 }
4697 } else {
4698 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4699
4700 if (stencil_only)
4701 level_info = &surf->u.legacy.stencil_level[level];
4702
4703 z_offs += surf->u.legacy.level[level].offset;
4704 s_offs += surf->u.legacy.stencil_level[level].offset;
4705
4706 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4707 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4708 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4709
4710 if (iview->image->info.samples > 1)
4711 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4712
4713 if (device->physical_device->rad_info.chip_class >= GFX7) {
4714 struct radeon_info *info = &device->physical_device->rad_info;
4715 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4716 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4717 unsigned macro_index = surf->u.legacy.macro_tile_index;
4718 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4719 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4720 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4721
4722 if (stencil_only)
4723 tile_mode = stencil_tile_mode;
4724
4725 ds->db_depth_info |=
4726 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4727 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4728 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4729 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4730 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4731 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4732 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4733 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4734 } else {
4735 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4736 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4737 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4738 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4739 if (stencil_only)
4740 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4741 }
4742
4743 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4744 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4745 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4746
4747 if (radv_htile_enabled(iview->image, level)) {
4748 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4749
4750 if (!surf->has_stencil &&
4751 !radv_image_is_tc_compat_htile(iview->image))
4752 /* Use all of the htile_buffer for depth if there's no stencil. */
4753 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4754
4755 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4756 iview->image->htile_offset;
4757 ds->db_htile_data_base = va >> 8;
4758 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4759
4760 if (radv_image_is_tc_compat_htile(iview->image)) {
4761 unsigned max_zplanes =
4762 radv_calc_decompress_on_z_planes(device, iview);
4763
4764 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4765 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4766 }
4767 }
4768 }
4769
4770 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4771 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4772 }
4773
4774 VkResult radv_CreateFramebuffer(
4775 VkDevice _device,
4776 const VkFramebufferCreateInfo* pCreateInfo,
4777 const VkAllocationCallbacks* pAllocator,
4778 VkFramebuffer* pFramebuffer)
4779 {
4780 RADV_FROM_HANDLE(radv_device, device, _device);
4781 struct radv_framebuffer *framebuffer;
4782
4783 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4784
4785 size_t size = sizeof(*framebuffer) +
4786 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4787 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4788 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4789 if (framebuffer == NULL)
4790 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4791
4792 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4793 framebuffer->width = pCreateInfo->width;
4794 framebuffer->height = pCreateInfo->height;
4795 framebuffer->layers = pCreateInfo->layers;
4796 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4797 VkImageView _iview = pCreateInfo->pAttachments[i];
4798 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4799 framebuffer->attachments[i].attachment = iview;
4800 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4801 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4802 } else {
4803 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4804 }
4805 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4806 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4807 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4808 }
4809
4810 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4811 return VK_SUCCESS;
4812 }
4813
4814 void radv_DestroyFramebuffer(
4815 VkDevice _device,
4816 VkFramebuffer _fb,
4817 const VkAllocationCallbacks* pAllocator)
4818 {
4819 RADV_FROM_HANDLE(radv_device, device, _device);
4820 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4821
4822 if (!fb)
4823 return;
4824 vk_free2(&device->alloc, pAllocator, fb);
4825 }
4826
4827 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4828 {
4829 switch (address_mode) {
4830 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4831 return V_008F30_SQ_TEX_WRAP;
4832 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4833 return V_008F30_SQ_TEX_MIRROR;
4834 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4835 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4836 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4837 return V_008F30_SQ_TEX_CLAMP_BORDER;
4838 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4839 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4840 default:
4841 unreachable("illegal tex wrap mode");
4842 break;
4843 }
4844 }
4845
4846 static unsigned
4847 radv_tex_compare(VkCompareOp op)
4848 {
4849 switch (op) {
4850 case VK_COMPARE_OP_NEVER:
4851 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4852 case VK_COMPARE_OP_LESS:
4853 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4854 case VK_COMPARE_OP_EQUAL:
4855 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4856 case VK_COMPARE_OP_LESS_OR_EQUAL:
4857 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4858 case VK_COMPARE_OP_GREATER:
4859 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4860 case VK_COMPARE_OP_NOT_EQUAL:
4861 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4862 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4863 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4864 case VK_COMPARE_OP_ALWAYS:
4865 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4866 default:
4867 unreachable("illegal compare mode");
4868 break;
4869 }
4870 }
4871
4872 static unsigned
4873 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4874 {
4875 switch (filter) {
4876 case VK_FILTER_NEAREST:
4877 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4878 V_008F38_SQ_TEX_XY_FILTER_POINT);
4879 case VK_FILTER_LINEAR:
4880 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4881 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4882 case VK_FILTER_CUBIC_IMG:
4883 default:
4884 fprintf(stderr, "illegal texture filter");
4885 return 0;
4886 }
4887 }
4888
4889 static unsigned
4890 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4891 {
4892 switch (mode) {
4893 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4894 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4895 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4896 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4897 default:
4898 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4899 }
4900 }
4901
4902 static unsigned
4903 radv_tex_bordercolor(VkBorderColor bcolor)
4904 {
4905 switch (bcolor) {
4906 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4907 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4908 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4909 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4910 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4911 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4912 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4913 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4914 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4915 default:
4916 break;
4917 }
4918 return 0;
4919 }
4920
4921 static unsigned
4922 radv_tex_aniso_filter(unsigned filter)
4923 {
4924 if (filter < 2)
4925 return 0;
4926 if (filter < 4)
4927 return 1;
4928 if (filter < 8)
4929 return 2;
4930 if (filter < 16)
4931 return 3;
4932 return 4;
4933 }
4934
4935 static unsigned
4936 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4937 {
4938 switch (mode) {
4939 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4940 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4941 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4942 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4943 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4944 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4945 default:
4946 break;
4947 }
4948 return 0;
4949 }
4950
4951 static uint32_t
4952 radv_get_max_anisotropy(struct radv_device *device,
4953 const VkSamplerCreateInfo *pCreateInfo)
4954 {
4955 if (device->force_aniso >= 0)
4956 return device->force_aniso;
4957
4958 if (pCreateInfo->anisotropyEnable &&
4959 pCreateInfo->maxAnisotropy > 1.0f)
4960 return (uint32_t)pCreateInfo->maxAnisotropy;
4961
4962 return 0;
4963 }
4964
4965 static void
4966 radv_init_sampler(struct radv_device *device,
4967 struct radv_sampler *sampler,
4968 const VkSamplerCreateInfo *pCreateInfo)
4969 {
4970 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4971 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4972 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4973 device->physical_device->rad_info.chip_class == GFX9;
4974 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4975
4976 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4977 vk_find_struct_const(pCreateInfo->pNext,
4978 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4979 if (sampler_reduction)
4980 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4981
4982 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4983 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4984 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4985 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4986 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4987 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4988 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4989 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4990 S_008F30_DISABLE_CUBE_WRAP(0) |
4991 S_008F30_COMPAT_MODE(compat_mode) |
4992 S_008F30_FILTER_MODE(filter_mode));
4993 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4994 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4995 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4996 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4997 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4998 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4999 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5000 S_008F38_MIP_POINT_PRECLAMP(0));
5001 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5002 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5003
5004 if (device->physical_device->rad_info.chip_class >= GFX10) {
5005 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5006 } else {
5007 sampler->state[2] |=
5008 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5009 S_008F38_FILTER_PREC_FIX(1) |
5010 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5011 }
5012 }
5013
5014 VkResult radv_CreateSampler(
5015 VkDevice _device,
5016 const VkSamplerCreateInfo* pCreateInfo,
5017 const VkAllocationCallbacks* pAllocator,
5018 VkSampler* pSampler)
5019 {
5020 RADV_FROM_HANDLE(radv_device, device, _device);
5021 struct radv_sampler *sampler;
5022
5023 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5024 vk_find_struct_const(pCreateInfo->pNext,
5025 SAMPLER_YCBCR_CONVERSION_INFO);
5026
5027 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5028
5029 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5030 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5031 if (!sampler)
5032 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5033
5034 radv_init_sampler(device, sampler, pCreateInfo);
5035
5036 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5037 *pSampler = radv_sampler_to_handle(sampler);
5038
5039 return VK_SUCCESS;
5040 }
5041
5042 void radv_DestroySampler(
5043 VkDevice _device,
5044 VkSampler _sampler,
5045 const VkAllocationCallbacks* pAllocator)
5046 {
5047 RADV_FROM_HANDLE(radv_device, device, _device);
5048 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5049
5050 if (!sampler)
5051 return;
5052 vk_free2(&device->alloc, pAllocator, sampler);
5053 }
5054
5055 /* vk_icd.h does not declare this function, so we declare it here to
5056 * suppress Wmissing-prototypes.
5057 */
5058 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5059 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5060
5061 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5062 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5063 {
5064 /* For the full details on loader interface versioning, see
5065 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5066 * What follows is a condensed summary, to help you navigate the large and
5067 * confusing official doc.
5068 *
5069 * - Loader interface v0 is incompatible with later versions. We don't
5070 * support it.
5071 *
5072 * - In loader interface v1:
5073 * - The first ICD entrypoint called by the loader is
5074 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5075 * entrypoint.
5076 * - The ICD must statically expose no other Vulkan symbol unless it is
5077 * linked with -Bsymbolic.
5078 * - Each dispatchable Vulkan handle created by the ICD must be
5079 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5080 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5081 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5082 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5083 * such loader-managed surfaces.
5084 *
5085 * - Loader interface v2 differs from v1 in:
5086 * - The first ICD entrypoint called by the loader is
5087 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5088 * statically expose this entrypoint.
5089 *
5090 * - Loader interface v3 differs from v2 in:
5091 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5092 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5093 * because the loader no longer does so.
5094 */
5095 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5096 return VK_SUCCESS;
5097 }
5098
5099 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5100 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5101 int *pFD)
5102 {
5103 RADV_FROM_HANDLE(radv_device, device, _device);
5104 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5105
5106 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5107
5108 /* At the moment, we support only the below handle types. */
5109 assert(pGetFdInfo->handleType ==
5110 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5111 pGetFdInfo->handleType ==
5112 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5113
5114 bool ret = radv_get_memory_fd(device, memory, pFD);
5115 if (ret == false)
5116 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5117 return VK_SUCCESS;
5118 }
5119
5120 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5121 VkExternalMemoryHandleTypeFlagBits handleType,
5122 int fd,
5123 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5124 {
5125 RADV_FROM_HANDLE(radv_device, device, _device);
5126
5127 switch (handleType) {
5128 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5129 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5130 return VK_SUCCESS;
5131
5132 default:
5133 /* The valid usage section for this function says:
5134 *
5135 * "handleType must not be one of the handle types defined as
5136 * opaque."
5137 *
5138 * So opaque handle types fall into the default "unsupported" case.
5139 */
5140 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5141 }
5142 }
5143
5144 static VkResult radv_import_opaque_fd(struct radv_device *device,
5145 int fd,
5146 uint32_t *syncobj)
5147 {
5148 uint32_t syncobj_handle = 0;
5149 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5150 if (ret != 0)
5151 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5152
5153 if (*syncobj)
5154 device->ws->destroy_syncobj(device->ws, *syncobj);
5155
5156 *syncobj = syncobj_handle;
5157 close(fd);
5158
5159 return VK_SUCCESS;
5160 }
5161
5162 static VkResult radv_import_sync_fd(struct radv_device *device,
5163 int fd,
5164 uint32_t *syncobj)
5165 {
5166 /* If we create a syncobj we do it locally so that if we have an error, we don't
5167 * leave a syncobj in an undetermined state in the fence. */
5168 uint32_t syncobj_handle = *syncobj;
5169 if (!syncobj_handle) {
5170 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5171 if (ret) {
5172 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5173 }
5174 }
5175
5176 if (fd == -1) {
5177 device->ws->signal_syncobj(device->ws, syncobj_handle);
5178 } else {
5179 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5180 if (ret != 0)
5181 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5182 }
5183
5184 *syncobj = syncobj_handle;
5185 if (fd != -1)
5186 close(fd);
5187
5188 return VK_SUCCESS;
5189 }
5190
5191 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5192 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5193 {
5194 RADV_FROM_HANDLE(radv_device, device, _device);
5195 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5196 uint32_t *syncobj_dst = NULL;
5197
5198 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5199 syncobj_dst = &sem->temp_syncobj;
5200 } else {
5201 syncobj_dst = &sem->syncobj;
5202 }
5203
5204 switch(pImportSemaphoreFdInfo->handleType) {
5205 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5206 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5207 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5208 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5209 default:
5210 unreachable("Unhandled semaphore handle type");
5211 }
5212 }
5213
5214 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5215 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5216 int *pFd)
5217 {
5218 RADV_FROM_HANDLE(radv_device, device, _device);
5219 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5220 int ret;
5221 uint32_t syncobj_handle;
5222
5223 if (sem->temp_syncobj)
5224 syncobj_handle = sem->temp_syncobj;
5225 else
5226 syncobj_handle = sem->syncobj;
5227
5228 switch(pGetFdInfo->handleType) {
5229 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5230 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5231 break;
5232 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5233 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5234 if (!ret) {
5235 if (sem->temp_syncobj) {
5236 close (sem->temp_syncobj);
5237 sem->temp_syncobj = 0;
5238 } else {
5239 device->ws->reset_syncobj(device->ws, syncobj_handle);
5240 }
5241 }
5242 break;
5243 default:
5244 unreachable("Unhandled semaphore handle type");
5245 }
5246
5247 if (ret)
5248 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5249 return VK_SUCCESS;
5250 }
5251
5252 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5253 VkPhysicalDevice physicalDevice,
5254 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5255 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5256 {
5257 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5258
5259 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5260 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5261 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5262 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5263 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5264 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5265 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5266 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5267 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5268 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5269 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5270 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5271 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5272 } else {
5273 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5274 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5275 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5276 }
5277 }
5278
5279 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5280 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5281 {
5282 RADV_FROM_HANDLE(radv_device, device, _device);
5283 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5284 uint32_t *syncobj_dst = NULL;
5285
5286
5287 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5288 syncobj_dst = &fence->temp_syncobj;
5289 } else {
5290 syncobj_dst = &fence->syncobj;
5291 }
5292
5293 switch(pImportFenceFdInfo->handleType) {
5294 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5295 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5296 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5297 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5298 default:
5299 unreachable("Unhandled fence handle type");
5300 }
5301 }
5302
5303 VkResult radv_GetFenceFdKHR(VkDevice _device,
5304 const VkFenceGetFdInfoKHR *pGetFdInfo,
5305 int *pFd)
5306 {
5307 RADV_FROM_HANDLE(radv_device, device, _device);
5308 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5309 int ret;
5310 uint32_t syncobj_handle;
5311
5312 if (fence->temp_syncobj)
5313 syncobj_handle = fence->temp_syncobj;
5314 else
5315 syncobj_handle = fence->syncobj;
5316
5317 switch(pGetFdInfo->handleType) {
5318 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5319 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5320 break;
5321 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5322 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5323 if (!ret) {
5324 if (fence->temp_syncobj) {
5325 close (fence->temp_syncobj);
5326 fence->temp_syncobj = 0;
5327 } else {
5328 device->ws->reset_syncobj(device->ws, syncobj_handle);
5329 }
5330 }
5331 break;
5332 default:
5333 unreachable("Unhandled fence handle type");
5334 }
5335
5336 if (ret)
5337 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5338 return VK_SUCCESS;
5339 }
5340
5341 void radv_GetPhysicalDeviceExternalFenceProperties(
5342 VkPhysicalDevice physicalDevice,
5343 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5344 VkExternalFenceProperties *pExternalFenceProperties)
5345 {
5346 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5347
5348 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5349 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5350 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5351 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5352 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5353 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5354 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5355 } else {
5356 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5357 pExternalFenceProperties->compatibleHandleTypes = 0;
5358 pExternalFenceProperties->externalFenceFeatures = 0;
5359 }
5360 }
5361
5362 VkResult
5363 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5364 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5365 const VkAllocationCallbacks* pAllocator,
5366 VkDebugReportCallbackEXT* pCallback)
5367 {
5368 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5369 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5370 pCreateInfo, pAllocator, &instance->alloc,
5371 pCallback);
5372 }
5373
5374 void
5375 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5376 VkDebugReportCallbackEXT _callback,
5377 const VkAllocationCallbacks* pAllocator)
5378 {
5379 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5380 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5381 _callback, pAllocator, &instance->alloc);
5382 }
5383
5384 void
5385 radv_DebugReportMessageEXT(VkInstance _instance,
5386 VkDebugReportFlagsEXT flags,
5387 VkDebugReportObjectTypeEXT objectType,
5388 uint64_t object,
5389 size_t location,
5390 int32_t messageCode,
5391 const char* pLayerPrefix,
5392 const char* pMessage)
5393 {
5394 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5395 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5396 object, location, messageCode, pLayerPrefix, pMessage);
5397 }
5398
5399 void
5400 radv_GetDeviceGroupPeerMemoryFeatures(
5401 VkDevice device,
5402 uint32_t heapIndex,
5403 uint32_t localDeviceIndex,
5404 uint32_t remoteDeviceIndex,
5405 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5406 {
5407 assert(localDeviceIndex == remoteDeviceIndex);
5408
5409 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5410 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5411 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5412 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5413 }
5414
5415 static const VkTimeDomainEXT radv_time_domains[] = {
5416 VK_TIME_DOMAIN_DEVICE_EXT,
5417 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5418 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5419 };
5420
5421 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5422 VkPhysicalDevice physicalDevice,
5423 uint32_t *pTimeDomainCount,
5424 VkTimeDomainEXT *pTimeDomains)
5425 {
5426 int d;
5427 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5428
5429 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5430 vk_outarray_append(&out, i) {
5431 *i = radv_time_domains[d];
5432 }
5433 }
5434
5435 return vk_outarray_status(&out);
5436 }
5437
5438 static uint64_t
5439 radv_clock_gettime(clockid_t clock_id)
5440 {
5441 struct timespec current;
5442 int ret;
5443
5444 ret = clock_gettime(clock_id, &current);
5445 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5446 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5447 if (ret < 0)
5448 return 0;
5449
5450 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5451 }
5452
5453 VkResult radv_GetCalibratedTimestampsEXT(
5454 VkDevice _device,
5455 uint32_t timestampCount,
5456 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5457 uint64_t *pTimestamps,
5458 uint64_t *pMaxDeviation)
5459 {
5460 RADV_FROM_HANDLE(radv_device, device, _device);
5461 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5462 int d;
5463 uint64_t begin, end;
5464 uint64_t max_clock_period = 0;
5465
5466 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5467
5468 for (d = 0; d < timestampCount; d++) {
5469 switch (pTimestampInfos[d].timeDomain) {
5470 case VK_TIME_DOMAIN_DEVICE_EXT:
5471 pTimestamps[d] = device->ws->query_value(device->ws,
5472 RADEON_TIMESTAMP);
5473 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5474 max_clock_period = MAX2(max_clock_period, device_period);
5475 break;
5476 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5477 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5478 max_clock_period = MAX2(max_clock_period, 1);
5479 break;
5480
5481 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5482 pTimestamps[d] = begin;
5483 break;
5484 default:
5485 pTimestamps[d] = 0;
5486 break;
5487 }
5488 }
5489
5490 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5491
5492 /*
5493 * The maximum deviation is the sum of the interval over which we
5494 * perform the sampling and the maximum period of any sampled
5495 * clock. That's because the maximum skew between any two sampled
5496 * clock edges is when the sampled clock with the largest period is
5497 * sampled at the end of that period but right at the beginning of the
5498 * sampling interval and some other clock is sampled right at the
5499 * begining of its sampling period and right at the end of the
5500 * sampling interval. Let's assume the GPU has the longest clock
5501 * period and that the application is sampling GPU and monotonic:
5502 *
5503 * s e
5504 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5505 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5506 *
5507 * g
5508 * 0 1 2 3
5509 * GPU -----_____-----_____-----_____-----_____
5510 *
5511 * m
5512 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5513 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5514 *
5515 * Interval <----------------->
5516 * Deviation <-------------------------->
5517 *
5518 * s = read(raw) 2
5519 * g = read(GPU) 1
5520 * m = read(monotonic) 2
5521 * e = read(raw) b
5522 *
5523 * We round the sample interval up by one tick to cover sampling error
5524 * in the interval clock
5525 */
5526
5527 uint64_t sample_interval = end - begin + 1;
5528
5529 *pMaxDeviation = sample_interval + max_clock_period;
5530
5531 return VK_SUCCESS;
5532 }
5533
5534 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5535 VkPhysicalDevice physicalDevice,
5536 VkSampleCountFlagBits samples,
5537 VkMultisamplePropertiesEXT* pMultisampleProperties)
5538 {
5539 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5540 VK_SAMPLE_COUNT_4_BIT |
5541 VK_SAMPLE_COUNT_8_BIT)) {
5542 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5543 } else {
5544 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5545 }
5546 }