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radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
120 }
121
122 static uint64_t
123 radv_get_visible_vram_size(struct radv_physical_device *device)
124 {
125 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
126 }
127
128 static uint64_t
129 radv_get_vram_size(struct radv_physical_device *device)
130 {
131 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
132 }
133
134 static void
135 radv_physical_device_init_mem_types(struct radv_physical_device *device)
136 {
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
138 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
139 uint64_t vram_size = radv_get_vram_size(device);
140 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
141 device->memory_properties.memoryHeapCount = 0;
142 if (vram_size > 0) {
143 vram_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
145 .size = vram_size,
146 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
147 };
148 }
149 if (visible_vram_size) {
150 visible_vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
152 .size = visible_vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156 if (device->rad_info.gart_size > 0) {
157 gart_index = device->memory_properties.memoryHeapCount++;
158 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
159 .size = device->rad_info.gart_size,
160 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
161 };
162 }
163
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
165 unsigned type_count = 0;
166 if (vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index,
171 };
172 }
173 if (gart_index >= 0) {
174 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
175 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
176 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
178 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
179 .heapIndex = gart_index,
180 };
181 }
182 if (visible_vram_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
188 .heapIndex = visible_vram_index,
189 };
190 }
191 if (gart_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
197 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
198 .heapIndex = gart_index,
199 };
200 }
201 device->memory_properties.memoryTypeCount = type_count;
202 }
203
204 static void
205 radv_handle_env_var_force_family(struct radv_physical_device *device)
206 {
207 const char *family = getenv("RADV_FORCE_FAMILY");
208 unsigned i;
209
210 if (!family)
211 return;
212
213 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
214 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
215 /* Override family and chip_class. */
216 device->rad_info.family = i;
217
218 if (i >= CHIP_VEGA10)
219 device->rad_info.chip_class = GFX9;
220 else if (i >= CHIP_TONGA)
221 device->rad_info.chip_class = GFX8;
222 else if (i >= CHIP_BONAIRE)
223 device->rad_info.chip_class = GFX7;
224 else
225 device->rad_info.chip_class = GFX6;
226
227 return;
228 }
229 }
230
231 fprintf(stderr, "radv: Unknown family: %s\n", family);
232 exit(1);
233 }
234
235 static VkResult
236 radv_physical_device_init(struct radv_physical_device *device,
237 struct radv_instance *instance,
238 drmDevicePtr drm_device)
239 {
240 const char *path = drm_device->nodes[DRM_NODE_RENDER];
241 VkResult result;
242 drmVersionPtr version;
243 int fd;
244 int master_fd = -1;
245
246 fd = open(path, O_RDWR | O_CLOEXEC);
247 if (fd < 0) {
248 if (instance->debug_flags & RADV_DEBUG_STARTUP)
249 radv_logi("Could not open device '%s'", path);
250
251 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
252 }
253
254 version = drmGetVersion(fd);
255 if (!version) {
256 close(fd);
257
258 if (instance->debug_flags & RADV_DEBUG_STARTUP)
259 radv_logi("Could not get the kernel driver version for device '%s'", path);
260
261 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
262 "failed to get version %s: %m", path);
263 }
264
265 if (strcmp(version->name, "amdgpu")) {
266 drmFreeVersion(version);
267 close(fd);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
271
272 return VK_ERROR_INCOMPATIBLE_DRIVER;
273 }
274 drmFreeVersion(version);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Found compatible device '%s'.", path);
278
279 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
280 device->instance = instance;
281
282 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
283 instance->perftest_flags);
284 if (!device->ws) {
285 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
286 goto fail;
287 }
288
289 if (instance->enabled_extensions.KHR_display) {
290 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
291 if (master_fd >= 0) {
292 uint32_t accel_working = 0;
293 struct drm_amdgpu_info request = {
294 .return_pointer = (uintptr_t)&accel_working,
295 .return_size = sizeof(accel_working),
296 .query = AMDGPU_INFO_ACCEL_WORKING
297 };
298
299 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
300 close(master_fd);
301 master_fd = -1;
302 }
303 }
304 }
305
306 device->master_fd = master_fd;
307 device->local_fd = fd;
308 device->ws->query_info(device->ws, &device->rad_info);
309
310 radv_handle_env_var_force_family(device);
311
312 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
313
314 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
315 device->ws->destroy(device->ws);
316 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
317 "cannot generate UUID");
318 goto fail;
319 }
320
321 /* These flags affect shader compilation. */
322 uint64_t shader_env_flags =
323 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
324 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
325
326 /* The gpu id is already embedded in the uuid so we just pass "radv"
327 * when creating the cache.
328 */
329 char buf[VK_UUID_SIZE * 2 + 1];
330 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
331 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
332
333 if (device->rad_info.chip_class < GFX8 ||
334 device->rad_info.chip_class > GFX9)
335 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
336
337 radv_get_driver_uuid(&device->driver_uuid);
338 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
339
340 if (device->rad_info.family == CHIP_STONEY ||
341 device->rad_info.chip_class >= GFX9) {
342 device->has_rbplus = true;
343 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.family == CHIP_VEGA12 ||
345 device->rad_info.family == CHIP_RAVEN ||
346 device->rad_info.family == CHIP_RAVEN2;
347 }
348
349 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
350 * on GFX6.
351 */
352 device->has_clear_state = device->rad_info.chip_class >= GFX7;
353
354 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
355
356 /* Vega10/Raven need a special workaround for a hardware bug. */
357 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
358 device->rad_info.family == CHIP_RAVEN;
359
360 /* Out-of-order primitive rasterization. */
361 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
362 device->rad_info.max_se >= 2;
363 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
364 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
365
366 device->dcc_msaa_allowed =
367 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
368
369 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
370 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
371 (device->rad_info.chip_class >= GFX8 &&
372 device->rad_info.me_fw_feature >= 41);
373
374 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
375
376 radv_physical_device_init_mem_types(device);
377 radv_fill_device_extension_table(device, &device->supported_extensions);
378
379 device->bus_info = *drm_device->businfo.pci;
380
381 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
382 ac_print_gpu_info(&device->rad_info);
383
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
386 * semi-layers).
387 */
388 result = radv_init_wsi(device);
389 if (result != VK_SUCCESS) {
390 device->ws->destroy(device->ws);
391 vk_error(instance, result);
392 goto fail;
393 }
394
395 return VK_SUCCESS;
396
397 fail:
398 close(fd);
399 if (master_fd != -1)
400 close(master_fd);
401 return result;
402 }
403
404 static void
405 radv_physical_device_finish(struct radv_physical_device *device)
406 {
407 radv_finish_wsi(device);
408 device->ws->destroy(device->ws);
409 disk_cache_destroy(device->disk_cache);
410 close(device->local_fd);
411 if (device->master_fd != -1)
412 close(device->master_fd);
413 }
414
415 static void *
416 default_alloc_func(void *pUserData, size_t size, size_t align,
417 VkSystemAllocationScope allocationScope)
418 {
419 return malloc(size);
420 }
421
422 static void *
423 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
424 size_t align, VkSystemAllocationScope allocationScope)
425 {
426 return realloc(pOriginal, size);
427 }
428
429 static void
430 default_free_func(void *pUserData, void *pMemory)
431 {
432 free(pMemory);
433 }
434
435 static const VkAllocationCallbacks default_alloc = {
436 .pUserData = NULL,
437 .pfnAllocation = default_alloc_func,
438 .pfnReallocation = default_realloc_func,
439 .pfnFree = default_free_func,
440 };
441
442 static const struct debug_control radv_debug_options[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
444 {"nodcc", RADV_DEBUG_NO_DCC},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS},
446 {"nocache", RADV_DEBUG_NO_CACHE},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
448 {"nohiz", RADV_DEBUG_NO_HIZ},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
451 {"allbos", RADV_DEBUG_ALL_BOS},
452 {"noibs", RADV_DEBUG_NO_IBS},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
457 {"nosisched", RADV_DEBUG_NO_SISCHED},
458 {"preoptir", RADV_DEBUG_PREOPTIR},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
461 {"info", RADV_DEBUG_INFO},
462 {"errors", RADV_DEBUG_ERRORS},
463 {"startup", RADV_DEBUG_STARTUP},
464 {"checkir", RADV_DEBUG_CHECKIR},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
466 {"nobinning", RADV_DEBUG_NOBINNING},
467 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {"bolist", RADV_PERFTEST_BO_LIST},
484 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
485 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
486 {NULL, 0}
487 };
488
489 const char *
490 radv_get_perftest_option_name(int id)
491 {
492 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
493 return radv_perftest_options[id].string;
494 }
495
496 static void
497 radv_handle_per_app_options(struct radv_instance *instance,
498 const VkApplicationInfo *info)
499 {
500 const char *name = info ? info->pApplicationName : NULL;
501
502 if (!name)
503 return;
504
505 if (!strcmp(name, "Talos - Linux - 32bit") ||
506 !strcmp(name, "Talos - Linux - 64bit")) {
507 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
508 /* Force enable LLVM sisched for Talos because it looks
509 * safe and it gives few more FPS.
510 */
511 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
512 }
513 } else if (!strcmp(name, "DOOM_VFR")) {
514 /* Work around a Doom VFR game bug */
515 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
516 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
517 /* Workaround for a WaW hazard when LLVM moves/merges
518 * load/store memory operations.
519 * See https://reviews.llvm.org/D61313
520 */
521 if (HAVE_LLVM < 0x900)
522 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
523 }
524 }
525
526 static int radv_get_instance_extension_index(const char *name)
527 {
528 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
529 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
530 return i;
531 }
532 return -1;
533 }
534
535 static const char radv_dri_options_xml[] =
536 DRI_CONF_BEGIN
537 DRI_CONF_SECTION_QUALITY
538 DRI_CONF_ADAPTIVE_SYNC("true")
539 DRI_CONF_SECTION_END
540 DRI_CONF_END;
541
542 static void radv_init_dri_options(struct radv_instance *instance)
543 {
544 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
545 driParseConfigFiles(&instance->dri_options,
546 &instance->available_dri_options,
547 0, "radv", NULL);
548 }
549
550 VkResult radv_CreateInstance(
551 const VkInstanceCreateInfo* pCreateInfo,
552 const VkAllocationCallbacks* pAllocator,
553 VkInstance* pInstance)
554 {
555 struct radv_instance *instance;
556 VkResult result;
557
558 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
559
560 uint32_t client_version;
561 if (pCreateInfo->pApplicationInfo &&
562 pCreateInfo->pApplicationInfo->apiVersion != 0) {
563 client_version = pCreateInfo->pApplicationInfo->apiVersion;
564 } else {
565 client_version = VK_API_VERSION_1_0;
566 }
567
568 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
569 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
570 if (!instance)
571 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
572
573 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
574
575 if (pAllocator)
576 instance->alloc = *pAllocator;
577 else
578 instance->alloc = default_alloc;
579
580 instance->apiVersion = client_version;
581 instance->physicalDeviceCount = -1;
582
583 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
584 radv_debug_options);
585
586 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
587 radv_perftest_options);
588
589
590 if (instance->debug_flags & RADV_DEBUG_STARTUP)
591 radv_logi("Created an instance");
592
593 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
594 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
595 int index = radv_get_instance_extension_index(ext_name);
596
597 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
598 vk_free2(&default_alloc, pAllocator, instance);
599 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
600 }
601
602 instance->enabled_extensions.extensions[index] = true;
603 }
604
605 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
606 if (result != VK_SUCCESS) {
607 vk_free2(&default_alloc, pAllocator, instance);
608 return vk_error(instance, result);
609 }
610
611 _mesa_locale_init();
612 glsl_type_singleton_init_or_ref();
613
614 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
615
616 radv_init_dri_options(instance);
617 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
618
619 *pInstance = radv_instance_to_handle(instance);
620
621 return VK_SUCCESS;
622 }
623
624 void radv_DestroyInstance(
625 VkInstance _instance,
626 const VkAllocationCallbacks* pAllocator)
627 {
628 RADV_FROM_HANDLE(radv_instance, instance, _instance);
629
630 if (!instance)
631 return;
632
633 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
634 radv_physical_device_finish(instance->physicalDevices + i);
635 }
636
637 VG(VALGRIND_DESTROY_MEMPOOL(instance));
638
639 glsl_type_singleton_decref();
640 _mesa_locale_fini();
641
642 driDestroyOptionCache(&instance->dri_options);
643 driDestroyOptionInfo(&instance->available_dri_options);
644
645 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
646
647 vk_free(&instance->alloc, instance);
648 }
649
650 static VkResult
651 radv_enumerate_devices(struct radv_instance *instance)
652 {
653 /* TODO: Check for more devices ? */
654 drmDevicePtr devices[8];
655 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
656 int max_devices;
657
658 instance->physicalDeviceCount = 0;
659
660 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
661
662 if (instance->debug_flags & RADV_DEBUG_STARTUP)
663 radv_logi("Found %d drm nodes", max_devices);
664
665 if (max_devices < 1)
666 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
667
668 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
669 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
670 devices[i]->bustype == DRM_BUS_PCI &&
671 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
672
673 result = radv_physical_device_init(instance->physicalDevices +
674 instance->physicalDeviceCount,
675 instance,
676 devices[i]);
677 if (result == VK_SUCCESS)
678 ++instance->physicalDeviceCount;
679 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
680 break;
681 }
682 }
683 drmFreeDevices(devices, max_devices);
684
685 return result;
686 }
687
688 VkResult radv_EnumeratePhysicalDevices(
689 VkInstance _instance,
690 uint32_t* pPhysicalDeviceCount,
691 VkPhysicalDevice* pPhysicalDevices)
692 {
693 RADV_FROM_HANDLE(radv_instance, instance, _instance);
694 VkResult result;
695
696 if (instance->physicalDeviceCount < 0) {
697 result = radv_enumerate_devices(instance);
698 if (result != VK_SUCCESS &&
699 result != VK_ERROR_INCOMPATIBLE_DRIVER)
700 return result;
701 }
702
703 if (!pPhysicalDevices) {
704 *pPhysicalDeviceCount = instance->physicalDeviceCount;
705 } else {
706 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
707 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
708 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
709 }
710
711 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
712 : VK_SUCCESS;
713 }
714
715 VkResult radv_EnumeratePhysicalDeviceGroups(
716 VkInstance _instance,
717 uint32_t* pPhysicalDeviceGroupCount,
718 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
719 {
720 RADV_FROM_HANDLE(radv_instance, instance, _instance);
721 VkResult result;
722
723 if (instance->physicalDeviceCount < 0) {
724 result = radv_enumerate_devices(instance);
725 if (result != VK_SUCCESS &&
726 result != VK_ERROR_INCOMPATIBLE_DRIVER)
727 return result;
728 }
729
730 if (!pPhysicalDeviceGroupProperties) {
731 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
732 } else {
733 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
734 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
735 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
736 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
737 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
738 }
739 }
740 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
741 : VK_SUCCESS;
742 }
743
744 void radv_GetPhysicalDeviceFeatures(
745 VkPhysicalDevice physicalDevice,
746 VkPhysicalDeviceFeatures* pFeatures)
747 {
748 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
749 memset(pFeatures, 0, sizeof(*pFeatures));
750
751 *pFeatures = (VkPhysicalDeviceFeatures) {
752 .robustBufferAccess = true,
753 .fullDrawIndexUint32 = true,
754 .imageCubeArray = true,
755 .independentBlend = true,
756 .geometryShader = true,
757 .tessellationShader = true,
758 .sampleRateShading = true,
759 .dualSrcBlend = true,
760 .logicOp = true,
761 .multiDrawIndirect = true,
762 .drawIndirectFirstInstance = true,
763 .depthClamp = true,
764 .depthBiasClamp = true,
765 .fillModeNonSolid = true,
766 .depthBounds = true,
767 .wideLines = true,
768 .largePoints = true,
769 .alphaToOne = true,
770 .multiViewport = true,
771 .samplerAnisotropy = true,
772 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
773 .textureCompressionASTC_LDR = false,
774 .textureCompressionBC = true,
775 .occlusionQueryPrecise = true,
776 .pipelineStatisticsQuery = true,
777 .vertexPipelineStoresAndAtomics = true,
778 .fragmentStoresAndAtomics = true,
779 .shaderTessellationAndGeometryPointSize = true,
780 .shaderImageGatherExtended = true,
781 .shaderStorageImageExtendedFormats = true,
782 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
783 .shaderUniformBufferArrayDynamicIndexing = true,
784 .shaderSampledImageArrayDynamicIndexing = true,
785 .shaderStorageBufferArrayDynamicIndexing = true,
786 .shaderStorageImageArrayDynamicIndexing = true,
787 .shaderStorageImageReadWithoutFormat = true,
788 .shaderStorageImageWriteWithoutFormat = true,
789 .shaderClipDistance = true,
790 .shaderCullDistance = true,
791 .shaderFloat64 = true,
792 .shaderInt64 = true,
793 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
794 .sparseBinding = true,
795 .variableMultisampleRate = true,
796 .inheritedQueries = true,
797 };
798 }
799
800 void radv_GetPhysicalDeviceFeatures2(
801 VkPhysicalDevice physicalDevice,
802 VkPhysicalDeviceFeatures2 *pFeatures)
803 {
804 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
805 vk_foreach_struct(ext, pFeatures->pNext) {
806 switch (ext->sType) {
807 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
808 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
809 features->variablePointersStorageBuffer = true;
810 features->variablePointers = true;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
814 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
815 features->multiview = true;
816 features->multiviewGeometryShader = true;
817 features->multiviewTessellationShader = true;
818 break;
819 }
820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
821 VkPhysicalDeviceShaderDrawParametersFeatures *features =
822 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
823 features->shaderDrawParameters = true;
824 break;
825 }
826 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
827 VkPhysicalDeviceProtectedMemoryFeatures *features =
828 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
829 features->protectedMemory = false;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
833 VkPhysicalDevice16BitStorageFeatures *features =
834 (VkPhysicalDevice16BitStorageFeatures*)ext;
835 bool enabled = pdevice->rad_info.chip_class >= GFX8;
836 features->storageBuffer16BitAccess = enabled;
837 features->uniformAndStorageBuffer16BitAccess = enabled;
838 features->storagePushConstant16 = enabled;
839 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
840 break;
841 }
842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
843 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
844 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
845 features->samplerYcbcrConversion = true;
846 break;
847 }
848 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
849 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
850 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
851 features->shaderInputAttachmentArrayDynamicIndexing = true;
852 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
853 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
854 features->shaderUniformBufferArrayNonUniformIndexing = true;
855 features->shaderSampledImageArrayNonUniformIndexing = true;
856 features->shaderStorageBufferArrayNonUniformIndexing = true;
857 features->shaderStorageImageArrayNonUniformIndexing = true;
858 features->shaderInputAttachmentArrayNonUniformIndexing = true;
859 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
860 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
861 features->descriptorBindingUniformBufferUpdateAfterBind = true;
862 features->descriptorBindingSampledImageUpdateAfterBind = true;
863 features->descriptorBindingStorageImageUpdateAfterBind = true;
864 features->descriptorBindingStorageBufferUpdateAfterBind = true;
865 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
866 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
867 features->descriptorBindingUpdateUnusedWhilePending = true;
868 features->descriptorBindingPartiallyBound = true;
869 features->descriptorBindingVariableDescriptorCount = true;
870 features->runtimeDescriptorArray = true;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
874 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
875 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
876 features->conditionalRendering = true;
877 features->inheritedConditionalRendering = false;
878 break;
879 }
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
881 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
882 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
883 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
884 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
885 break;
886 }
887 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
888 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
889 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
890 features->transformFeedback = true;
891 features->geometryStreams = true;
892 break;
893 }
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
895 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
896 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
897 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
898 break;
899 }
900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
901 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
902 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
903 features->memoryPriority = VK_TRUE;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
907 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
908 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
909 features->bufferDeviceAddress = true;
910 features->bufferDeviceAddressCaptureReplay = false;
911 features->bufferDeviceAddressMultiDevice = false;
912 break;
913 }
914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
915 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
916 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
917 features->depthClipEnable = true;
918 break;
919 }
920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
921 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
922 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
923 features->hostQueryReset = true;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
927 VkPhysicalDevice8BitStorageFeaturesKHR *features =
928 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
929 bool enabled = pdevice->rad_info.chip_class >= GFX8;
930 features->storageBuffer8BitAccess = enabled;
931 features->uniformAndStorageBuffer8BitAccess = enabled;
932 features->storagePushConstant8 = enabled;
933 break;
934 }
935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
936 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
937 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
938 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
939 features->shaderInt8 = true;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
943 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
944 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
945 /* TODO: Enable this once the driver supports 64-bit
946 * compare&swap atomic operations.
947 */
948 features->shaderBufferInt64Atomics = false;
949 features->shaderSharedInt64Atomics = false;
950 break;
951 }
952 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
953 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
954 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
955
956 features->inlineUniformBlock = true;
957 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
961 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
962 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
963 features->computeDerivativeGroupQuads = false;
964 features->computeDerivativeGroupLinear = true;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
968 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
969 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
970 features->ycbcrImageArrays = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
974 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
975 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
976 features->uniformBufferStandardLayout = true;
977 break;
978 }
979 default:
980 break;
981 }
982 }
983 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
984 }
985
986 void radv_GetPhysicalDeviceProperties(
987 VkPhysicalDevice physicalDevice,
988 VkPhysicalDeviceProperties* pProperties)
989 {
990 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
991 VkSampleCountFlags sample_counts = 0xf;
992
993 /* make sure that the entire descriptor set is addressable with a signed
994 * 32-bit int. So the sum of all limits scaled by descriptor size has to
995 * be at most 2 GiB. the combined image & samples object count as one of
996 * both. This limit is for the pipeline layout, not for the set layout, but
997 * there is no set limit, so we just set a pipeline limit. I don't think
998 * any app is going to hit this soon. */
999 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1000 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1001 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1002 32 /* sampler, largest when combined with image */ +
1003 64 /* sampled image */ +
1004 64 /* storage image */);
1005
1006 VkPhysicalDeviceLimits limits = {
1007 .maxImageDimension1D = (1 << 14),
1008 .maxImageDimension2D = (1 << 14),
1009 .maxImageDimension3D = (1 << 11),
1010 .maxImageDimensionCube = (1 << 14),
1011 .maxImageArrayLayers = (1 << 11),
1012 .maxTexelBufferElements = 128 * 1024 * 1024,
1013 .maxUniformBufferRange = UINT32_MAX,
1014 .maxStorageBufferRange = UINT32_MAX,
1015 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1016 .maxMemoryAllocationCount = UINT32_MAX,
1017 .maxSamplerAllocationCount = 64 * 1024,
1018 .bufferImageGranularity = 64, /* A cache line */
1019 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1020 .maxBoundDescriptorSets = MAX_SETS,
1021 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1022 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1023 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1024 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1025 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1026 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1027 .maxPerStageResources = max_descriptor_set_size,
1028 .maxDescriptorSetSamplers = max_descriptor_set_size,
1029 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1030 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1031 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1032 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1033 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1034 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1035 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1036 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1037 .maxVertexInputBindings = MAX_VBS,
1038 .maxVertexInputAttributeOffset = 2047,
1039 .maxVertexInputBindingStride = 2048,
1040 .maxVertexOutputComponents = 128,
1041 .maxTessellationGenerationLevel = 64,
1042 .maxTessellationPatchSize = 32,
1043 .maxTessellationControlPerVertexInputComponents = 128,
1044 .maxTessellationControlPerVertexOutputComponents = 128,
1045 .maxTessellationControlPerPatchOutputComponents = 120,
1046 .maxTessellationControlTotalOutputComponents = 4096,
1047 .maxTessellationEvaluationInputComponents = 128,
1048 .maxTessellationEvaluationOutputComponents = 128,
1049 .maxGeometryShaderInvocations = 127,
1050 .maxGeometryInputComponents = 64,
1051 .maxGeometryOutputComponents = 128,
1052 .maxGeometryOutputVertices = 256,
1053 .maxGeometryTotalOutputComponents = 1024,
1054 .maxFragmentInputComponents = 128,
1055 .maxFragmentOutputAttachments = 8,
1056 .maxFragmentDualSrcAttachments = 1,
1057 .maxFragmentCombinedOutputResources = 8,
1058 .maxComputeSharedMemorySize = 32768,
1059 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1060 .maxComputeWorkGroupInvocations = 2048,
1061 .maxComputeWorkGroupSize = {
1062 2048,
1063 2048,
1064 2048
1065 },
1066 .subPixelPrecisionBits = 8,
1067 .subTexelPrecisionBits = 8,
1068 .mipmapPrecisionBits = 8,
1069 .maxDrawIndexedIndexValue = UINT32_MAX,
1070 .maxDrawIndirectCount = UINT32_MAX,
1071 .maxSamplerLodBias = 16,
1072 .maxSamplerAnisotropy = 16,
1073 .maxViewports = MAX_VIEWPORTS,
1074 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1075 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1076 .viewportSubPixelBits = 8,
1077 .minMemoryMapAlignment = 4096, /* A page */
1078 .minTexelBufferOffsetAlignment = 1,
1079 .minUniformBufferOffsetAlignment = 4,
1080 .minStorageBufferOffsetAlignment = 4,
1081 .minTexelOffset = -32,
1082 .maxTexelOffset = 31,
1083 .minTexelGatherOffset = -32,
1084 .maxTexelGatherOffset = 31,
1085 .minInterpolationOffset = -2,
1086 .maxInterpolationOffset = 2,
1087 .subPixelInterpolationOffsetBits = 8,
1088 .maxFramebufferWidth = (1 << 14),
1089 .maxFramebufferHeight = (1 << 14),
1090 .maxFramebufferLayers = (1 << 10),
1091 .framebufferColorSampleCounts = sample_counts,
1092 .framebufferDepthSampleCounts = sample_counts,
1093 .framebufferStencilSampleCounts = sample_counts,
1094 .framebufferNoAttachmentsSampleCounts = sample_counts,
1095 .maxColorAttachments = MAX_RTS,
1096 .sampledImageColorSampleCounts = sample_counts,
1097 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1098 .sampledImageDepthSampleCounts = sample_counts,
1099 .sampledImageStencilSampleCounts = sample_counts,
1100 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1101 .maxSampleMaskWords = 1,
1102 .timestampComputeAndGraphics = true,
1103 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1104 .maxClipDistances = 8,
1105 .maxCullDistances = 8,
1106 .maxCombinedClipAndCullDistances = 8,
1107 .discreteQueuePriorities = 2,
1108 .pointSizeRange = { 0.0, 8192.0 },
1109 .lineWidthRange = { 0.0, 7.9921875 },
1110 .pointSizeGranularity = (1.0 / 8.0),
1111 .lineWidthGranularity = (1.0 / 128.0),
1112 .strictLines = false, /* FINISHME */
1113 .standardSampleLocations = true,
1114 .optimalBufferCopyOffsetAlignment = 128,
1115 .optimalBufferCopyRowPitchAlignment = 128,
1116 .nonCoherentAtomSize = 64,
1117 };
1118
1119 *pProperties = (VkPhysicalDeviceProperties) {
1120 .apiVersion = radv_physical_device_api_version(pdevice),
1121 .driverVersion = vk_get_driver_version(),
1122 .vendorID = ATI_VENDOR_ID,
1123 .deviceID = pdevice->rad_info.pci_id,
1124 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1125 .limits = limits,
1126 .sparseProperties = {0},
1127 };
1128
1129 strcpy(pProperties->deviceName, pdevice->name);
1130 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1131 }
1132
1133 void radv_GetPhysicalDeviceProperties2(
1134 VkPhysicalDevice physicalDevice,
1135 VkPhysicalDeviceProperties2 *pProperties)
1136 {
1137 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1138 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1139
1140 vk_foreach_struct(ext, pProperties->pNext) {
1141 switch (ext->sType) {
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1143 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1144 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1145 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1149 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1150 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1151 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1152 properties->deviceLUIDValid = false;
1153 break;
1154 }
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1156 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1157 properties->maxMultiviewViewCount = MAX_VIEWS;
1158 properties->maxMultiviewInstanceIndex = INT_MAX;
1159 break;
1160 }
1161 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1162 VkPhysicalDevicePointClippingProperties *properties =
1163 (VkPhysicalDevicePointClippingProperties*)ext;
1164 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1165 break;
1166 }
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1168 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1169 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1170 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1174 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1175 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1176 properties->minImportedHostPointerAlignment = 4096;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1180 VkPhysicalDeviceSubgroupProperties *properties =
1181 (VkPhysicalDeviceSubgroupProperties*)ext;
1182 properties->subgroupSize = 64;
1183 properties->supportedStages = VK_SHADER_STAGE_ALL;
1184 properties->supportedOperations =
1185 VK_SUBGROUP_FEATURE_BASIC_BIT |
1186 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1187 VK_SUBGROUP_FEATURE_QUAD_BIT |
1188 VK_SUBGROUP_FEATURE_VOTE_BIT;
1189 if (pdevice->rad_info.chip_class >= GFX8) {
1190 properties->supportedOperations |=
1191 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1192 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1193 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1194 }
1195 properties->quadOperationsInAllStages = true;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1199 VkPhysicalDeviceMaintenance3Properties *properties =
1200 (VkPhysicalDeviceMaintenance3Properties*)ext;
1201 /* Make sure everything is addressable by a signed 32-bit int, and
1202 * our largest descriptors are 96 bytes. */
1203 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1204 /* Our buffer size fields allow only this much */
1205 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1206 break;
1207 }
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1209 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1210 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1211 /* GFX6-8 only support single channel min/max filter. */
1212 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1213 properties->filterMinmaxSingleComponentFormats = true;
1214 break;
1215 }
1216 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1217 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1218 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1219
1220 /* Shader engines. */
1221 properties->shaderEngineCount =
1222 pdevice->rad_info.max_se;
1223 properties->shaderArraysPerEngineCount =
1224 pdevice->rad_info.max_sh_per_se;
1225 properties->computeUnitsPerShaderArray =
1226 pdevice->rad_info.num_good_cu_per_sh;
1227 properties->simdPerComputeUnit = 4;
1228 properties->wavefrontsPerSimd =
1229 pdevice->rad_info.family == CHIP_TONGA ||
1230 pdevice->rad_info.family == CHIP_ICELAND ||
1231 pdevice->rad_info.family == CHIP_POLARIS10 ||
1232 pdevice->rad_info.family == CHIP_POLARIS11 ||
1233 pdevice->rad_info.family == CHIP_POLARIS12 ||
1234 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1235 properties->wavefrontSize = 64;
1236
1237 /* SGPR. */
1238 properties->sgprsPerSimd =
1239 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1240 properties->minSgprAllocation =
1241 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1242 properties->maxSgprAllocation =
1243 pdevice->rad_info.family == CHIP_TONGA ||
1244 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1245 properties->sgprAllocationGranularity =
1246 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1247
1248 /* VGPR. */
1249 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1250 properties->minVgprAllocation = 4;
1251 properties->maxVgprAllocation = 256;
1252 properties->vgprAllocationGranularity = 4;
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1256 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1257 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1258 properties->maxVertexAttribDivisor = UINT32_MAX;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1262 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1263 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1264 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1265 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1266 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1267 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1268 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1269 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1270 properties->robustBufferAccessUpdateAfterBind = false;
1271 properties->quadDivergentImplicitLod = false;
1272
1273 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1274 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1275 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1276 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1277 32 /* sampler, largest when combined with image */ +
1278 64 /* sampled image */ +
1279 64 /* storage image */);
1280 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1281 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1282 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1283 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1284 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1285 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1286 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1287 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1288 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1289 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1290 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1292 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1293 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1294 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1295 break;
1296 }
1297 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1298 VkPhysicalDeviceProtectedMemoryProperties *properties =
1299 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1300 properties->protectedNoFault = false;
1301 break;
1302 }
1303 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1304 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1305 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1306 properties->primitiveOverestimationSize = 0;
1307 properties->maxExtraPrimitiveOverestimationSize = 0;
1308 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1309 properties->primitiveUnderestimation = VK_FALSE;
1310 properties->conservativePointAndLineRasterization = VK_FALSE;
1311 properties->degenerateTrianglesRasterized = VK_FALSE;
1312 properties->degenerateLinesRasterized = VK_FALSE;
1313 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1314 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1315 break;
1316 }
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1318 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1319 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1320 properties->pciDomain = pdevice->bus_info.domain;
1321 properties->pciBus = pdevice->bus_info.bus;
1322 properties->pciDevice = pdevice->bus_info.dev;
1323 properties->pciFunction = pdevice->bus_info.func;
1324 break;
1325 }
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1327 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1328 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1329
1330 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1331 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1332 strcpy(driver_props->driverName, "radv");
1333
1334 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1335 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1336 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1337 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1338
1339 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1340 .major = 1,
1341 .minor = 1,
1342 .subminor = 2,
1343 .patch = 0,
1344 };
1345 break;
1346 }
1347 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1348 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1349 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1350 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1351 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1352 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1353 properties->maxTransformFeedbackStreamDataSize = 512;
1354 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1355 properties->maxTransformFeedbackBufferDataStride = 512;
1356 properties->transformFeedbackQueries = true;
1357 properties->transformFeedbackStreamsLinesTriangles = true;
1358 properties->transformFeedbackRasterizationStreamSelect = false;
1359 properties->transformFeedbackDraw = true;
1360 break;
1361 }
1362 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1363 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1364 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1365
1366 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1367 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1368 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1369 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1370 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1374 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1375 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1376 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1377 VK_SAMPLE_COUNT_4_BIT |
1378 VK_SAMPLE_COUNT_8_BIT;
1379 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1380 properties->sampleLocationCoordinateRange[0] = 0.0f;
1381 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1382 properties->sampleLocationSubPixelBits = 4;
1383 properties->variableSampleLocations = VK_FALSE;
1384 break;
1385 }
1386 default:
1387 break;
1388 }
1389 }
1390 }
1391
1392 static void radv_get_physical_device_queue_family_properties(
1393 struct radv_physical_device* pdevice,
1394 uint32_t* pCount,
1395 VkQueueFamilyProperties** pQueueFamilyProperties)
1396 {
1397 int num_queue_families = 1;
1398 int idx;
1399 if (pdevice->rad_info.num_compute_rings > 0 &&
1400 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1401 num_queue_families++;
1402
1403 if (pQueueFamilyProperties == NULL) {
1404 *pCount = num_queue_families;
1405 return;
1406 }
1407
1408 if (!*pCount)
1409 return;
1410
1411 idx = 0;
1412 if (*pCount >= 1) {
1413 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1414 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1415 VK_QUEUE_COMPUTE_BIT |
1416 VK_QUEUE_TRANSFER_BIT |
1417 VK_QUEUE_SPARSE_BINDING_BIT,
1418 .queueCount = 1,
1419 .timestampValidBits = 64,
1420 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1421 };
1422 idx++;
1423 }
1424
1425 if (pdevice->rad_info.num_compute_rings > 0 &&
1426 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1427 if (*pCount > idx) {
1428 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1429 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1430 VK_QUEUE_TRANSFER_BIT |
1431 VK_QUEUE_SPARSE_BINDING_BIT,
1432 .queueCount = pdevice->rad_info.num_compute_rings,
1433 .timestampValidBits = 64,
1434 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1435 };
1436 idx++;
1437 }
1438 }
1439 *pCount = idx;
1440 }
1441
1442 void radv_GetPhysicalDeviceQueueFamilyProperties(
1443 VkPhysicalDevice physicalDevice,
1444 uint32_t* pCount,
1445 VkQueueFamilyProperties* pQueueFamilyProperties)
1446 {
1447 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1448 if (!pQueueFamilyProperties) {
1449 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1450 return;
1451 }
1452 VkQueueFamilyProperties *properties[] = {
1453 pQueueFamilyProperties + 0,
1454 pQueueFamilyProperties + 1,
1455 pQueueFamilyProperties + 2,
1456 };
1457 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1458 assert(*pCount <= 3);
1459 }
1460
1461 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1462 VkPhysicalDevice physicalDevice,
1463 uint32_t* pCount,
1464 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1465 {
1466 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1467 if (!pQueueFamilyProperties) {
1468 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1469 return;
1470 }
1471 VkQueueFamilyProperties *properties[] = {
1472 &pQueueFamilyProperties[0].queueFamilyProperties,
1473 &pQueueFamilyProperties[1].queueFamilyProperties,
1474 &pQueueFamilyProperties[2].queueFamilyProperties,
1475 };
1476 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1477 assert(*pCount <= 3);
1478 }
1479
1480 void radv_GetPhysicalDeviceMemoryProperties(
1481 VkPhysicalDevice physicalDevice,
1482 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1483 {
1484 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1485
1486 *pMemoryProperties = physical_device->memory_properties;
1487 }
1488
1489 static void
1490 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1491 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1492 {
1493 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1494 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1495 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1496 uint64_t vram_size = radv_get_vram_size(device);
1497 uint64_t gtt_size = device->rad_info.gart_size;
1498 uint64_t heap_budget, heap_usage;
1499
1500 /* For all memory heaps, the computation of budget is as follow:
1501 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1502 *
1503 * The Vulkan spec 1.1.97 says that the budget should include any
1504 * currently allocated device memory.
1505 *
1506 * Note that the application heap usages are not really accurate (eg.
1507 * in presence of shared buffers).
1508 */
1509 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1510 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1511
1512 switch (device->mem_type_indices[i]) {
1513 case RADV_MEM_TYPE_VRAM:
1514 heap_usage = device->ws->query_value(device->ws,
1515 RADEON_ALLOCATED_VRAM);
1516
1517 heap_budget = vram_size -
1518 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1519 heap_usage;
1520
1521 memoryBudget->heapBudget[heap_index] = heap_budget;
1522 memoryBudget->heapUsage[heap_index] = heap_usage;
1523 break;
1524 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1525 heap_usage = device->ws->query_value(device->ws,
1526 RADEON_ALLOCATED_VRAM_VIS);
1527
1528 heap_budget = visible_vram_size -
1529 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1530 heap_usage;
1531
1532 memoryBudget->heapBudget[heap_index] = heap_budget;
1533 memoryBudget->heapUsage[heap_index] = heap_usage;
1534 break;
1535 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1536 heap_usage = device->ws->query_value(device->ws,
1537 RADEON_ALLOCATED_GTT);
1538
1539 heap_budget = gtt_size -
1540 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1541 heap_usage;
1542
1543 memoryBudget->heapBudget[heap_index] = heap_budget;
1544 memoryBudget->heapUsage[heap_index] = heap_usage;
1545 break;
1546 default:
1547 break;
1548 }
1549 }
1550
1551 /* The heapBudget and heapUsage values must be zero for array elements
1552 * greater than or equal to
1553 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1554 */
1555 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1556 memoryBudget->heapBudget[i] = 0;
1557 memoryBudget->heapUsage[i] = 0;
1558 }
1559 }
1560
1561 void radv_GetPhysicalDeviceMemoryProperties2(
1562 VkPhysicalDevice physicalDevice,
1563 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1564 {
1565 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1566 &pMemoryProperties->memoryProperties);
1567
1568 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1569 vk_find_struct(pMemoryProperties->pNext,
1570 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1571 if (memory_budget)
1572 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1573 }
1574
1575 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1576 VkDevice _device,
1577 VkExternalMemoryHandleTypeFlagBits handleType,
1578 const void *pHostPointer,
1579 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1580 {
1581 RADV_FROM_HANDLE(radv_device, device, _device);
1582
1583 switch (handleType)
1584 {
1585 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1586 const struct radv_physical_device *physical_device = device->physical_device;
1587 uint32_t memoryTypeBits = 0;
1588 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1589 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1590 memoryTypeBits = (1 << i);
1591 break;
1592 }
1593 }
1594 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1595 return VK_SUCCESS;
1596 }
1597 default:
1598 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1599 }
1600 }
1601
1602 static enum radeon_ctx_priority
1603 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1604 {
1605 /* Default to MEDIUM when a specific global priority isn't requested */
1606 if (!pObj)
1607 return RADEON_CTX_PRIORITY_MEDIUM;
1608
1609 switch(pObj->globalPriority) {
1610 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1611 return RADEON_CTX_PRIORITY_REALTIME;
1612 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1613 return RADEON_CTX_PRIORITY_HIGH;
1614 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1615 return RADEON_CTX_PRIORITY_MEDIUM;
1616 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1617 return RADEON_CTX_PRIORITY_LOW;
1618 default:
1619 unreachable("Illegal global priority value");
1620 return RADEON_CTX_PRIORITY_INVALID;
1621 }
1622 }
1623
1624 static int
1625 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1626 uint32_t queue_family_index, int idx,
1627 VkDeviceQueueCreateFlags flags,
1628 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1629 {
1630 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1631 queue->device = device;
1632 queue->queue_family_index = queue_family_index;
1633 queue->queue_idx = idx;
1634 queue->priority = radv_get_queue_global_priority(global_priority);
1635 queue->flags = flags;
1636
1637 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1638 if (!queue->hw_ctx)
1639 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1640
1641 return VK_SUCCESS;
1642 }
1643
1644 static void
1645 radv_queue_finish(struct radv_queue *queue)
1646 {
1647 if (queue->hw_ctx)
1648 queue->device->ws->ctx_destroy(queue->hw_ctx);
1649
1650 if (queue->initial_full_flush_preamble_cs)
1651 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1652 if (queue->initial_preamble_cs)
1653 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1654 if (queue->continue_preamble_cs)
1655 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1656 if (queue->descriptor_bo)
1657 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1658 if (queue->scratch_bo)
1659 queue->device->ws->buffer_destroy(queue->scratch_bo);
1660 if (queue->esgs_ring_bo)
1661 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1662 if (queue->gsvs_ring_bo)
1663 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1664 if (queue->tess_rings_bo)
1665 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1666 if (queue->compute_scratch_bo)
1667 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1668 }
1669
1670 static void
1671 radv_bo_list_init(struct radv_bo_list *bo_list)
1672 {
1673 pthread_mutex_init(&bo_list->mutex, NULL);
1674 bo_list->list.count = bo_list->capacity = 0;
1675 bo_list->list.bos = NULL;
1676 }
1677
1678 static void
1679 radv_bo_list_finish(struct radv_bo_list *bo_list)
1680 {
1681 free(bo_list->list.bos);
1682 pthread_mutex_destroy(&bo_list->mutex);
1683 }
1684
1685 static VkResult radv_bo_list_add(struct radv_device *device,
1686 struct radeon_winsys_bo *bo)
1687 {
1688 struct radv_bo_list *bo_list = &device->bo_list;
1689
1690 if (bo->is_local)
1691 return VK_SUCCESS;
1692
1693 if (unlikely(!device->use_global_bo_list))
1694 return VK_SUCCESS;
1695
1696 pthread_mutex_lock(&bo_list->mutex);
1697 if (bo_list->list.count == bo_list->capacity) {
1698 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1699 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1700
1701 if (!data) {
1702 pthread_mutex_unlock(&bo_list->mutex);
1703 return VK_ERROR_OUT_OF_HOST_MEMORY;
1704 }
1705
1706 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1707 bo_list->capacity = capacity;
1708 }
1709
1710 bo_list->list.bos[bo_list->list.count++] = bo;
1711 pthread_mutex_unlock(&bo_list->mutex);
1712 return VK_SUCCESS;
1713 }
1714
1715 static void radv_bo_list_remove(struct radv_device *device,
1716 struct radeon_winsys_bo *bo)
1717 {
1718 struct radv_bo_list *bo_list = &device->bo_list;
1719
1720 if (bo->is_local)
1721 return;
1722
1723 if (unlikely(!device->use_global_bo_list))
1724 return;
1725
1726 pthread_mutex_lock(&bo_list->mutex);
1727 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1728 if (bo_list->list.bos[i] == bo) {
1729 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1730 --bo_list->list.count;
1731 break;
1732 }
1733 }
1734 pthread_mutex_unlock(&bo_list->mutex);
1735 }
1736
1737 static void
1738 radv_device_init_gs_info(struct radv_device *device)
1739 {
1740 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1741 device->physical_device->rad_info.family);
1742 }
1743
1744 static int radv_get_device_extension_index(const char *name)
1745 {
1746 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1747 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1748 return i;
1749 }
1750 return -1;
1751 }
1752
1753 static int
1754 radv_get_int_debug_option(const char *name, int default_value)
1755 {
1756 const char *str;
1757 int result;
1758
1759 str = getenv(name);
1760 if (!str) {
1761 result = default_value;
1762 } else {
1763 char *endptr;
1764
1765 result = strtol(str, &endptr, 0);
1766 if (str == endptr) {
1767 /* No digits founs. */
1768 result = default_value;
1769 }
1770 }
1771
1772 return result;
1773 }
1774
1775 VkResult radv_CreateDevice(
1776 VkPhysicalDevice physicalDevice,
1777 const VkDeviceCreateInfo* pCreateInfo,
1778 const VkAllocationCallbacks* pAllocator,
1779 VkDevice* pDevice)
1780 {
1781 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1782 VkResult result;
1783 struct radv_device *device;
1784
1785 bool keep_shader_info = false;
1786
1787 /* Check enabled features */
1788 if (pCreateInfo->pEnabledFeatures) {
1789 VkPhysicalDeviceFeatures supported_features;
1790 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1791 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1792 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1793 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1794 for (uint32_t i = 0; i < num_features; i++) {
1795 if (enabled_feature[i] && !supported_feature[i])
1796 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1797 }
1798 }
1799
1800 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1801 sizeof(*device), 8,
1802 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1803 if (!device)
1804 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1805
1806 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1807 device->instance = physical_device->instance;
1808 device->physical_device = physical_device;
1809
1810 device->ws = physical_device->ws;
1811 if (pAllocator)
1812 device->alloc = *pAllocator;
1813 else
1814 device->alloc = physical_device->instance->alloc;
1815
1816 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1817 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1818 int index = radv_get_device_extension_index(ext_name);
1819 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1820 vk_free(&device->alloc, device);
1821 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1822 }
1823
1824 device->enabled_extensions.extensions[index] = true;
1825 }
1826
1827 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1828
1829 /* With update after bind we can't attach bo's to the command buffer
1830 * from the descriptor set anymore, so we have to use a global BO list.
1831 */
1832 device->use_global_bo_list =
1833 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1834 device->enabled_extensions.EXT_descriptor_indexing ||
1835 device->enabled_extensions.EXT_buffer_device_address;
1836
1837 mtx_init(&device->shader_slab_mutex, mtx_plain);
1838 list_inithead(&device->shader_slabs);
1839
1840 radv_bo_list_init(&device->bo_list);
1841
1842 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1843 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1844 uint32_t qfi = queue_create->queueFamilyIndex;
1845 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1846 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1847
1848 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1849
1850 device->queues[qfi] = vk_alloc(&device->alloc,
1851 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1852 if (!device->queues[qfi]) {
1853 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1854 goto fail;
1855 }
1856
1857 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1858
1859 device->queue_count[qfi] = queue_create->queueCount;
1860
1861 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1862 result = radv_queue_init(device, &device->queues[qfi][q],
1863 qfi, q, queue_create->flags,
1864 global_priority);
1865 if (result != VK_SUCCESS)
1866 goto fail;
1867 }
1868 }
1869
1870 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1871 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1872
1873 /* Disabled and not implemented for now. */
1874 device->dfsm_allowed = device->pbb_allowed &&
1875 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1876 device->physical_device->rad_info.family == CHIP_RAVEN2);
1877
1878 #ifdef ANDROID
1879 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1880 #endif
1881
1882 /* The maximum number of scratch waves. Scratch space isn't divided
1883 * evenly between CUs. The number is only a function of the number of CUs.
1884 * We can decrease the constant to decrease the scratch buffer size.
1885 *
1886 * sctx->scratch_waves must be >= the maximum possible size of
1887 * 1 threadgroup, so that the hw doesn't hang from being unable
1888 * to start any.
1889 *
1890 * The recommended value is 4 per CU at most. Higher numbers don't
1891 * bring much benefit, but they still occupy chip resources (think
1892 * async compute). I've seen ~2% performance difference between 4 and 32.
1893 */
1894 uint32_t max_threads_per_block = 2048;
1895 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1896 max_threads_per_block / 64);
1897
1898 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1899
1900 if (device->physical_device->rad_info.chip_class >= GFX7) {
1901 /* If the KMD allows it (there is a KMD hw register for it),
1902 * allow launching waves out-of-order.
1903 */
1904 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1905 }
1906
1907 radv_device_init_gs_info(device);
1908
1909 device->tess_offchip_block_dw_size =
1910 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1911 device->has_distributed_tess =
1912 device->physical_device->rad_info.chip_class >= GFX8 &&
1913 device->physical_device->rad_info.max_se >= 2;
1914
1915 if (getenv("RADV_TRACE_FILE")) {
1916 const char *filename = getenv("RADV_TRACE_FILE");
1917
1918 keep_shader_info = true;
1919
1920 if (!radv_init_trace(device))
1921 goto fail;
1922
1923 fprintf(stderr, "*****************************************************************************\n");
1924 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1925 fprintf(stderr, "*****************************************************************************\n");
1926
1927 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1928 radv_dump_enabled_options(device, stderr);
1929 }
1930
1931 device->keep_shader_info = keep_shader_info;
1932
1933 result = radv_device_init_meta(device);
1934 if (result != VK_SUCCESS)
1935 goto fail;
1936
1937 radv_device_init_msaa(device);
1938
1939 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1940 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1941 switch (family) {
1942 case RADV_QUEUE_GENERAL:
1943 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1944 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1945 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1946 break;
1947 case RADV_QUEUE_COMPUTE:
1948 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1949 radeon_emit(device->empty_cs[family], 0);
1950 break;
1951 }
1952 device->ws->cs_finalize(device->empty_cs[family]);
1953 }
1954
1955 if (device->physical_device->rad_info.chip_class >= GFX7)
1956 cik_create_gfx_config(device);
1957
1958 VkPipelineCacheCreateInfo ci;
1959 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1960 ci.pNext = NULL;
1961 ci.flags = 0;
1962 ci.pInitialData = NULL;
1963 ci.initialDataSize = 0;
1964 VkPipelineCache pc;
1965 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1966 &ci, NULL, &pc);
1967 if (result != VK_SUCCESS)
1968 goto fail_meta;
1969
1970 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1971
1972 device->force_aniso =
1973 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1974 if (device->force_aniso >= 0) {
1975 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1976 1 << util_logbase2(device->force_aniso));
1977 }
1978
1979 *pDevice = radv_device_to_handle(device);
1980 return VK_SUCCESS;
1981
1982 fail_meta:
1983 radv_device_finish_meta(device);
1984 fail:
1985 radv_bo_list_finish(&device->bo_list);
1986
1987 if (device->trace_bo)
1988 device->ws->buffer_destroy(device->trace_bo);
1989
1990 if (device->gfx_init)
1991 device->ws->buffer_destroy(device->gfx_init);
1992
1993 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1994 for (unsigned q = 0; q < device->queue_count[i]; q++)
1995 radv_queue_finish(&device->queues[i][q]);
1996 if (device->queue_count[i])
1997 vk_free(&device->alloc, device->queues[i]);
1998 }
1999
2000 vk_free(&device->alloc, device);
2001 return result;
2002 }
2003
2004 void radv_DestroyDevice(
2005 VkDevice _device,
2006 const VkAllocationCallbacks* pAllocator)
2007 {
2008 RADV_FROM_HANDLE(radv_device, device, _device);
2009
2010 if (!device)
2011 return;
2012
2013 if (device->trace_bo)
2014 device->ws->buffer_destroy(device->trace_bo);
2015
2016 if (device->gfx_init)
2017 device->ws->buffer_destroy(device->gfx_init);
2018
2019 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2020 for (unsigned q = 0; q < device->queue_count[i]; q++)
2021 radv_queue_finish(&device->queues[i][q]);
2022 if (device->queue_count[i])
2023 vk_free(&device->alloc, device->queues[i]);
2024 if (device->empty_cs[i])
2025 device->ws->cs_destroy(device->empty_cs[i]);
2026 }
2027 radv_device_finish_meta(device);
2028
2029 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2030 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2031
2032 radv_destroy_shader_slabs(device);
2033
2034 radv_bo_list_finish(&device->bo_list);
2035 vk_free(&device->alloc, device);
2036 }
2037
2038 VkResult radv_EnumerateInstanceLayerProperties(
2039 uint32_t* pPropertyCount,
2040 VkLayerProperties* pProperties)
2041 {
2042 if (pProperties == NULL) {
2043 *pPropertyCount = 0;
2044 return VK_SUCCESS;
2045 }
2046
2047 /* None supported at this time */
2048 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2049 }
2050
2051 VkResult radv_EnumerateDeviceLayerProperties(
2052 VkPhysicalDevice physicalDevice,
2053 uint32_t* pPropertyCount,
2054 VkLayerProperties* pProperties)
2055 {
2056 if (pProperties == NULL) {
2057 *pPropertyCount = 0;
2058 return VK_SUCCESS;
2059 }
2060
2061 /* None supported at this time */
2062 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2063 }
2064
2065 void radv_GetDeviceQueue2(
2066 VkDevice _device,
2067 const VkDeviceQueueInfo2* pQueueInfo,
2068 VkQueue* pQueue)
2069 {
2070 RADV_FROM_HANDLE(radv_device, device, _device);
2071 struct radv_queue *queue;
2072
2073 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2074 if (pQueueInfo->flags != queue->flags) {
2075 /* From the Vulkan 1.1.70 spec:
2076 *
2077 * "The queue returned by vkGetDeviceQueue2 must have the same
2078 * flags value from this structure as that used at device
2079 * creation time in a VkDeviceQueueCreateInfo instance. If no
2080 * matching flags were specified at device creation time then
2081 * pQueue will return VK_NULL_HANDLE."
2082 */
2083 *pQueue = VK_NULL_HANDLE;
2084 return;
2085 }
2086
2087 *pQueue = radv_queue_to_handle(queue);
2088 }
2089
2090 void radv_GetDeviceQueue(
2091 VkDevice _device,
2092 uint32_t queueFamilyIndex,
2093 uint32_t queueIndex,
2094 VkQueue* pQueue)
2095 {
2096 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2097 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2098 .queueFamilyIndex = queueFamilyIndex,
2099 .queueIndex = queueIndex
2100 };
2101
2102 radv_GetDeviceQueue2(_device, &info, pQueue);
2103 }
2104
2105 static void
2106 fill_geom_tess_rings(struct radv_queue *queue,
2107 uint32_t *map,
2108 bool add_sample_positions,
2109 uint32_t esgs_ring_size,
2110 struct radeon_winsys_bo *esgs_ring_bo,
2111 uint32_t gsvs_ring_size,
2112 struct radeon_winsys_bo *gsvs_ring_bo,
2113 uint32_t tess_factor_ring_size,
2114 uint32_t tess_offchip_ring_offset,
2115 uint32_t tess_offchip_ring_size,
2116 struct radeon_winsys_bo *tess_rings_bo)
2117 {
2118 uint32_t *desc = &map[4];
2119
2120 if (esgs_ring_bo) {
2121 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2122
2123 /* stride 0, num records - size, add tid, swizzle, elsize4,
2124 index stride 64 */
2125 desc[0] = esgs_va;
2126 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2127 S_008F04_STRIDE(0) |
2128 S_008F04_SWIZZLE_ENABLE(true);
2129 desc[2] = esgs_ring_size;
2130 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2131 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2132 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2133 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2134 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2135 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2136 S_008F0C_ELEMENT_SIZE(1) |
2137 S_008F0C_INDEX_STRIDE(3) |
2138 S_008F0C_ADD_TID_ENABLE(true);
2139
2140 /* GS entry for ES->GS ring */
2141 /* stride 0, num records - size, elsize0,
2142 index stride 0 */
2143 desc[4] = esgs_va;
2144 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2145 S_008F04_STRIDE(0) |
2146 S_008F04_SWIZZLE_ENABLE(false);
2147 desc[6] = esgs_ring_size;
2148 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2152 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2154 S_008F0C_ELEMENT_SIZE(0) |
2155 S_008F0C_INDEX_STRIDE(0) |
2156 S_008F0C_ADD_TID_ENABLE(false);
2157 }
2158
2159 desc += 8;
2160
2161 if (gsvs_ring_bo) {
2162 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2163
2164 /* VS entry for GS->VS ring */
2165 /* stride 0, num records - size, elsize0,
2166 index stride 0 */
2167 desc[0] = gsvs_va;
2168 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2169 S_008F04_STRIDE(0) |
2170 S_008F04_SWIZZLE_ENABLE(false);
2171 desc[2] = gsvs_ring_size;
2172 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2173 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2174 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2175 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2176 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2177 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2178 S_008F0C_ELEMENT_SIZE(0) |
2179 S_008F0C_INDEX_STRIDE(0) |
2180 S_008F0C_ADD_TID_ENABLE(false);
2181
2182 /* stride gsvs_itemsize, num records 64
2183 elsize 4, index stride 16 */
2184 /* shader will patch stride and desc[2] */
2185 desc[4] = gsvs_va;
2186 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2187 S_008F04_STRIDE(0) |
2188 S_008F04_SWIZZLE_ENABLE(true);
2189 desc[6] = 0;
2190 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2191 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2192 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2193 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2194 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2196 S_008F0C_ELEMENT_SIZE(1) |
2197 S_008F0C_INDEX_STRIDE(1) |
2198 S_008F0C_ADD_TID_ENABLE(true);
2199 }
2200
2201 desc += 8;
2202
2203 if (tess_rings_bo) {
2204 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2205 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2206
2207 desc[0] = tess_va;
2208 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2209 S_008F04_STRIDE(0) |
2210 S_008F04_SWIZZLE_ENABLE(false);
2211 desc[2] = tess_factor_ring_size;
2212 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2213 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2214 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2215 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2216 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2217 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2218 S_008F0C_ELEMENT_SIZE(0) |
2219 S_008F0C_INDEX_STRIDE(0) |
2220 S_008F0C_ADD_TID_ENABLE(false);
2221
2222 desc[4] = tess_offchip_va;
2223 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2224 S_008F04_STRIDE(0) |
2225 S_008F04_SWIZZLE_ENABLE(false);
2226 desc[6] = tess_offchip_ring_size;
2227 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2228 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2229 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2230 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2231 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2232 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2233 S_008F0C_ELEMENT_SIZE(0) |
2234 S_008F0C_INDEX_STRIDE(0) |
2235 S_008F0C_ADD_TID_ENABLE(false);
2236 }
2237
2238 desc += 8;
2239
2240 if (add_sample_positions) {
2241 /* add sample positions after all rings */
2242 memcpy(desc, queue->device->sample_locations_1x, 8);
2243 desc += 2;
2244 memcpy(desc, queue->device->sample_locations_2x, 16);
2245 desc += 4;
2246 memcpy(desc, queue->device->sample_locations_4x, 32);
2247 desc += 8;
2248 memcpy(desc, queue->device->sample_locations_8x, 64);
2249 }
2250 }
2251
2252 static unsigned
2253 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2254 {
2255 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2256 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2257 device->physical_device->rad_info.family != CHIP_STONEY;
2258 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2259 unsigned max_offchip_buffers;
2260 unsigned offchip_granularity;
2261 unsigned hs_offchip_param;
2262
2263 /*
2264 * Per RadeonSI:
2265 * This must be one less than the maximum number due to a hw limitation.
2266 * Various hardware bugs need thGFX7
2267 *
2268 * Per AMDVLK:
2269 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2270 * Gfx7 should limit max_offchip_buffers to 508
2271 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2272 *
2273 * Follow AMDVLK here.
2274 */
2275 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2276 device->physical_device->rad_info.chip_class == GFX7 ||
2277 device->physical_device->rad_info.chip_class == GFX6)
2278 --max_offchip_buffers_per_se;
2279
2280 max_offchip_buffers = max_offchip_buffers_per_se *
2281 device->physical_device->rad_info.max_se;
2282
2283 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2284 * around by setting 4K granularity.
2285 */
2286 if (device->tess_offchip_block_dw_size == 4096) {
2287 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2288 offchip_granularity = V_03093C_X_4K_DWORDS;
2289 } else {
2290 assert(device->tess_offchip_block_dw_size == 8192);
2291 offchip_granularity = V_03093C_X_8K_DWORDS;
2292 }
2293
2294 switch (device->physical_device->rad_info.chip_class) {
2295 case GFX6:
2296 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2297 break;
2298 case GFX7:
2299 case GFX8:
2300 case GFX9:
2301 default:
2302 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2303 break;
2304 }
2305
2306 *max_offchip_buffers_p = max_offchip_buffers;
2307 if (device->physical_device->rad_info.chip_class >= GFX7) {
2308 if (device->physical_device->rad_info.chip_class >= GFX8)
2309 --max_offchip_buffers;
2310 hs_offchip_param =
2311 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2312 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2313 } else {
2314 hs_offchip_param =
2315 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2316 }
2317 return hs_offchip_param;
2318 }
2319
2320 static void
2321 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2322 struct radeon_winsys_bo *esgs_ring_bo,
2323 uint32_t esgs_ring_size,
2324 struct radeon_winsys_bo *gsvs_ring_bo,
2325 uint32_t gsvs_ring_size)
2326 {
2327 if (!esgs_ring_bo && !gsvs_ring_bo)
2328 return;
2329
2330 if (esgs_ring_bo)
2331 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2332
2333 if (gsvs_ring_bo)
2334 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2335
2336 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2337 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2338 radeon_emit(cs, esgs_ring_size >> 8);
2339 radeon_emit(cs, gsvs_ring_size >> 8);
2340 } else {
2341 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2342 radeon_emit(cs, esgs_ring_size >> 8);
2343 radeon_emit(cs, gsvs_ring_size >> 8);
2344 }
2345 }
2346
2347 static void
2348 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2349 unsigned hs_offchip_param, unsigned tf_ring_size,
2350 struct radeon_winsys_bo *tess_rings_bo)
2351 {
2352 uint64_t tf_va;
2353
2354 if (!tess_rings_bo)
2355 return;
2356
2357 tf_va = radv_buffer_get_va(tess_rings_bo);
2358
2359 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2360
2361 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2362 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2363 S_030938_SIZE(tf_ring_size / 4));
2364 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2365 tf_va >> 8);
2366 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2367 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2368 S_030944_BASE_HI(tf_va >> 40));
2369 }
2370 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2371 hs_offchip_param);
2372 } else {
2373 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2374 S_008988_SIZE(tf_ring_size / 4));
2375 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2376 tf_va >> 8);
2377 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2378 hs_offchip_param);
2379 }
2380 }
2381
2382 static void
2383 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2384 struct radeon_winsys_bo *compute_scratch_bo)
2385 {
2386 uint64_t scratch_va;
2387
2388 if (!compute_scratch_bo)
2389 return;
2390
2391 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2392
2393 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2394
2395 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2396 radeon_emit(cs, scratch_va);
2397 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2398 S_008F04_SWIZZLE_ENABLE(1));
2399 }
2400
2401 static void
2402 radv_emit_global_shader_pointers(struct radv_queue *queue,
2403 struct radeon_cmdbuf *cs,
2404 struct radeon_winsys_bo *descriptor_bo)
2405 {
2406 uint64_t va;
2407
2408 if (!descriptor_bo)
2409 return;
2410
2411 va = radv_buffer_get_va(descriptor_bo);
2412
2413 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2414
2415 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2416 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2417 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2418 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2419 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2420
2421 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2422 radv_emit_shader_pointer(queue->device, cs, regs[i],
2423 va, true);
2424 }
2425 } else {
2426 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2427 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2428 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2429 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2430 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2431 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2432
2433 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2434 radv_emit_shader_pointer(queue->device, cs, regs[i],
2435 va, true);
2436 }
2437 }
2438 }
2439
2440 static void
2441 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2442 {
2443 struct radv_device *device = queue->device;
2444
2445 if (device->gfx_init) {
2446 uint64_t va = radv_buffer_get_va(device->gfx_init);
2447
2448 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2449 radeon_emit(cs, va);
2450 radeon_emit(cs, va >> 32);
2451 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2452
2453 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2454 } else {
2455 struct radv_physical_device *physical_device = device->physical_device;
2456 si_emit_graphics(physical_device, cs);
2457 }
2458 }
2459
2460 static void
2461 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2462 {
2463 struct radv_physical_device *physical_device = queue->device->physical_device;
2464 si_emit_compute(physical_device, cs);
2465 }
2466
2467 static VkResult
2468 radv_get_preamble_cs(struct radv_queue *queue,
2469 uint32_t scratch_size,
2470 uint32_t compute_scratch_size,
2471 uint32_t esgs_ring_size,
2472 uint32_t gsvs_ring_size,
2473 bool needs_tess_rings,
2474 bool needs_sample_positions,
2475 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2476 struct radeon_cmdbuf **initial_preamble_cs,
2477 struct radeon_cmdbuf **continue_preamble_cs)
2478 {
2479 struct radeon_winsys_bo *scratch_bo = NULL;
2480 struct radeon_winsys_bo *descriptor_bo = NULL;
2481 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2482 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2483 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2484 struct radeon_winsys_bo *tess_rings_bo = NULL;
2485 struct radeon_cmdbuf *dest_cs[3] = {0};
2486 bool add_tess_rings = false, add_sample_positions = false;
2487 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2488 unsigned max_offchip_buffers;
2489 unsigned hs_offchip_param = 0;
2490 unsigned tess_offchip_ring_offset;
2491 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2492 if (!queue->has_tess_rings) {
2493 if (needs_tess_rings)
2494 add_tess_rings = true;
2495 }
2496 if (!queue->has_sample_positions) {
2497 if (needs_sample_positions)
2498 add_sample_positions = true;
2499 }
2500 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2501 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2502 &max_offchip_buffers);
2503 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2504 tess_offchip_ring_size = max_offchip_buffers *
2505 queue->device->tess_offchip_block_dw_size * 4;
2506
2507 if (scratch_size <= queue->scratch_size &&
2508 compute_scratch_size <= queue->compute_scratch_size &&
2509 esgs_ring_size <= queue->esgs_ring_size &&
2510 gsvs_ring_size <= queue->gsvs_ring_size &&
2511 !add_tess_rings && !add_sample_positions &&
2512 queue->initial_preamble_cs) {
2513 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2514 *initial_preamble_cs = queue->initial_preamble_cs;
2515 *continue_preamble_cs = queue->continue_preamble_cs;
2516 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2517 *continue_preamble_cs = NULL;
2518 return VK_SUCCESS;
2519 }
2520
2521 if (scratch_size > queue->scratch_size) {
2522 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2523 scratch_size,
2524 4096,
2525 RADEON_DOMAIN_VRAM,
2526 ring_bo_flags,
2527 RADV_BO_PRIORITY_SCRATCH);
2528 if (!scratch_bo)
2529 goto fail;
2530 } else
2531 scratch_bo = queue->scratch_bo;
2532
2533 if (compute_scratch_size > queue->compute_scratch_size) {
2534 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2535 compute_scratch_size,
2536 4096,
2537 RADEON_DOMAIN_VRAM,
2538 ring_bo_flags,
2539 RADV_BO_PRIORITY_SCRATCH);
2540 if (!compute_scratch_bo)
2541 goto fail;
2542
2543 } else
2544 compute_scratch_bo = queue->compute_scratch_bo;
2545
2546 if (esgs_ring_size > queue->esgs_ring_size) {
2547 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2548 esgs_ring_size,
2549 4096,
2550 RADEON_DOMAIN_VRAM,
2551 ring_bo_flags,
2552 RADV_BO_PRIORITY_SCRATCH);
2553 if (!esgs_ring_bo)
2554 goto fail;
2555 } else {
2556 esgs_ring_bo = queue->esgs_ring_bo;
2557 esgs_ring_size = queue->esgs_ring_size;
2558 }
2559
2560 if (gsvs_ring_size > queue->gsvs_ring_size) {
2561 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2562 gsvs_ring_size,
2563 4096,
2564 RADEON_DOMAIN_VRAM,
2565 ring_bo_flags,
2566 RADV_BO_PRIORITY_SCRATCH);
2567 if (!gsvs_ring_bo)
2568 goto fail;
2569 } else {
2570 gsvs_ring_bo = queue->gsvs_ring_bo;
2571 gsvs_ring_size = queue->gsvs_ring_size;
2572 }
2573
2574 if (add_tess_rings) {
2575 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2576 tess_offchip_ring_offset + tess_offchip_ring_size,
2577 256,
2578 RADEON_DOMAIN_VRAM,
2579 ring_bo_flags,
2580 RADV_BO_PRIORITY_SCRATCH);
2581 if (!tess_rings_bo)
2582 goto fail;
2583 } else {
2584 tess_rings_bo = queue->tess_rings_bo;
2585 }
2586
2587 if (scratch_bo != queue->scratch_bo ||
2588 esgs_ring_bo != queue->esgs_ring_bo ||
2589 gsvs_ring_bo != queue->gsvs_ring_bo ||
2590 tess_rings_bo != queue->tess_rings_bo ||
2591 add_sample_positions) {
2592 uint32_t size = 0;
2593 if (gsvs_ring_bo || esgs_ring_bo ||
2594 tess_rings_bo || add_sample_positions) {
2595 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2596 if (add_sample_positions)
2597 size += 128; /* 64+32+16+8 = 120 bytes */
2598 }
2599 else if (scratch_bo)
2600 size = 8; /* 2 dword */
2601
2602 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2603 size,
2604 4096,
2605 RADEON_DOMAIN_VRAM,
2606 RADEON_FLAG_CPU_ACCESS |
2607 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2608 RADEON_FLAG_READ_ONLY,
2609 RADV_BO_PRIORITY_DESCRIPTOR);
2610 if (!descriptor_bo)
2611 goto fail;
2612 } else
2613 descriptor_bo = queue->descriptor_bo;
2614
2615 if (descriptor_bo != queue->descriptor_bo) {
2616 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2617
2618 if (scratch_bo) {
2619 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2620 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2621 S_008F04_SWIZZLE_ENABLE(1);
2622 map[0] = scratch_va;
2623 map[1] = rsrc1;
2624 }
2625
2626 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2627 fill_geom_tess_rings(queue, map, add_sample_positions,
2628 esgs_ring_size, esgs_ring_bo,
2629 gsvs_ring_size, gsvs_ring_bo,
2630 tess_factor_ring_size,
2631 tess_offchip_ring_offset,
2632 tess_offchip_ring_size,
2633 tess_rings_bo);
2634
2635 queue->device->ws->buffer_unmap(descriptor_bo);
2636 }
2637
2638 for(int i = 0; i < 3; ++i) {
2639 struct radeon_cmdbuf *cs = NULL;
2640 cs = queue->device->ws->cs_create(queue->device->ws,
2641 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2642 if (!cs)
2643 goto fail;
2644
2645 dest_cs[i] = cs;
2646
2647 if (scratch_bo)
2648 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2649
2650 /* Emit initial configuration. */
2651 switch (queue->queue_family_index) {
2652 case RADV_QUEUE_GENERAL:
2653 radv_init_graphics_state(cs, queue);
2654 break;
2655 case RADV_QUEUE_COMPUTE:
2656 radv_init_compute_state(cs, queue);
2657 break;
2658 case RADV_QUEUE_TRANSFER:
2659 break;
2660 }
2661
2662 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2663 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2664 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2665 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2666 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2667 }
2668
2669 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2670 gsvs_ring_bo, gsvs_ring_size);
2671 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2672 tess_factor_ring_size, tess_rings_bo);
2673 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2674 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2675
2676 if (i == 0) {
2677 si_cs_emit_cache_flush(cs,
2678 queue->device->physical_device->rad_info.chip_class,
2679 NULL, 0,
2680 queue->queue_family_index == RING_COMPUTE &&
2681 queue->device->physical_device->rad_info.chip_class >= GFX7,
2682 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2683 RADV_CMD_FLAG_INV_ICACHE |
2684 RADV_CMD_FLAG_INV_SMEM_L1 |
2685 RADV_CMD_FLAG_INV_VMEM_L1 |
2686 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2687 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2688 } else if (i == 1) {
2689 si_cs_emit_cache_flush(cs,
2690 queue->device->physical_device->rad_info.chip_class,
2691 NULL, 0,
2692 queue->queue_family_index == RING_COMPUTE &&
2693 queue->device->physical_device->rad_info.chip_class >= GFX7,
2694 RADV_CMD_FLAG_INV_ICACHE |
2695 RADV_CMD_FLAG_INV_SMEM_L1 |
2696 RADV_CMD_FLAG_INV_VMEM_L1 |
2697 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2698 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2699 }
2700
2701 if (!queue->device->ws->cs_finalize(cs))
2702 goto fail;
2703 }
2704
2705 if (queue->initial_full_flush_preamble_cs)
2706 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2707
2708 if (queue->initial_preamble_cs)
2709 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2710
2711 if (queue->continue_preamble_cs)
2712 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2713
2714 queue->initial_full_flush_preamble_cs = dest_cs[0];
2715 queue->initial_preamble_cs = dest_cs[1];
2716 queue->continue_preamble_cs = dest_cs[2];
2717
2718 if (scratch_bo != queue->scratch_bo) {
2719 if (queue->scratch_bo)
2720 queue->device->ws->buffer_destroy(queue->scratch_bo);
2721 queue->scratch_bo = scratch_bo;
2722 queue->scratch_size = scratch_size;
2723 }
2724
2725 if (compute_scratch_bo != queue->compute_scratch_bo) {
2726 if (queue->compute_scratch_bo)
2727 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2728 queue->compute_scratch_bo = compute_scratch_bo;
2729 queue->compute_scratch_size = compute_scratch_size;
2730 }
2731
2732 if (esgs_ring_bo != queue->esgs_ring_bo) {
2733 if (queue->esgs_ring_bo)
2734 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2735 queue->esgs_ring_bo = esgs_ring_bo;
2736 queue->esgs_ring_size = esgs_ring_size;
2737 }
2738
2739 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2740 if (queue->gsvs_ring_bo)
2741 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2742 queue->gsvs_ring_bo = gsvs_ring_bo;
2743 queue->gsvs_ring_size = gsvs_ring_size;
2744 }
2745
2746 if (tess_rings_bo != queue->tess_rings_bo) {
2747 queue->tess_rings_bo = tess_rings_bo;
2748 queue->has_tess_rings = true;
2749 }
2750
2751 if (descriptor_bo != queue->descriptor_bo) {
2752 if (queue->descriptor_bo)
2753 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2754
2755 queue->descriptor_bo = descriptor_bo;
2756 }
2757
2758 if (add_sample_positions)
2759 queue->has_sample_positions = true;
2760
2761 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2762 *initial_preamble_cs = queue->initial_preamble_cs;
2763 *continue_preamble_cs = queue->continue_preamble_cs;
2764 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2765 *continue_preamble_cs = NULL;
2766 return VK_SUCCESS;
2767 fail:
2768 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2769 if (dest_cs[i])
2770 queue->device->ws->cs_destroy(dest_cs[i]);
2771 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2772 queue->device->ws->buffer_destroy(descriptor_bo);
2773 if (scratch_bo && scratch_bo != queue->scratch_bo)
2774 queue->device->ws->buffer_destroy(scratch_bo);
2775 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2776 queue->device->ws->buffer_destroy(compute_scratch_bo);
2777 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2778 queue->device->ws->buffer_destroy(esgs_ring_bo);
2779 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2780 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2781 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2782 queue->device->ws->buffer_destroy(tess_rings_bo);
2783 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2784 }
2785
2786 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2787 struct radv_winsys_sem_counts *counts,
2788 int num_sems,
2789 const VkSemaphore *sems,
2790 VkFence _fence,
2791 bool reset_temp)
2792 {
2793 int syncobj_idx = 0, sem_idx = 0;
2794
2795 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2796 return VK_SUCCESS;
2797
2798 for (uint32_t i = 0; i < num_sems; i++) {
2799 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2800
2801 if (sem->temp_syncobj || sem->syncobj)
2802 counts->syncobj_count++;
2803 else
2804 counts->sem_count++;
2805 }
2806
2807 if (_fence != VK_NULL_HANDLE) {
2808 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2809 if (fence->temp_syncobj || fence->syncobj)
2810 counts->syncobj_count++;
2811 }
2812
2813 if (counts->syncobj_count) {
2814 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2815 if (!counts->syncobj)
2816 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2817 }
2818
2819 if (counts->sem_count) {
2820 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2821 if (!counts->sem) {
2822 free(counts->syncobj);
2823 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2824 }
2825 }
2826
2827 for (uint32_t i = 0; i < num_sems; i++) {
2828 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2829
2830 if (sem->temp_syncobj) {
2831 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2832 }
2833 else if (sem->syncobj)
2834 counts->syncobj[syncobj_idx++] = sem->syncobj;
2835 else {
2836 assert(sem->sem);
2837 counts->sem[sem_idx++] = sem->sem;
2838 }
2839 }
2840
2841 if (_fence != VK_NULL_HANDLE) {
2842 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2843 if (fence->temp_syncobj)
2844 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2845 else if (fence->syncobj)
2846 counts->syncobj[syncobj_idx++] = fence->syncobj;
2847 }
2848
2849 return VK_SUCCESS;
2850 }
2851
2852 static void
2853 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2854 {
2855 free(sem_info->wait.syncobj);
2856 free(sem_info->wait.sem);
2857 free(sem_info->signal.syncobj);
2858 free(sem_info->signal.sem);
2859 }
2860
2861
2862 static void radv_free_temp_syncobjs(struct radv_device *device,
2863 int num_sems,
2864 const VkSemaphore *sems)
2865 {
2866 for (uint32_t i = 0; i < num_sems; i++) {
2867 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2868
2869 if (sem->temp_syncobj) {
2870 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2871 sem->temp_syncobj = 0;
2872 }
2873 }
2874 }
2875
2876 static VkResult
2877 radv_alloc_sem_info(struct radv_instance *instance,
2878 struct radv_winsys_sem_info *sem_info,
2879 int num_wait_sems,
2880 const VkSemaphore *wait_sems,
2881 int num_signal_sems,
2882 const VkSemaphore *signal_sems,
2883 VkFence fence)
2884 {
2885 VkResult ret;
2886 memset(sem_info, 0, sizeof(*sem_info));
2887
2888 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2889 if (ret)
2890 return ret;
2891 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2892 if (ret)
2893 radv_free_sem_info(sem_info);
2894
2895 /* caller can override these */
2896 sem_info->cs_emit_wait = true;
2897 sem_info->cs_emit_signal = true;
2898 return ret;
2899 }
2900
2901 /* Signals fence as soon as all the work currently put on queue is done. */
2902 static VkResult radv_signal_fence(struct radv_queue *queue,
2903 struct radv_fence *fence)
2904 {
2905 int ret;
2906 VkResult result;
2907 struct radv_winsys_sem_info sem_info;
2908
2909 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2910 radv_fence_to_handle(fence));
2911 if (result != VK_SUCCESS)
2912 return result;
2913
2914 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2915 &queue->device->empty_cs[queue->queue_family_index],
2916 1, NULL, NULL, &sem_info, NULL,
2917 false, fence->fence);
2918 radv_free_sem_info(&sem_info);
2919
2920 if (ret)
2921 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2922
2923 return VK_SUCCESS;
2924 }
2925
2926 VkResult radv_QueueSubmit(
2927 VkQueue _queue,
2928 uint32_t submitCount,
2929 const VkSubmitInfo* pSubmits,
2930 VkFence _fence)
2931 {
2932 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2933 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2934 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2935 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2936 int ret;
2937 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2938 uint32_t scratch_size = 0;
2939 uint32_t compute_scratch_size = 0;
2940 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2941 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2942 VkResult result;
2943 bool fence_emitted = false;
2944 bool tess_rings_needed = false;
2945 bool sample_positions_needed = false;
2946
2947 /* Do this first so failing to allocate scratch buffers can't result in
2948 * partially executed submissions. */
2949 for (uint32_t i = 0; i < submitCount; i++) {
2950 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2951 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2952 pSubmits[i].pCommandBuffers[j]);
2953
2954 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2955 compute_scratch_size = MAX2(compute_scratch_size,
2956 cmd_buffer->compute_scratch_size_needed);
2957 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2958 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2959 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2960 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2961 }
2962 }
2963
2964 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2965 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2966 sample_positions_needed, &initial_flush_preamble_cs,
2967 &initial_preamble_cs, &continue_preamble_cs);
2968 if (result != VK_SUCCESS)
2969 return result;
2970
2971 for (uint32_t i = 0; i < submitCount; i++) {
2972 struct radeon_cmdbuf **cs_array;
2973 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2974 bool can_patch = true;
2975 uint32_t advance;
2976 struct radv_winsys_sem_info sem_info;
2977
2978 result = radv_alloc_sem_info(queue->device->instance,
2979 &sem_info,
2980 pSubmits[i].waitSemaphoreCount,
2981 pSubmits[i].pWaitSemaphores,
2982 pSubmits[i].signalSemaphoreCount,
2983 pSubmits[i].pSignalSemaphores,
2984 _fence);
2985 if (result != VK_SUCCESS)
2986 return result;
2987
2988 if (!pSubmits[i].commandBufferCount) {
2989 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2990 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2991 &queue->device->empty_cs[queue->queue_family_index],
2992 1, NULL, NULL,
2993 &sem_info, NULL,
2994 false, base_fence);
2995 if (ret) {
2996 radv_loge("failed to submit CS %d\n", i);
2997 abort();
2998 }
2999 fence_emitted = true;
3000 }
3001 radv_free_sem_info(&sem_info);
3002 continue;
3003 }
3004
3005 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3006 (pSubmits[i].commandBufferCount));
3007
3008 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3009 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3010 pSubmits[i].pCommandBuffers[j]);
3011 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3012
3013 cs_array[j] = cmd_buffer->cs;
3014 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3015 can_patch = false;
3016
3017 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3018 }
3019
3020 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3021 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3022 const struct radv_winsys_bo_list *bo_list = NULL;
3023
3024 advance = MIN2(max_cs_submission,
3025 pSubmits[i].commandBufferCount - j);
3026
3027 if (queue->device->trace_bo)
3028 *queue->device->trace_id_ptr = 0;
3029
3030 sem_info.cs_emit_wait = j == 0;
3031 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3032
3033 if (unlikely(queue->device->use_global_bo_list)) {
3034 pthread_mutex_lock(&queue->device->bo_list.mutex);
3035 bo_list = &queue->device->bo_list.list;
3036 }
3037
3038 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3039 advance, initial_preamble, continue_preamble_cs,
3040 &sem_info, bo_list,
3041 can_patch, base_fence);
3042
3043 if (unlikely(queue->device->use_global_bo_list))
3044 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3045
3046 if (ret) {
3047 radv_loge("failed to submit CS %d\n", i);
3048 abort();
3049 }
3050 fence_emitted = true;
3051 if (queue->device->trace_bo) {
3052 radv_check_gpu_hangs(queue, cs_array[j]);
3053 }
3054 }
3055
3056 radv_free_temp_syncobjs(queue->device,
3057 pSubmits[i].waitSemaphoreCount,
3058 pSubmits[i].pWaitSemaphores);
3059 radv_free_sem_info(&sem_info);
3060 free(cs_array);
3061 }
3062
3063 if (fence) {
3064 if (!fence_emitted) {
3065 result = radv_signal_fence(queue, fence);
3066 if (result != VK_SUCCESS)
3067 return result;
3068 }
3069 }
3070
3071 return VK_SUCCESS;
3072 }
3073
3074 VkResult radv_QueueWaitIdle(
3075 VkQueue _queue)
3076 {
3077 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3078
3079 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3080 radv_queue_family_to_ring(queue->queue_family_index),
3081 queue->queue_idx);
3082 return VK_SUCCESS;
3083 }
3084
3085 VkResult radv_DeviceWaitIdle(
3086 VkDevice _device)
3087 {
3088 RADV_FROM_HANDLE(radv_device, device, _device);
3089
3090 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3091 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3092 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3093 }
3094 }
3095 return VK_SUCCESS;
3096 }
3097
3098 VkResult radv_EnumerateInstanceExtensionProperties(
3099 const char* pLayerName,
3100 uint32_t* pPropertyCount,
3101 VkExtensionProperties* pProperties)
3102 {
3103 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3104
3105 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3106 if (radv_supported_instance_extensions.extensions[i]) {
3107 vk_outarray_append(&out, prop) {
3108 *prop = radv_instance_extensions[i];
3109 }
3110 }
3111 }
3112
3113 return vk_outarray_status(&out);
3114 }
3115
3116 VkResult radv_EnumerateDeviceExtensionProperties(
3117 VkPhysicalDevice physicalDevice,
3118 const char* pLayerName,
3119 uint32_t* pPropertyCount,
3120 VkExtensionProperties* pProperties)
3121 {
3122 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3123 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3124
3125 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3126 if (device->supported_extensions.extensions[i]) {
3127 vk_outarray_append(&out, prop) {
3128 *prop = radv_device_extensions[i];
3129 }
3130 }
3131 }
3132
3133 return vk_outarray_status(&out);
3134 }
3135
3136 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3137 VkInstance _instance,
3138 const char* pName)
3139 {
3140 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3141
3142 return radv_lookup_entrypoint_checked(pName,
3143 instance ? instance->apiVersion : 0,
3144 instance ? &instance->enabled_extensions : NULL,
3145 NULL);
3146 }
3147
3148 /* The loader wants us to expose a second GetInstanceProcAddr function
3149 * to work around certain LD_PRELOAD issues seen in apps.
3150 */
3151 PUBLIC
3152 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3153 VkInstance instance,
3154 const char* pName);
3155
3156 PUBLIC
3157 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3158 VkInstance instance,
3159 const char* pName)
3160 {
3161 return radv_GetInstanceProcAddr(instance, pName);
3162 }
3163
3164 PUBLIC
3165 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3166 VkInstance _instance,
3167 const char* pName);
3168
3169 PUBLIC
3170 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3171 VkInstance _instance,
3172 const char* pName)
3173 {
3174 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3175
3176 return radv_lookup_physical_device_entrypoint_checked(pName,
3177 instance ? instance->apiVersion : 0,
3178 instance ? &instance->enabled_extensions : NULL);
3179 }
3180
3181 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3182 VkDevice _device,
3183 const char* pName)
3184 {
3185 RADV_FROM_HANDLE(radv_device, device, _device);
3186
3187 return radv_lookup_entrypoint_checked(pName,
3188 device->instance->apiVersion,
3189 &device->instance->enabled_extensions,
3190 &device->enabled_extensions);
3191 }
3192
3193 bool radv_get_memory_fd(struct radv_device *device,
3194 struct radv_device_memory *memory,
3195 int *pFD)
3196 {
3197 struct radeon_bo_metadata metadata;
3198
3199 if (memory->image) {
3200 radv_init_metadata(device, memory->image, &metadata);
3201 device->ws->buffer_set_metadata(memory->bo, &metadata);
3202 }
3203
3204 return device->ws->buffer_get_fd(device->ws, memory->bo,
3205 pFD);
3206 }
3207
3208 static VkResult radv_alloc_memory(struct radv_device *device,
3209 const VkMemoryAllocateInfo* pAllocateInfo,
3210 const VkAllocationCallbacks* pAllocator,
3211 VkDeviceMemory* pMem)
3212 {
3213 struct radv_device_memory *mem;
3214 VkResult result;
3215 enum radeon_bo_domain domain;
3216 uint32_t flags = 0;
3217 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3218
3219 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3220
3221 if (pAllocateInfo->allocationSize == 0) {
3222 /* Apparently, this is allowed */
3223 *pMem = VK_NULL_HANDLE;
3224 return VK_SUCCESS;
3225 }
3226
3227 const VkImportMemoryFdInfoKHR *import_info =
3228 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3229 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3230 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3231 const VkExportMemoryAllocateInfo *export_info =
3232 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3233 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3234 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3235
3236 const struct wsi_memory_allocate_info *wsi_info =
3237 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3238
3239 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3240 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3241 if (mem == NULL)
3242 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3243
3244 if (wsi_info && wsi_info->implicit_sync)
3245 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3246
3247 if (dedicate_info) {
3248 mem->image = radv_image_from_handle(dedicate_info->image);
3249 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3250 } else {
3251 mem->image = NULL;
3252 mem->buffer = NULL;
3253 }
3254
3255 float priority_float = 0.5;
3256 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3257 vk_find_struct_const(pAllocateInfo->pNext,
3258 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3259 if (priority_ext)
3260 priority_float = priority_ext->priority;
3261
3262 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3263 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3264
3265 mem->user_ptr = NULL;
3266
3267 if (import_info) {
3268 assert(import_info->handleType ==
3269 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3270 import_info->handleType ==
3271 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3272 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3273 priority, NULL, NULL);
3274 if (!mem->bo) {
3275 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3276 goto fail;
3277 } else {
3278 close(import_info->fd);
3279 }
3280 } else if (host_ptr_info) {
3281 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3282 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3283 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3284 pAllocateInfo->allocationSize,
3285 priority);
3286 if (!mem->bo) {
3287 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3288 goto fail;
3289 } else {
3290 mem->user_ptr = host_ptr_info->pHostPointer;
3291 }
3292 } else {
3293 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3294 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3295 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3296 domain = RADEON_DOMAIN_GTT;
3297 else
3298 domain = RADEON_DOMAIN_VRAM;
3299
3300 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3301 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3302 else
3303 flags |= RADEON_FLAG_CPU_ACCESS;
3304
3305 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3306 flags |= RADEON_FLAG_GTT_WC;
3307
3308 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3309 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3310 if (device->use_global_bo_list) {
3311 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3312 }
3313 }
3314
3315 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3316 domain, flags, priority);
3317
3318 if (!mem->bo) {
3319 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3320 goto fail;
3321 }
3322 mem->type_index = mem_type_index;
3323 }
3324
3325 result = radv_bo_list_add(device, mem->bo);
3326 if (result != VK_SUCCESS)
3327 goto fail_bo;
3328
3329 *pMem = radv_device_memory_to_handle(mem);
3330
3331 return VK_SUCCESS;
3332
3333 fail_bo:
3334 device->ws->buffer_destroy(mem->bo);
3335 fail:
3336 vk_free2(&device->alloc, pAllocator, mem);
3337
3338 return result;
3339 }
3340
3341 VkResult radv_AllocateMemory(
3342 VkDevice _device,
3343 const VkMemoryAllocateInfo* pAllocateInfo,
3344 const VkAllocationCallbacks* pAllocator,
3345 VkDeviceMemory* pMem)
3346 {
3347 RADV_FROM_HANDLE(radv_device, device, _device);
3348 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3349 }
3350
3351 void radv_FreeMemory(
3352 VkDevice _device,
3353 VkDeviceMemory _mem,
3354 const VkAllocationCallbacks* pAllocator)
3355 {
3356 RADV_FROM_HANDLE(radv_device, device, _device);
3357 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3358
3359 if (mem == NULL)
3360 return;
3361
3362 radv_bo_list_remove(device, mem->bo);
3363 device->ws->buffer_destroy(mem->bo);
3364 mem->bo = NULL;
3365
3366 vk_free2(&device->alloc, pAllocator, mem);
3367 }
3368
3369 VkResult radv_MapMemory(
3370 VkDevice _device,
3371 VkDeviceMemory _memory,
3372 VkDeviceSize offset,
3373 VkDeviceSize size,
3374 VkMemoryMapFlags flags,
3375 void** ppData)
3376 {
3377 RADV_FROM_HANDLE(radv_device, device, _device);
3378 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3379
3380 if (mem == NULL) {
3381 *ppData = NULL;
3382 return VK_SUCCESS;
3383 }
3384
3385 if (mem->user_ptr)
3386 *ppData = mem->user_ptr;
3387 else
3388 *ppData = device->ws->buffer_map(mem->bo);
3389
3390 if (*ppData) {
3391 *ppData += offset;
3392 return VK_SUCCESS;
3393 }
3394
3395 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3396 }
3397
3398 void radv_UnmapMemory(
3399 VkDevice _device,
3400 VkDeviceMemory _memory)
3401 {
3402 RADV_FROM_HANDLE(radv_device, device, _device);
3403 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3404
3405 if (mem == NULL)
3406 return;
3407
3408 if (mem->user_ptr == NULL)
3409 device->ws->buffer_unmap(mem->bo);
3410 }
3411
3412 VkResult radv_FlushMappedMemoryRanges(
3413 VkDevice _device,
3414 uint32_t memoryRangeCount,
3415 const VkMappedMemoryRange* pMemoryRanges)
3416 {
3417 return VK_SUCCESS;
3418 }
3419
3420 VkResult radv_InvalidateMappedMemoryRanges(
3421 VkDevice _device,
3422 uint32_t memoryRangeCount,
3423 const VkMappedMemoryRange* pMemoryRanges)
3424 {
3425 return VK_SUCCESS;
3426 }
3427
3428 void radv_GetBufferMemoryRequirements(
3429 VkDevice _device,
3430 VkBuffer _buffer,
3431 VkMemoryRequirements* pMemoryRequirements)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3435
3436 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3437
3438 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3439 pMemoryRequirements->alignment = 4096;
3440 else
3441 pMemoryRequirements->alignment = 16;
3442
3443 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3444 }
3445
3446 void radv_GetBufferMemoryRequirements2(
3447 VkDevice device,
3448 const VkBufferMemoryRequirementsInfo2 *pInfo,
3449 VkMemoryRequirements2 *pMemoryRequirements)
3450 {
3451 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3452 &pMemoryRequirements->memoryRequirements);
3453 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3454 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3455 switch (ext->sType) {
3456 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3457 VkMemoryDedicatedRequirements *req =
3458 (VkMemoryDedicatedRequirements *) ext;
3459 req->requiresDedicatedAllocation = buffer->shareable;
3460 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3461 break;
3462 }
3463 default:
3464 break;
3465 }
3466 }
3467 }
3468
3469 void radv_GetImageMemoryRequirements(
3470 VkDevice _device,
3471 VkImage _image,
3472 VkMemoryRequirements* pMemoryRequirements)
3473 {
3474 RADV_FROM_HANDLE(radv_device, device, _device);
3475 RADV_FROM_HANDLE(radv_image, image, _image);
3476
3477 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3478
3479 pMemoryRequirements->size = image->size;
3480 pMemoryRequirements->alignment = image->alignment;
3481 }
3482
3483 void radv_GetImageMemoryRequirements2(
3484 VkDevice device,
3485 const VkImageMemoryRequirementsInfo2 *pInfo,
3486 VkMemoryRequirements2 *pMemoryRequirements)
3487 {
3488 radv_GetImageMemoryRequirements(device, pInfo->image,
3489 &pMemoryRequirements->memoryRequirements);
3490
3491 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3492
3493 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3494 switch (ext->sType) {
3495 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3496 VkMemoryDedicatedRequirements *req =
3497 (VkMemoryDedicatedRequirements *) ext;
3498 req->requiresDedicatedAllocation = image->shareable;
3499 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3500 break;
3501 }
3502 default:
3503 break;
3504 }
3505 }
3506 }
3507
3508 void radv_GetImageSparseMemoryRequirements(
3509 VkDevice device,
3510 VkImage image,
3511 uint32_t* pSparseMemoryRequirementCount,
3512 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3513 {
3514 stub();
3515 }
3516
3517 void radv_GetImageSparseMemoryRequirements2(
3518 VkDevice device,
3519 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3520 uint32_t* pSparseMemoryRequirementCount,
3521 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3522 {
3523 stub();
3524 }
3525
3526 void radv_GetDeviceMemoryCommitment(
3527 VkDevice device,
3528 VkDeviceMemory memory,
3529 VkDeviceSize* pCommittedMemoryInBytes)
3530 {
3531 *pCommittedMemoryInBytes = 0;
3532 }
3533
3534 VkResult radv_BindBufferMemory2(VkDevice device,
3535 uint32_t bindInfoCount,
3536 const VkBindBufferMemoryInfo *pBindInfos)
3537 {
3538 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3539 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3540 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3541
3542 if (mem) {
3543 buffer->bo = mem->bo;
3544 buffer->offset = pBindInfos[i].memoryOffset;
3545 } else {
3546 buffer->bo = NULL;
3547 }
3548 }
3549 return VK_SUCCESS;
3550 }
3551
3552 VkResult radv_BindBufferMemory(
3553 VkDevice device,
3554 VkBuffer buffer,
3555 VkDeviceMemory memory,
3556 VkDeviceSize memoryOffset)
3557 {
3558 const VkBindBufferMemoryInfo info = {
3559 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3560 .buffer = buffer,
3561 .memory = memory,
3562 .memoryOffset = memoryOffset
3563 };
3564
3565 return radv_BindBufferMemory2(device, 1, &info);
3566 }
3567
3568 VkResult radv_BindImageMemory2(VkDevice device,
3569 uint32_t bindInfoCount,
3570 const VkBindImageMemoryInfo *pBindInfos)
3571 {
3572 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3573 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3574 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3575
3576 if (mem) {
3577 image->bo = mem->bo;
3578 image->offset = pBindInfos[i].memoryOffset;
3579 } else {
3580 image->bo = NULL;
3581 image->offset = 0;
3582 }
3583 }
3584 return VK_SUCCESS;
3585 }
3586
3587
3588 VkResult radv_BindImageMemory(
3589 VkDevice device,
3590 VkImage image,
3591 VkDeviceMemory memory,
3592 VkDeviceSize memoryOffset)
3593 {
3594 const VkBindImageMemoryInfo info = {
3595 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3596 .image = image,
3597 .memory = memory,
3598 .memoryOffset = memoryOffset
3599 };
3600
3601 return radv_BindImageMemory2(device, 1, &info);
3602 }
3603
3604
3605 static void
3606 radv_sparse_buffer_bind_memory(struct radv_device *device,
3607 const VkSparseBufferMemoryBindInfo *bind)
3608 {
3609 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3610
3611 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3612 struct radv_device_memory *mem = NULL;
3613
3614 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3615 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3616
3617 device->ws->buffer_virtual_bind(buffer->bo,
3618 bind->pBinds[i].resourceOffset,
3619 bind->pBinds[i].size,
3620 mem ? mem->bo : NULL,
3621 bind->pBinds[i].memoryOffset);
3622 }
3623 }
3624
3625 static void
3626 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3627 const VkSparseImageOpaqueMemoryBindInfo *bind)
3628 {
3629 RADV_FROM_HANDLE(radv_image, image, bind->image);
3630
3631 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3632 struct radv_device_memory *mem = NULL;
3633
3634 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3635 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3636
3637 device->ws->buffer_virtual_bind(image->bo,
3638 bind->pBinds[i].resourceOffset,
3639 bind->pBinds[i].size,
3640 mem ? mem->bo : NULL,
3641 bind->pBinds[i].memoryOffset);
3642 }
3643 }
3644
3645 VkResult radv_QueueBindSparse(
3646 VkQueue _queue,
3647 uint32_t bindInfoCount,
3648 const VkBindSparseInfo* pBindInfo,
3649 VkFence _fence)
3650 {
3651 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3652 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3653 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3654 bool fence_emitted = false;
3655 VkResult result;
3656 int ret;
3657
3658 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3659 struct radv_winsys_sem_info sem_info;
3660 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3661 radv_sparse_buffer_bind_memory(queue->device,
3662 pBindInfo[i].pBufferBinds + j);
3663 }
3664
3665 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3666 radv_sparse_image_opaque_bind_memory(queue->device,
3667 pBindInfo[i].pImageOpaqueBinds + j);
3668 }
3669
3670 VkResult result;
3671 result = radv_alloc_sem_info(queue->device->instance,
3672 &sem_info,
3673 pBindInfo[i].waitSemaphoreCount,
3674 pBindInfo[i].pWaitSemaphores,
3675 pBindInfo[i].signalSemaphoreCount,
3676 pBindInfo[i].pSignalSemaphores,
3677 _fence);
3678 if (result != VK_SUCCESS)
3679 return result;
3680
3681 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3682 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3683 &queue->device->empty_cs[queue->queue_family_index],
3684 1, NULL, NULL,
3685 &sem_info, NULL,
3686 false, base_fence);
3687 if (ret) {
3688 radv_loge("failed to submit CS %d\n", i);
3689 abort();
3690 }
3691
3692 fence_emitted = true;
3693 }
3694
3695 radv_free_sem_info(&sem_info);
3696
3697 }
3698
3699 if (fence) {
3700 if (!fence_emitted) {
3701 result = radv_signal_fence(queue, fence);
3702 if (result != VK_SUCCESS)
3703 return result;
3704 }
3705 }
3706
3707 return VK_SUCCESS;
3708 }
3709
3710 VkResult radv_CreateFence(
3711 VkDevice _device,
3712 const VkFenceCreateInfo* pCreateInfo,
3713 const VkAllocationCallbacks* pAllocator,
3714 VkFence* pFence)
3715 {
3716 RADV_FROM_HANDLE(radv_device, device, _device);
3717 const VkExportFenceCreateInfo *export =
3718 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3719 VkExternalFenceHandleTypeFlags handleTypes =
3720 export ? export->handleTypes : 0;
3721
3722 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3723 sizeof(*fence), 8,
3724 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3725
3726 if (!fence)
3727 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3728
3729 fence->fence_wsi = NULL;
3730 fence->temp_syncobj = 0;
3731 if (device->always_use_syncobj || handleTypes) {
3732 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3733 if (ret) {
3734 vk_free2(&device->alloc, pAllocator, fence);
3735 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3736 }
3737 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3738 device->ws->signal_syncobj(device->ws, fence->syncobj);
3739 }
3740 fence->fence = NULL;
3741 } else {
3742 fence->fence = device->ws->create_fence();
3743 if (!fence->fence) {
3744 vk_free2(&device->alloc, pAllocator, fence);
3745 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3746 }
3747 fence->syncobj = 0;
3748 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3749 device->ws->signal_fence(fence->fence);
3750 }
3751
3752 *pFence = radv_fence_to_handle(fence);
3753
3754 return VK_SUCCESS;
3755 }
3756
3757 void radv_DestroyFence(
3758 VkDevice _device,
3759 VkFence _fence,
3760 const VkAllocationCallbacks* pAllocator)
3761 {
3762 RADV_FROM_HANDLE(radv_device, device, _device);
3763 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3764
3765 if (!fence)
3766 return;
3767
3768 if (fence->temp_syncobj)
3769 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3770 if (fence->syncobj)
3771 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3772 if (fence->fence)
3773 device->ws->destroy_fence(fence->fence);
3774 if (fence->fence_wsi)
3775 fence->fence_wsi->destroy(fence->fence_wsi);
3776 vk_free2(&device->alloc, pAllocator, fence);
3777 }
3778
3779
3780 uint64_t radv_get_current_time(void)
3781 {
3782 struct timespec tv;
3783 clock_gettime(CLOCK_MONOTONIC, &tv);
3784 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3785 }
3786
3787 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3788 {
3789 uint64_t current_time = radv_get_current_time();
3790
3791 timeout = MIN2(UINT64_MAX - current_time, timeout);
3792
3793 return current_time + timeout;
3794 }
3795
3796
3797 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3798 uint32_t fenceCount, const VkFence *pFences)
3799 {
3800 for (uint32_t i = 0; i < fenceCount; ++i) {
3801 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3802 if (fence->fence == NULL || fence->syncobj ||
3803 fence->temp_syncobj || fence->fence_wsi ||
3804 (!device->ws->is_fence_waitable(fence->fence)))
3805 return false;
3806 }
3807 return true;
3808 }
3809
3810 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3811 {
3812 for (uint32_t i = 0; i < fenceCount; ++i) {
3813 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3814 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3815 return false;
3816 }
3817 return true;
3818 }
3819
3820 VkResult radv_WaitForFences(
3821 VkDevice _device,
3822 uint32_t fenceCount,
3823 const VkFence* pFences,
3824 VkBool32 waitAll,
3825 uint64_t timeout)
3826 {
3827 RADV_FROM_HANDLE(radv_device, device, _device);
3828 timeout = radv_get_absolute_timeout(timeout);
3829
3830 if (device->always_use_syncobj &&
3831 radv_all_fences_syncobj(fenceCount, pFences))
3832 {
3833 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3834 if (!handles)
3835 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3836
3837 for (uint32_t i = 0; i < fenceCount; ++i) {
3838 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3839 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3840 }
3841
3842 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3843
3844 free(handles);
3845 return success ? VK_SUCCESS : VK_TIMEOUT;
3846 }
3847
3848 if (!waitAll && fenceCount > 1) {
3849 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3850 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3851 uint32_t wait_count = 0;
3852 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3853 if (!fences)
3854 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3855
3856 for (uint32_t i = 0; i < fenceCount; ++i) {
3857 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3858
3859 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3860 free(fences);
3861 return VK_SUCCESS;
3862 }
3863
3864 fences[wait_count++] = fence->fence;
3865 }
3866
3867 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3868 waitAll, timeout - radv_get_current_time());
3869
3870 free(fences);
3871 return success ? VK_SUCCESS : VK_TIMEOUT;
3872 }
3873
3874 while(radv_get_current_time() <= timeout) {
3875 for (uint32_t i = 0; i < fenceCount; ++i) {
3876 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3877 return VK_SUCCESS;
3878 }
3879 }
3880 return VK_TIMEOUT;
3881 }
3882
3883 for (uint32_t i = 0; i < fenceCount; ++i) {
3884 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3885 bool expired = false;
3886
3887 if (fence->temp_syncobj) {
3888 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3889 return VK_TIMEOUT;
3890 continue;
3891 }
3892
3893 if (fence->syncobj) {
3894 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3895 return VK_TIMEOUT;
3896 continue;
3897 }
3898
3899 if (fence->fence) {
3900 if (!device->ws->is_fence_waitable(fence->fence)) {
3901 while(!device->ws->is_fence_waitable(fence->fence) &&
3902 radv_get_current_time() <= timeout)
3903 /* Do nothing */;
3904 }
3905
3906 expired = device->ws->fence_wait(device->ws,
3907 fence->fence,
3908 true, timeout);
3909 if (!expired)
3910 return VK_TIMEOUT;
3911 }
3912
3913 if (fence->fence_wsi) {
3914 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3915 if (result != VK_SUCCESS)
3916 return result;
3917 }
3918 }
3919
3920 return VK_SUCCESS;
3921 }
3922
3923 VkResult radv_ResetFences(VkDevice _device,
3924 uint32_t fenceCount,
3925 const VkFence *pFences)
3926 {
3927 RADV_FROM_HANDLE(radv_device, device, _device);
3928
3929 for (unsigned i = 0; i < fenceCount; ++i) {
3930 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3931 if (fence->fence)
3932 device->ws->reset_fence(fence->fence);
3933
3934 /* Per spec, we first restore the permanent payload, and then reset, so
3935 * having a temp syncobj should not skip resetting the permanent syncobj. */
3936 if (fence->temp_syncobj) {
3937 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3938 fence->temp_syncobj = 0;
3939 }
3940
3941 if (fence->syncobj) {
3942 device->ws->reset_syncobj(device->ws, fence->syncobj);
3943 }
3944 }
3945
3946 return VK_SUCCESS;
3947 }
3948
3949 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3950 {
3951 RADV_FROM_HANDLE(radv_device, device, _device);
3952 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3953
3954 if (fence->temp_syncobj) {
3955 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3956 return success ? VK_SUCCESS : VK_NOT_READY;
3957 }
3958
3959 if (fence->syncobj) {
3960 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3961 return success ? VK_SUCCESS : VK_NOT_READY;
3962 }
3963
3964 if (fence->fence) {
3965 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3966 return VK_NOT_READY;
3967 }
3968 if (fence->fence_wsi) {
3969 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3970
3971 if (result != VK_SUCCESS) {
3972 if (result == VK_TIMEOUT)
3973 return VK_NOT_READY;
3974 return result;
3975 }
3976 }
3977 return VK_SUCCESS;
3978 }
3979
3980
3981 // Queue semaphore functions
3982
3983 VkResult radv_CreateSemaphore(
3984 VkDevice _device,
3985 const VkSemaphoreCreateInfo* pCreateInfo,
3986 const VkAllocationCallbacks* pAllocator,
3987 VkSemaphore* pSemaphore)
3988 {
3989 RADV_FROM_HANDLE(radv_device, device, _device);
3990 const VkExportSemaphoreCreateInfo *export =
3991 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3992 VkExternalSemaphoreHandleTypeFlags handleTypes =
3993 export ? export->handleTypes : 0;
3994
3995 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3996 sizeof(*sem), 8,
3997 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3998 if (!sem)
3999 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4000
4001 sem->temp_syncobj = 0;
4002 /* create a syncobject if we are going to export this semaphore */
4003 if (device->always_use_syncobj || handleTypes) {
4004 assert (device->physical_device->rad_info.has_syncobj);
4005 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4006 if (ret) {
4007 vk_free2(&device->alloc, pAllocator, sem);
4008 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4009 }
4010 sem->sem = NULL;
4011 } else {
4012 sem->sem = device->ws->create_sem(device->ws);
4013 if (!sem->sem) {
4014 vk_free2(&device->alloc, pAllocator, sem);
4015 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4016 }
4017 sem->syncobj = 0;
4018 }
4019
4020 *pSemaphore = radv_semaphore_to_handle(sem);
4021 return VK_SUCCESS;
4022 }
4023
4024 void radv_DestroySemaphore(
4025 VkDevice _device,
4026 VkSemaphore _semaphore,
4027 const VkAllocationCallbacks* pAllocator)
4028 {
4029 RADV_FROM_HANDLE(radv_device, device, _device);
4030 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4031 if (!_semaphore)
4032 return;
4033
4034 if (sem->syncobj)
4035 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4036 else
4037 device->ws->destroy_sem(sem->sem);
4038 vk_free2(&device->alloc, pAllocator, sem);
4039 }
4040
4041 VkResult radv_CreateEvent(
4042 VkDevice _device,
4043 const VkEventCreateInfo* pCreateInfo,
4044 const VkAllocationCallbacks* pAllocator,
4045 VkEvent* pEvent)
4046 {
4047 RADV_FROM_HANDLE(radv_device, device, _device);
4048 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4049 sizeof(*event), 8,
4050 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4051
4052 if (!event)
4053 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4054
4055 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4056 RADEON_DOMAIN_GTT,
4057 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4058 RADV_BO_PRIORITY_FENCE);
4059 if (!event->bo) {
4060 vk_free2(&device->alloc, pAllocator, event);
4061 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4062 }
4063
4064 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4065
4066 *pEvent = radv_event_to_handle(event);
4067
4068 return VK_SUCCESS;
4069 }
4070
4071 void radv_DestroyEvent(
4072 VkDevice _device,
4073 VkEvent _event,
4074 const VkAllocationCallbacks* pAllocator)
4075 {
4076 RADV_FROM_HANDLE(radv_device, device, _device);
4077 RADV_FROM_HANDLE(radv_event, event, _event);
4078
4079 if (!event)
4080 return;
4081 device->ws->buffer_destroy(event->bo);
4082 vk_free2(&device->alloc, pAllocator, event);
4083 }
4084
4085 VkResult radv_GetEventStatus(
4086 VkDevice _device,
4087 VkEvent _event)
4088 {
4089 RADV_FROM_HANDLE(radv_event, event, _event);
4090
4091 if (*event->map == 1)
4092 return VK_EVENT_SET;
4093 return VK_EVENT_RESET;
4094 }
4095
4096 VkResult radv_SetEvent(
4097 VkDevice _device,
4098 VkEvent _event)
4099 {
4100 RADV_FROM_HANDLE(radv_event, event, _event);
4101 *event->map = 1;
4102
4103 return VK_SUCCESS;
4104 }
4105
4106 VkResult radv_ResetEvent(
4107 VkDevice _device,
4108 VkEvent _event)
4109 {
4110 RADV_FROM_HANDLE(radv_event, event, _event);
4111 *event->map = 0;
4112
4113 return VK_SUCCESS;
4114 }
4115
4116 VkResult radv_CreateBuffer(
4117 VkDevice _device,
4118 const VkBufferCreateInfo* pCreateInfo,
4119 const VkAllocationCallbacks* pAllocator,
4120 VkBuffer* pBuffer)
4121 {
4122 RADV_FROM_HANDLE(radv_device, device, _device);
4123 struct radv_buffer *buffer;
4124
4125 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4126
4127 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4128 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4129 if (buffer == NULL)
4130 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4131
4132 buffer->size = pCreateInfo->size;
4133 buffer->usage = pCreateInfo->usage;
4134 buffer->bo = NULL;
4135 buffer->offset = 0;
4136 buffer->flags = pCreateInfo->flags;
4137
4138 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4139 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4140
4141 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4142 buffer->bo = device->ws->buffer_create(device->ws,
4143 align64(buffer->size, 4096),
4144 4096, 0, RADEON_FLAG_VIRTUAL,
4145 RADV_BO_PRIORITY_VIRTUAL);
4146 if (!buffer->bo) {
4147 vk_free2(&device->alloc, pAllocator, buffer);
4148 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4149 }
4150 }
4151
4152 *pBuffer = radv_buffer_to_handle(buffer);
4153
4154 return VK_SUCCESS;
4155 }
4156
4157 void radv_DestroyBuffer(
4158 VkDevice _device,
4159 VkBuffer _buffer,
4160 const VkAllocationCallbacks* pAllocator)
4161 {
4162 RADV_FROM_HANDLE(radv_device, device, _device);
4163 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4164
4165 if (!buffer)
4166 return;
4167
4168 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4169 device->ws->buffer_destroy(buffer->bo);
4170
4171 vk_free2(&device->alloc, pAllocator, buffer);
4172 }
4173
4174 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4175 VkDevice device,
4176 const VkBufferDeviceAddressInfoEXT* pInfo)
4177 {
4178 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4179 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4180 }
4181
4182
4183 static inline unsigned
4184 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4185 {
4186 if (stencil)
4187 return plane->surface.u.legacy.stencil_tiling_index[level];
4188 else
4189 return plane->surface.u.legacy.tiling_index[level];
4190 }
4191
4192 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4193 {
4194 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4195 }
4196
4197 static uint32_t
4198 radv_init_dcc_control_reg(struct radv_device *device,
4199 struct radv_image_view *iview)
4200 {
4201 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4202 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4203 unsigned max_compressed_block_size;
4204 unsigned independent_64b_blocks;
4205
4206 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4207 return 0;
4208
4209 if (iview->image->info.samples > 1) {
4210 if (iview->image->planes[0].surface.bpe == 1)
4211 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4212 else if (iview->image->planes[0].surface.bpe == 2)
4213 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4214 }
4215
4216 if (!device->physical_device->rad_info.has_dedicated_vram) {
4217 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4218 * dGPU and 64 for APU because all of our APUs to date use
4219 * DIMMs which have a request granularity size of 64B while all
4220 * other chips have a 32B request size.
4221 */
4222 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4223 }
4224
4225 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4226 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4227 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4228 /* If this DCC image is potentially going to be used in texture
4229 * fetches, we need some special settings.
4230 */
4231 independent_64b_blocks = 1;
4232 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4233 } else {
4234 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4235 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4236 * big as possible for better compression state.
4237 */
4238 independent_64b_blocks = 0;
4239 max_compressed_block_size = max_uncompressed_block_size;
4240 }
4241
4242 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4243 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4244 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4245 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4246 }
4247
4248 static void
4249 radv_initialise_color_surface(struct radv_device *device,
4250 struct radv_color_buffer_info *cb,
4251 struct radv_image_view *iview)
4252 {
4253 const struct vk_format_description *desc;
4254 unsigned ntype, format, swap, endian;
4255 unsigned blend_clamp = 0, blend_bypass = 0;
4256 uint64_t va;
4257 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4258 const struct radeon_surf *surf = &plane->surface;
4259
4260 desc = vk_format_description(iview->vk_format);
4261
4262 memset(cb, 0, sizeof(*cb));
4263
4264 /* Intensity is implemented as Red, so treat it that way. */
4265 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4266
4267 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4268
4269 cb->cb_color_base = va >> 8;
4270
4271 if (device->physical_device->rad_info.chip_class >= GFX9) {
4272 struct gfx9_surf_meta_flags meta;
4273 if (iview->image->dcc_offset)
4274 meta = surf->u.gfx9.dcc;
4275 else
4276 meta = surf->u.gfx9.cmask;
4277
4278 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4279 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4280 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4281 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4282
4283 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4284 cb->cb_color_base |= surf->tile_swizzle;
4285
4286 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4287 } else {
4288 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4289 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4290
4291 cb->cb_color_base += level_info->offset >> 8;
4292 if (level_info->mode == RADEON_SURF_MODE_2D)
4293 cb->cb_color_base |= surf->tile_swizzle;
4294
4295 pitch_tile_max = level_info->nblk_x / 8 - 1;
4296 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4297 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4298
4299 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4300 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4301 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4302
4303 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4304
4305 if (radv_image_has_fmask(iview->image)) {
4306 if (device->physical_device->rad_info.chip_class >= GFX7)
4307 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4308 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4309 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4310 } else {
4311 /* This must be set for fast clear to work without FMASK. */
4312 if (device->physical_device->rad_info.chip_class >= GFX7)
4313 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4314 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4315 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4316 }
4317 }
4318
4319 /* CMASK variables */
4320 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4321 va += iview->image->cmask.offset;
4322 cb->cb_color_cmask = va >> 8;
4323
4324 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4325 va += iview->image->dcc_offset;
4326
4327 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4328 device->physical_device->rad_info.chip_class <= GFX8)
4329 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4330
4331 cb->cb_dcc_base = va >> 8;
4332 cb->cb_dcc_base |= surf->tile_swizzle;
4333
4334 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4335 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4336 S_028C6C_SLICE_MAX(max_slice);
4337
4338 if (iview->image->info.samples > 1) {
4339 unsigned log_samples = util_logbase2(iview->image->info.samples);
4340
4341 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4342 S_028C74_NUM_FRAGMENTS(log_samples);
4343 }
4344
4345 if (radv_image_has_fmask(iview->image)) {
4346 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4347 cb->cb_color_fmask = va >> 8;
4348 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4349 } else {
4350 cb->cb_color_fmask = cb->cb_color_base;
4351 }
4352
4353 ntype = radv_translate_color_numformat(iview->vk_format,
4354 desc,
4355 vk_format_get_first_non_void_channel(iview->vk_format));
4356 format = radv_translate_colorformat(iview->vk_format);
4357 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4358 radv_finishme("Illegal color\n");
4359 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4360 endian = radv_colorformat_endian_swap(format);
4361
4362 /* blend clamp should be set for all NORM/SRGB types */
4363 if (ntype == V_028C70_NUMBER_UNORM ||
4364 ntype == V_028C70_NUMBER_SNORM ||
4365 ntype == V_028C70_NUMBER_SRGB)
4366 blend_clamp = 1;
4367
4368 /* set blend bypass according to docs if SINT/UINT or
4369 8/24 COLOR variants */
4370 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4371 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4372 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4373 blend_clamp = 0;
4374 blend_bypass = 1;
4375 }
4376 #if 0
4377 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4378 (format == V_028C70_COLOR_8 ||
4379 format == V_028C70_COLOR_8_8 ||
4380 format == V_028C70_COLOR_8_8_8_8))
4381 ->color_is_int8 = true;
4382 #endif
4383 cb->cb_color_info = S_028C70_FORMAT(format) |
4384 S_028C70_COMP_SWAP(swap) |
4385 S_028C70_BLEND_CLAMP(blend_clamp) |
4386 S_028C70_BLEND_BYPASS(blend_bypass) |
4387 S_028C70_SIMPLE_FLOAT(1) |
4388 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4389 ntype != V_028C70_NUMBER_SNORM &&
4390 ntype != V_028C70_NUMBER_SRGB &&
4391 format != V_028C70_COLOR_8_24 &&
4392 format != V_028C70_COLOR_24_8) |
4393 S_028C70_NUMBER_TYPE(ntype) |
4394 S_028C70_ENDIAN(endian);
4395 if (radv_image_has_fmask(iview->image)) {
4396 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4397 if (device->physical_device->rad_info.chip_class == GFX6) {
4398 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4399 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4400 }
4401
4402 if (radv_image_is_tc_compat_cmask(iview->image)) {
4403 /* Allow the texture block to read FMASK directly
4404 * without decompressing it. This bit must be cleared
4405 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4406 * otherwise the operation doesn't happen.
4407 */
4408 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4409
4410 /* Set CMASK into a tiling format that allows the
4411 * texture block to read it.
4412 */
4413 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4414 }
4415 }
4416
4417 if (radv_image_has_cmask(iview->image) &&
4418 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4419 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4420
4421 if (radv_dcc_enabled(iview->image, iview->base_mip))
4422 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4423
4424 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4425
4426 /* This must be set for fast clear to work without FMASK. */
4427 if (!radv_image_has_fmask(iview->image) &&
4428 device->physical_device->rad_info.chip_class == GFX6) {
4429 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4430 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4431 }
4432
4433 if (device->physical_device->rad_info.chip_class >= GFX9) {
4434 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4435
4436 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4437 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4438 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4439 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4440
4441 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4442 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4443 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4444 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4445 S_028C68_MIP0_HEIGHT(height - 1) |
4446 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4447 }
4448 }
4449
4450 static unsigned
4451 radv_calc_decompress_on_z_planes(struct radv_device *device,
4452 struct radv_image_view *iview)
4453 {
4454 unsigned max_zplanes = 0;
4455
4456 assert(radv_image_is_tc_compat_htile(iview->image));
4457
4458 if (device->physical_device->rad_info.chip_class >= GFX9) {
4459 /* Default value for 32-bit depth surfaces. */
4460 max_zplanes = 4;
4461
4462 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4463 iview->image->info.samples > 1)
4464 max_zplanes = 2;
4465
4466 max_zplanes = max_zplanes + 1;
4467 } else {
4468 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4469 /* Do not enable Z plane compression for 16-bit depth
4470 * surfaces because isn't supported on GFX8. Only
4471 * 32-bit depth surfaces are supported by the hardware.
4472 * This allows to maintain shader compatibility and to
4473 * reduce the number of depth decompressions.
4474 */
4475 max_zplanes = 1;
4476 } else {
4477 if (iview->image->info.samples <= 1)
4478 max_zplanes = 5;
4479 else if (iview->image->info.samples <= 4)
4480 max_zplanes = 3;
4481 else
4482 max_zplanes = 2;
4483 }
4484 }
4485
4486 return max_zplanes;
4487 }
4488
4489 static void
4490 radv_initialise_ds_surface(struct radv_device *device,
4491 struct radv_ds_buffer_info *ds,
4492 struct radv_image_view *iview)
4493 {
4494 unsigned level = iview->base_mip;
4495 unsigned format, stencil_format;
4496 uint64_t va, s_offs, z_offs;
4497 bool stencil_only = false;
4498 const struct radv_image_plane *plane = &iview->image->planes[0];
4499 const struct radeon_surf *surf = &plane->surface;
4500
4501 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4502
4503 memset(ds, 0, sizeof(*ds));
4504 switch (iview->image->vk_format) {
4505 case VK_FORMAT_D24_UNORM_S8_UINT:
4506 case VK_FORMAT_X8_D24_UNORM_PACK32:
4507 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4508 ds->offset_scale = 2.0f;
4509 break;
4510 case VK_FORMAT_D16_UNORM:
4511 case VK_FORMAT_D16_UNORM_S8_UINT:
4512 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4513 ds->offset_scale = 4.0f;
4514 break;
4515 case VK_FORMAT_D32_SFLOAT:
4516 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4517 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4518 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4519 ds->offset_scale = 1.0f;
4520 break;
4521 case VK_FORMAT_S8_UINT:
4522 stencil_only = true;
4523 break;
4524 default:
4525 break;
4526 }
4527
4528 format = radv_translate_dbformat(iview->image->vk_format);
4529 stencil_format = surf->has_stencil ?
4530 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4531
4532 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4533 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4534 S_028008_SLICE_MAX(max_slice);
4535
4536 ds->db_htile_data_base = 0;
4537 ds->db_htile_surface = 0;
4538
4539 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4540 s_offs = z_offs = va;
4541
4542 if (device->physical_device->rad_info.chip_class >= GFX9) {
4543 assert(surf->u.gfx9.surf_offset == 0);
4544 s_offs += surf->u.gfx9.stencil_offset;
4545
4546 ds->db_z_info = S_028038_FORMAT(format) |
4547 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4548 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4549 S_028038_MAXMIP(iview->image->info.levels - 1) |
4550 S_028038_ZRANGE_PRECISION(1);
4551 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4552 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4553
4554 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4555 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4556 ds->db_depth_view |= S_028008_MIPID(level);
4557
4558 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4559 S_02801C_Y_MAX(iview->image->info.height - 1);
4560
4561 if (radv_htile_enabled(iview->image, level)) {
4562 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4563
4564 if (radv_image_is_tc_compat_htile(iview->image)) {
4565 unsigned max_zplanes =
4566 radv_calc_decompress_on_z_planes(device, iview);
4567
4568 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4569 S_028038_ITERATE_FLUSH(1);
4570 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4571 }
4572
4573 if (!surf->has_stencil)
4574 /* Use all of the htile_buffer for depth if there's no stencil. */
4575 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4576 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4577 iview->image->htile_offset;
4578 ds->db_htile_data_base = va >> 8;
4579 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4580 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4581 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4582 }
4583 } else {
4584 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4585
4586 if (stencil_only)
4587 level_info = &surf->u.legacy.stencil_level[level];
4588
4589 z_offs += surf->u.legacy.level[level].offset;
4590 s_offs += surf->u.legacy.stencil_level[level].offset;
4591
4592 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4593 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4594 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4595
4596 if (iview->image->info.samples > 1)
4597 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4598
4599 if (device->physical_device->rad_info.chip_class >= GFX7) {
4600 struct radeon_info *info = &device->physical_device->rad_info;
4601 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4602 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4603 unsigned macro_index = surf->u.legacy.macro_tile_index;
4604 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4605 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4606 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4607
4608 if (stencil_only)
4609 tile_mode = stencil_tile_mode;
4610
4611 ds->db_depth_info |=
4612 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4613 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4614 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4615 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4616 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4617 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4618 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4619 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4620 } else {
4621 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4622 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4623 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4624 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4625 if (stencil_only)
4626 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4627 }
4628
4629 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4630 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4631 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4632
4633 if (radv_htile_enabled(iview->image, level)) {
4634 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4635
4636 if (!surf->has_stencil &&
4637 !radv_image_is_tc_compat_htile(iview->image))
4638 /* Use all of the htile_buffer for depth if there's no stencil. */
4639 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4640
4641 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4642 iview->image->htile_offset;
4643 ds->db_htile_data_base = va >> 8;
4644 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4645
4646 if (radv_image_is_tc_compat_htile(iview->image)) {
4647 unsigned max_zplanes =
4648 radv_calc_decompress_on_z_planes(device, iview);
4649
4650 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4651 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4652 }
4653 }
4654 }
4655
4656 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4657 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4658 }
4659
4660 VkResult radv_CreateFramebuffer(
4661 VkDevice _device,
4662 const VkFramebufferCreateInfo* pCreateInfo,
4663 const VkAllocationCallbacks* pAllocator,
4664 VkFramebuffer* pFramebuffer)
4665 {
4666 RADV_FROM_HANDLE(radv_device, device, _device);
4667 struct radv_framebuffer *framebuffer;
4668
4669 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4670
4671 size_t size = sizeof(*framebuffer) +
4672 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4673 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4674 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4675 if (framebuffer == NULL)
4676 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4677
4678 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4679 framebuffer->width = pCreateInfo->width;
4680 framebuffer->height = pCreateInfo->height;
4681 framebuffer->layers = pCreateInfo->layers;
4682 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4683 VkImageView _iview = pCreateInfo->pAttachments[i];
4684 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4685 framebuffer->attachments[i].attachment = iview;
4686 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4687 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4688 } else {
4689 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4690 }
4691 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4692 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4693 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4694 }
4695
4696 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4697 return VK_SUCCESS;
4698 }
4699
4700 void radv_DestroyFramebuffer(
4701 VkDevice _device,
4702 VkFramebuffer _fb,
4703 const VkAllocationCallbacks* pAllocator)
4704 {
4705 RADV_FROM_HANDLE(radv_device, device, _device);
4706 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4707
4708 if (!fb)
4709 return;
4710 vk_free2(&device->alloc, pAllocator, fb);
4711 }
4712
4713 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4714 {
4715 switch (address_mode) {
4716 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4717 return V_008F30_SQ_TEX_WRAP;
4718 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4719 return V_008F30_SQ_TEX_MIRROR;
4720 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4721 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4722 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4723 return V_008F30_SQ_TEX_CLAMP_BORDER;
4724 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4725 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4726 default:
4727 unreachable("illegal tex wrap mode");
4728 break;
4729 }
4730 }
4731
4732 static unsigned
4733 radv_tex_compare(VkCompareOp op)
4734 {
4735 switch (op) {
4736 case VK_COMPARE_OP_NEVER:
4737 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4738 case VK_COMPARE_OP_LESS:
4739 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4740 case VK_COMPARE_OP_EQUAL:
4741 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4742 case VK_COMPARE_OP_LESS_OR_EQUAL:
4743 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4744 case VK_COMPARE_OP_GREATER:
4745 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4746 case VK_COMPARE_OP_NOT_EQUAL:
4747 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4748 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4749 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4750 case VK_COMPARE_OP_ALWAYS:
4751 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4752 default:
4753 unreachable("illegal compare mode");
4754 break;
4755 }
4756 }
4757
4758 static unsigned
4759 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4760 {
4761 switch (filter) {
4762 case VK_FILTER_NEAREST:
4763 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4764 V_008F38_SQ_TEX_XY_FILTER_POINT);
4765 case VK_FILTER_LINEAR:
4766 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4767 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4768 case VK_FILTER_CUBIC_IMG:
4769 default:
4770 fprintf(stderr, "illegal texture filter");
4771 return 0;
4772 }
4773 }
4774
4775 static unsigned
4776 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4777 {
4778 switch (mode) {
4779 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4780 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4781 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4782 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4783 default:
4784 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4785 }
4786 }
4787
4788 static unsigned
4789 radv_tex_bordercolor(VkBorderColor bcolor)
4790 {
4791 switch (bcolor) {
4792 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4793 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4794 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4795 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4796 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4797 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4798 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4799 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4800 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4801 default:
4802 break;
4803 }
4804 return 0;
4805 }
4806
4807 static unsigned
4808 radv_tex_aniso_filter(unsigned filter)
4809 {
4810 if (filter < 2)
4811 return 0;
4812 if (filter < 4)
4813 return 1;
4814 if (filter < 8)
4815 return 2;
4816 if (filter < 16)
4817 return 3;
4818 return 4;
4819 }
4820
4821 static unsigned
4822 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4823 {
4824 switch (mode) {
4825 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4826 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4827 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4828 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4829 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4830 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4831 default:
4832 break;
4833 }
4834 return 0;
4835 }
4836
4837 static uint32_t
4838 radv_get_max_anisotropy(struct radv_device *device,
4839 const VkSamplerCreateInfo *pCreateInfo)
4840 {
4841 if (device->force_aniso >= 0)
4842 return device->force_aniso;
4843
4844 if (pCreateInfo->anisotropyEnable &&
4845 pCreateInfo->maxAnisotropy > 1.0f)
4846 return (uint32_t)pCreateInfo->maxAnisotropy;
4847
4848 return 0;
4849 }
4850
4851 static void
4852 radv_init_sampler(struct radv_device *device,
4853 struct radv_sampler *sampler,
4854 const VkSamplerCreateInfo *pCreateInfo)
4855 {
4856 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4857 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4858 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4859 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4860
4861 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4862 vk_find_struct_const(pCreateInfo->pNext,
4863 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4864 if (sampler_reduction)
4865 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4866
4867 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4868 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4869 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4870 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4871 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4872 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4873 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4874 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4875 S_008F30_DISABLE_CUBE_WRAP(0) |
4876 S_008F30_COMPAT_MODE(is_vi) |
4877 S_008F30_FILTER_MODE(filter_mode));
4878 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4879 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4880 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4881 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4882 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4883 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4884 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4885 S_008F38_MIP_POINT_PRECLAMP(0) |
4886 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4887 S_008F38_FILTER_PREC_FIX(1) |
4888 S_008F38_ANISO_OVERRIDE(is_vi));
4889 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4890 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4891 }
4892
4893 VkResult radv_CreateSampler(
4894 VkDevice _device,
4895 const VkSamplerCreateInfo* pCreateInfo,
4896 const VkAllocationCallbacks* pAllocator,
4897 VkSampler* pSampler)
4898 {
4899 RADV_FROM_HANDLE(radv_device, device, _device);
4900 struct radv_sampler *sampler;
4901
4902 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4903 vk_find_struct_const(pCreateInfo->pNext,
4904 SAMPLER_YCBCR_CONVERSION_INFO);
4905
4906 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4907
4908 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4909 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4910 if (!sampler)
4911 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4912
4913 radv_init_sampler(device, sampler, pCreateInfo);
4914
4915 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4916 *pSampler = radv_sampler_to_handle(sampler);
4917
4918 return VK_SUCCESS;
4919 }
4920
4921 void radv_DestroySampler(
4922 VkDevice _device,
4923 VkSampler _sampler,
4924 const VkAllocationCallbacks* pAllocator)
4925 {
4926 RADV_FROM_HANDLE(radv_device, device, _device);
4927 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4928
4929 if (!sampler)
4930 return;
4931 vk_free2(&device->alloc, pAllocator, sampler);
4932 }
4933
4934 /* vk_icd.h does not declare this function, so we declare it here to
4935 * suppress Wmissing-prototypes.
4936 */
4937 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4938 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4939
4940 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4941 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4942 {
4943 /* For the full details on loader interface versioning, see
4944 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4945 * What follows is a condensed summary, to help you navigate the large and
4946 * confusing official doc.
4947 *
4948 * - Loader interface v0 is incompatible with later versions. We don't
4949 * support it.
4950 *
4951 * - In loader interface v1:
4952 * - The first ICD entrypoint called by the loader is
4953 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4954 * entrypoint.
4955 * - The ICD must statically expose no other Vulkan symbol unless it is
4956 * linked with -Bsymbolic.
4957 * - Each dispatchable Vulkan handle created by the ICD must be
4958 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4959 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4960 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4961 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4962 * such loader-managed surfaces.
4963 *
4964 * - Loader interface v2 differs from v1 in:
4965 * - The first ICD entrypoint called by the loader is
4966 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4967 * statically expose this entrypoint.
4968 *
4969 * - Loader interface v3 differs from v2 in:
4970 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4971 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4972 * because the loader no longer does so.
4973 */
4974 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4975 return VK_SUCCESS;
4976 }
4977
4978 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4979 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4980 int *pFD)
4981 {
4982 RADV_FROM_HANDLE(radv_device, device, _device);
4983 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4984
4985 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4986
4987 /* At the moment, we support only the below handle types. */
4988 assert(pGetFdInfo->handleType ==
4989 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4990 pGetFdInfo->handleType ==
4991 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4992
4993 bool ret = radv_get_memory_fd(device, memory, pFD);
4994 if (ret == false)
4995 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4996 return VK_SUCCESS;
4997 }
4998
4999 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5000 VkExternalMemoryHandleTypeFlagBits handleType,
5001 int fd,
5002 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5003 {
5004 RADV_FROM_HANDLE(radv_device, device, _device);
5005
5006 switch (handleType) {
5007 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5008 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5009 return VK_SUCCESS;
5010
5011 default:
5012 /* The valid usage section for this function says:
5013 *
5014 * "handleType must not be one of the handle types defined as
5015 * opaque."
5016 *
5017 * So opaque handle types fall into the default "unsupported" case.
5018 */
5019 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5020 }
5021 }
5022
5023 static VkResult radv_import_opaque_fd(struct radv_device *device,
5024 int fd,
5025 uint32_t *syncobj)
5026 {
5027 uint32_t syncobj_handle = 0;
5028 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5029 if (ret != 0)
5030 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5031
5032 if (*syncobj)
5033 device->ws->destroy_syncobj(device->ws, *syncobj);
5034
5035 *syncobj = syncobj_handle;
5036 close(fd);
5037
5038 return VK_SUCCESS;
5039 }
5040
5041 static VkResult radv_import_sync_fd(struct radv_device *device,
5042 int fd,
5043 uint32_t *syncobj)
5044 {
5045 /* If we create a syncobj we do it locally so that if we have an error, we don't
5046 * leave a syncobj in an undetermined state in the fence. */
5047 uint32_t syncobj_handle = *syncobj;
5048 if (!syncobj_handle) {
5049 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5050 if (ret) {
5051 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5052 }
5053 }
5054
5055 if (fd == -1) {
5056 device->ws->signal_syncobj(device->ws, syncobj_handle);
5057 } else {
5058 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5059 if (ret != 0)
5060 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5061 }
5062
5063 *syncobj = syncobj_handle;
5064 if (fd != -1)
5065 close(fd);
5066
5067 return VK_SUCCESS;
5068 }
5069
5070 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5071 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5072 {
5073 RADV_FROM_HANDLE(radv_device, device, _device);
5074 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5075 uint32_t *syncobj_dst = NULL;
5076
5077 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5078 syncobj_dst = &sem->temp_syncobj;
5079 } else {
5080 syncobj_dst = &sem->syncobj;
5081 }
5082
5083 switch(pImportSemaphoreFdInfo->handleType) {
5084 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5085 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5086 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5087 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5088 default:
5089 unreachable("Unhandled semaphore handle type");
5090 }
5091 }
5092
5093 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5094 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5095 int *pFd)
5096 {
5097 RADV_FROM_HANDLE(radv_device, device, _device);
5098 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5099 int ret;
5100 uint32_t syncobj_handle;
5101
5102 if (sem->temp_syncobj)
5103 syncobj_handle = sem->temp_syncobj;
5104 else
5105 syncobj_handle = sem->syncobj;
5106
5107 switch(pGetFdInfo->handleType) {
5108 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5109 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5110 break;
5111 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5112 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5113 if (!ret) {
5114 if (sem->temp_syncobj) {
5115 close (sem->temp_syncobj);
5116 sem->temp_syncobj = 0;
5117 } else {
5118 device->ws->reset_syncobj(device->ws, syncobj_handle);
5119 }
5120 }
5121 break;
5122 default:
5123 unreachable("Unhandled semaphore handle type");
5124 }
5125
5126 if (ret)
5127 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5128 return VK_SUCCESS;
5129 }
5130
5131 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5132 VkPhysicalDevice physicalDevice,
5133 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5134 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5135 {
5136 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5137
5138 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5139 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5140 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5141 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5142 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5143 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5144 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5145 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5146 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5147 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5148 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5149 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5150 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5151 } else {
5152 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5153 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5154 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5155 }
5156 }
5157
5158 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5159 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5160 {
5161 RADV_FROM_HANDLE(radv_device, device, _device);
5162 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5163 uint32_t *syncobj_dst = NULL;
5164
5165
5166 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5167 syncobj_dst = &fence->temp_syncobj;
5168 } else {
5169 syncobj_dst = &fence->syncobj;
5170 }
5171
5172 switch(pImportFenceFdInfo->handleType) {
5173 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5174 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5175 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5176 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5177 default:
5178 unreachable("Unhandled fence handle type");
5179 }
5180 }
5181
5182 VkResult radv_GetFenceFdKHR(VkDevice _device,
5183 const VkFenceGetFdInfoKHR *pGetFdInfo,
5184 int *pFd)
5185 {
5186 RADV_FROM_HANDLE(radv_device, device, _device);
5187 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5188 int ret;
5189 uint32_t syncobj_handle;
5190
5191 if (fence->temp_syncobj)
5192 syncobj_handle = fence->temp_syncobj;
5193 else
5194 syncobj_handle = fence->syncobj;
5195
5196 switch(pGetFdInfo->handleType) {
5197 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5198 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5199 break;
5200 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5201 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5202 if (!ret) {
5203 if (fence->temp_syncobj) {
5204 close (fence->temp_syncobj);
5205 fence->temp_syncobj = 0;
5206 } else {
5207 device->ws->reset_syncobj(device->ws, syncobj_handle);
5208 }
5209 }
5210 break;
5211 default:
5212 unreachable("Unhandled fence handle type");
5213 }
5214
5215 if (ret)
5216 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5217 return VK_SUCCESS;
5218 }
5219
5220 void radv_GetPhysicalDeviceExternalFenceProperties(
5221 VkPhysicalDevice physicalDevice,
5222 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5223 VkExternalFenceProperties *pExternalFenceProperties)
5224 {
5225 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5226
5227 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5228 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5229 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5230 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5231 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5232 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5233 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5234 } else {
5235 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5236 pExternalFenceProperties->compatibleHandleTypes = 0;
5237 pExternalFenceProperties->externalFenceFeatures = 0;
5238 }
5239 }
5240
5241 VkResult
5242 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5243 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5244 const VkAllocationCallbacks* pAllocator,
5245 VkDebugReportCallbackEXT* pCallback)
5246 {
5247 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5248 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5249 pCreateInfo, pAllocator, &instance->alloc,
5250 pCallback);
5251 }
5252
5253 void
5254 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5255 VkDebugReportCallbackEXT _callback,
5256 const VkAllocationCallbacks* pAllocator)
5257 {
5258 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5259 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5260 _callback, pAllocator, &instance->alloc);
5261 }
5262
5263 void
5264 radv_DebugReportMessageEXT(VkInstance _instance,
5265 VkDebugReportFlagsEXT flags,
5266 VkDebugReportObjectTypeEXT objectType,
5267 uint64_t object,
5268 size_t location,
5269 int32_t messageCode,
5270 const char* pLayerPrefix,
5271 const char* pMessage)
5272 {
5273 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5274 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5275 object, location, messageCode, pLayerPrefix, pMessage);
5276 }
5277
5278 void
5279 radv_GetDeviceGroupPeerMemoryFeatures(
5280 VkDevice device,
5281 uint32_t heapIndex,
5282 uint32_t localDeviceIndex,
5283 uint32_t remoteDeviceIndex,
5284 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5285 {
5286 assert(localDeviceIndex == remoteDeviceIndex);
5287
5288 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5289 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5290 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5291 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5292 }
5293
5294 static const VkTimeDomainEXT radv_time_domains[] = {
5295 VK_TIME_DOMAIN_DEVICE_EXT,
5296 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5297 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5298 };
5299
5300 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5301 VkPhysicalDevice physicalDevice,
5302 uint32_t *pTimeDomainCount,
5303 VkTimeDomainEXT *pTimeDomains)
5304 {
5305 int d;
5306 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5307
5308 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5309 vk_outarray_append(&out, i) {
5310 *i = radv_time_domains[d];
5311 }
5312 }
5313
5314 return vk_outarray_status(&out);
5315 }
5316
5317 static uint64_t
5318 radv_clock_gettime(clockid_t clock_id)
5319 {
5320 struct timespec current;
5321 int ret;
5322
5323 ret = clock_gettime(clock_id, &current);
5324 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5325 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5326 if (ret < 0)
5327 return 0;
5328
5329 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5330 }
5331
5332 VkResult radv_GetCalibratedTimestampsEXT(
5333 VkDevice _device,
5334 uint32_t timestampCount,
5335 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5336 uint64_t *pTimestamps,
5337 uint64_t *pMaxDeviation)
5338 {
5339 RADV_FROM_HANDLE(radv_device, device, _device);
5340 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5341 int d;
5342 uint64_t begin, end;
5343 uint64_t max_clock_period = 0;
5344
5345 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5346
5347 for (d = 0; d < timestampCount; d++) {
5348 switch (pTimestampInfos[d].timeDomain) {
5349 case VK_TIME_DOMAIN_DEVICE_EXT:
5350 pTimestamps[d] = device->ws->query_value(device->ws,
5351 RADEON_TIMESTAMP);
5352 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5353 max_clock_period = MAX2(max_clock_period, device_period);
5354 break;
5355 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5356 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5357 max_clock_period = MAX2(max_clock_period, 1);
5358 break;
5359
5360 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5361 pTimestamps[d] = begin;
5362 break;
5363 default:
5364 pTimestamps[d] = 0;
5365 break;
5366 }
5367 }
5368
5369 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5370
5371 /*
5372 * The maximum deviation is the sum of the interval over which we
5373 * perform the sampling and the maximum period of any sampled
5374 * clock. That's because the maximum skew between any two sampled
5375 * clock edges is when the sampled clock with the largest period is
5376 * sampled at the end of that period but right at the beginning of the
5377 * sampling interval and some other clock is sampled right at the
5378 * begining of its sampling period and right at the end of the
5379 * sampling interval. Let's assume the GPU has the longest clock
5380 * period and that the application is sampling GPU and monotonic:
5381 *
5382 * s e
5383 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5384 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5385 *
5386 * g
5387 * 0 1 2 3
5388 * GPU -----_____-----_____-----_____-----_____
5389 *
5390 * m
5391 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5392 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5393 *
5394 * Interval <----------------->
5395 * Deviation <-------------------------->
5396 *
5397 * s = read(raw) 2
5398 * g = read(GPU) 1
5399 * m = read(monotonic) 2
5400 * e = read(raw) b
5401 *
5402 * We round the sample interval up by one tick to cover sampling error
5403 * in the interval clock
5404 */
5405
5406 uint64_t sample_interval = end - begin + 1;
5407
5408 *pMaxDeviation = sample_interval + max_clock_period;
5409
5410 return VK_SUCCESS;
5411 }
5412
5413 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5414 VkPhysicalDevice physicalDevice,
5415 VkSampleCountFlagBits samples,
5416 VkMultisamplePropertiesEXT* pMultisampleProperties)
5417 {
5418 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5419 VK_SAMPLE_COUNT_4_BIT |
5420 VK_SAMPLE_COUNT_8_BIT)) {
5421 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5422 } else {
5423 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5424 }
5425 }