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util: disable cache if we have no build-id and timestamp is zero
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static bool
53 radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
54 {
55 uint32_t timestamp;
56
57 #ifdef HAVE_DL_ITERATE_PHDR
58 const struct build_id_note *note = NULL;
59 if ((note = build_id_find_nhdr_for_addr(ptr))) {
60 _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
61 } else
62 #endif
63 if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
64 _mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
65 } else
66 return false;
67 return true;
68 }
69
70 static int
71 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
72 {
73 struct mesa_sha1 ctx;
74 unsigned char sha1[20];
75 unsigned ptr_size = sizeof(void*);
76
77 memset(uuid, 0, VK_UUID_SIZE);
78 _mesa_sha1_init(&ctx);
79
80 if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
81 !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
82 return -1;
83
84 _mesa_sha1_update(&ctx, &family, sizeof(family));
85 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
86 _mesa_sha1_final(&ctx, sha1);
87
88 memcpy(uuid, sha1, VK_UUID_SIZE);
89 return 0;
90 }
91
92 static void
93 radv_get_driver_uuid(void *uuid)
94 {
95 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
96 }
97
98 static void
99 radv_get_device_uuid(struct radeon_info *info, void *uuid)
100 {
101 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
102 }
103
104 static void
105 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
106 {
107 const char *chip_string;
108 char llvm_string[32] = {};
109
110 switch (family) {
111 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
112 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
113 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
114 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
115 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
116 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
117 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
118 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
119 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
120 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
121 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
122 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
123 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
124 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
125 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
126 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
127 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
128 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
129 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
130 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
131 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
132 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
133 default: chip_string = "AMD RADV unknown"; break;
134 }
135
136 snprintf(llvm_string, sizeof(llvm_string),
137 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
138 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
139 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
140 }
141
142 static void
143 radv_physical_device_init_mem_types(struct radv_physical_device *device)
144 {
145 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
146 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
147 device->rad_info.vram_vis_size);
148
149 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
150 device->memory_properties.memoryHeapCount = 0;
151 if (device->rad_info.vram_size - visible_vram_size > 0) {
152 vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
154 .size = device->rad_info.vram_size - visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (visible_vram_size) {
159 visible_vram_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
161 .size = visible_vram_size,
162 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165 if (device->rad_info.gart_size > 0) {
166 gart_index = device->memory_properties.memoryHeapCount++;
167 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
168 .size = device->rad_info.gart_size,
169 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
170 };
171 }
172
173 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
174 unsigned type_count = 0;
175 if (vram_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
179 .heapIndex = vram_index,
180 };
181 }
182 if (gart_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
186 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
187 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
188 .heapIndex = gart_index,
189 };
190 }
191 if (visible_vram_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
195 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
197 .heapIndex = visible_vram_index,
198 };
199 }
200 if (gart_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
204 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
205 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
206 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
207 .heapIndex = gart_index,
208 };
209 }
210 device->memory_properties.memoryTypeCount = type_count;
211 }
212
213 static void
214 radv_handle_env_var_force_family(struct radv_physical_device *device)
215 {
216 const char *family = getenv("RADV_FORCE_FAMILY");
217 unsigned i;
218
219 if (!family)
220 return;
221
222 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
223 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
224 /* Override family and chip_class. */
225 device->rad_info.family = i;
226
227 if (i >= CHIP_VEGA10)
228 device->rad_info.chip_class = GFX9;
229 else if (i >= CHIP_TONGA)
230 device->rad_info.chip_class = VI;
231 else if (i >= CHIP_BONAIRE)
232 device->rad_info.chip_class = CIK;
233 else
234 device->rad_info.chip_class = SI;
235
236 return;
237 }
238 }
239
240 fprintf(stderr, "radv: Unknown family: %s\n", family);
241 exit(1);
242 }
243
244 static VkResult
245 radv_physical_device_init(struct radv_physical_device *device,
246 struct radv_instance *instance,
247 drmDevicePtr drm_device)
248 {
249 const char *path = drm_device->nodes[DRM_NODE_RENDER];
250 VkResult result;
251 drmVersionPtr version;
252 int fd;
253 int master_fd = -1;
254
255 fd = open(path, O_RDWR | O_CLOEXEC);
256 if (fd < 0) {
257 if (instance->debug_flags & RADV_DEBUG_STARTUP)
258 radv_logi("Could not open device '%s'", path);
259
260 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
261 }
262
263 version = drmGetVersion(fd);
264 if (!version) {
265 close(fd);
266
267 if (instance->debug_flags & RADV_DEBUG_STARTUP)
268 radv_logi("Could not get the kernel driver version for device '%s'", path);
269
270 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
271 "failed to get version %s: %m", path);
272 }
273
274 if (strcmp(version->name, "amdgpu")) {
275 drmFreeVersion(version);
276 if (master_fd != -1)
277 close(master_fd);
278 close(fd);
279
280 if (instance->debug_flags & RADV_DEBUG_STARTUP)
281 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
282
283 return VK_ERROR_INCOMPATIBLE_DRIVER;
284 }
285 drmFreeVersion(version);
286
287 if (instance->debug_flags & RADV_DEBUG_STARTUP)
288 radv_logi("Found compatible device '%s'.", path);
289
290 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
291 device->instance = instance;
292 assert(strlen(path) < ARRAY_SIZE(device->path));
293 strncpy(device->path, path, ARRAY_SIZE(device->path));
294
295 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
296 instance->perftest_flags);
297 if (!device->ws) {
298 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
299 goto fail;
300 }
301
302 if (instance->enabled_extensions.KHR_display) {
303 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
304 if (master_fd >= 0) {
305 uint32_t accel_working = 0;
306 struct drm_amdgpu_info request = {
307 .return_pointer = (uintptr_t)&accel_working,
308 .return_size = sizeof(accel_working),
309 .query = AMDGPU_INFO_ACCEL_WORKING
310 };
311
312 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
313 close(master_fd);
314 master_fd = -1;
315 }
316 }
317 }
318
319 device->master_fd = master_fd;
320 device->local_fd = fd;
321 device->ws->query_info(device->ws, &device->rad_info);
322
323 radv_handle_env_var_force_family(device);
324
325 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
326
327 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
328 device->ws->destroy(device->ws);
329 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
330 "cannot generate UUID");
331 goto fail;
332 }
333
334 /* These flags affect shader compilation. */
335 uint64_t shader_env_flags =
336 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
337 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
338
339 /* The gpu id is already embedded in the uuid so we just pass "radv"
340 * when creating the cache.
341 */
342 char buf[VK_UUID_SIZE * 2 + 1];
343 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
344 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
345
346 if (device->rad_info.chip_class < VI ||
347 device->rad_info.chip_class > GFX9)
348 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
349
350 radv_get_driver_uuid(&device->device_uuid);
351 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
352
353 if (device->rad_info.family == CHIP_STONEY ||
354 device->rad_info.chip_class >= GFX9) {
355 device->has_rbplus = true;
356 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
357 device->rad_info.family == CHIP_VEGA12 ||
358 device->rad_info.family == CHIP_RAVEN;
359 }
360
361 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
362 * on SI.
363 */
364 device->has_clear_state = device->rad_info.chip_class >= CIK;
365
366 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
367
368 /* Vega10/Raven need a special workaround for a hardware bug. */
369 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
370 device->rad_info.family == CHIP_RAVEN;
371
372 /* Out-of-order primitive rasterization. */
373 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
374 device->rad_info.max_se >= 2;
375 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
376 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
377
378 device->dcc_msaa_allowed =
379 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
380
381 radv_physical_device_init_mem_types(device);
382 radv_fill_device_extension_table(device, &device->supported_extensions);
383
384 result = radv_init_wsi(device);
385 if (result != VK_SUCCESS) {
386 device->ws->destroy(device->ws);
387 vk_error(instance, result);
388 goto fail;
389 }
390
391 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
392 ac_print_gpu_info(&device->rad_info);
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {NULL, 0}
466 };
467
468 const char *
469 radv_get_debug_option_name(int id)
470 {
471 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
472 return radv_debug_options[id].string;
473 }
474
475 static const struct debug_control radv_perftest_options[] = {
476 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
477 {"sisched", RADV_PERFTEST_SISCHED},
478 {"localbos", RADV_PERFTEST_LOCAL_BOS},
479 {"binning", RADV_PERFTEST_BINNING},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
481 {NULL, 0}
482 };
483
484 const char *
485 radv_get_perftest_option_name(int id)
486 {
487 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
488 return radv_perftest_options[id].string;
489 }
490
491 static void
492 radv_handle_per_app_options(struct radv_instance *instance,
493 const VkApplicationInfo *info)
494 {
495 const char *name = info ? info->pApplicationName : NULL;
496
497 if (!name)
498 return;
499
500 if (!strcmp(name, "Talos - Linux - 32bit") ||
501 !strcmp(name, "Talos - Linux - 64bit")) {
502 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
503 /* Force enable LLVM sisched for Talos because it looks
504 * safe and it gives few more FPS.
505 */
506 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
507 }
508 } else if (!strcmp(name, "DOOM_VFR")) {
509 /* Work around a Doom VFR game bug */
510 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
511 }
512 }
513
514 static int radv_get_instance_extension_index(const char *name)
515 {
516 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
517 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
518 return i;
519 }
520 return -1;
521 }
522
523
524 VkResult radv_CreateInstance(
525 const VkInstanceCreateInfo* pCreateInfo,
526 const VkAllocationCallbacks* pAllocator,
527 VkInstance* pInstance)
528 {
529 struct radv_instance *instance;
530 VkResult result;
531
532 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
533
534 uint32_t client_version;
535 if (pCreateInfo->pApplicationInfo &&
536 pCreateInfo->pApplicationInfo->apiVersion != 0) {
537 client_version = pCreateInfo->pApplicationInfo->apiVersion;
538 } else {
539 radv_EnumerateInstanceVersion(&client_version);
540 }
541
542 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
543 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
544 if (!instance)
545 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
546
547 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
548
549 if (pAllocator)
550 instance->alloc = *pAllocator;
551 else
552 instance->alloc = default_alloc;
553
554 instance->apiVersion = client_version;
555 instance->physicalDeviceCount = -1;
556
557 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
558 radv_debug_options);
559
560 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
561 radv_perftest_options);
562
563
564 if (instance->debug_flags & RADV_DEBUG_STARTUP)
565 radv_logi("Created an instance");
566
567 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
568 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
569 int index = radv_get_instance_extension_index(ext_name);
570
571 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
572 vk_free2(&default_alloc, pAllocator, instance);
573 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
574 }
575
576 instance->enabled_extensions.extensions[index] = true;
577 }
578
579 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
580 if (result != VK_SUCCESS) {
581 vk_free2(&default_alloc, pAllocator, instance);
582 return vk_error(instance, result);
583 }
584
585 _mesa_locale_init();
586
587 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
588
589 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
590
591 *pInstance = radv_instance_to_handle(instance);
592
593 return VK_SUCCESS;
594 }
595
596 void radv_DestroyInstance(
597 VkInstance _instance,
598 const VkAllocationCallbacks* pAllocator)
599 {
600 RADV_FROM_HANDLE(radv_instance, instance, _instance);
601
602 if (!instance)
603 return;
604
605 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
606 radv_physical_device_finish(instance->physicalDevices + i);
607 }
608
609 VG(VALGRIND_DESTROY_MEMPOOL(instance));
610
611 _mesa_locale_fini();
612
613 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
614
615 vk_free(&instance->alloc, instance);
616 }
617
618 static VkResult
619 radv_enumerate_devices(struct radv_instance *instance)
620 {
621 /* TODO: Check for more devices ? */
622 drmDevicePtr devices[8];
623 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
624 int max_devices;
625
626 instance->physicalDeviceCount = 0;
627
628 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
629
630 if (instance->debug_flags & RADV_DEBUG_STARTUP)
631 radv_logi("Found %d drm nodes", max_devices);
632
633 if (max_devices < 1)
634 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
635
636 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
637 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
638 devices[i]->bustype == DRM_BUS_PCI &&
639 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
640
641 result = radv_physical_device_init(instance->physicalDevices +
642 instance->physicalDeviceCount,
643 instance,
644 devices[i]);
645 if (result == VK_SUCCESS)
646 ++instance->physicalDeviceCount;
647 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
648 break;
649 }
650 }
651 drmFreeDevices(devices, max_devices);
652
653 return result;
654 }
655
656 VkResult radv_EnumeratePhysicalDevices(
657 VkInstance _instance,
658 uint32_t* pPhysicalDeviceCount,
659 VkPhysicalDevice* pPhysicalDevices)
660 {
661 RADV_FROM_HANDLE(radv_instance, instance, _instance);
662 VkResult result;
663
664 if (instance->physicalDeviceCount < 0) {
665 result = radv_enumerate_devices(instance);
666 if (result != VK_SUCCESS &&
667 result != VK_ERROR_INCOMPATIBLE_DRIVER)
668 return result;
669 }
670
671 if (!pPhysicalDevices) {
672 *pPhysicalDeviceCount = instance->physicalDeviceCount;
673 } else {
674 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
675 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
676 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 }
678
679 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
680 : VK_SUCCESS;
681 }
682
683 VkResult radv_EnumeratePhysicalDeviceGroups(
684 VkInstance _instance,
685 uint32_t* pPhysicalDeviceGroupCount,
686 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
687 {
688 RADV_FROM_HANDLE(radv_instance, instance, _instance);
689 VkResult result;
690
691 if (instance->physicalDeviceCount < 0) {
692 result = radv_enumerate_devices(instance);
693 if (result != VK_SUCCESS &&
694 result != VK_ERROR_INCOMPATIBLE_DRIVER)
695 return result;
696 }
697
698 if (!pPhysicalDeviceGroupProperties) {
699 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
700 } else {
701 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
702 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
703 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
704 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
705 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
706 }
707 }
708 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
709 : VK_SUCCESS;
710 }
711
712 void radv_GetPhysicalDeviceFeatures(
713 VkPhysicalDevice physicalDevice,
714 VkPhysicalDeviceFeatures* pFeatures)
715 {
716 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
717 memset(pFeatures, 0, sizeof(*pFeatures));
718
719 *pFeatures = (VkPhysicalDeviceFeatures) {
720 .robustBufferAccess = true,
721 .fullDrawIndexUint32 = true,
722 .imageCubeArray = true,
723 .independentBlend = true,
724 .geometryShader = true,
725 .tessellationShader = true,
726 .sampleRateShading = true,
727 .dualSrcBlend = true,
728 .logicOp = true,
729 .multiDrawIndirect = true,
730 .drawIndirectFirstInstance = true,
731 .depthClamp = true,
732 .depthBiasClamp = true,
733 .fillModeNonSolid = true,
734 .depthBounds = true,
735 .wideLines = true,
736 .largePoints = true,
737 .alphaToOne = true,
738 .multiViewport = true,
739 .samplerAnisotropy = true,
740 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
741 pdevice->rad_info.family == CHIP_STONEY,
742 .textureCompressionASTC_LDR = false,
743 .textureCompressionBC = true,
744 .occlusionQueryPrecise = true,
745 .pipelineStatisticsQuery = true,
746 .vertexPipelineStoresAndAtomics = true,
747 .fragmentStoresAndAtomics = true,
748 .shaderTessellationAndGeometryPointSize = true,
749 .shaderImageGatherExtended = true,
750 .shaderStorageImageExtendedFormats = true,
751 .shaderStorageImageMultisample = false,
752 .shaderUniformBufferArrayDynamicIndexing = true,
753 .shaderSampledImageArrayDynamicIndexing = true,
754 .shaderStorageBufferArrayDynamicIndexing = true,
755 .shaderStorageImageArrayDynamicIndexing = true,
756 .shaderStorageImageReadWithoutFormat = true,
757 .shaderStorageImageWriteWithoutFormat = true,
758 .shaderClipDistance = true,
759 .shaderCullDistance = true,
760 .shaderFloat64 = true,
761 .shaderInt64 = true,
762 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && HAVE_LLVM >= 0x700,
763 .sparseBinding = true,
764 .variableMultisampleRate = true,
765 .inheritedQueries = true,
766 };
767 }
768
769 void radv_GetPhysicalDeviceFeatures2(
770 VkPhysicalDevice physicalDevice,
771 VkPhysicalDeviceFeatures2KHR *pFeatures)
772 {
773 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
774 vk_foreach_struct(ext, pFeatures->pNext) {
775 switch (ext->sType) {
776 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
777 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
778 features->variablePointersStorageBuffer = true;
779 features->variablePointers = false;
780 break;
781 }
782 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
783 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
784 features->multiview = true;
785 features->multiviewGeometryShader = true;
786 features->multiviewTessellationShader = true;
787 break;
788 }
789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
790 VkPhysicalDeviceShaderDrawParameterFeatures *features =
791 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
792 features->shaderDrawParameters = true;
793 break;
794 }
795 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
796 VkPhysicalDeviceProtectedMemoryFeatures *features =
797 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
798 features->protectedMemory = false;
799 break;
800 }
801 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
802 VkPhysicalDevice16BitStorageFeatures *features =
803 (VkPhysicalDevice16BitStorageFeatures*)ext;
804 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
805 features->storageBuffer16BitAccess = enabled;
806 features->uniformAndStorageBuffer16BitAccess = enabled;
807 features->storagePushConstant16 = enabled;
808 features->storageInputOutput16 = enabled;
809 break;
810 }
811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
812 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
813 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
814 features->samplerYcbcrConversion = false;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
818 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
819 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
820 features->shaderInputAttachmentArrayDynamicIndexing = true;
821 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
822 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
823 features->shaderUniformBufferArrayNonUniformIndexing = false;
824 features->shaderSampledImageArrayNonUniformIndexing = false;
825 features->shaderStorageBufferArrayNonUniformIndexing = false;
826 features->shaderStorageImageArrayNonUniformIndexing = false;
827 features->shaderInputAttachmentArrayNonUniformIndexing = false;
828 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
829 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
830 features->descriptorBindingUniformBufferUpdateAfterBind = true;
831 features->descriptorBindingSampledImageUpdateAfterBind = true;
832 features->descriptorBindingStorageImageUpdateAfterBind = true;
833 features->descriptorBindingStorageBufferUpdateAfterBind = true;
834 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
835 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
836 features->descriptorBindingUpdateUnusedWhilePending = true;
837 features->descriptorBindingPartiallyBound = true;
838 features->descriptorBindingVariableDescriptorCount = true;
839 features->runtimeDescriptorArray = true;
840 break;
841 }
842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
843 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
844 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
845 features->conditionalRendering = true;
846 features->inheritedConditionalRendering = false;
847 break;
848 }
849 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
850 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
851 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
852 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
853 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
854 break;
855 }
856 default:
857 break;
858 }
859 }
860 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
861 }
862
863 void radv_GetPhysicalDeviceProperties(
864 VkPhysicalDevice physicalDevice,
865 VkPhysicalDeviceProperties* pProperties)
866 {
867 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
868 VkSampleCountFlags sample_counts = 0xf;
869
870 /* make sure that the entire descriptor set is addressable with a signed
871 * 32-bit int. So the sum of all limits scaled by descriptor size has to
872 * be at most 2 GiB. the combined image & samples object count as one of
873 * both. This limit is for the pipeline layout, not for the set layout, but
874 * there is no set limit, so we just set a pipeline limit. I don't think
875 * any app is going to hit this soon. */
876 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
877 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
878 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
879 32 /* sampler, largest when combined with image */ +
880 64 /* sampled image */ +
881 64 /* storage image */);
882
883 VkPhysicalDeviceLimits limits = {
884 .maxImageDimension1D = (1 << 14),
885 .maxImageDimension2D = (1 << 14),
886 .maxImageDimension3D = (1 << 11),
887 .maxImageDimensionCube = (1 << 14),
888 .maxImageArrayLayers = (1 << 11),
889 .maxTexelBufferElements = 128 * 1024 * 1024,
890 .maxUniformBufferRange = UINT32_MAX,
891 .maxStorageBufferRange = UINT32_MAX,
892 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
893 .maxMemoryAllocationCount = UINT32_MAX,
894 .maxSamplerAllocationCount = 64 * 1024,
895 .bufferImageGranularity = 64, /* A cache line */
896 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
897 .maxBoundDescriptorSets = MAX_SETS,
898 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
899 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
900 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
901 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
902 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
903 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
904 .maxPerStageResources = max_descriptor_set_size,
905 .maxDescriptorSetSamplers = max_descriptor_set_size,
906 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
907 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
908 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
909 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
910 .maxDescriptorSetSampledImages = max_descriptor_set_size,
911 .maxDescriptorSetStorageImages = max_descriptor_set_size,
912 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
913 .maxVertexInputAttributes = 32,
914 .maxVertexInputBindings = 32,
915 .maxVertexInputAttributeOffset = 2047,
916 .maxVertexInputBindingStride = 2048,
917 .maxVertexOutputComponents = 128,
918 .maxTessellationGenerationLevel = 64,
919 .maxTessellationPatchSize = 32,
920 .maxTessellationControlPerVertexInputComponents = 128,
921 .maxTessellationControlPerVertexOutputComponents = 128,
922 .maxTessellationControlPerPatchOutputComponents = 120,
923 .maxTessellationControlTotalOutputComponents = 4096,
924 .maxTessellationEvaluationInputComponents = 128,
925 .maxTessellationEvaluationOutputComponents = 128,
926 .maxGeometryShaderInvocations = 127,
927 .maxGeometryInputComponents = 64,
928 .maxGeometryOutputComponents = 128,
929 .maxGeometryOutputVertices = 256,
930 .maxGeometryTotalOutputComponents = 1024,
931 .maxFragmentInputComponents = 128,
932 .maxFragmentOutputAttachments = 8,
933 .maxFragmentDualSrcAttachments = 1,
934 .maxFragmentCombinedOutputResources = 8,
935 .maxComputeSharedMemorySize = 32768,
936 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
937 .maxComputeWorkGroupInvocations = 2048,
938 .maxComputeWorkGroupSize = {
939 2048,
940 2048,
941 2048
942 },
943 .subPixelPrecisionBits = 4 /* FIXME */,
944 .subTexelPrecisionBits = 4 /* FIXME */,
945 .mipmapPrecisionBits = 4 /* FIXME */,
946 .maxDrawIndexedIndexValue = UINT32_MAX,
947 .maxDrawIndirectCount = UINT32_MAX,
948 .maxSamplerLodBias = 16,
949 .maxSamplerAnisotropy = 16,
950 .maxViewports = MAX_VIEWPORTS,
951 .maxViewportDimensions = { (1 << 14), (1 << 14) },
952 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
953 .viewportSubPixelBits = 8,
954 .minMemoryMapAlignment = 4096, /* A page */
955 .minTexelBufferOffsetAlignment = 1,
956 .minUniformBufferOffsetAlignment = 4,
957 .minStorageBufferOffsetAlignment = 4,
958 .minTexelOffset = -32,
959 .maxTexelOffset = 31,
960 .minTexelGatherOffset = -32,
961 .maxTexelGatherOffset = 31,
962 .minInterpolationOffset = -2,
963 .maxInterpolationOffset = 2,
964 .subPixelInterpolationOffsetBits = 8,
965 .maxFramebufferWidth = (1 << 14),
966 .maxFramebufferHeight = (1 << 14),
967 .maxFramebufferLayers = (1 << 10),
968 .framebufferColorSampleCounts = sample_counts,
969 .framebufferDepthSampleCounts = sample_counts,
970 .framebufferStencilSampleCounts = sample_counts,
971 .framebufferNoAttachmentsSampleCounts = sample_counts,
972 .maxColorAttachments = MAX_RTS,
973 .sampledImageColorSampleCounts = sample_counts,
974 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
975 .sampledImageDepthSampleCounts = sample_counts,
976 .sampledImageStencilSampleCounts = sample_counts,
977 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
978 .maxSampleMaskWords = 1,
979 .timestampComputeAndGraphics = true,
980 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
981 .maxClipDistances = 8,
982 .maxCullDistances = 8,
983 .maxCombinedClipAndCullDistances = 8,
984 .discreteQueuePriorities = 1,
985 .pointSizeRange = { 0.125, 255.875 },
986 .lineWidthRange = { 0.0, 7.9921875 },
987 .pointSizeGranularity = (1.0 / 8.0),
988 .lineWidthGranularity = (1.0 / 128.0),
989 .strictLines = false, /* FINISHME */
990 .standardSampleLocations = true,
991 .optimalBufferCopyOffsetAlignment = 128,
992 .optimalBufferCopyRowPitchAlignment = 128,
993 .nonCoherentAtomSize = 64,
994 };
995
996 *pProperties = (VkPhysicalDeviceProperties) {
997 .apiVersion = radv_physical_device_api_version(pdevice),
998 .driverVersion = vk_get_driver_version(),
999 .vendorID = ATI_VENDOR_ID,
1000 .deviceID = pdevice->rad_info.pci_id,
1001 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1002 .limits = limits,
1003 .sparseProperties = {0},
1004 };
1005
1006 strcpy(pProperties->deviceName, pdevice->name);
1007 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1008 }
1009
1010 void radv_GetPhysicalDeviceProperties2(
1011 VkPhysicalDevice physicalDevice,
1012 VkPhysicalDeviceProperties2KHR *pProperties)
1013 {
1014 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1015 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1016
1017 vk_foreach_struct(ext, pProperties->pNext) {
1018 switch (ext->sType) {
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1020 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1021 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1022 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1023 break;
1024 }
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1026 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1027 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1028 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1029 properties->deviceLUIDValid = false;
1030 break;
1031 }
1032 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1033 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1034 properties->maxMultiviewViewCount = MAX_VIEWS;
1035 properties->maxMultiviewInstanceIndex = INT_MAX;
1036 break;
1037 }
1038 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1039 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1040 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1041 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1042 break;
1043 }
1044 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1045 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1046 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1047 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1048 break;
1049 }
1050 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1051 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1052 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1053 properties->minImportedHostPointerAlignment = 4096;
1054 break;
1055 }
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1057 VkPhysicalDeviceSubgroupProperties *properties =
1058 (VkPhysicalDeviceSubgroupProperties*)ext;
1059 properties->subgroupSize = 64;
1060 properties->supportedStages = VK_SHADER_STAGE_ALL;
1061 properties->supportedOperations =
1062 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1063 VK_SUBGROUP_FEATURE_BASIC_BIT |
1064 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1065 VK_SUBGROUP_FEATURE_QUAD_BIT |
1066 VK_SUBGROUP_FEATURE_VOTE_BIT;
1067 if (pdevice->rad_info.chip_class >= VI) {
1068 properties->supportedOperations |=
1069 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1070 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1071 }
1072 properties->quadOperationsInAllStages = true;
1073 break;
1074 }
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1076 VkPhysicalDeviceMaintenance3Properties *properties =
1077 (VkPhysicalDeviceMaintenance3Properties*)ext;
1078 /* Make sure everything is addressable by a signed 32-bit int, and
1079 * our largest descriptors are 96 bytes. */
1080 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1081 /* Our buffer size fields allow only this much */
1082 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1083 break;
1084 }
1085 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1086 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1087 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1088 /* GFX6-8 only support single channel min/max filter. */
1089 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1090 properties->filterMinmaxSingleComponentFormats = true;
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1094 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1095 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1096
1097 /* Shader engines. */
1098 properties->shaderEngineCount =
1099 pdevice->rad_info.max_se;
1100 properties->shaderArraysPerEngineCount =
1101 pdevice->rad_info.max_sh_per_se;
1102 properties->computeUnitsPerShaderArray =
1103 pdevice->rad_info.num_good_compute_units /
1104 (pdevice->rad_info.max_se *
1105 pdevice->rad_info.max_sh_per_se);
1106 properties->simdPerComputeUnit = 4;
1107 properties->wavefrontsPerSimd =
1108 pdevice->rad_info.family == CHIP_TONGA ||
1109 pdevice->rad_info.family == CHIP_ICELAND ||
1110 pdevice->rad_info.family == CHIP_POLARIS10 ||
1111 pdevice->rad_info.family == CHIP_POLARIS11 ||
1112 pdevice->rad_info.family == CHIP_POLARIS12 ||
1113 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1114 properties->wavefrontSize = 64;
1115
1116 /* SGPR. */
1117 properties->sgprsPerSimd =
1118 radv_get_num_physical_sgprs(pdevice);
1119 properties->minSgprAllocation =
1120 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1121 properties->maxSgprAllocation =
1122 pdevice->rad_info.family == CHIP_TONGA ||
1123 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1124 properties->sgprAllocationGranularity =
1125 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1126
1127 /* VGPR. */
1128 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1129 properties->minVgprAllocation = 4;
1130 properties->maxVgprAllocation = 256;
1131 properties->vgprAllocationGranularity = 4;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1135 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1136 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1137 properties->maxVertexAttribDivisor = UINT32_MAX;
1138 break;
1139 }
1140 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1141 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1142 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1143 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1144 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1145 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1146 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1147 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1148 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1149 properties->robustBufferAccessUpdateAfterBind = false;
1150 properties->quadDivergentImplicitLod = false;
1151
1152 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1153 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1154 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1155 32 /* sampler, largest when combined with image */ +
1156 64 /* sampled image */ +
1157 64 /* storage image */);
1158 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1159 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1160 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1162 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1163 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1164 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1165 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1166 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1167 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1168 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1169 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1170 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1171 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1172 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1176 VkPhysicalDeviceProtectedMemoryProperties *properties =
1177 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1178 properties->protectedNoFault = false;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1182 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1183 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1184 properties->primitiveOverestimationSize = 0;
1185 properties->maxExtraPrimitiveOverestimationSize = 0;
1186 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1187 properties->primitiveUnderestimation = VK_FALSE;
1188 properties->conservativePointAndLineRasterization = VK_FALSE;
1189 properties->degenerateTrianglesRasterized = VK_FALSE;
1190 properties->degenerateLinesRasterized = VK_FALSE;
1191 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1192 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1193 break;
1194 }
1195 default:
1196 break;
1197 }
1198 }
1199 }
1200
1201 static void radv_get_physical_device_queue_family_properties(
1202 struct radv_physical_device* pdevice,
1203 uint32_t* pCount,
1204 VkQueueFamilyProperties** pQueueFamilyProperties)
1205 {
1206 int num_queue_families = 1;
1207 int idx;
1208 if (pdevice->rad_info.num_compute_rings > 0 &&
1209 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1210 num_queue_families++;
1211
1212 if (pQueueFamilyProperties == NULL) {
1213 *pCount = num_queue_families;
1214 return;
1215 }
1216
1217 if (!*pCount)
1218 return;
1219
1220 idx = 0;
1221 if (*pCount >= 1) {
1222 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1223 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1224 VK_QUEUE_COMPUTE_BIT |
1225 VK_QUEUE_TRANSFER_BIT |
1226 VK_QUEUE_SPARSE_BINDING_BIT,
1227 .queueCount = 1,
1228 .timestampValidBits = 64,
1229 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1230 };
1231 idx++;
1232 }
1233
1234 if (pdevice->rad_info.num_compute_rings > 0 &&
1235 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1236 if (*pCount > idx) {
1237 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1238 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1239 VK_QUEUE_TRANSFER_BIT |
1240 VK_QUEUE_SPARSE_BINDING_BIT,
1241 .queueCount = pdevice->rad_info.num_compute_rings,
1242 .timestampValidBits = 64,
1243 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1244 };
1245 idx++;
1246 }
1247 }
1248 *pCount = idx;
1249 }
1250
1251 void radv_GetPhysicalDeviceQueueFamilyProperties(
1252 VkPhysicalDevice physicalDevice,
1253 uint32_t* pCount,
1254 VkQueueFamilyProperties* pQueueFamilyProperties)
1255 {
1256 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1257 if (!pQueueFamilyProperties) {
1258 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1259 return;
1260 }
1261 VkQueueFamilyProperties *properties[] = {
1262 pQueueFamilyProperties + 0,
1263 pQueueFamilyProperties + 1,
1264 pQueueFamilyProperties + 2,
1265 };
1266 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1267 assert(*pCount <= 3);
1268 }
1269
1270 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1271 VkPhysicalDevice physicalDevice,
1272 uint32_t* pCount,
1273 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1274 {
1275 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1276 if (!pQueueFamilyProperties) {
1277 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1278 return;
1279 }
1280 VkQueueFamilyProperties *properties[] = {
1281 &pQueueFamilyProperties[0].queueFamilyProperties,
1282 &pQueueFamilyProperties[1].queueFamilyProperties,
1283 &pQueueFamilyProperties[2].queueFamilyProperties,
1284 };
1285 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1286 assert(*pCount <= 3);
1287 }
1288
1289 void radv_GetPhysicalDeviceMemoryProperties(
1290 VkPhysicalDevice physicalDevice,
1291 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1292 {
1293 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1294
1295 *pMemoryProperties = physical_device->memory_properties;
1296 }
1297
1298 void radv_GetPhysicalDeviceMemoryProperties2(
1299 VkPhysicalDevice physicalDevice,
1300 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1301 {
1302 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1303 &pMemoryProperties->memoryProperties);
1304 }
1305
1306 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1307 VkDevice _device,
1308 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1309 const void *pHostPointer,
1310 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1311 {
1312 RADV_FROM_HANDLE(radv_device, device, _device);
1313
1314 switch (handleType)
1315 {
1316 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1317 const struct radv_physical_device *physical_device = device->physical_device;
1318 uint32_t memoryTypeBits = 0;
1319 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1320 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1321 memoryTypeBits = (1 << i);
1322 break;
1323 }
1324 }
1325 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1326 return VK_SUCCESS;
1327 }
1328 default:
1329 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1330 }
1331 }
1332
1333 static enum radeon_ctx_priority
1334 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1335 {
1336 /* Default to MEDIUM when a specific global priority isn't requested */
1337 if (!pObj)
1338 return RADEON_CTX_PRIORITY_MEDIUM;
1339
1340 switch(pObj->globalPriority) {
1341 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1342 return RADEON_CTX_PRIORITY_REALTIME;
1343 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1344 return RADEON_CTX_PRIORITY_HIGH;
1345 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1346 return RADEON_CTX_PRIORITY_MEDIUM;
1347 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1348 return RADEON_CTX_PRIORITY_LOW;
1349 default:
1350 unreachable("Illegal global priority value");
1351 return RADEON_CTX_PRIORITY_INVALID;
1352 }
1353 }
1354
1355 static int
1356 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1357 uint32_t queue_family_index, int idx,
1358 VkDeviceQueueCreateFlags flags,
1359 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1360 {
1361 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1362 queue->device = device;
1363 queue->queue_family_index = queue_family_index;
1364 queue->queue_idx = idx;
1365 queue->priority = radv_get_queue_global_priority(global_priority);
1366 queue->flags = flags;
1367
1368 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1369 if (!queue->hw_ctx)
1370 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1371
1372 return VK_SUCCESS;
1373 }
1374
1375 static void
1376 radv_queue_finish(struct radv_queue *queue)
1377 {
1378 if (queue->hw_ctx)
1379 queue->device->ws->ctx_destroy(queue->hw_ctx);
1380
1381 if (queue->initial_full_flush_preamble_cs)
1382 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1383 if (queue->initial_preamble_cs)
1384 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1385 if (queue->continue_preamble_cs)
1386 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1387 if (queue->descriptor_bo)
1388 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1389 if (queue->scratch_bo)
1390 queue->device->ws->buffer_destroy(queue->scratch_bo);
1391 if (queue->esgs_ring_bo)
1392 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1393 if (queue->gsvs_ring_bo)
1394 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1395 if (queue->tess_rings_bo)
1396 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1397 if (queue->compute_scratch_bo)
1398 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1399 }
1400
1401 static void
1402 radv_bo_list_init(struct radv_bo_list *bo_list)
1403 {
1404 pthread_mutex_init(&bo_list->mutex, NULL);
1405 bo_list->list.count = bo_list->capacity = 0;
1406 bo_list->list.bos = NULL;
1407 }
1408
1409 static void
1410 radv_bo_list_finish(struct radv_bo_list *bo_list)
1411 {
1412 free(bo_list->list.bos);
1413 pthread_mutex_destroy(&bo_list->mutex);
1414 }
1415
1416 static VkResult radv_bo_list_add(struct radv_device *device,
1417 struct radeon_winsys_bo *bo)
1418 {
1419 struct radv_bo_list *bo_list = &device->bo_list;
1420
1421 if (unlikely(!device->use_global_bo_list))
1422 return VK_SUCCESS;
1423
1424 pthread_mutex_lock(&bo_list->mutex);
1425 if (bo_list->list.count == bo_list->capacity) {
1426 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1427 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1428
1429 if (!data) {
1430 pthread_mutex_unlock(&bo_list->mutex);
1431 return VK_ERROR_OUT_OF_HOST_MEMORY;
1432 }
1433
1434 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1435 bo_list->capacity = capacity;
1436 }
1437
1438 bo_list->list.bos[bo_list->list.count++] = bo;
1439 pthread_mutex_unlock(&bo_list->mutex);
1440 return VK_SUCCESS;
1441 }
1442
1443 static void radv_bo_list_remove(struct radv_device *device,
1444 struct radeon_winsys_bo *bo)
1445 {
1446 struct radv_bo_list *bo_list = &device->bo_list;
1447
1448 if (unlikely(!device->use_global_bo_list))
1449 return;
1450
1451 pthread_mutex_lock(&bo_list->mutex);
1452 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1453 if (bo_list->list.bos[i] == bo) {
1454 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1455 --bo_list->list.count;
1456 break;
1457 }
1458 }
1459 pthread_mutex_unlock(&bo_list->mutex);
1460 }
1461
1462 static void
1463 radv_device_init_gs_info(struct radv_device *device)
1464 {
1465 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1466 device->physical_device->rad_info.family);
1467 }
1468
1469 static int radv_get_device_extension_index(const char *name)
1470 {
1471 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1472 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1473 return i;
1474 }
1475 return -1;
1476 }
1477
1478 static int
1479 radv_get_int_debug_option(const char *name, int default_value)
1480 {
1481 const char *str;
1482 int result;
1483
1484 str = getenv(name);
1485 if (!str) {
1486 result = default_value;
1487 } else {
1488 char *endptr;
1489
1490 result = strtol(str, &endptr, 0);
1491 if (str == endptr) {
1492 /* No digits founs. */
1493 result = default_value;
1494 }
1495 }
1496
1497 return result;
1498 }
1499
1500 VkResult radv_CreateDevice(
1501 VkPhysicalDevice physicalDevice,
1502 const VkDeviceCreateInfo* pCreateInfo,
1503 const VkAllocationCallbacks* pAllocator,
1504 VkDevice* pDevice)
1505 {
1506 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1507 VkResult result;
1508 struct radv_device *device;
1509
1510 bool keep_shader_info = false;
1511
1512 /* Check enabled features */
1513 if (pCreateInfo->pEnabledFeatures) {
1514 VkPhysicalDeviceFeatures supported_features;
1515 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1516 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1517 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1518 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1519 for (uint32_t i = 0; i < num_features; i++) {
1520 if (enabled_feature[i] && !supported_feature[i])
1521 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1522 }
1523 }
1524
1525 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1526 sizeof(*device), 8,
1527 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1528 if (!device)
1529 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1530
1531 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1532 device->instance = physical_device->instance;
1533 device->physical_device = physical_device;
1534
1535 device->ws = physical_device->ws;
1536 if (pAllocator)
1537 device->alloc = *pAllocator;
1538 else
1539 device->alloc = physical_device->instance->alloc;
1540
1541 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1542 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1543 int index = radv_get_device_extension_index(ext_name);
1544 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1545 vk_free(&device->alloc, device);
1546 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1547 }
1548
1549 device->enabled_extensions.extensions[index] = true;
1550 }
1551
1552 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1553
1554 /* With update after bind we can't attach bo's to the command buffer
1555 * from the descriptor set anymore, so we have to use a global BO list.
1556 */
1557 device->use_global_bo_list =
1558 device->enabled_extensions.EXT_descriptor_indexing;
1559
1560 mtx_init(&device->shader_slab_mutex, mtx_plain);
1561 list_inithead(&device->shader_slabs);
1562
1563 radv_bo_list_init(&device->bo_list);
1564
1565 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1566 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1567 uint32_t qfi = queue_create->queueFamilyIndex;
1568 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1569 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1570
1571 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1572
1573 device->queues[qfi] = vk_alloc(&device->alloc,
1574 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1575 if (!device->queues[qfi]) {
1576 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1577 goto fail;
1578 }
1579
1580 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1581
1582 device->queue_count[qfi] = queue_create->queueCount;
1583
1584 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1585 result = radv_queue_init(device, &device->queues[qfi][q],
1586 qfi, q, queue_create->flags,
1587 global_priority);
1588 if (result != VK_SUCCESS)
1589 goto fail;
1590 }
1591 }
1592
1593 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1594 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1595 device->physical_device->rad_info.family == CHIP_RAVEN);
1596
1597 /* Disabled and not implemented for now. */
1598 device->dfsm_allowed = device->pbb_allowed &&
1599 device->physical_device->rad_info.family == CHIP_RAVEN;
1600
1601 #ifdef ANDROID
1602 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1603 #endif
1604
1605 /* The maximum number of scratch waves. Scratch space isn't divided
1606 * evenly between CUs. The number is only a function of the number of CUs.
1607 * We can decrease the constant to decrease the scratch buffer size.
1608 *
1609 * sctx->scratch_waves must be >= the maximum possible size of
1610 * 1 threadgroup, so that the hw doesn't hang from being unable
1611 * to start any.
1612 *
1613 * The recommended value is 4 per CU at most. Higher numbers don't
1614 * bring much benefit, but they still occupy chip resources (think
1615 * async compute). I've seen ~2% performance difference between 4 and 32.
1616 */
1617 uint32_t max_threads_per_block = 2048;
1618 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1619 max_threads_per_block / 64);
1620
1621 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1622
1623 if (device->physical_device->rad_info.chip_class >= CIK) {
1624 /* If the KMD allows it (there is a KMD hw register for it),
1625 * allow launching waves out-of-order.
1626 */
1627 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1628 }
1629
1630 radv_device_init_gs_info(device);
1631
1632 device->tess_offchip_block_dw_size =
1633 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1634 device->has_distributed_tess =
1635 device->physical_device->rad_info.chip_class >= VI &&
1636 device->physical_device->rad_info.max_se >= 2;
1637
1638 if (getenv("RADV_TRACE_FILE")) {
1639 const char *filename = getenv("RADV_TRACE_FILE");
1640
1641 keep_shader_info = true;
1642
1643 if (!radv_init_trace(device))
1644 goto fail;
1645
1646 fprintf(stderr, "*****************************************************************************\n");
1647 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1648 fprintf(stderr, "*****************************************************************************\n");
1649
1650 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1651 radv_dump_enabled_options(device, stderr);
1652 }
1653
1654 device->keep_shader_info = keep_shader_info;
1655
1656 result = radv_device_init_meta(device);
1657 if (result != VK_SUCCESS)
1658 goto fail;
1659
1660 radv_device_init_msaa(device);
1661
1662 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1663 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1664 switch (family) {
1665 case RADV_QUEUE_GENERAL:
1666 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1667 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1668 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1669 break;
1670 case RADV_QUEUE_COMPUTE:
1671 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1672 radeon_emit(device->empty_cs[family], 0);
1673 break;
1674 }
1675 device->ws->cs_finalize(device->empty_cs[family]);
1676 }
1677
1678 if (device->physical_device->rad_info.chip_class >= CIK)
1679 cik_create_gfx_config(device);
1680
1681 VkPipelineCacheCreateInfo ci;
1682 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1683 ci.pNext = NULL;
1684 ci.flags = 0;
1685 ci.pInitialData = NULL;
1686 ci.initialDataSize = 0;
1687 VkPipelineCache pc;
1688 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1689 &ci, NULL, &pc);
1690 if (result != VK_SUCCESS)
1691 goto fail_meta;
1692
1693 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1694
1695 device->force_aniso =
1696 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1697 if (device->force_aniso >= 0) {
1698 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1699 1 << util_logbase2(device->force_aniso));
1700 }
1701
1702 *pDevice = radv_device_to_handle(device);
1703 return VK_SUCCESS;
1704
1705 fail_meta:
1706 radv_device_finish_meta(device);
1707 fail:
1708 radv_bo_list_finish(&device->bo_list);
1709
1710 if (device->trace_bo)
1711 device->ws->buffer_destroy(device->trace_bo);
1712
1713 if (device->gfx_init)
1714 device->ws->buffer_destroy(device->gfx_init);
1715
1716 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1717 for (unsigned q = 0; q < device->queue_count[i]; q++)
1718 radv_queue_finish(&device->queues[i][q]);
1719 if (device->queue_count[i])
1720 vk_free(&device->alloc, device->queues[i]);
1721 }
1722
1723 vk_free(&device->alloc, device);
1724 return result;
1725 }
1726
1727 void radv_DestroyDevice(
1728 VkDevice _device,
1729 const VkAllocationCallbacks* pAllocator)
1730 {
1731 RADV_FROM_HANDLE(radv_device, device, _device);
1732
1733 if (!device)
1734 return;
1735
1736 if (device->trace_bo)
1737 device->ws->buffer_destroy(device->trace_bo);
1738
1739 if (device->gfx_init)
1740 device->ws->buffer_destroy(device->gfx_init);
1741
1742 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1743 for (unsigned q = 0; q < device->queue_count[i]; q++)
1744 radv_queue_finish(&device->queues[i][q]);
1745 if (device->queue_count[i])
1746 vk_free(&device->alloc, device->queues[i]);
1747 if (device->empty_cs[i])
1748 device->ws->cs_destroy(device->empty_cs[i]);
1749 }
1750 radv_device_finish_meta(device);
1751
1752 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1753 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1754
1755 radv_destroy_shader_slabs(device);
1756
1757 radv_bo_list_finish(&device->bo_list);
1758 vk_free(&device->alloc, device);
1759 }
1760
1761 VkResult radv_EnumerateInstanceLayerProperties(
1762 uint32_t* pPropertyCount,
1763 VkLayerProperties* pProperties)
1764 {
1765 if (pProperties == NULL) {
1766 *pPropertyCount = 0;
1767 return VK_SUCCESS;
1768 }
1769
1770 /* None supported at this time */
1771 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1772 }
1773
1774 VkResult radv_EnumerateDeviceLayerProperties(
1775 VkPhysicalDevice physicalDevice,
1776 uint32_t* pPropertyCount,
1777 VkLayerProperties* pProperties)
1778 {
1779 if (pProperties == NULL) {
1780 *pPropertyCount = 0;
1781 return VK_SUCCESS;
1782 }
1783
1784 /* None supported at this time */
1785 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1786 }
1787
1788 void radv_GetDeviceQueue2(
1789 VkDevice _device,
1790 const VkDeviceQueueInfo2* pQueueInfo,
1791 VkQueue* pQueue)
1792 {
1793 RADV_FROM_HANDLE(radv_device, device, _device);
1794 struct radv_queue *queue;
1795
1796 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1797 if (pQueueInfo->flags != queue->flags) {
1798 /* From the Vulkan 1.1.70 spec:
1799 *
1800 * "The queue returned by vkGetDeviceQueue2 must have the same
1801 * flags value from this structure as that used at device
1802 * creation time in a VkDeviceQueueCreateInfo instance. If no
1803 * matching flags were specified at device creation time then
1804 * pQueue will return VK_NULL_HANDLE."
1805 */
1806 *pQueue = VK_NULL_HANDLE;
1807 return;
1808 }
1809
1810 *pQueue = radv_queue_to_handle(queue);
1811 }
1812
1813 void radv_GetDeviceQueue(
1814 VkDevice _device,
1815 uint32_t queueFamilyIndex,
1816 uint32_t queueIndex,
1817 VkQueue* pQueue)
1818 {
1819 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1820 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1821 .queueFamilyIndex = queueFamilyIndex,
1822 .queueIndex = queueIndex
1823 };
1824
1825 radv_GetDeviceQueue2(_device, &info, pQueue);
1826 }
1827
1828 static void
1829 fill_geom_tess_rings(struct radv_queue *queue,
1830 uint32_t *map,
1831 bool add_sample_positions,
1832 uint32_t esgs_ring_size,
1833 struct radeon_winsys_bo *esgs_ring_bo,
1834 uint32_t gsvs_ring_size,
1835 struct radeon_winsys_bo *gsvs_ring_bo,
1836 uint32_t tess_factor_ring_size,
1837 uint32_t tess_offchip_ring_offset,
1838 uint32_t tess_offchip_ring_size,
1839 struct radeon_winsys_bo *tess_rings_bo)
1840 {
1841 uint64_t esgs_va = 0, gsvs_va = 0;
1842 uint64_t tess_va = 0, tess_offchip_va = 0;
1843 uint32_t *desc = &map[4];
1844
1845 if (esgs_ring_bo)
1846 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1847 if (gsvs_ring_bo)
1848 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1849 if (tess_rings_bo) {
1850 tess_va = radv_buffer_get_va(tess_rings_bo);
1851 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1852 }
1853
1854 /* stride 0, num records - size, add tid, swizzle, elsize4,
1855 index stride 64 */
1856 desc[0] = esgs_va;
1857 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1858 S_008F04_STRIDE(0) |
1859 S_008F04_SWIZZLE_ENABLE(true);
1860 desc[2] = esgs_ring_size;
1861 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1862 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1863 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1864 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1865 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1866 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1867 S_008F0C_ELEMENT_SIZE(1) |
1868 S_008F0C_INDEX_STRIDE(3) |
1869 S_008F0C_ADD_TID_ENABLE(true);
1870
1871 desc += 4;
1872 /* GS entry for ES->GS ring */
1873 /* stride 0, num records - size, elsize0,
1874 index stride 0 */
1875 desc[0] = esgs_va;
1876 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1877 S_008F04_STRIDE(0) |
1878 S_008F04_SWIZZLE_ENABLE(false);
1879 desc[2] = esgs_ring_size;
1880 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1881 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1882 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1883 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1884 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1885 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1886 S_008F0C_ELEMENT_SIZE(0) |
1887 S_008F0C_INDEX_STRIDE(0) |
1888 S_008F0C_ADD_TID_ENABLE(false);
1889
1890 desc += 4;
1891 /* VS entry for GS->VS ring */
1892 /* stride 0, num records - size, elsize0,
1893 index stride 0 */
1894 desc[0] = gsvs_va;
1895 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1896 S_008F04_STRIDE(0) |
1897 S_008F04_SWIZZLE_ENABLE(false);
1898 desc[2] = gsvs_ring_size;
1899 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1900 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1901 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1902 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1903 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1904 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1905 S_008F0C_ELEMENT_SIZE(0) |
1906 S_008F0C_INDEX_STRIDE(0) |
1907 S_008F0C_ADD_TID_ENABLE(false);
1908 desc += 4;
1909
1910 /* stride gsvs_itemsize, num records 64
1911 elsize 4, index stride 16 */
1912 /* shader will patch stride and desc[2] */
1913 desc[0] = gsvs_va;
1914 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1915 S_008F04_STRIDE(0) |
1916 S_008F04_SWIZZLE_ENABLE(true);
1917 desc[2] = 0;
1918 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1919 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1920 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1921 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1922 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1923 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1924 S_008F0C_ELEMENT_SIZE(1) |
1925 S_008F0C_INDEX_STRIDE(1) |
1926 S_008F0C_ADD_TID_ENABLE(true);
1927 desc += 4;
1928
1929 desc[0] = tess_va;
1930 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1931 S_008F04_STRIDE(0) |
1932 S_008F04_SWIZZLE_ENABLE(false);
1933 desc[2] = tess_factor_ring_size;
1934 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1935 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1936 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1937 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1938 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1939 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1940 S_008F0C_ELEMENT_SIZE(0) |
1941 S_008F0C_INDEX_STRIDE(0) |
1942 S_008F0C_ADD_TID_ENABLE(false);
1943 desc += 4;
1944
1945 desc[0] = tess_offchip_va;
1946 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1947 S_008F04_STRIDE(0) |
1948 S_008F04_SWIZZLE_ENABLE(false);
1949 desc[2] = tess_offchip_ring_size;
1950 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1951 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1952 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1953 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1954 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1955 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1956 S_008F0C_ELEMENT_SIZE(0) |
1957 S_008F0C_INDEX_STRIDE(0) |
1958 S_008F0C_ADD_TID_ENABLE(false);
1959 desc += 4;
1960
1961 /* add sample positions after all rings */
1962 memcpy(desc, queue->device->sample_locations_1x, 8);
1963 desc += 2;
1964 memcpy(desc, queue->device->sample_locations_2x, 16);
1965 desc += 4;
1966 memcpy(desc, queue->device->sample_locations_4x, 32);
1967 desc += 8;
1968 memcpy(desc, queue->device->sample_locations_8x, 64);
1969 desc += 16;
1970 memcpy(desc, queue->device->sample_locations_16x, 128);
1971 }
1972
1973 static unsigned
1974 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1975 {
1976 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1977 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1978 device->physical_device->rad_info.family != CHIP_STONEY;
1979 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1980 unsigned max_offchip_buffers;
1981 unsigned offchip_granularity;
1982 unsigned hs_offchip_param;
1983
1984 /*
1985 * Per RadeonSI:
1986 * This must be one less than the maximum number due to a hw limitation.
1987 * Various hardware bugs in SI, CIK, and GFX9 need this.
1988 *
1989 * Per AMDVLK:
1990 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1991 * Gfx7 should limit max_offchip_buffers to 508
1992 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1993 *
1994 * Follow AMDVLK here.
1995 */
1996 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1997 device->physical_device->rad_info.chip_class == CIK ||
1998 device->physical_device->rad_info.chip_class == SI)
1999 --max_offchip_buffers_per_se;
2000
2001 max_offchip_buffers = max_offchip_buffers_per_se *
2002 device->physical_device->rad_info.max_se;
2003
2004 switch (device->tess_offchip_block_dw_size) {
2005 default:
2006 assert(0);
2007 /* fall through */
2008 case 8192:
2009 offchip_granularity = V_03093C_X_8K_DWORDS;
2010 break;
2011 case 4096:
2012 offchip_granularity = V_03093C_X_4K_DWORDS;
2013 break;
2014 }
2015
2016 switch (device->physical_device->rad_info.chip_class) {
2017 case SI:
2018 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2019 break;
2020 case CIK:
2021 case VI:
2022 case GFX9:
2023 default:
2024 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2025 break;
2026 }
2027
2028 *max_offchip_buffers_p = max_offchip_buffers;
2029 if (device->physical_device->rad_info.chip_class >= CIK) {
2030 if (device->physical_device->rad_info.chip_class >= VI)
2031 --max_offchip_buffers;
2032 hs_offchip_param =
2033 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2034 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2035 } else {
2036 hs_offchip_param =
2037 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2038 }
2039 return hs_offchip_param;
2040 }
2041
2042 static void
2043 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2044 struct radeon_winsys_bo *esgs_ring_bo,
2045 uint32_t esgs_ring_size,
2046 struct radeon_winsys_bo *gsvs_ring_bo,
2047 uint32_t gsvs_ring_size)
2048 {
2049 if (!esgs_ring_bo && !gsvs_ring_bo)
2050 return;
2051
2052 if (esgs_ring_bo)
2053 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2054
2055 if (gsvs_ring_bo)
2056 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2057
2058 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2059 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2060 radeon_emit(cs, esgs_ring_size >> 8);
2061 radeon_emit(cs, gsvs_ring_size >> 8);
2062 } else {
2063 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2064 radeon_emit(cs, esgs_ring_size >> 8);
2065 radeon_emit(cs, gsvs_ring_size >> 8);
2066 }
2067 }
2068
2069 static void
2070 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2071 unsigned hs_offchip_param, unsigned tf_ring_size,
2072 struct radeon_winsys_bo *tess_rings_bo)
2073 {
2074 uint64_t tf_va;
2075
2076 if (!tess_rings_bo)
2077 return;
2078
2079 tf_va = radv_buffer_get_va(tess_rings_bo);
2080
2081 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2082
2083 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2084 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2085 S_030938_SIZE(tf_ring_size / 4));
2086 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2087 tf_va >> 8);
2088 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2089 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2090 S_030944_BASE_HI(tf_va >> 40));
2091 }
2092 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2093 hs_offchip_param);
2094 } else {
2095 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2096 S_008988_SIZE(tf_ring_size / 4));
2097 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2098 tf_va >> 8);
2099 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2100 hs_offchip_param);
2101 }
2102 }
2103
2104 static void
2105 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2106 struct radeon_winsys_bo *compute_scratch_bo)
2107 {
2108 uint64_t scratch_va;
2109
2110 if (!compute_scratch_bo)
2111 return;
2112
2113 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2114
2115 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2116
2117 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2118 radeon_emit(cs, scratch_va);
2119 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2120 S_008F04_SWIZZLE_ENABLE(1));
2121 }
2122
2123 static void
2124 radv_emit_global_shader_pointers(struct radv_queue *queue,
2125 struct radeon_cmdbuf *cs,
2126 struct radeon_winsys_bo *descriptor_bo)
2127 {
2128 uint64_t va;
2129
2130 if (!descriptor_bo)
2131 return;
2132
2133 va = radv_buffer_get_va(descriptor_bo);
2134
2135 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2136
2137 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2138 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2139 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2140 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2141 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2142
2143 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2144 radv_emit_shader_pointer(queue->device, cs, regs[i],
2145 va, true);
2146 }
2147 } else {
2148 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2149 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2150 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2151 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2152 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2153 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2154
2155 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2156 radv_emit_shader_pointer(queue->device, cs, regs[i],
2157 va, true);
2158 }
2159 }
2160 }
2161
2162 static void
2163 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2164 {
2165 struct radv_device *device = queue->device;
2166
2167 if (device->gfx_init) {
2168 uint64_t va = radv_buffer_get_va(device->gfx_init);
2169
2170 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2171 radeon_emit(cs, va);
2172 radeon_emit(cs, va >> 32);
2173 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2174
2175 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2176 } else {
2177 struct radv_physical_device *physical_device = device->physical_device;
2178 si_emit_graphics(physical_device, cs);
2179 }
2180 }
2181
2182 static void
2183 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2184 {
2185 struct radv_physical_device *physical_device = queue->device->physical_device;
2186 si_emit_compute(physical_device, cs);
2187 }
2188
2189 static VkResult
2190 radv_get_preamble_cs(struct radv_queue *queue,
2191 uint32_t scratch_size,
2192 uint32_t compute_scratch_size,
2193 uint32_t esgs_ring_size,
2194 uint32_t gsvs_ring_size,
2195 bool needs_tess_rings,
2196 bool needs_sample_positions,
2197 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2198 struct radeon_cmdbuf **initial_preamble_cs,
2199 struct radeon_cmdbuf **continue_preamble_cs)
2200 {
2201 struct radeon_winsys_bo *scratch_bo = NULL;
2202 struct radeon_winsys_bo *descriptor_bo = NULL;
2203 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2204 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2205 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2206 struct radeon_winsys_bo *tess_rings_bo = NULL;
2207 struct radeon_cmdbuf *dest_cs[3] = {0};
2208 bool add_tess_rings = false, add_sample_positions = false;
2209 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2210 unsigned max_offchip_buffers;
2211 unsigned hs_offchip_param = 0;
2212 unsigned tess_offchip_ring_offset;
2213 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2214 if (!queue->has_tess_rings) {
2215 if (needs_tess_rings)
2216 add_tess_rings = true;
2217 }
2218 if (!queue->has_sample_positions) {
2219 if (needs_sample_positions)
2220 add_sample_positions = true;
2221 }
2222 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2223 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2224 &max_offchip_buffers);
2225 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2226 tess_offchip_ring_size = max_offchip_buffers *
2227 queue->device->tess_offchip_block_dw_size * 4;
2228
2229 if (scratch_size <= queue->scratch_size &&
2230 compute_scratch_size <= queue->compute_scratch_size &&
2231 esgs_ring_size <= queue->esgs_ring_size &&
2232 gsvs_ring_size <= queue->gsvs_ring_size &&
2233 !add_tess_rings && !add_sample_positions &&
2234 queue->initial_preamble_cs) {
2235 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2236 *initial_preamble_cs = queue->initial_preamble_cs;
2237 *continue_preamble_cs = queue->continue_preamble_cs;
2238 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2239 *continue_preamble_cs = NULL;
2240 return VK_SUCCESS;
2241 }
2242
2243 if (scratch_size > queue->scratch_size) {
2244 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2245 scratch_size,
2246 4096,
2247 RADEON_DOMAIN_VRAM,
2248 ring_bo_flags);
2249 if (!scratch_bo)
2250 goto fail;
2251 } else
2252 scratch_bo = queue->scratch_bo;
2253
2254 if (compute_scratch_size > queue->compute_scratch_size) {
2255 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2256 compute_scratch_size,
2257 4096,
2258 RADEON_DOMAIN_VRAM,
2259 ring_bo_flags);
2260 if (!compute_scratch_bo)
2261 goto fail;
2262
2263 } else
2264 compute_scratch_bo = queue->compute_scratch_bo;
2265
2266 if (esgs_ring_size > queue->esgs_ring_size) {
2267 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2268 esgs_ring_size,
2269 4096,
2270 RADEON_DOMAIN_VRAM,
2271 ring_bo_flags);
2272 if (!esgs_ring_bo)
2273 goto fail;
2274 } else {
2275 esgs_ring_bo = queue->esgs_ring_bo;
2276 esgs_ring_size = queue->esgs_ring_size;
2277 }
2278
2279 if (gsvs_ring_size > queue->gsvs_ring_size) {
2280 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2281 gsvs_ring_size,
2282 4096,
2283 RADEON_DOMAIN_VRAM,
2284 ring_bo_flags);
2285 if (!gsvs_ring_bo)
2286 goto fail;
2287 } else {
2288 gsvs_ring_bo = queue->gsvs_ring_bo;
2289 gsvs_ring_size = queue->gsvs_ring_size;
2290 }
2291
2292 if (add_tess_rings) {
2293 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2294 tess_offchip_ring_offset + tess_offchip_ring_size,
2295 256,
2296 RADEON_DOMAIN_VRAM,
2297 ring_bo_flags);
2298 if (!tess_rings_bo)
2299 goto fail;
2300 } else {
2301 tess_rings_bo = queue->tess_rings_bo;
2302 }
2303
2304 if (scratch_bo != queue->scratch_bo ||
2305 esgs_ring_bo != queue->esgs_ring_bo ||
2306 gsvs_ring_bo != queue->gsvs_ring_bo ||
2307 tess_rings_bo != queue->tess_rings_bo ||
2308 add_sample_positions) {
2309 uint32_t size = 0;
2310 if (gsvs_ring_bo || esgs_ring_bo ||
2311 tess_rings_bo || add_sample_positions) {
2312 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2313 if (add_sample_positions)
2314 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2315 }
2316 else if (scratch_bo)
2317 size = 8; /* 2 dword */
2318
2319 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2320 size,
2321 4096,
2322 RADEON_DOMAIN_VRAM,
2323 RADEON_FLAG_CPU_ACCESS |
2324 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2325 RADEON_FLAG_READ_ONLY);
2326 if (!descriptor_bo)
2327 goto fail;
2328 } else
2329 descriptor_bo = queue->descriptor_bo;
2330
2331 for(int i = 0; i < 3; ++i) {
2332 struct radeon_cmdbuf *cs = NULL;
2333 cs = queue->device->ws->cs_create(queue->device->ws,
2334 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2335 if (!cs)
2336 goto fail;
2337
2338 dest_cs[i] = cs;
2339
2340 if (scratch_bo)
2341 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2342
2343 /* Emit initial configuration. */
2344 switch (queue->queue_family_index) {
2345 case RADV_QUEUE_GENERAL:
2346 radv_init_graphics_state(cs, queue);
2347 break;
2348 case RADV_QUEUE_COMPUTE:
2349 radv_init_compute_state(cs, queue);
2350 break;
2351 case RADV_QUEUE_TRANSFER:
2352 break;
2353 }
2354
2355 if (descriptor_bo != queue->descriptor_bo) {
2356 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2357
2358 if (scratch_bo) {
2359 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2360 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2361 S_008F04_SWIZZLE_ENABLE(1);
2362 map[0] = scratch_va;
2363 map[1] = rsrc1;
2364 }
2365
2366 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2367 add_sample_positions)
2368 fill_geom_tess_rings(queue, map, add_sample_positions,
2369 esgs_ring_size, esgs_ring_bo,
2370 gsvs_ring_size, gsvs_ring_bo,
2371 tess_factor_ring_size,
2372 tess_offchip_ring_offset,
2373 tess_offchip_ring_size,
2374 tess_rings_bo);
2375
2376 queue->device->ws->buffer_unmap(descriptor_bo);
2377 }
2378
2379 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2380 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2381 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2382 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2383 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2384 }
2385
2386 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2387 gsvs_ring_bo, gsvs_ring_size);
2388 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2389 tess_factor_ring_size, tess_rings_bo);
2390 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2391 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2392
2393 if (i == 0) {
2394 si_cs_emit_cache_flush(cs,
2395 queue->device->physical_device->rad_info.chip_class,
2396 NULL, 0,
2397 queue->queue_family_index == RING_COMPUTE &&
2398 queue->device->physical_device->rad_info.chip_class >= CIK,
2399 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2400 RADV_CMD_FLAG_INV_ICACHE |
2401 RADV_CMD_FLAG_INV_SMEM_L1 |
2402 RADV_CMD_FLAG_INV_VMEM_L1 |
2403 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2404 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2405 } else if (i == 1) {
2406 si_cs_emit_cache_flush(cs,
2407 queue->device->physical_device->rad_info.chip_class,
2408 NULL, 0,
2409 queue->queue_family_index == RING_COMPUTE &&
2410 queue->device->physical_device->rad_info.chip_class >= CIK,
2411 RADV_CMD_FLAG_INV_ICACHE |
2412 RADV_CMD_FLAG_INV_SMEM_L1 |
2413 RADV_CMD_FLAG_INV_VMEM_L1 |
2414 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2415 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2416 }
2417
2418 if (!queue->device->ws->cs_finalize(cs))
2419 goto fail;
2420 }
2421
2422 if (queue->initial_full_flush_preamble_cs)
2423 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2424
2425 if (queue->initial_preamble_cs)
2426 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2427
2428 if (queue->continue_preamble_cs)
2429 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2430
2431 queue->initial_full_flush_preamble_cs = dest_cs[0];
2432 queue->initial_preamble_cs = dest_cs[1];
2433 queue->continue_preamble_cs = dest_cs[2];
2434
2435 if (scratch_bo != queue->scratch_bo) {
2436 if (queue->scratch_bo)
2437 queue->device->ws->buffer_destroy(queue->scratch_bo);
2438 queue->scratch_bo = scratch_bo;
2439 queue->scratch_size = scratch_size;
2440 }
2441
2442 if (compute_scratch_bo != queue->compute_scratch_bo) {
2443 if (queue->compute_scratch_bo)
2444 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2445 queue->compute_scratch_bo = compute_scratch_bo;
2446 queue->compute_scratch_size = compute_scratch_size;
2447 }
2448
2449 if (esgs_ring_bo != queue->esgs_ring_bo) {
2450 if (queue->esgs_ring_bo)
2451 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2452 queue->esgs_ring_bo = esgs_ring_bo;
2453 queue->esgs_ring_size = esgs_ring_size;
2454 }
2455
2456 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2457 if (queue->gsvs_ring_bo)
2458 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2459 queue->gsvs_ring_bo = gsvs_ring_bo;
2460 queue->gsvs_ring_size = gsvs_ring_size;
2461 }
2462
2463 if (tess_rings_bo != queue->tess_rings_bo) {
2464 queue->tess_rings_bo = tess_rings_bo;
2465 queue->has_tess_rings = true;
2466 }
2467
2468 if (descriptor_bo != queue->descriptor_bo) {
2469 if (queue->descriptor_bo)
2470 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2471
2472 queue->descriptor_bo = descriptor_bo;
2473 }
2474
2475 if (add_sample_positions)
2476 queue->has_sample_positions = true;
2477
2478 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2479 *initial_preamble_cs = queue->initial_preamble_cs;
2480 *continue_preamble_cs = queue->continue_preamble_cs;
2481 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2482 *continue_preamble_cs = NULL;
2483 return VK_SUCCESS;
2484 fail:
2485 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2486 if (dest_cs[i])
2487 queue->device->ws->cs_destroy(dest_cs[i]);
2488 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2489 queue->device->ws->buffer_destroy(descriptor_bo);
2490 if (scratch_bo && scratch_bo != queue->scratch_bo)
2491 queue->device->ws->buffer_destroy(scratch_bo);
2492 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2493 queue->device->ws->buffer_destroy(compute_scratch_bo);
2494 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2495 queue->device->ws->buffer_destroy(esgs_ring_bo);
2496 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2497 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2498 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2499 queue->device->ws->buffer_destroy(tess_rings_bo);
2500 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2501 }
2502
2503 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2504 struct radv_winsys_sem_counts *counts,
2505 int num_sems,
2506 const VkSemaphore *sems,
2507 VkFence _fence,
2508 bool reset_temp)
2509 {
2510 int syncobj_idx = 0, sem_idx = 0;
2511
2512 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2513 return VK_SUCCESS;
2514
2515 for (uint32_t i = 0; i < num_sems; i++) {
2516 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2517
2518 if (sem->temp_syncobj || sem->syncobj)
2519 counts->syncobj_count++;
2520 else
2521 counts->sem_count++;
2522 }
2523
2524 if (_fence != VK_NULL_HANDLE) {
2525 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2526 if (fence->temp_syncobj || fence->syncobj)
2527 counts->syncobj_count++;
2528 }
2529
2530 if (counts->syncobj_count) {
2531 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2532 if (!counts->syncobj)
2533 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2534 }
2535
2536 if (counts->sem_count) {
2537 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2538 if (!counts->sem) {
2539 free(counts->syncobj);
2540 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2541 }
2542 }
2543
2544 for (uint32_t i = 0; i < num_sems; i++) {
2545 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2546
2547 if (sem->temp_syncobj) {
2548 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2549 }
2550 else if (sem->syncobj)
2551 counts->syncobj[syncobj_idx++] = sem->syncobj;
2552 else {
2553 assert(sem->sem);
2554 counts->sem[sem_idx++] = sem->sem;
2555 }
2556 }
2557
2558 if (_fence != VK_NULL_HANDLE) {
2559 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2560 if (fence->temp_syncobj)
2561 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2562 else if (fence->syncobj)
2563 counts->syncobj[syncobj_idx++] = fence->syncobj;
2564 }
2565
2566 return VK_SUCCESS;
2567 }
2568
2569 static void
2570 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2571 {
2572 free(sem_info->wait.syncobj);
2573 free(sem_info->wait.sem);
2574 free(sem_info->signal.syncobj);
2575 free(sem_info->signal.sem);
2576 }
2577
2578
2579 static void radv_free_temp_syncobjs(struct radv_device *device,
2580 int num_sems,
2581 const VkSemaphore *sems)
2582 {
2583 for (uint32_t i = 0; i < num_sems; i++) {
2584 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2585
2586 if (sem->temp_syncobj) {
2587 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2588 sem->temp_syncobj = 0;
2589 }
2590 }
2591 }
2592
2593 static VkResult
2594 radv_alloc_sem_info(struct radv_instance *instance,
2595 struct radv_winsys_sem_info *sem_info,
2596 int num_wait_sems,
2597 const VkSemaphore *wait_sems,
2598 int num_signal_sems,
2599 const VkSemaphore *signal_sems,
2600 VkFence fence)
2601 {
2602 VkResult ret;
2603 memset(sem_info, 0, sizeof(*sem_info));
2604
2605 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2606 if (ret)
2607 return ret;
2608 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2609 if (ret)
2610 radv_free_sem_info(sem_info);
2611
2612 /* caller can override these */
2613 sem_info->cs_emit_wait = true;
2614 sem_info->cs_emit_signal = true;
2615 return ret;
2616 }
2617
2618 /* Signals fence as soon as all the work currently put on queue is done. */
2619 static VkResult radv_signal_fence(struct radv_queue *queue,
2620 struct radv_fence *fence)
2621 {
2622 int ret;
2623 VkResult result;
2624 struct radv_winsys_sem_info sem_info;
2625
2626 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2627 radv_fence_to_handle(fence));
2628 if (result != VK_SUCCESS)
2629 return result;
2630
2631 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2632 &queue->device->empty_cs[queue->queue_family_index],
2633 1, NULL, NULL, &sem_info, NULL,
2634 false, fence->fence);
2635 radv_free_sem_info(&sem_info);
2636
2637 if (ret)
2638 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2639
2640 return VK_SUCCESS;
2641 }
2642
2643 VkResult radv_QueueSubmit(
2644 VkQueue _queue,
2645 uint32_t submitCount,
2646 const VkSubmitInfo* pSubmits,
2647 VkFence _fence)
2648 {
2649 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2650 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2651 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2652 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2653 int ret;
2654 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2655 uint32_t scratch_size = 0;
2656 uint32_t compute_scratch_size = 0;
2657 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2658 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2659 VkResult result;
2660 bool fence_emitted = false;
2661 bool tess_rings_needed = false;
2662 bool sample_positions_needed = false;
2663
2664 /* Do this first so failing to allocate scratch buffers can't result in
2665 * partially executed submissions. */
2666 for (uint32_t i = 0; i < submitCount; i++) {
2667 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2668 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2669 pSubmits[i].pCommandBuffers[j]);
2670
2671 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2672 compute_scratch_size = MAX2(compute_scratch_size,
2673 cmd_buffer->compute_scratch_size_needed);
2674 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2675 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2676 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2677 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2678 }
2679 }
2680
2681 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2682 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2683 sample_positions_needed, &initial_flush_preamble_cs,
2684 &initial_preamble_cs, &continue_preamble_cs);
2685 if (result != VK_SUCCESS)
2686 return result;
2687
2688 for (uint32_t i = 0; i < submitCount; i++) {
2689 struct radeon_cmdbuf **cs_array;
2690 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2691 bool can_patch = true;
2692 uint32_t advance;
2693 struct radv_winsys_sem_info sem_info;
2694
2695 result = radv_alloc_sem_info(queue->device->instance,
2696 &sem_info,
2697 pSubmits[i].waitSemaphoreCount,
2698 pSubmits[i].pWaitSemaphores,
2699 pSubmits[i].signalSemaphoreCount,
2700 pSubmits[i].pSignalSemaphores,
2701 _fence);
2702 if (result != VK_SUCCESS)
2703 return result;
2704
2705 if (!pSubmits[i].commandBufferCount) {
2706 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2707 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2708 &queue->device->empty_cs[queue->queue_family_index],
2709 1, NULL, NULL,
2710 &sem_info, NULL,
2711 false, base_fence);
2712 if (ret) {
2713 radv_loge("failed to submit CS %d\n", i);
2714 abort();
2715 }
2716 fence_emitted = true;
2717 }
2718 radv_free_sem_info(&sem_info);
2719 continue;
2720 }
2721
2722 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2723 (pSubmits[i].commandBufferCount));
2724
2725 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2726 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2727 pSubmits[i].pCommandBuffers[j]);
2728 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2729
2730 cs_array[j] = cmd_buffer->cs;
2731 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2732 can_patch = false;
2733
2734 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2735 }
2736
2737 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2738 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2739 const struct radv_winsys_bo_list *bo_list = NULL;
2740
2741 advance = MIN2(max_cs_submission,
2742 pSubmits[i].commandBufferCount - j);
2743
2744 if (queue->device->trace_bo)
2745 *queue->device->trace_id_ptr = 0;
2746
2747 sem_info.cs_emit_wait = j == 0;
2748 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2749
2750 if (unlikely(queue->device->use_global_bo_list)) {
2751 pthread_mutex_lock(&queue->device->bo_list.mutex);
2752 bo_list = &queue->device->bo_list.list;
2753 }
2754
2755 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2756 advance, initial_preamble, continue_preamble_cs,
2757 &sem_info, bo_list,
2758 can_patch, base_fence);
2759
2760 if (unlikely(queue->device->use_global_bo_list))
2761 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2762
2763 if (ret) {
2764 radv_loge("failed to submit CS %d\n", i);
2765 abort();
2766 }
2767 fence_emitted = true;
2768 if (queue->device->trace_bo) {
2769 radv_check_gpu_hangs(queue, cs_array[j]);
2770 }
2771 }
2772
2773 radv_free_temp_syncobjs(queue->device,
2774 pSubmits[i].waitSemaphoreCount,
2775 pSubmits[i].pWaitSemaphores);
2776 radv_free_sem_info(&sem_info);
2777 free(cs_array);
2778 }
2779
2780 if (fence) {
2781 if (!fence_emitted) {
2782 result = radv_signal_fence(queue, fence);
2783 if (result != VK_SUCCESS)
2784 return result;
2785 }
2786 fence->submitted = true;
2787 }
2788
2789 return VK_SUCCESS;
2790 }
2791
2792 VkResult radv_QueueWaitIdle(
2793 VkQueue _queue)
2794 {
2795 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2796
2797 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2798 radv_queue_family_to_ring(queue->queue_family_index),
2799 queue->queue_idx);
2800 return VK_SUCCESS;
2801 }
2802
2803 VkResult radv_DeviceWaitIdle(
2804 VkDevice _device)
2805 {
2806 RADV_FROM_HANDLE(radv_device, device, _device);
2807
2808 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2809 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2810 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2811 }
2812 }
2813 return VK_SUCCESS;
2814 }
2815
2816 VkResult radv_EnumerateInstanceExtensionProperties(
2817 const char* pLayerName,
2818 uint32_t* pPropertyCount,
2819 VkExtensionProperties* pProperties)
2820 {
2821 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2822
2823 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2824 if (radv_supported_instance_extensions.extensions[i]) {
2825 vk_outarray_append(&out, prop) {
2826 *prop = radv_instance_extensions[i];
2827 }
2828 }
2829 }
2830
2831 return vk_outarray_status(&out);
2832 }
2833
2834 VkResult radv_EnumerateDeviceExtensionProperties(
2835 VkPhysicalDevice physicalDevice,
2836 const char* pLayerName,
2837 uint32_t* pPropertyCount,
2838 VkExtensionProperties* pProperties)
2839 {
2840 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2841 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2842
2843 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2844 if (device->supported_extensions.extensions[i]) {
2845 vk_outarray_append(&out, prop) {
2846 *prop = radv_device_extensions[i];
2847 }
2848 }
2849 }
2850
2851 return vk_outarray_status(&out);
2852 }
2853
2854 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2855 VkInstance _instance,
2856 const char* pName)
2857 {
2858 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2859
2860 return radv_lookup_entrypoint_checked(pName,
2861 instance ? instance->apiVersion : 0,
2862 instance ? &instance->enabled_extensions : NULL,
2863 NULL);
2864 }
2865
2866 /* The loader wants us to expose a second GetInstanceProcAddr function
2867 * to work around certain LD_PRELOAD issues seen in apps.
2868 */
2869 PUBLIC
2870 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2871 VkInstance instance,
2872 const char* pName);
2873
2874 PUBLIC
2875 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2876 VkInstance instance,
2877 const char* pName)
2878 {
2879 return radv_GetInstanceProcAddr(instance, pName);
2880 }
2881
2882 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2883 VkDevice _device,
2884 const char* pName)
2885 {
2886 RADV_FROM_HANDLE(radv_device, device, _device);
2887
2888 return radv_lookup_entrypoint_checked(pName,
2889 device->instance->apiVersion,
2890 &device->instance->enabled_extensions,
2891 &device->enabled_extensions);
2892 }
2893
2894 bool radv_get_memory_fd(struct radv_device *device,
2895 struct radv_device_memory *memory,
2896 int *pFD)
2897 {
2898 struct radeon_bo_metadata metadata;
2899
2900 if (memory->image) {
2901 radv_init_metadata(device, memory->image, &metadata);
2902 device->ws->buffer_set_metadata(memory->bo, &metadata);
2903 }
2904
2905 return device->ws->buffer_get_fd(device->ws, memory->bo,
2906 pFD);
2907 }
2908
2909 static VkResult radv_alloc_memory(struct radv_device *device,
2910 const VkMemoryAllocateInfo* pAllocateInfo,
2911 const VkAllocationCallbacks* pAllocator,
2912 VkDeviceMemory* pMem)
2913 {
2914 struct radv_device_memory *mem;
2915 VkResult result;
2916 enum radeon_bo_domain domain;
2917 uint32_t flags = 0;
2918 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2919
2920 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2921
2922 if (pAllocateInfo->allocationSize == 0) {
2923 /* Apparently, this is allowed */
2924 *pMem = VK_NULL_HANDLE;
2925 return VK_SUCCESS;
2926 }
2927
2928 const VkImportMemoryFdInfoKHR *import_info =
2929 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2930 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2931 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2932 const VkExportMemoryAllocateInfoKHR *export_info =
2933 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2934 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2935 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2936
2937 const struct wsi_memory_allocate_info *wsi_info =
2938 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2939
2940 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2941 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2942 if (mem == NULL)
2943 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2944
2945 if (wsi_info && wsi_info->implicit_sync)
2946 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2947
2948 if (dedicate_info) {
2949 mem->image = radv_image_from_handle(dedicate_info->image);
2950 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2951 } else {
2952 mem->image = NULL;
2953 mem->buffer = NULL;
2954 }
2955
2956 mem->user_ptr = NULL;
2957
2958 if (import_info) {
2959 assert(import_info->handleType ==
2960 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2961 import_info->handleType ==
2962 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2963 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2964 NULL, NULL);
2965 if (!mem->bo) {
2966 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2967 goto fail;
2968 } else {
2969 close(import_info->fd);
2970 }
2971 } else if (host_ptr_info) {
2972 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2973 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2974 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2975 pAllocateInfo->allocationSize);
2976 if (!mem->bo) {
2977 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2978 goto fail;
2979 } else {
2980 mem->user_ptr = host_ptr_info->pHostPointer;
2981 }
2982 } else {
2983 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2984 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2985 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2986 domain = RADEON_DOMAIN_GTT;
2987 else
2988 domain = RADEON_DOMAIN_VRAM;
2989
2990 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2991 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2992 else
2993 flags |= RADEON_FLAG_CPU_ACCESS;
2994
2995 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2996 flags |= RADEON_FLAG_GTT_WC;
2997
2998 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2999 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3000
3001 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3002 domain, flags);
3003
3004 if (!mem->bo) {
3005 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3006 goto fail;
3007 }
3008 mem->type_index = mem_type_index;
3009 }
3010
3011 result = radv_bo_list_add(device, mem->bo);
3012 if (result != VK_SUCCESS)
3013 goto fail_bo;
3014
3015 *pMem = radv_device_memory_to_handle(mem);
3016
3017 return VK_SUCCESS;
3018
3019 fail_bo:
3020 device->ws->buffer_destroy(mem->bo);
3021 fail:
3022 vk_free2(&device->alloc, pAllocator, mem);
3023
3024 return result;
3025 }
3026
3027 VkResult radv_AllocateMemory(
3028 VkDevice _device,
3029 const VkMemoryAllocateInfo* pAllocateInfo,
3030 const VkAllocationCallbacks* pAllocator,
3031 VkDeviceMemory* pMem)
3032 {
3033 RADV_FROM_HANDLE(radv_device, device, _device);
3034 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3035 }
3036
3037 void radv_FreeMemory(
3038 VkDevice _device,
3039 VkDeviceMemory _mem,
3040 const VkAllocationCallbacks* pAllocator)
3041 {
3042 RADV_FROM_HANDLE(radv_device, device, _device);
3043 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3044
3045 if (mem == NULL)
3046 return;
3047
3048 radv_bo_list_remove(device, mem->bo);
3049 device->ws->buffer_destroy(mem->bo);
3050 mem->bo = NULL;
3051
3052 vk_free2(&device->alloc, pAllocator, mem);
3053 }
3054
3055 VkResult radv_MapMemory(
3056 VkDevice _device,
3057 VkDeviceMemory _memory,
3058 VkDeviceSize offset,
3059 VkDeviceSize size,
3060 VkMemoryMapFlags flags,
3061 void** ppData)
3062 {
3063 RADV_FROM_HANDLE(radv_device, device, _device);
3064 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3065
3066 if (mem == NULL) {
3067 *ppData = NULL;
3068 return VK_SUCCESS;
3069 }
3070
3071 if (mem->user_ptr)
3072 *ppData = mem->user_ptr;
3073 else
3074 *ppData = device->ws->buffer_map(mem->bo);
3075
3076 if (*ppData) {
3077 *ppData += offset;
3078 return VK_SUCCESS;
3079 }
3080
3081 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3082 }
3083
3084 void radv_UnmapMemory(
3085 VkDevice _device,
3086 VkDeviceMemory _memory)
3087 {
3088 RADV_FROM_HANDLE(radv_device, device, _device);
3089 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3090
3091 if (mem == NULL)
3092 return;
3093
3094 if (mem->user_ptr == NULL)
3095 device->ws->buffer_unmap(mem->bo);
3096 }
3097
3098 VkResult radv_FlushMappedMemoryRanges(
3099 VkDevice _device,
3100 uint32_t memoryRangeCount,
3101 const VkMappedMemoryRange* pMemoryRanges)
3102 {
3103 return VK_SUCCESS;
3104 }
3105
3106 VkResult radv_InvalidateMappedMemoryRanges(
3107 VkDevice _device,
3108 uint32_t memoryRangeCount,
3109 const VkMappedMemoryRange* pMemoryRanges)
3110 {
3111 return VK_SUCCESS;
3112 }
3113
3114 void radv_GetBufferMemoryRequirements(
3115 VkDevice _device,
3116 VkBuffer _buffer,
3117 VkMemoryRequirements* pMemoryRequirements)
3118 {
3119 RADV_FROM_HANDLE(radv_device, device, _device);
3120 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3121
3122 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3123
3124 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3125 pMemoryRequirements->alignment = 4096;
3126 else
3127 pMemoryRequirements->alignment = 16;
3128
3129 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3130 }
3131
3132 void radv_GetBufferMemoryRequirements2(
3133 VkDevice device,
3134 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3135 VkMemoryRequirements2KHR* pMemoryRequirements)
3136 {
3137 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3138 &pMemoryRequirements->memoryRequirements);
3139 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3140 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3141 switch (ext->sType) {
3142 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3143 VkMemoryDedicatedRequirementsKHR *req =
3144 (VkMemoryDedicatedRequirementsKHR *) ext;
3145 req->requiresDedicatedAllocation = buffer->shareable;
3146 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3147 break;
3148 }
3149 default:
3150 break;
3151 }
3152 }
3153 }
3154
3155 void radv_GetImageMemoryRequirements(
3156 VkDevice _device,
3157 VkImage _image,
3158 VkMemoryRequirements* pMemoryRequirements)
3159 {
3160 RADV_FROM_HANDLE(radv_device, device, _device);
3161 RADV_FROM_HANDLE(radv_image, image, _image);
3162
3163 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3164
3165 pMemoryRequirements->size = image->size;
3166 pMemoryRequirements->alignment = image->alignment;
3167 }
3168
3169 void radv_GetImageMemoryRequirements2(
3170 VkDevice device,
3171 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3172 VkMemoryRequirements2KHR* pMemoryRequirements)
3173 {
3174 radv_GetImageMemoryRequirements(device, pInfo->image,
3175 &pMemoryRequirements->memoryRequirements);
3176
3177 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3178
3179 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3180 switch (ext->sType) {
3181 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3182 VkMemoryDedicatedRequirementsKHR *req =
3183 (VkMemoryDedicatedRequirementsKHR *) ext;
3184 req->requiresDedicatedAllocation = image->shareable;
3185 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3186 break;
3187 }
3188 default:
3189 break;
3190 }
3191 }
3192 }
3193
3194 void radv_GetImageSparseMemoryRequirements(
3195 VkDevice device,
3196 VkImage image,
3197 uint32_t* pSparseMemoryRequirementCount,
3198 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3199 {
3200 stub();
3201 }
3202
3203 void radv_GetImageSparseMemoryRequirements2(
3204 VkDevice device,
3205 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3206 uint32_t* pSparseMemoryRequirementCount,
3207 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3208 {
3209 stub();
3210 }
3211
3212 void radv_GetDeviceMemoryCommitment(
3213 VkDevice device,
3214 VkDeviceMemory memory,
3215 VkDeviceSize* pCommittedMemoryInBytes)
3216 {
3217 *pCommittedMemoryInBytes = 0;
3218 }
3219
3220 VkResult radv_BindBufferMemory2(VkDevice device,
3221 uint32_t bindInfoCount,
3222 const VkBindBufferMemoryInfoKHR *pBindInfos)
3223 {
3224 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3225 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3226 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3227
3228 if (mem) {
3229 buffer->bo = mem->bo;
3230 buffer->offset = pBindInfos[i].memoryOffset;
3231 } else {
3232 buffer->bo = NULL;
3233 }
3234 }
3235 return VK_SUCCESS;
3236 }
3237
3238 VkResult radv_BindBufferMemory(
3239 VkDevice device,
3240 VkBuffer buffer,
3241 VkDeviceMemory memory,
3242 VkDeviceSize memoryOffset)
3243 {
3244 const VkBindBufferMemoryInfoKHR info = {
3245 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3246 .buffer = buffer,
3247 .memory = memory,
3248 .memoryOffset = memoryOffset
3249 };
3250
3251 return radv_BindBufferMemory2(device, 1, &info);
3252 }
3253
3254 VkResult radv_BindImageMemory2(VkDevice device,
3255 uint32_t bindInfoCount,
3256 const VkBindImageMemoryInfoKHR *pBindInfos)
3257 {
3258 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3259 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3260 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3261
3262 if (mem) {
3263 image->bo = mem->bo;
3264 image->offset = pBindInfos[i].memoryOffset;
3265 } else {
3266 image->bo = NULL;
3267 image->offset = 0;
3268 }
3269 }
3270 return VK_SUCCESS;
3271 }
3272
3273
3274 VkResult radv_BindImageMemory(
3275 VkDevice device,
3276 VkImage image,
3277 VkDeviceMemory memory,
3278 VkDeviceSize memoryOffset)
3279 {
3280 const VkBindImageMemoryInfoKHR info = {
3281 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3282 .image = image,
3283 .memory = memory,
3284 .memoryOffset = memoryOffset
3285 };
3286
3287 return radv_BindImageMemory2(device, 1, &info);
3288 }
3289
3290
3291 static void
3292 radv_sparse_buffer_bind_memory(struct radv_device *device,
3293 const VkSparseBufferMemoryBindInfo *bind)
3294 {
3295 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3296
3297 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3298 struct radv_device_memory *mem = NULL;
3299
3300 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3301 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3302
3303 device->ws->buffer_virtual_bind(buffer->bo,
3304 bind->pBinds[i].resourceOffset,
3305 bind->pBinds[i].size,
3306 mem ? mem->bo : NULL,
3307 bind->pBinds[i].memoryOffset);
3308 }
3309 }
3310
3311 static void
3312 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3313 const VkSparseImageOpaqueMemoryBindInfo *bind)
3314 {
3315 RADV_FROM_HANDLE(radv_image, image, bind->image);
3316
3317 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3318 struct radv_device_memory *mem = NULL;
3319
3320 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3321 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3322
3323 device->ws->buffer_virtual_bind(image->bo,
3324 bind->pBinds[i].resourceOffset,
3325 bind->pBinds[i].size,
3326 mem ? mem->bo : NULL,
3327 bind->pBinds[i].memoryOffset);
3328 }
3329 }
3330
3331 VkResult radv_QueueBindSparse(
3332 VkQueue _queue,
3333 uint32_t bindInfoCount,
3334 const VkBindSparseInfo* pBindInfo,
3335 VkFence _fence)
3336 {
3337 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3338 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3339 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3340 bool fence_emitted = false;
3341 VkResult result;
3342 int ret;
3343
3344 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3345 struct radv_winsys_sem_info sem_info;
3346 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3347 radv_sparse_buffer_bind_memory(queue->device,
3348 pBindInfo[i].pBufferBinds + j);
3349 }
3350
3351 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3352 radv_sparse_image_opaque_bind_memory(queue->device,
3353 pBindInfo[i].pImageOpaqueBinds + j);
3354 }
3355
3356 VkResult result;
3357 result = radv_alloc_sem_info(queue->device->instance,
3358 &sem_info,
3359 pBindInfo[i].waitSemaphoreCount,
3360 pBindInfo[i].pWaitSemaphores,
3361 pBindInfo[i].signalSemaphoreCount,
3362 pBindInfo[i].pSignalSemaphores,
3363 _fence);
3364 if (result != VK_SUCCESS)
3365 return result;
3366
3367 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3368 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3369 &queue->device->empty_cs[queue->queue_family_index],
3370 1, NULL, NULL,
3371 &sem_info, NULL,
3372 false, base_fence);
3373 if (ret) {
3374 radv_loge("failed to submit CS %d\n", i);
3375 abort();
3376 }
3377
3378 fence_emitted = true;
3379 if (fence)
3380 fence->submitted = true;
3381 }
3382
3383 radv_free_sem_info(&sem_info);
3384
3385 }
3386
3387 if (fence) {
3388 if (!fence_emitted) {
3389 result = radv_signal_fence(queue, fence);
3390 if (result != VK_SUCCESS)
3391 return result;
3392 }
3393 fence->submitted = true;
3394 }
3395
3396 return VK_SUCCESS;
3397 }
3398
3399 VkResult radv_CreateFence(
3400 VkDevice _device,
3401 const VkFenceCreateInfo* pCreateInfo,
3402 const VkAllocationCallbacks* pAllocator,
3403 VkFence* pFence)
3404 {
3405 RADV_FROM_HANDLE(radv_device, device, _device);
3406 const VkExportFenceCreateInfoKHR *export =
3407 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3408 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3409 export ? export->handleTypes : 0;
3410
3411 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3412 sizeof(*fence), 8,
3413 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3414
3415 if (!fence)
3416 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3417
3418 fence->fence_wsi = NULL;
3419 fence->submitted = false;
3420 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3421 fence->temp_syncobj = 0;
3422 if (device->always_use_syncobj || handleTypes) {
3423 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3424 if (ret) {
3425 vk_free2(&device->alloc, pAllocator, fence);
3426 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3427 }
3428 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3429 device->ws->signal_syncobj(device->ws, fence->syncobj);
3430 }
3431 fence->fence = NULL;
3432 } else {
3433 fence->fence = device->ws->create_fence();
3434 if (!fence->fence) {
3435 vk_free2(&device->alloc, pAllocator, fence);
3436 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3437 }
3438 fence->syncobj = 0;
3439 }
3440
3441 *pFence = radv_fence_to_handle(fence);
3442
3443 return VK_SUCCESS;
3444 }
3445
3446 void radv_DestroyFence(
3447 VkDevice _device,
3448 VkFence _fence,
3449 const VkAllocationCallbacks* pAllocator)
3450 {
3451 RADV_FROM_HANDLE(radv_device, device, _device);
3452 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3453
3454 if (!fence)
3455 return;
3456
3457 if (fence->temp_syncobj)
3458 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3459 if (fence->syncobj)
3460 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3461 if (fence->fence)
3462 device->ws->destroy_fence(fence->fence);
3463 if (fence->fence_wsi)
3464 fence->fence_wsi->destroy(fence->fence_wsi);
3465 vk_free2(&device->alloc, pAllocator, fence);
3466 }
3467
3468
3469 static uint64_t radv_get_current_time()
3470 {
3471 struct timespec tv;
3472 clock_gettime(CLOCK_MONOTONIC, &tv);
3473 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3474 }
3475
3476 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3477 {
3478 uint64_t current_time = radv_get_current_time();
3479
3480 timeout = MIN2(UINT64_MAX - current_time, timeout);
3481
3482 return current_time + timeout;
3483 }
3484
3485
3486 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3487 {
3488 for (uint32_t i = 0; i < fenceCount; ++i) {
3489 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3490 if (fence->fence == NULL || fence->syncobj ||
3491 fence->temp_syncobj ||
3492 (!fence->signalled && !fence->submitted))
3493 return false;
3494 }
3495 return true;
3496 }
3497
3498 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3499 {
3500 for (uint32_t i = 0; i < fenceCount; ++i) {
3501 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3502 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3503 return false;
3504 }
3505 return true;
3506 }
3507
3508 VkResult radv_WaitForFences(
3509 VkDevice _device,
3510 uint32_t fenceCount,
3511 const VkFence* pFences,
3512 VkBool32 waitAll,
3513 uint64_t timeout)
3514 {
3515 RADV_FROM_HANDLE(radv_device, device, _device);
3516 timeout = radv_get_absolute_timeout(timeout);
3517
3518 if (device->always_use_syncobj &&
3519 radv_all_fences_syncobj(fenceCount, pFences))
3520 {
3521 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3522 if (!handles)
3523 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3524
3525 for (uint32_t i = 0; i < fenceCount; ++i) {
3526 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3527 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3528 }
3529
3530 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3531
3532 free(handles);
3533 return success ? VK_SUCCESS : VK_TIMEOUT;
3534 }
3535
3536 if (!waitAll && fenceCount > 1) {
3537 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3538 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3539 uint32_t wait_count = 0;
3540 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3541 if (!fences)
3542 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3543
3544 for (uint32_t i = 0; i < fenceCount; ++i) {
3545 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3546
3547 if (fence->signalled) {
3548 free(fences);
3549 return VK_SUCCESS;
3550 }
3551
3552 fences[wait_count++] = fence->fence;
3553 }
3554
3555 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3556 waitAll, timeout - radv_get_current_time());
3557
3558 free(fences);
3559 return success ? VK_SUCCESS : VK_TIMEOUT;
3560 }
3561
3562 while(radv_get_current_time() <= timeout) {
3563 for (uint32_t i = 0; i < fenceCount; ++i) {
3564 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3565 return VK_SUCCESS;
3566 }
3567 }
3568 return VK_TIMEOUT;
3569 }
3570
3571 for (uint32_t i = 0; i < fenceCount; ++i) {
3572 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3573 bool expired = false;
3574
3575 if (fence->temp_syncobj) {
3576 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3577 return VK_TIMEOUT;
3578 continue;
3579 }
3580
3581 if (fence->syncobj) {
3582 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3583 return VK_TIMEOUT;
3584 continue;
3585 }
3586
3587 if (fence->signalled)
3588 continue;
3589
3590 if (fence->fence) {
3591 if (!fence->submitted) {
3592 while(radv_get_current_time() <= timeout &&
3593 !fence->submitted)
3594 /* Do nothing */;
3595
3596 if (!fence->submitted)
3597 return VK_TIMEOUT;
3598
3599 /* Recheck as it may have been set by
3600 * submitting operations. */
3601
3602 if (fence->signalled)
3603 continue;
3604 }
3605
3606 expired = device->ws->fence_wait(device->ws,
3607 fence->fence,
3608 true, timeout);
3609 if (!expired)
3610 return VK_TIMEOUT;
3611 }
3612
3613 if (fence->fence_wsi) {
3614 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3615 if (result != VK_SUCCESS)
3616 return result;
3617 }
3618
3619 fence->signalled = true;
3620 }
3621
3622 return VK_SUCCESS;
3623 }
3624
3625 VkResult radv_ResetFences(VkDevice _device,
3626 uint32_t fenceCount,
3627 const VkFence *pFences)
3628 {
3629 RADV_FROM_HANDLE(radv_device, device, _device);
3630
3631 for (unsigned i = 0; i < fenceCount; ++i) {
3632 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3633 fence->submitted = fence->signalled = false;
3634
3635 /* Per spec, we first restore the permanent payload, and then reset, so
3636 * having a temp syncobj should not skip resetting the permanent syncobj. */
3637 if (fence->temp_syncobj) {
3638 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3639 fence->temp_syncobj = 0;
3640 }
3641
3642 if (fence->syncobj) {
3643 device->ws->reset_syncobj(device->ws, fence->syncobj);
3644 }
3645 }
3646
3647 return VK_SUCCESS;
3648 }
3649
3650 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3651 {
3652 RADV_FROM_HANDLE(radv_device, device, _device);
3653 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3654
3655 if (fence->temp_syncobj) {
3656 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3657 return success ? VK_SUCCESS : VK_NOT_READY;
3658 }
3659
3660 if (fence->syncobj) {
3661 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3662 return success ? VK_SUCCESS : VK_NOT_READY;
3663 }
3664
3665 if (fence->signalled)
3666 return VK_SUCCESS;
3667 if (!fence->submitted)
3668 return VK_NOT_READY;
3669 if (fence->fence) {
3670 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3671 return VK_NOT_READY;
3672 }
3673 if (fence->fence_wsi) {
3674 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3675
3676 if (result != VK_SUCCESS) {
3677 if (result == VK_TIMEOUT)
3678 return VK_NOT_READY;
3679 return result;
3680 }
3681 }
3682 return VK_SUCCESS;
3683 }
3684
3685
3686 // Queue semaphore functions
3687
3688 VkResult radv_CreateSemaphore(
3689 VkDevice _device,
3690 const VkSemaphoreCreateInfo* pCreateInfo,
3691 const VkAllocationCallbacks* pAllocator,
3692 VkSemaphore* pSemaphore)
3693 {
3694 RADV_FROM_HANDLE(radv_device, device, _device);
3695 const VkExportSemaphoreCreateInfoKHR *export =
3696 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3697 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3698 export ? export->handleTypes : 0;
3699
3700 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3701 sizeof(*sem), 8,
3702 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3703 if (!sem)
3704 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3705
3706 sem->temp_syncobj = 0;
3707 /* create a syncobject if we are going to export this semaphore */
3708 if (device->always_use_syncobj || handleTypes) {
3709 assert (device->physical_device->rad_info.has_syncobj);
3710 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3711 if (ret) {
3712 vk_free2(&device->alloc, pAllocator, sem);
3713 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3714 }
3715 sem->sem = NULL;
3716 } else {
3717 sem->sem = device->ws->create_sem(device->ws);
3718 if (!sem->sem) {
3719 vk_free2(&device->alloc, pAllocator, sem);
3720 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3721 }
3722 sem->syncobj = 0;
3723 }
3724
3725 *pSemaphore = radv_semaphore_to_handle(sem);
3726 return VK_SUCCESS;
3727 }
3728
3729 void radv_DestroySemaphore(
3730 VkDevice _device,
3731 VkSemaphore _semaphore,
3732 const VkAllocationCallbacks* pAllocator)
3733 {
3734 RADV_FROM_HANDLE(radv_device, device, _device);
3735 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3736 if (!_semaphore)
3737 return;
3738
3739 if (sem->syncobj)
3740 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3741 else
3742 device->ws->destroy_sem(sem->sem);
3743 vk_free2(&device->alloc, pAllocator, sem);
3744 }
3745
3746 VkResult radv_CreateEvent(
3747 VkDevice _device,
3748 const VkEventCreateInfo* pCreateInfo,
3749 const VkAllocationCallbacks* pAllocator,
3750 VkEvent* pEvent)
3751 {
3752 RADV_FROM_HANDLE(radv_device, device, _device);
3753 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3754 sizeof(*event), 8,
3755 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3756
3757 if (!event)
3758 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3759
3760 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3761 RADEON_DOMAIN_GTT,
3762 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3763 if (!event->bo) {
3764 vk_free2(&device->alloc, pAllocator, event);
3765 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3766 }
3767
3768 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3769
3770 *pEvent = radv_event_to_handle(event);
3771
3772 return VK_SUCCESS;
3773 }
3774
3775 void radv_DestroyEvent(
3776 VkDevice _device,
3777 VkEvent _event,
3778 const VkAllocationCallbacks* pAllocator)
3779 {
3780 RADV_FROM_HANDLE(radv_device, device, _device);
3781 RADV_FROM_HANDLE(radv_event, event, _event);
3782
3783 if (!event)
3784 return;
3785 device->ws->buffer_destroy(event->bo);
3786 vk_free2(&device->alloc, pAllocator, event);
3787 }
3788
3789 VkResult radv_GetEventStatus(
3790 VkDevice _device,
3791 VkEvent _event)
3792 {
3793 RADV_FROM_HANDLE(radv_event, event, _event);
3794
3795 if (*event->map == 1)
3796 return VK_EVENT_SET;
3797 return VK_EVENT_RESET;
3798 }
3799
3800 VkResult radv_SetEvent(
3801 VkDevice _device,
3802 VkEvent _event)
3803 {
3804 RADV_FROM_HANDLE(radv_event, event, _event);
3805 *event->map = 1;
3806
3807 return VK_SUCCESS;
3808 }
3809
3810 VkResult radv_ResetEvent(
3811 VkDevice _device,
3812 VkEvent _event)
3813 {
3814 RADV_FROM_HANDLE(radv_event, event, _event);
3815 *event->map = 0;
3816
3817 return VK_SUCCESS;
3818 }
3819
3820 VkResult radv_CreateBuffer(
3821 VkDevice _device,
3822 const VkBufferCreateInfo* pCreateInfo,
3823 const VkAllocationCallbacks* pAllocator,
3824 VkBuffer* pBuffer)
3825 {
3826 RADV_FROM_HANDLE(radv_device, device, _device);
3827 struct radv_buffer *buffer;
3828
3829 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3830
3831 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3832 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3833 if (buffer == NULL)
3834 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3835
3836 buffer->size = pCreateInfo->size;
3837 buffer->usage = pCreateInfo->usage;
3838 buffer->bo = NULL;
3839 buffer->offset = 0;
3840 buffer->flags = pCreateInfo->flags;
3841
3842 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3843 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3844
3845 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3846 buffer->bo = device->ws->buffer_create(device->ws,
3847 align64(buffer->size, 4096),
3848 4096, 0, RADEON_FLAG_VIRTUAL);
3849 if (!buffer->bo) {
3850 vk_free2(&device->alloc, pAllocator, buffer);
3851 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3852 }
3853 }
3854
3855 *pBuffer = radv_buffer_to_handle(buffer);
3856
3857 return VK_SUCCESS;
3858 }
3859
3860 void radv_DestroyBuffer(
3861 VkDevice _device,
3862 VkBuffer _buffer,
3863 const VkAllocationCallbacks* pAllocator)
3864 {
3865 RADV_FROM_HANDLE(radv_device, device, _device);
3866 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3867
3868 if (!buffer)
3869 return;
3870
3871 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3872 device->ws->buffer_destroy(buffer->bo);
3873
3874 vk_free2(&device->alloc, pAllocator, buffer);
3875 }
3876
3877 static inline unsigned
3878 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3879 {
3880 if (stencil)
3881 return image->surface.u.legacy.stencil_tiling_index[level];
3882 else
3883 return image->surface.u.legacy.tiling_index[level];
3884 }
3885
3886 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3887 {
3888 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3889 }
3890
3891 static uint32_t
3892 radv_init_dcc_control_reg(struct radv_device *device,
3893 struct radv_image_view *iview)
3894 {
3895 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3896 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3897 unsigned max_compressed_block_size;
3898 unsigned independent_64b_blocks;
3899
3900 if (!radv_image_has_dcc(iview->image))
3901 return 0;
3902
3903 if (iview->image->info.samples > 1) {
3904 if (iview->image->surface.bpe == 1)
3905 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3906 else if (iview->image->surface.bpe == 2)
3907 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3908 }
3909
3910 if (!device->physical_device->rad_info.has_dedicated_vram) {
3911 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3912 * dGPU and 64 for APU because all of our APUs to date use
3913 * DIMMs which have a request granularity size of 64B while all
3914 * other chips have a 32B request size.
3915 */
3916 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3917 }
3918
3919 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3920 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3921 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3922 /* If this DCC image is potentially going to be used in texture
3923 * fetches, we need some special settings.
3924 */
3925 independent_64b_blocks = 1;
3926 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3927 } else {
3928 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3929 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3930 * big as possible for better compression state.
3931 */
3932 independent_64b_blocks = 0;
3933 max_compressed_block_size = max_uncompressed_block_size;
3934 }
3935
3936 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3937 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3938 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3939 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3940 }
3941
3942 static void
3943 radv_initialise_color_surface(struct radv_device *device,
3944 struct radv_color_buffer_info *cb,
3945 struct radv_image_view *iview)
3946 {
3947 const struct vk_format_description *desc;
3948 unsigned ntype, format, swap, endian;
3949 unsigned blend_clamp = 0, blend_bypass = 0;
3950 uint64_t va;
3951 const struct radeon_surf *surf = &iview->image->surface;
3952
3953 desc = vk_format_description(iview->vk_format);
3954
3955 memset(cb, 0, sizeof(*cb));
3956
3957 /* Intensity is implemented as Red, so treat it that way. */
3958 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3959
3960 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3961
3962 cb->cb_color_base = va >> 8;
3963
3964 if (device->physical_device->rad_info.chip_class >= GFX9) {
3965 struct gfx9_surf_meta_flags meta;
3966 if (iview->image->dcc_offset)
3967 meta = iview->image->surface.u.gfx9.dcc;
3968 else
3969 meta = iview->image->surface.u.gfx9.cmask;
3970
3971 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3972 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3973 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3974 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3975
3976 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3977 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3978 } else {
3979 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3980 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3981
3982 cb->cb_color_base += level_info->offset >> 8;
3983 if (level_info->mode == RADEON_SURF_MODE_2D)
3984 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3985
3986 pitch_tile_max = level_info->nblk_x / 8 - 1;
3987 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3988 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3989
3990 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3991 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3992 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3993
3994 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3995
3996 if (radv_image_has_fmask(iview->image)) {
3997 if (device->physical_device->rad_info.chip_class >= CIK)
3998 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3999 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4000 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4001 } else {
4002 /* This must be set for fast clear to work without FMASK. */
4003 if (device->physical_device->rad_info.chip_class >= CIK)
4004 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4005 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4006 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4007 }
4008 }
4009
4010 /* CMASK variables */
4011 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4012 va += iview->image->cmask.offset;
4013 cb->cb_color_cmask = va >> 8;
4014
4015 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4016 va += iview->image->dcc_offset;
4017 cb->cb_dcc_base = va >> 8;
4018 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4019
4020 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4021 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4022 S_028C6C_SLICE_MAX(max_slice);
4023
4024 if (iview->image->info.samples > 1) {
4025 unsigned log_samples = util_logbase2(iview->image->info.samples);
4026
4027 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4028 S_028C74_NUM_FRAGMENTS(log_samples);
4029 }
4030
4031 if (radv_image_has_fmask(iview->image)) {
4032 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4033 cb->cb_color_fmask = va >> 8;
4034 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4035 } else {
4036 cb->cb_color_fmask = cb->cb_color_base;
4037 }
4038
4039 ntype = radv_translate_color_numformat(iview->vk_format,
4040 desc,
4041 vk_format_get_first_non_void_channel(iview->vk_format));
4042 format = radv_translate_colorformat(iview->vk_format);
4043 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4044 radv_finishme("Illegal color\n");
4045 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4046 endian = radv_colorformat_endian_swap(format);
4047
4048 /* blend clamp should be set for all NORM/SRGB types */
4049 if (ntype == V_028C70_NUMBER_UNORM ||
4050 ntype == V_028C70_NUMBER_SNORM ||
4051 ntype == V_028C70_NUMBER_SRGB)
4052 blend_clamp = 1;
4053
4054 /* set blend bypass according to docs if SINT/UINT or
4055 8/24 COLOR variants */
4056 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4057 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4058 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4059 blend_clamp = 0;
4060 blend_bypass = 1;
4061 }
4062 #if 0
4063 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4064 (format == V_028C70_COLOR_8 ||
4065 format == V_028C70_COLOR_8_8 ||
4066 format == V_028C70_COLOR_8_8_8_8))
4067 ->color_is_int8 = true;
4068 #endif
4069 cb->cb_color_info = S_028C70_FORMAT(format) |
4070 S_028C70_COMP_SWAP(swap) |
4071 S_028C70_BLEND_CLAMP(blend_clamp) |
4072 S_028C70_BLEND_BYPASS(blend_bypass) |
4073 S_028C70_SIMPLE_FLOAT(1) |
4074 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4075 ntype != V_028C70_NUMBER_SNORM &&
4076 ntype != V_028C70_NUMBER_SRGB &&
4077 format != V_028C70_COLOR_8_24 &&
4078 format != V_028C70_COLOR_24_8) |
4079 S_028C70_NUMBER_TYPE(ntype) |
4080 S_028C70_ENDIAN(endian);
4081 if (radv_image_has_fmask(iview->image)) {
4082 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4083 if (device->physical_device->rad_info.chip_class == SI) {
4084 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4085 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4086 }
4087 }
4088
4089 if (radv_image_has_cmask(iview->image) &&
4090 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4091 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4092
4093 if (radv_dcc_enabled(iview->image, iview->base_mip))
4094 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4095
4096 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4097
4098 /* This must be set for fast clear to work without FMASK. */
4099 if (!radv_image_has_fmask(iview->image) &&
4100 device->physical_device->rad_info.chip_class == SI) {
4101 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4102 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4103 }
4104
4105 if (device->physical_device->rad_info.chip_class >= GFX9) {
4106 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4107 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4108
4109 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4110 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4111 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4112 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4113 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4114 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4115 }
4116 }
4117
4118 static unsigned
4119 radv_calc_decompress_on_z_planes(struct radv_device *device,
4120 struct radv_image_view *iview)
4121 {
4122 unsigned max_zplanes = 0;
4123
4124 assert(radv_image_is_tc_compat_htile(iview->image));
4125
4126 if (device->physical_device->rad_info.chip_class >= GFX9) {
4127 /* Default value for 32-bit depth surfaces. */
4128 max_zplanes = 4;
4129
4130 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4131 iview->image->info.samples > 1)
4132 max_zplanes = 2;
4133
4134 max_zplanes = max_zplanes + 1;
4135 } else {
4136 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4137 /* Do not enable Z plane compression for 16-bit depth
4138 * surfaces because isn't supported on GFX8. Only
4139 * 32-bit depth surfaces are supported by the hardware.
4140 * This allows to maintain shader compatibility and to
4141 * reduce the number of depth decompressions.
4142 */
4143 max_zplanes = 1;
4144 } else {
4145 if (iview->image->info.samples <= 1)
4146 max_zplanes = 5;
4147 else if (iview->image->info.samples <= 4)
4148 max_zplanes = 3;
4149 else
4150 max_zplanes = 2;
4151 }
4152 }
4153
4154 return max_zplanes;
4155 }
4156
4157 static void
4158 radv_initialise_ds_surface(struct radv_device *device,
4159 struct radv_ds_buffer_info *ds,
4160 struct radv_image_view *iview)
4161 {
4162 unsigned level = iview->base_mip;
4163 unsigned format, stencil_format;
4164 uint64_t va, s_offs, z_offs;
4165 bool stencil_only = false;
4166 memset(ds, 0, sizeof(*ds));
4167 switch (iview->image->vk_format) {
4168 case VK_FORMAT_D24_UNORM_S8_UINT:
4169 case VK_FORMAT_X8_D24_UNORM_PACK32:
4170 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4171 ds->offset_scale = 2.0f;
4172 break;
4173 case VK_FORMAT_D16_UNORM:
4174 case VK_FORMAT_D16_UNORM_S8_UINT:
4175 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4176 ds->offset_scale = 4.0f;
4177 break;
4178 case VK_FORMAT_D32_SFLOAT:
4179 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4180 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4181 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4182 ds->offset_scale = 1.0f;
4183 break;
4184 case VK_FORMAT_S8_UINT:
4185 stencil_only = true;
4186 break;
4187 default:
4188 break;
4189 }
4190
4191 format = radv_translate_dbformat(iview->image->vk_format);
4192 stencil_format = iview->image->surface.has_stencil ?
4193 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4194
4195 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4196 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4197 S_028008_SLICE_MAX(max_slice);
4198
4199 ds->db_htile_data_base = 0;
4200 ds->db_htile_surface = 0;
4201
4202 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4203 s_offs = z_offs = va;
4204
4205 if (device->physical_device->rad_info.chip_class >= GFX9) {
4206 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4207 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4208
4209 ds->db_z_info = S_028038_FORMAT(format) |
4210 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4211 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4212 S_028038_MAXMIP(iview->image->info.levels - 1) |
4213 S_028038_ZRANGE_PRECISION(1);
4214 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4215 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4216
4217 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4218 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4219 ds->db_depth_view |= S_028008_MIPID(level);
4220
4221 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4222 S_02801C_Y_MAX(iview->image->info.height - 1);
4223
4224 if (radv_htile_enabled(iview->image, level)) {
4225 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4226
4227 if (radv_image_is_tc_compat_htile(iview->image)) {
4228 unsigned max_zplanes =
4229 radv_calc_decompress_on_z_planes(device, iview);
4230
4231 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4232 S_028038_ITERATE_FLUSH(1);
4233 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4234 }
4235
4236 if (!iview->image->surface.has_stencil)
4237 /* Use all of the htile_buffer for depth if there's no stencil. */
4238 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4239 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4240 iview->image->htile_offset;
4241 ds->db_htile_data_base = va >> 8;
4242 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4243 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4244 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4245 }
4246 } else {
4247 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4248
4249 if (stencil_only)
4250 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4251
4252 z_offs += iview->image->surface.u.legacy.level[level].offset;
4253 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4254
4255 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4256 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4257 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4258
4259 if (iview->image->info.samples > 1)
4260 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4261
4262 if (device->physical_device->rad_info.chip_class >= CIK) {
4263 struct radeon_info *info = &device->physical_device->rad_info;
4264 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4265 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4266 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4267 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4268 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4269 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4270
4271 if (stencil_only)
4272 tile_mode = stencil_tile_mode;
4273
4274 ds->db_depth_info |=
4275 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4276 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4277 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4278 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4279 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4280 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4281 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4282 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4283 } else {
4284 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4285 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4286 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4287 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4288 if (stencil_only)
4289 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4290 }
4291
4292 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4293 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4294 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4295
4296 if (radv_htile_enabled(iview->image, level)) {
4297 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4298
4299 if (!iview->image->surface.has_stencil &&
4300 !radv_image_is_tc_compat_htile(iview->image))
4301 /* Use all of the htile_buffer for depth if there's no stencil. */
4302 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4303
4304 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4305 iview->image->htile_offset;
4306 ds->db_htile_data_base = va >> 8;
4307 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4308
4309 if (radv_image_is_tc_compat_htile(iview->image)) {
4310 unsigned max_zplanes =
4311 radv_calc_decompress_on_z_planes(device, iview);
4312
4313 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4314 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4315 }
4316 }
4317 }
4318
4319 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4320 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4321 }
4322
4323 VkResult radv_CreateFramebuffer(
4324 VkDevice _device,
4325 const VkFramebufferCreateInfo* pCreateInfo,
4326 const VkAllocationCallbacks* pAllocator,
4327 VkFramebuffer* pFramebuffer)
4328 {
4329 RADV_FROM_HANDLE(radv_device, device, _device);
4330 struct radv_framebuffer *framebuffer;
4331
4332 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4333
4334 size_t size = sizeof(*framebuffer) +
4335 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4336 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4337 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4338 if (framebuffer == NULL)
4339 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4340
4341 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4342 framebuffer->width = pCreateInfo->width;
4343 framebuffer->height = pCreateInfo->height;
4344 framebuffer->layers = pCreateInfo->layers;
4345 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4346 VkImageView _iview = pCreateInfo->pAttachments[i];
4347 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4348 framebuffer->attachments[i].attachment = iview;
4349 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4350 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4351 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4352 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4353 }
4354 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4355 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4356 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4357 }
4358
4359 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4360 return VK_SUCCESS;
4361 }
4362
4363 void radv_DestroyFramebuffer(
4364 VkDevice _device,
4365 VkFramebuffer _fb,
4366 const VkAllocationCallbacks* pAllocator)
4367 {
4368 RADV_FROM_HANDLE(radv_device, device, _device);
4369 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4370
4371 if (!fb)
4372 return;
4373 vk_free2(&device->alloc, pAllocator, fb);
4374 }
4375
4376 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4377 {
4378 switch (address_mode) {
4379 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4380 return V_008F30_SQ_TEX_WRAP;
4381 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4382 return V_008F30_SQ_TEX_MIRROR;
4383 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4384 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4385 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4386 return V_008F30_SQ_TEX_CLAMP_BORDER;
4387 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4388 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4389 default:
4390 unreachable("illegal tex wrap mode");
4391 break;
4392 }
4393 }
4394
4395 static unsigned
4396 radv_tex_compare(VkCompareOp op)
4397 {
4398 switch (op) {
4399 case VK_COMPARE_OP_NEVER:
4400 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4401 case VK_COMPARE_OP_LESS:
4402 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4403 case VK_COMPARE_OP_EQUAL:
4404 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4405 case VK_COMPARE_OP_LESS_OR_EQUAL:
4406 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4407 case VK_COMPARE_OP_GREATER:
4408 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4409 case VK_COMPARE_OP_NOT_EQUAL:
4410 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4411 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4412 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4413 case VK_COMPARE_OP_ALWAYS:
4414 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4415 default:
4416 unreachable("illegal compare mode");
4417 break;
4418 }
4419 }
4420
4421 static unsigned
4422 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4423 {
4424 switch (filter) {
4425 case VK_FILTER_NEAREST:
4426 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4427 V_008F38_SQ_TEX_XY_FILTER_POINT);
4428 case VK_FILTER_LINEAR:
4429 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4430 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4431 case VK_FILTER_CUBIC_IMG:
4432 default:
4433 fprintf(stderr, "illegal texture filter");
4434 return 0;
4435 }
4436 }
4437
4438 static unsigned
4439 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4440 {
4441 switch (mode) {
4442 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4443 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4444 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4445 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4446 default:
4447 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4448 }
4449 }
4450
4451 static unsigned
4452 radv_tex_bordercolor(VkBorderColor bcolor)
4453 {
4454 switch (bcolor) {
4455 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4456 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4457 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4458 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4459 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4460 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4461 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4462 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4463 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4464 default:
4465 break;
4466 }
4467 return 0;
4468 }
4469
4470 static unsigned
4471 radv_tex_aniso_filter(unsigned filter)
4472 {
4473 if (filter < 2)
4474 return 0;
4475 if (filter < 4)
4476 return 1;
4477 if (filter < 8)
4478 return 2;
4479 if (filter < 16)
4480 return 3;
4481 return 4;
4482 }
4483
4484 static unsigned
4485 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4486 {
4487 switch (mode) {
4488 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4489 return SQ_IMG_FILTER_MODE_BLEND;
4490 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4491 return SQ_IMG_FILTER_MODE_MIN;
4492 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4493 return SQ_IMG_FILTER_MODE_MAX;
4494 default:
4495 break;
4496 }
4497 return 0;
4498 }
4499
4500 static uint32_t
4501 radv_get_max_anisotropy(struct radv_device *device,
4502 const VkSamplerCreateInfo *pCreateInfo)
4503 {
4504 if (device->force_aniso >= 0)
4505 return device->force_aniso;
4506
4507 if (pCreateInfo->anisotropyEnable &&
4508 pCreateInfo->maxAnisotropy > 1.0f)
4509 return (uint32_t)pCreateInfo->maxAnisotropy;
4510
4511 return 0;
4512 }
4513
4514 static void
4515 radv_init_sampler(struct radv_device *device,
4516 struct radv_sampler *sampler,
4517 const VkSamplerCreateInfo *pCreateInfo)
4518 {
4519 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4520 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4521 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4522 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4523
4524 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4525 vk_find_struct_const(pCreateInfo->pNext,
4526 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4527 if (sampler_reduction)
4528 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4529
4530 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4531 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4532 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4533 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4534 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4535 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4536 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4537 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4538 S_008F30_DISABLE_CUBE_WRAP(0) |
4539 S_008F30_COMPAT_MODE(is_vi) |
4540 S_008F30_FILTER_MODE(filter_mode));
4541 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4542 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4543 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4544 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4545 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4546 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4547 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4548 S_008F38_MIP_POINT_PRECLAMP(0) |
4549 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4550 S_008F38_FILTER_PREC_FIX(1) |
4551 S_008F38_ANISO_OVERRIDE(is_vi));
4552 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4553 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4554 }
4555
4556 VkResult radv_CreateSampler(
4557 VkDevice _device,
4558 const VkSamplerCreateInfo* pCreateInfo,
4559 const VkAllocationCallbacks* pAllocator,
4560 VkSampler* pSampler)
4561 {
4562 RADV_FROM_HANDLE(radv_device, device, _device);
4563 struct radv_sampler *sampler;
4564
4565 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4566
4567 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4568 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4569 if (!sampler)
4570 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4571
4572 radv_init_sampler(device, sampler, pCreateInfo);
4573 *pSampler = radv_sampler_to_handle(sampler);
4574
4575 return VK_SUCCESS;
4576 }
4577
4578 void radv_DestroySampler(
4579 VkDevice _device,
4580 VkSampler _sampler,
4581 const VkAllocationCallbacks* pAllocator)
4582 {
4583 RADV_FROM_HANDLE(radv_device, device, _device);
4584 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4585
4586 if (!sampler)
4587 return;
4588 vk_free2(&device->alloc, pAllocator, sampler);
4589 }
4590
4591 /* vk_icd.h does not declare this function, so we declare it here to
4592 * suppress Wmissing-prototypes.
4593 */
4594 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4595 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4596
4597 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4598 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4599 {
4600 /* For the full details on loader interface versioning, see
4601 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4602 * What follows is a condensed summary, to help you navigate the large and
4603 * confusing official doc.
4604 *
4605 * - Loader interface v0 is incompatible with later versions. We don't
4606 * support it.
4607 *
4608 * - In loader interface v1:
4609 * - The first ICD entrypoint called by the loader is
4610 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4611 * entrypoint.
4612 * - The ICD must statically expose no other Vulkan symbol unless it is
4613 * linked with -Bsymbolic.
4614 * - Each dispatchable Vulkan handle created by the ICD must be
4615 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4616 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4617 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4618 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4619 * such loader-managed surfaces.
4620 *
4621 * - Loader interface v2 differs from v1 in:
4622 * - The first ICD entrypoint called by the loader is
4623 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4624 * statically expose this entrypoint.
4625 *
4626 * - Loader interface v3 differs from v2 in:
4627 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4628 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4629 * because the loader no longer does so.
4630 */
4631 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4632 return VK_SUCCESS;
4633 }
4634
4635 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4636 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4637 int *pFD)
4638 {
4639 RADV_FROM_HANDLE(radv_device, device, _device);
4640 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4641
4642 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4643
4644 /* At the moment, we support only the below handle types. */
4645 assert(pGetFdInfo->handleType ==
4646 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4647 pGetFdInfo->handleType ==
4648 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4649
4650 bool ret = radv_get_memory_fd(device, memory, pFD);
4651 if (ret == false)
4652 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4653 return VK_SUCCESS;
4654 }
4655
4656 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4657 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4658 int fd,
4659 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4660 {
4661 RADV_FROM_HANDLE(radv_device, device, _device);
4662
4663 switch (handleType) {
4664 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4665 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4666 return VK_SUCCESS;
4667
4668 default:
4669 /* The valid usage section for this function says:
4670 *
4671 * "handleType must not be one of the handle types defined as
4672 * opaque."
4673 *
4674 * So opaque handle types fall into the default "unsupported" case.
4675 */
4676 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4677 }
4678 }
4679
4680 static VkResult radv_import_opaque_fd(struct radv_device *device,
4681 int fd,
4682 uint32_t *syncobj)
4683 {
4684 uint32_t syncobj_handle = 0;
4685 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4686 if (ret != 0)
4687 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4688
4689 if (*syncobj)
4690 device->ws->destroy_syncobj(device->ws, *syncobj);
4691
4692 *syncobj = syncobj_handle;
4693 close(fd);
4694
4695 return VK_SUCCESS;
4696 }
4697
4698 static VkResult radv_import_sync_fd(struct radv_device *device,
4699 int fd,
4700 uint32_t *syncobj)
4701 {
4702 /* If we create a syncobj we do it locally so that if we have an error, we don't
4703 * leave a syncobj in an undetermined state in the fence. */
4704 uint32_t syncobj_handle = *syncobj;
4705 if (!syncobj_handle) {
4706 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4707 if (ret) {
4708 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4709 }
4710 }
4711
4712 if (fd == -1) {
4713 device->ws->signal_syncobj(device->ws, syncobj_handle);
4714 } else {
4715 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4716 if (ret != 0)
4717 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4718 }
4719
4720 *syncobj = syncobj_handle;
4721 if (fd != -1)
4722 close(fd);
4723
4724 return VK_SUCCESS;
4725 }
4726
4727 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4728 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4729 {
4730 RADV_FROM_HANDLE(radv_device, device, _device);
4731 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4732 uint32_t *syncobj_dst = NULL;
4733
4734 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4735 syncobj_dst = &sem->temp_syncobj;
4736 } else {
4737 syncobj_dst = &sem->syncobj;
4738 }
4739
4740 switch(pImportSemaphoreFdInfo->handleType) {
4741 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4742 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4743 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4744 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4745 default:
4746 unreachable("Unhandled semaphore handle type");
4747 }
4748 }
4749
4750 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4751 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4752 int *pFd)
4753 {
4754 RADV_FROM_HANDLE(radv_device, device, _device);
4755 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4756 int ret;
4757 uint32_t syncobj_handle;
4758
4759 if (sem->temp_syncobj)
4760 syncobj_handle = sem->temp_syncobj;
4761 else
4762 syncobj_handle = sem->syncobj;
4763
4764 switch(pGetFdInfo->handleType) {
4765 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4766 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4767 break;
4768 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4769 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4770 if (!ret) {
4771 if (sem->temp_syncobj) {
4772 close (sem->temp_syncobj);
4773 sem->temp_syncobj = 0;
4774 } else {
4775 device->ws->reset_syncobj(device->ws, syncobj_handle);
4776 }
4777 }
4778 break;
4779 default:
4780 unreachable("Unhandled semaphore handle type");
4781 }
4782
4783 if (ret)
4784 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4785 return VK_SUCCESS;
4786 }
4787
4788 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4789 VkPhysicalDevice physicalDevice,
4790 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4791 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4792 {
4793 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4794
4795 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4796 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4797 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4798 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4799 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4800 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4801 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4802 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4803 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4804 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4805 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4806 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4807 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4808 } else {
4809 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4810 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4811 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4812 }
4813 }
4814
4815 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4816 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4817 {
4818 RADV_FROM_HANDLE(radv_device, device, _device);
4819 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4820 uint32_t *syncobj_dst = NULL;
4821
4822
4823 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4824 syncobj_dst = &fence->temp_syncobj;
4825 } else {
4826 syncobj_dst = &fence->syncobj;
4827 }
4828
4829 switch(pImportFenceFdInfo->handleType) {
4830 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4831 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4832 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4833 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4834 default:
4835 unreachable("Unhandled fence handle type");
4836 }
4837 }
4838
4839 VkResult radv_GetFenceFdKHR(VkDevice _device,
4840 const VkFenceGetFdInfoKHR *pGetFdInfo,
4841 int *pFd)
4842 {
4843 RADV_FROM_HANDLE(radv_device, device, _device);
4844 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4845 int ret;
4846 uint32_t syncobj_handle;
4847
4848 if (fence->temp_syncobj)
4849 syncobj_handle = fence->temp_syncobj;
4850 else
4851 syncobj_handle = fence->syncobj;
4852
4853 switch(pGetFdInfo->handleType) {
4854 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4855 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4856 break;
4857 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4858 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4859 if (!ret) {
4860 if (fence->temp_syncobj) {
4861 close (fence->temp_syncobj);
4862 fence->temp_syncobj = 0;
4863 } else {
4864 device->ws->reset_syncobj(device->ws, syncobj_handle);
4865 }
4866 }
4867 break;
4868 default:
4869 unreachable("Unhandled fence handle type");
4870 }
4871
4872 if (ret)
4873 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4874 return VK_SUCCESS;
4875 }
4876
4877 void radv_GetPhysicalDeviceExternalFenceProperties(
4878 VkPhysicalDevice physicalDevice,
4879 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4880 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4881 {
4882 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4883
4884 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4885 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4886 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4887 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4888 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4889 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4890 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4891 } else {
4892 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4893 pExternalFenceProperties->compatibleHandleTypes = 0;
4894 pExternalFenceProperties->externalFenceFeatures = 0;
4895 }
4896 }
4897
4898 VkResult
4899 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4900 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4901 const VkAllocationCallbacks* pAllocator,
4902 VkDebugReportCallbackEXT* pCallback)
4903 {
4904 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4905 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4906 pCreateInfo, pAllocator, &instance->alloc,
4907 pCallback);
4908 }
4909
4910 void
4911 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4912 VkDebugReportCallbackEXT _callback,
4913 const VkAllocationCallbacks* pAllocator)
4914 {
4915 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4916 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4917 _callback, pAllocator, &instance->alloc);
4918 }
4919
4920 void
4921 radv_DebugReportMessageEXT(VkInstance _instance,
4922 VkDebugReportFlagsEXT flags,
4923 VkDebugReportObjectTypeEXT objectType,
4924 uint64_t object,
4925 size_t location,
4926 int32_t messageCode,
4927 const char* pLayerPrefix,
4928 const char* pMessage)
4929 {
4930 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4931 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4932 object, location, messageCode, pLayerPrefix, pMessage);
4933 }
4934
4935 void
4936 radv_GetDeviceGroupPeerMemoryFeatures(
4937 VkDevice device,
4938 uint32_t heapIndex,
4939 uint32_t localDeviceIndex,
4940 uint32_t remoteDeviceIndex,
4941 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4942 {
4943 assert(localDeviceIndex == remoteDeviceIndex);
4944
4945 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4946 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4947 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4948 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4949 }