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radv/gfx10: disable the TC compat zrange workaround
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
358 device->rad_info.chip_class <= GFX9;
359
360 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
361
362 /* Vega10/Raven need a special workaround for a hardware bug. */
363 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
364 device->rad_info.family == CHIP_RAVEN;
365
366 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
367
368 /* Out-of-order primitive rasterization. */
369 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
370 device->rad_info.max_se >= 2;
371 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
372 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
373
374 device->dcc_msaa_allowed =
375 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
376
377 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
378 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
379 (device->rad_info.chip_class >= GFX8 &&
380 device->rad_info.me_fw_feature >= 41);
381
382 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
383 device->rad_info.chip_class >= GFX10;
384
385 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
386
387 radv_physical_device_init_mem_types(device);
388 radv_fill_device_extension_table(device, &device->supported_extensions);
389
390 device->bus_info = *drm_device->businfo.pci;
391
392 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
393 ac_print_gpu_info(&device->rad_info);
394
395 /* The WSI is structured as a layer on top of the driver, so this has
396 * to be the last part of initialization (at least until we get other
397 * semi-layers).
398 */
399 result = radv_init_wsi(device);
400 if (result != VK_SUCCESS) {
401 device->ws->destroy(device->ws);
402 vk_error(instance, result);
403 goto fail;
404 }
405
406 return VK_SUCCESS;
407
408 fail:
409 close(fd);
410 if (master_fd != -1)
411 close(master_fd);
412 return result;
413 }
414
415 static void
416 radv_physical_device_finish(struct radv_physical_device *device)
417 {
418 radv_finish_wsi(device);
419 device->ws->destroy(device->ws);
420 disk_cache_destroy(device->disk_cache);
421 close(device->local_fd);
422 if (device->master_fd != -1)
423 close(device->master_fd);
424 }
425
426 static void *
427 default_alloc_func(void *pUserData, size_t size, size_t align,
428 VkSystemAllocationScope allocationScope)
429 {
430 return malloc(size);
431 }
432
433 static void *
434 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
435 size_t align, VkSystemAllocationScope allocationScope)
436 {
437 return realloc(pOriginal, size);
438 }
439
440 static void
441 default_free_func(void *pUserData, void *pMemory)
442 {
443 free(pMemory);
444 }
445
446 static const VkAllocationCallbacks default_alloc = {
447 .pUserData = NULL,
448 .pfnAllocation = default_alloc_func,
449 .pfnReallocation = default_realloc_func,
450 .pfnFree = default_free_func,
451 };
452
453 static const struct debug_control radv_debug_options[] = {
454 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
455 {"nodcc", RADV_DEBUG_NO_DCC},
456 {"shaders", RADV_DEBUG_DUMP_SHADERS},
457 {"nocache", RADV_DEBUG_NO_CACHE},
458 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
459 {"nohiz", RADV_DEBUG_NO_HIZ},
460 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
461 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
462 {"allbos", RADV_DEBUG_ALL_BOS},
463 {"noibs", RADV_DEBUG_NO_IBS},
464 {"spirv", RADV_DEBUG_DUMP_SPIRV},
465 {"vmfaults", RADV_DEBUG_VM_FAULTS},
466 {"zerovram", RADV_DEBUG_ZERO_VRAM},
467 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
468 {"nosisched", RADV_DEBUG_NO_SISCHED},
469 {"preoptir", RADV_DEBUG_PREOPTIR},
470 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
471 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
472 {"info", RADV_DEBUG_INFO},
473 {"errors", RADV_DEBUG_ERRORS},
474 {"startup", RADV_DEBUG_STARTUP},
475 {"checkir", RADV_DEBUG_CHECKIR},
476 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
477 {"nobinning", RADV_DEBUG_NOBINNING},
478 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_debug_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
486 return radv_debug_options[id].string;
487 }
488
489 static const struct debug_control radv_perftest_options[] = {
490 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
491 {"sisched", RADV_PERFTEST_SISCHED},
492 {"localbos", RADV_PERFTEST_LOCAL_BOS},
493 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
494 {"bolist", RADV_PERFTEST_BO_LIST},
495 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
496 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
497 {NULL, 0}
498 };
499
500 const char *
501 radv_get_perftest_option_name(int id)
502 {
503 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
504 return radv_perftest_options[id].string;
505 }
506
507 static void
508 radv_handle_per_app_options(struct radv_instance *instance,
509 const VkApplicationInfo *info)
510 {
511 const char *name = info ? info->pApplicationName : NULL;
512
513 if (!name)
514 return;
515
516 if (!strcmp(name, "Talos - Linux - 32bit") ||
517 !strcmp(name, "Talos - Linux - 64bit")) {
518 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
519 /* Force enable LLVM sisched for Talos because it looks
520 * safe and it gives few more FPS.
521 */
522 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
523 }
524 } else if (!strcmp(name, "DOOM_VFR")) {
525 /* Work around a Doom VFR game bug */
526 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
527 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
528 /* Workaround for a WaW hazard when LLVM moves/merges
529 * load/store memory operations.
530 * See https://reviews.llvm.org/D61313
531 */
532 if (HAVE_LLVM < 0x900)
533 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
534 }
535 }
536
537 static int radv_get_instance_extension_index(const char *name)
538 {
539 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
540 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
541 return i;
542 }
543 return -1;
544 }
545
546 static const char radv_dri_options_xml[] =
547 DRI_CONF_BEGIN
548 DRI_CONF_SECTION_QUALITY
549 DRI_CONF_ADAPTIVE_SYNC("true")
550 DRI_CONF_SECTION_END
551 DRI_CONF_END;
552
553 static void radv_init_dri_options(struct radv_instance *instance)
554 {
555 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
556 driParseConfigFiles(&instance->dri_options,
557 &instance->available_dri_options,
558 0, "radv", NULL);
559 }
560
561 VkResult radv_CreateInstance(
562 const VkInstanceCreateInfo* pCreateInfo,
563 const VkAllocationCallbacks* pAllocator,
564 VkInstance* pInstance)
565 {
566 struct radv_instance *instance;
567 VkResult result;
568
569 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
570
571 uint32_t client_version;
572 if (pCreateInfo->pApplicationInfo &&
573 pCreateInfo->pApplicationInfo->apiVersion != 0) {
574 client_version = pCreateInfo->pApplicationInfo->apiVersion;
575 } else {
576 client_version = VK_API_VERSION_1_0;
577 }
578
579 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
580 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
581 if (!instance)
582 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
583
584 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
585
586 if (pAllocator)
587 instance->alloc = *pAllocator;
588 else
589 instance->alloc = default_alloc;
590
591 instance->apiVersion = client_version;
592 instance->physicalDeviceCount = -1;
593
594 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
595 radv_debug_options);
596
597 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
598 radv_perftest_options);
599
600
601 if (instance->debug_flags & RADV_DEBUG_STARTUP)
602 radv_logi("Created an instance");
603
604 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
605 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
606 int index = radv_get_instance_extension_index(ext_name);
607
608 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
609 vk_free2(&default_alloc, pAllocator, instance);
610 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
611 }
612
613 instance->enabled_extensions.extensions[index] = true;
614 }
615
616 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
617 if (result != VK_SUCCESS) {
618 vk_free2(&default_alloc, pAllocator, instance);
619 return vk_error(instance, result);
620 }
621
622 _mesa_locale_init();
623 glsl_type_singleton_init_or_ref();
624
625 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
626
627 radv_init_dri_options(instance);
628 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
629
630 *pInstance = radv_instance_to_handle(instance);
631
632 return VK_SUCCESS;
633 }
634
635 void radv_DestroyInstance(
636 VkInstance _instance,
637 const VkAllocationCallbacks* pAllocator)
638 {
639 RADV_FROM_HANDLE(radv_instance, instance, _instance);
640
641 if (!instance)
642 return;
643
644 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
645 radv_physical_device_finish(instance->physicalDevices + i);
646 }
647
648 VG(VALGRIND_DESTROY_MEMPOOL(instance));
649
650 glsl_type_singleton_decref();
651 _mesa_locale_fini();
652
653 driDestroyOptionCache(&instance->dri_options);
654 driDestroyOptionInfo(&instance->available_dri_options);
655
656 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
657
658 vk_free(&instance->alloc, instance);
659 }
660
661 static VkResult
662 radv_enumerate_devices(struct radv_instance *instance)
663 {
664 /* TODO: Check for more devices ? */
665 drmDevicePtr devices[8];
666 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
667 int max_devices;
668
669 instance->physicalDeviceCount = 0;
670
671 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
672
673 if (instance->debug_flags & RADV_DEBUG_STARTUP)
674 radv_logi("Found %d drm nodes", max_devices);
675
676 if (max_devices < 1)
677 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
678
679 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
680 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
681 devices[i]->bustype == DRM_BUS_PCI &&
682 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
683
684 result = radv_physical_device_init(instance->physicalDevices +
685 instance->physicalDeviceCount,
686 instance,
687 devices[i]);
688 if (result == VK_SUCCESS)
689 ++instance->physicalDeviceCount;
690 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
691 break;
692 }
693 }
694 drmFreeDevices(devices, max_devices);
695
696 return result;
697 }
698
699 VkResult radv_EnumeratePhysicalDevices(
700 VkInstance _instance,
701 uint32_t* pPhysicalDeviceCount,
702 VkPhysicalDevice* pPhysicalDevices)
703 {
704 RADV_FROM_HANDLE(radv_instance, instance, _instance);
705 VkResult result;
706
707 if (instance->physicalDeviceCount < 0) {
708 result = radv_enumerate_devices(instance);
709 if (result != VK_SUCCESS &&
710 result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 return result;
712 }
713
714 if (!pPhysicalDevices) {
715 *pPhysicalDeviceCount = instance->physicalDeviceCount;
716 } else {
717 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
718 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
719 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
720 }
721
722 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
723 : VK_SUCCESS;
724 }
725
726 VkResult radv_EnumeratePhysicalDeviceGroups(
727 VkInstance _instance,
728 uint32_t* pPhysicalDeviceGroupCount,
729 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
730 {
731 RADV_FROM_HANDLE(radv_instance, instance, _instance);
732 VkResult result;
733
734 if (instance->physicalDeviceCount < 0) {
735 result = radv_enumerate_devices(instance);
736 if (result != VK_SUCCESS &&
737 result != VK_ERROR_INCOMPATIBLE_DRIVER)
738 return result;
739 }
740
741 if (!pPhysicalDeviceGroupProperties) {
742 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
743 } else {
744 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
745 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
746 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
747 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
748 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
749 }
750 }
751 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
752 : VK_SUCCESS;
753 }
754
755 void radv_GetPhysicalDeviceFeatures(
756 VkPhysicalDevice physicalDevice,
757 VkPhysicalDeviceFeatures* pFeatures)
758 {
759 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
760 memset(pFeatures, 0, sizeof(*pFeatures));
761
762 *pFeatures = (VkPhysicalDeviceFeatures) {
763 .robustBufferAccess = true,
764 .fullDrawIndexUint32 = true,
765 .imageCubeArray = true,
766 .independentBlend = true,
767 .geometryShader = true,
768 .tessellationShader = true,
769 .sampleRateShading = true,
770 .dualSrcBlend = true,
771 .logicOp = true,
772 .multiDrawIndirect = true,
773 .drawIndirectFirstInstance = true,
774 .depthClamp = true,
775 .depthBiasClamp = true,
776 .fillModeNonSolid = true,
777 .depthBounds = true,
778 .wideLines = true,
779 .largePoints = true,
780 .alphaToOne = true,
781 .multiViewport = true,
782 .samplerAnisotropy = true,
783 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
784 .textureCompressionASTC_LDR = false,
785 .textureCompressionBC = true,
786 .occlusionQueryPrecise = true,
787 .pipelineStatisticsQuery = true,
788 .vertexPipelineStoresAndAtomics = true,
789 .fragmentStoresAndAtomics = true,
790 .shaderTessellationAndGeometryPointSize = true,
791 .shaderImageGatherExtended = true,
792 .shaderStorageImageExtendedFormats = true,
793 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
794 .shaderUniformBufferArrayDynamicIndexing = true,
795 .shaderSampledImageArrayDynamicIndexing = true,
796 .shaderStorageBufferArrayDynamicIndexing = true,
797 .shaderStorageImageArrayDynamicIndexing = true,
798 .shaderStorageImageReadWithoutFormat = true,
799 .shaderStorageImageWriteWithoutFormat = true,
800 .shaderClipDistance = true,
801 .shaderCullDistance = true,
802 .shaderFloat64 = true,
803 .shaderInt64 = true,
804 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
805 .sparseBinding = true,
806 .variableMultisampleRate = true,
807 .inheritedQueries = true,
808 };
809 }
810
811 void radv_GetPhysicalDeviceFeatures2(
812 VkPhysicalDevice physicalDevice,
813 VkPhysicalDeviceFeatures2 *pFeatures)
814 {
815 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
816 vk_foreach_struct(ext, pFeatures->pNext) {
817 switch (ext->sType) {
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
819 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
820 features->variablePointersStorageBuffer = true;
821 features->variablePointers = true;
822 break;
823 }
824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
825 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
826 features->multiview = true;
827 features->multiviewGeometryShader = true;
828 features->multiviewTessellationShader = true;
829 break;
830 }
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
832 VkPhysicalDeviceShaderDrawParametersFeatures *features =
833 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
834 features->shaderDrawParameters = true;
835 break;
836 }
837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
838 VkPhysicalDeviceProtectedMemoryFeatures *features =
839 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
840 features->protectedMemory = false;
841 break;
842 }
843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
844 VkPhysicalDevice16BitStorageFeatures *features =
845 (VkPhysicalDevice16BitStorageFeatures*)ext;
846 bool enabled = pdevice->rad_info.chip_class >= GFX8;
847 features->storageBuffer16BitAccess = enabled;
848 features->uniformAndStorageBuffer16BitAccess = enabled;
849 features->storagePushConstant16 = enabled;
850 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
854 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
855 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
856 features->samplerYcbcrConversion = true;
857 break;
858 }
859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
860 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
861 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
862 features->shaderInputAttachmentArrayDynamicIndexing = true;
863 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
864 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
865 features->shaderUniformBufferArrayNonUniformIndexing = true;
866 features->shaderSampledImageArrayNonUniformIndexing = true;
867 features->shaderStorageBufferArrayNonUniformIndexing = true;
868 features->shaderStorageImageArrayNonUniformIndexing = true;
869 features->shaderInputAttachmentArrayNonUniformIndexing = true;
870 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
871 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
872 features->descriptorBindingUniformBufferUpdateAfterBind = true;
873 features->descriptorBindingSampledImageUpdateAfterBind = true;
874 features->descriptorBindingStorageImageUpdateAfterBind = true;
875 features->descriptorBindingStorageBufferUpdateAfterBind = true;
876 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
877 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
878 features->descriptorBindingUpdateUnusedWhilePending = true;
879 features->descriptorBindingPartiallyBound = true;
880 features->descriptorBindingVariableDescriptorCount = true;
881 features->runtimeDescriptorArray = true;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
885 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
886 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
887 features->conditionalRendering = true;
888 features->inheritedConditionalRendering = false;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
892 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
893 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
894 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
895 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
896 break;
897 }
898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
899 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
900 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
901 features->transformFeedback = true;
902 features->geometryStreams = true;
903 break;
904 }
905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
906 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
907 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
908 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
912 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
913 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
914 features->memoryPriority = VK_TRUE;
915 break;
916 }
917 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
918 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
919 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
920 features->bufferDeviceAddress = true;
921 features->bufferDeviceAddressCaptureReplay = false;
922 features->bufferDeviceAddressMultiDevice = false;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
926 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
927 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
928 features->depthClipEnable = true;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
932 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
933 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
934 features->hostQueryReset = true;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
938 VkPhysicalDevice8BitStorageFeaturesKHR *features =
939 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
940 bool enabled = pdevice->rad_info.chip_class >= GFX8;
941 features->storageBuffer8BitAccess = enabled;
942 features->uniformAndStorageBuffer8BitAccess = enabled;
943 features->storagePushConstant8 = enabled;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
947 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
948 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
949 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
950 features->shaderInt8 = true;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
954 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
955 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
956 /* TODO: Enable this once the driver supports 64-bit
957 * compare&swap atomic operations.
958 */
959 features->shaderBufferInt64Atomics = false;
960 features->shaderSharedInt64Atomics = false;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
964 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
965 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
966
967 features->inlineUniformBlock = true;
968 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
972 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
973 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
974 features->computeDerivativeGroupQuads = false;
975 features->computeDerivativeGroupLinear = true;
976 break;
977 }
978 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
979 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
980 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
981 features->ycbcrImageArrays = true;
982 break;
983 }
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
985 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
986 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
987 features->uniformBufferStandardLayout = true;
988 break;
989 }
990 default:
991 break;
992 }
993 }
994 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
995 }
996
997 void radv_GetPhysicalDeviceProperties(
998 VkPhysicalDevice physicalDevice,
999 VkPhysicalDeviceProperties* pProperties)
1000 {
1001 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1002 VkSampleCountFlags sample_counts = 0xf;
1003
1004 /* make sure that the entire descriptor set is addressable with a signed
1005 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1006 * be at most 2 GiB. the combined image & samples object count as one of
1007 * both. This limit is for the pipeline layout, not for the set layout, but
1008 * there is no set limit, so we just set a pipeline limit. I don't think
1009 * any app is going to hit this soon. */
1010 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1011 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1012 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1013 32 /* sampler, largest when combined with image */ +
1014 64 /* sampled image */ +
1015 64 /* storage image */);
1016
1017 VkPhysicalDeviceLimits limits = {
1018 .maxImageDimension1D = (1 << 14),
1019 .maxImageDimension2D = (1 << 14),
1020 .maxImageDimension3D = (1 << 11),
1021 .maxImageDimensionCube = (1 << 14),
1022 .maxImageArrayLayers = (1 << 11),
1023 .maxTexelBufferElements = 128 * 1024 * 1024,
1024 .maxUniformBufferRange = UINT32_MAX,
1025 .maxStorageBufferRange = UINT32_MAX,
1026 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1027 .maxMemoryAllocationCount = UINT32_MAX,
1028 .maxSamplerAllocationCount = 64 * 1024,
1029 .bufferImageGranularity = 64, /* A cache line */
1030 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1031 .maxBoundDescriptorSets = MAX_SETS,
1032 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1033 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1034 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1035 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1036 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1037 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1038 .maxPerStageResources = max_descriptor_set_size,
1039 .maxDescriptorSetSamplers = max_descriptor_set_size,
1040 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1041 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1042 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1043 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1044 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1045 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1046 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1047 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1048 .maxVertexInputBindings = MAX_VBS,
1049 .maxVertexInputAttributeOffset = 2047,
1050 .maxVertexInputBindingStride = 2048,
1051 .maxVertexOutputComponents = 128,
1052 .maxTessellationGenerationLevel = 64,
1053 .maxTessellationPatchSize = 32,
1054 .maxTessellationControlPerVertexInputComponents = 128,
1055 .maxTessellationControlPerVertexOutputComponents = 128,
1056 .maxTessellationControlPerPatchOutputComponents = 120,
1057 .maxTessellationControlTotalOutputComponents = 4096,
1058 .maxTessellationEvaluationInputComponents = 128,
1059 .maxTessellationEvaluationOutputComponents = 128,
1060 .maxGeometryShaderInvocations = 127,
1061 .maxGeometryInputComponents = 64,
1062 .maxGeometryOutputComponents = 128,
1063 .maxGeometryOutputVertices = 256,
1064 .maxGeometryTotalOutputComponents = 1024,
1065 .maxFragmentInputComponents = 128,
1066 .maxFragmentOutputAttachments = 8,
1067 .maxFragmentDualSrcAttachments = 1,
1068 .maxFragmentCombinedOutputResources = 8,
1069 .maxComputeSharedMemorySize = 32768,
1070 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1071 .maxComputeWorkGroupInvocations = 2048,
1072 .maxComputeWorkGroupSize = {
1073 2048,
1074 2048,
1075 2048
1076 },
1077 .subPixelPrecisionBits = 8,
1078 .subTexelPrecisionBits = 8,
1079 .mipmapPrecisionBits = 8,
1080 .maxDrawIndexedIndexValue = UINT32_MAX,
1081 .maxDrawIndirectCount = UINT32_MAX,
1082 .maxSamplerLodBias = 16,
1083 .maxSamplerAnisotropy = 16,
1084 .maxViewports = MAX_VIEWPORTS,
1085 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1086 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1087 .viewportSubPixelBits = 8,
1088 .minMemoryMapAlignment = 4096, /* A page */
1089 .minTexelBufferOffsetAlignment = 1,
1090 .minUniformBufferOffsetAlignment = 4,
1091 .minStorageBufferOffsetAlignment = 4,
1092 .minTexelOffset = -32,
1093 .maxTexelOffset = 31,
1094 .minTexelGatherOffset = -32,
1095 .maxTexelGatherOffset = 31,
1096 .minInterpolationOffset = -2,
1097 .maxInterpolationOffset = 2,
1098 .subPixelInterpolationOffsetBits = 8,
1099 .maxFramebufferWidth = (1 << 14),
1100 .maxFramebufferHeight = (1 << 14),
1101 .maxFramebufferLayers = (1 << 10),
1102 .framebufferColorSampleCounts = sample_counts,
1103 .framebufferDepthSampleCounts = sample_counts,
1104 .framebufferStencilSampleCounts = sample_counts,
1105 .framebufferNoAttachmentsSampleCounts = sample_counts,
1106 .maxColorAttachments = MAX_RTS,
1107 .sampledImageColorSampleCounts = sample_counts,
1108 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1109 .sampledImageDepthSampleCounts = sample_counts,
1110 .sampledImageStencilSampleCounts = sample_counts,
1111 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1112 .maxSampleMaskWords = 1,
1113 .timestampComputeAndGraphics = true,
1114 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1115 .maxClipDistances = 8,
1116 .maxCullDistances = 8,
1117 .maxCombinedClipAndCullDistances = 8,
1118 .discreteQueuePriorities = 2,
1119 .pointSizeRange = { 0.0, 8192.0 },
1120 .lineWidthRange = { 0.0, 7.9921875 },
1121 .pointSizeGranularity = (1.0 / 8.0),
1122 .lineWidthGranularity = (1.0 / 128.0),
1123 .strictLines = false, /* FINISHME */
1124 .standardSampleLocations = true,
1125 .optimalBufferCopyOffsetAlignment = 128,
1126 .optimalBufferCopyRowPitchAlignment = 128,
1127 .nonCoherentAtomSize = 64,
1128 };
1129
1130 *pProperties = (VkPhysicalDeviceProperties) {
1131 .apiVersion = radv_physical_device_api_version(pdevice),
1132 .driverVersion = vk_get_driver_version(),
1133 .vendorID = ATI_VENDOR_ID,
1134 .deviceID = pdevice->rad_info.pci_id,
1135 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1136 .limits = limits,
1137 .sparseProperties = {0},
1138 };
1139
1140 strcpy(pProperties->deviceName, pdevice->name);
1141 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1142 }
1143
1144 void radv_GetPhysicalDeviceProperties2(
1145 VkPhysicalDevice physicalDevice,
1146 VkPhysicalDeviceProperties2 *pProperties)
1147 {
1148 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1149 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1150
1151 vk_foreach_struct(ext, pProperties->pNext) {
1152 switch (ext->sType) {
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1154 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1155 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1156 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1157 break;
1158 }
1159 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1160 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1161 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1162 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1163 properties->deviceLUIDValid = false;
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1167 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1168 properties->maxMultiviewViewCount = MAX_VIEWS;
1169 properties->maxMultiviewInstanceIndex = INT_MAX;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1173 VkPhysicalDevicePointClippingProperties *properties =
1174 (VkPhysicalDevicePointClippingProperties*)ext;
1175 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1176 break;
1177 }
1178 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1179 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1180 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1181 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1185 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1186 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1187 properties->minImportedHostPointerAlignment = 4096;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1191 VkPhysicalDeviceSubgroupProperties *properties =
1192 (VkPhysicalDeviceSubgroupProperties*)ext;
1193 properties->subgroupSize = 64;
1194 properties->supportedStages = VK_SHADER_STAGE_ALL;
1195 properties->supportedOperations =
1196 VK_SUBGROUP_FEATURE_BASIC_BIT |
1197 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1198 VK_SUBGROUP_FEATURE_QUAD_BIT |
1199 VK_SUBGROUP_FEATURE_VOTE_BIT;
1200 if (pdevice->rad_info.chip_class >= GFX8) {
1201 properties->supportedOperations |=
1202 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1203 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1204 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1205 }
1206 properties->quadOperationsInAllStages = true;
1207 break;
1208 }
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1210 VkPhysicalDeviceMaintenance3Properties *properties =
1211 (VkPhysicalDeviceMaintenance3Properties*)ext;
1212 /* Make sure everything is addressable by a signed 32-bit int, and
1213 * our largest descriptors are 96 bytes. */
1214 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1215 /* Our buffer size fields allow only this much */
1216 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1220 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1221 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1222 /* GFX6-8 only support single channel min/max filter. */
1223 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1224 properties->filterMinmaxSingleComponentFormats = true;
1225 break;
1226 }
1227 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1228 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1229 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1230
1231 /* Shader engines. */
1232 properties->shaderEngineCount =
1233 pdevice->rad_info.max_se;
1234 properties->shaderArraysPerEngineCount =
1235 pdevice->rad_info.max_sh_per_se;
1236 properties->computeUnitsPerShaderArray =
1237 pdevice->rad_info.num_good_cu_per_sh;
1238 properties->simdPerComputeUnit = 4;
1239 properties->wavefrontsPerSimd =
1240 pdevice->rad_info.family == CHIP_TONGA ||
1241 pdevice->rad_info.family == CHIP_ICELAND ||
1242 pdevice->rad_info.family == CHIP_POLARIS10 ||
1243 pdevice->rad_info.family == CHIP_POLARIS11 ||
1244 pdevice->rad_info.family == CHIP_POLARIS12 ||
1245 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1246 properties->wavefrontSize = 64;
1247
1248 /* SGPR. */
1249 properties->sgprsPerSimd =
1250 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1251 properties->minSgprAllocation =
1252 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1253 properties->maxSgprAllocation =
1254 pdevice->rad_info.family == CHIP_TONGA ||
1255 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1256 properties->sgprAllocationGranularity =
1257 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1258
1259 /* VGPR. */
1260 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1261 properties->minVgprAllocation = 4;
1262 properties->maxVgprAllocation = 256;
1263 properties->vgprAllocationGranularity = 4;
1264 break;
1265 }
1266 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1267 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1268 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1269 properties->maxVertexAttribDivisor = UINT32_MAX;
1270 break;
1271 }
1272 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1273 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1274 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1275 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1276 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1277 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1278 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1279 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1280 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1281 properties->robustBufferAccessUpdateAfterBind = false;
1282 properties->quadDivergentImplicitLod = false;
1283
1284 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1285 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1286 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1287 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1288 32 /* sampler, largest when combined with image */ +
1289 64 /* sampled image */ +
1290 64 /* storage image */);
1291 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1292 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1293 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1294 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1295 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1296 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1297 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1299 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1300 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1301 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1302 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1303 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1304 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1305 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1306 break;
1307 }
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1309 VkPhysicalDeviceProtectedMemoryProperties *properties =
1310 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1311 properties->protectedNoFault = false;
1312 break;
1313 }
1314 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1315 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1316 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1317 properties->primitiveOverestimationSize = 0;
1318 properties->maxExtraPrimitiveOverestimationSize = 0;
1319 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1320 properties->primitiveUnderestimation = VK_FALSE;
1321 properties->conservativePointAndLineRasterization = VK_FALSE;
1322 properties->degenerateTrianglesRasterized = VK_FALSE;
1323 properties->degenerateLinesRasterized = VK_FALSE;
1324 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1325 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1326 break;
1327 }
1328 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1329 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1330 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1331 properties->pciDomain = pdevice->bus_info.domain;
1332 properties->pciBus = pdevice->bus_info.bus;
1333 properties->pciDevice = pdevice->bus_info.dev;
1334 properties->pciFunction = pdevice->bus_info.func;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1338 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1339 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1340
1341 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1342 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1343 strcpy(driver_props->driverName, "radv");
1344
1345 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1346 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1347 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1348 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1349
1350 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1351 .major = 1,
1352 .minor = 1,
1353 .subminor = 2,
1354 .patch = 0,
1355 };
1356 break;
1357 }
1358 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1359 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1360 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1361 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1362 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1363 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1364 properties->maxTransformFeedbackStreamDataSize = 512;
1365 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1366 properties->maxTransformFeedbackBufferDataStride = 512;
1367 properties->transformFeedbackQueries = true;
1368 properties->transformFeedbackStreamsLinesTriangles = true;
1369 properties->transformFeedbackRasterizationStreamSelect = false;
1370 properties->transformFeedbackDraw = true;
1371 break;
1372 }
1373 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1374 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1375 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1376
1377 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1378 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1379 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1380 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1381 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1382 break;
1383 }
1384 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1385 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1386 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1387 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1388 VK_SAMPLE_COUNT_4_BIT |
1389 VK_SAMPLE_COUNT_8_BIT;
1390 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1391 properties->sampleLocationCoordinateRange[0] = 0.0f;
1392 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1393 properties->sampleLocationSubPixelBits = 4;
1394 properties->variableSampleLocations = VK_FALSE;
1395 break;
1396 }
1397 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1398 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1399 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1400
1401 /* We support all of the depth resolve modes */
1402 properties->supportedDepthResolveModes =
1403 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1404 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1405 VK_RESOLVE_MODE_MIN_BIT_KHR |
1406 VK_RESOLVE_MODE_MAX_BIT_KHR;
1407
1408 /* Average doesn't make sense for stencil so we don't support that */
1409 properties->supportedStencilResolveModes =
1410 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1411 VK_RESOLVE_MODE_MIN_BIT_KHR |
1412 VK_RESOLVE_MODE_MAX_BIT_KHR;
1413
1414 properties->independentResolveNone = VK_TRUE;
1415 properties->independentResolve = VK_TRUE;
1416 break;
1417 }
1418 default:
1419 break;
1420 }
1421 }
1422 }
1423
1424 static void radv_get_physical_device_queue_family_properties(
1425 struct radv_physical_device* pdevice,
1426 uint32_t* pCount,
1427 VkQueueFamilyProperties** pQueueFamilyProperties)
1428 {
1429 int num_queue_families = 1;
1430 int idx;
1431 if (pdevice->rad_info.num_compute_rings > 0 &&
1432 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1433 num_queue_families++;
1434
1435 if (pQueueFamilyProperties == NULL) {
1436 *pCount = num_queue_families;
1437 return;
1438 }
1439
1440 if (!*pCount)
1441 return;
1442
1443 idx = 0;
1444 if (*pCount >= 1) {
1445 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1446 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1447 VK_QUEUE_COMPUTE_BIT |
1448 VK_QUEUE_TRANSFER_BIT |
1449 VK_QUEUE_SPARSE_BINDING_BIT,
1450 .queueCount = 1,
1451 .timestampValidBits = 64,
1452 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1453 };
1454 idx++;
1455 }
1456
1457 if (pdevice->rad_info.num_compute_rings > 0 &&
1458 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1459 if (*pCount > idx) {
1460 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1461 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1462 VK_QUEUE_TRANSFER_BIT |
1463 VK_QUEUE_SPARSE_BINDING_BIT,
1464 .queueCount = pdevice->rad_info.num_compute_rings,
1465 .timestampValidBits = 64,
1466 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1467 };
1468 idx++;
1469 }
1470 }
1471 *pCount = idx;
1472 }
1473
1474 void radv_GetPhysicalDeviceQueueFamilyProperties(
1475 VkPhysicalDevice physicalDevice,
1476 uint32_t* pCount,
1477 VkQueueFamilyProperties* pQueueFamilyProperties)
1478 {
1479 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1480 if (!pQueueFamilyProperties) {
1481 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1482 return;
1483 }
1484 VkQueueFamilyProperties *properties[] = {
1485 pQueueFamilyProperties + 0,
1486 pQueueFamilyProperties + 1,
1487 pQueueFamilyProperties + 2,
1488 };
1489 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1490 assert(*pCount <= 3);
1491 }
1492
1493 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1494 VkPhysicalDevice physicalDevice,
1495 uint32_t* pCount,
1496 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1497 {
1498 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1499 if (!pQueueFamilyProperties) {
1500 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1501 return;
1502 }
1503 VkQueueFamilyProperties *properties[] = {
1504 &pQueueFamilyProperties[0].queueFamilyProperties,
1505 &pQueueFamilyProperties[1].queueFamilyProperties,
1506 &pQueueFamilyProperties[2].queueFamilyProperties,
1507 };
1508 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1509 assert(*pCount <= 3);
1510 }
1511
1512 void radv_GetPhysicalDeviceMemoryProperties(
1513 VkPhysicalDevice physicalDevice,
1514 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1515 {
1516 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1517
1518 *pMemoryProperties = physical_device->memory_properties;
1519 }
1520
1521 static void
1522 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1523 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1524 {
1525 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1526 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1527 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1528 uint64_t vram_size = radv_get_vram_size(device);
1529 uint64_t gtt_size = device->rad_info.gart_size;
1530 uint64_t heap_budget, heap_usage;
1531
1532 /* For all memory heaps, the computation of budget is as follow:
1533 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1534 *
1535 * The Vulkan spec 1.1.97 says that the budget should include any
1536 * currently allocated device memory.
1537 *
1538 * Note that the application heap usages are not really accurate (eg.
1539 * in presence of shared buffers).
1540 */
1541 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1542 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1543
1544 switch (device->mem_type_indices[i]) {
1545 case RADV_MEM_TYPE_VRAM:
1546 heap_usage = device->ws->query_value(device->ws,
1547 RADEON_ALLOCATED_VRAM);
1548
1549 heap_budget = vram_size -
1550 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1551 heap_usage;
1552
1553 memoryBudget->heapBudget[heap_index] = heap_budget;
1554 memoryBudget->heapUsage[heap_index] = heap_usage;
1555 break;
1556 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1557 heap_usage = device->ws->query_value(device->ws,
1558 RADEON_ALLOCATED_VRAM_VIS);
1559
1560 heap_budget = visible_vram_size -
1561 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1562 heap_usage;
1563
1564 memoryBudget->heapBudget[heap_index] = heap_budget;
1565 memoryBudget->heapUsage[heap_index] = heap_usage;
1566 break;
1567 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1568 heap_usage = device->ws->query_value(device->ws,
1569 RADEON_ALLOCATED_GTT);
1570
1571 heap_budget = gtt_size -
1572 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1573 heap_usage;
1574
1575 memoryBudget->heapBudget[heap_index] = heap_budget;
1576 memoryBudget->heapUsage[heap_index] = heap_usage;
1577 break;
1578 default:
1579 break;
1580 }
1581 }
1582
1583 /* The heapBudget and heapUsage values must be zero for array elements
1584 * greater than or equal to
1585 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1586 */
1587 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1588 memoryBudget->heapBudget[i] = 0;
1589 memoryBudget->heapUsage[i] = 0;
1590 }
1591 }
1592
1593 void radv_GetPhysicalDeviceMemoryProperties2(
1594 VkPhysicalDevice physicalDevice,
1595 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1596 {
1597 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1598 &pMemoryProperties->memoryProperties);
1599
1600 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1601 vk_find_struct(pMemoryProperties->pNext,
1602 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1603 if (memory_budget)
1604 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1605 }
1606
1607 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1608 VkDevice _device,
1609 VkExternalMemoryHandleTypeFlagBits handleType,
1610 const void *pHostPointer,
1611 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1612 {
1613 RADV_FROM_HANDLE(radv_device, device, _device);
1614
1615 switch (handleType)
1616 {
1617 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1618 const struct radv_physical_device *physical_device = device->physical_device;
1619 uint32_t memoryTypeBits = 0;
1620 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1621 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1622 memoryTypeBits = (1 << i);
1623 break;
1624 }
1625 }
1626 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1627 return VK_SUCCESS;
1628 }
1629 default:
1630 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1631 }
1632 }
1633
1634 static enum radeon_ctx_priority
1635 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1636 {
1637 /* Default to MEDIUM when a specific global priority isn't requested */
1638 if (!pObj)
1639 return RADEON_CTX_PRIORITY_MEDIUM;
1640
1641 switch(pObj->globalPriority) {
1642 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1643 return RADEON_CTX_PRIORITY_REALTIME;
1644 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1645 return RADEON_CTX_PRIORITY_HIGH;
1646 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1647 return RADEON_CTX_PRIORITY_MEDIUM;
1648 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1649 return RADEON_CTX_PRIORITY_LOW;
1650 default:
1651 unreachable("Illegal global priority value");
1652 return RADEON_CTX_PRIORITY_INVALID;
1653 }
1654 }
1655
1656 static int
1657 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1658 uint32_t queue_family_index, int idx,
1659 VkDeviceQueueCreateFlags flags,
1660 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1661 {
1662 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1663 queue->device = device;
1664 queue->queue_family_index = queue_family_index;
1665 queue->queue_idx = idx;
1666 queue->priority = radv_get_queue_global_priority(global_priority);
1667 queue->flags = flags;
1668
1669 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1670 if (!queue->hw_ctx)
1671 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1672
1673 return VK_SUCCESS;
1674 }
1675
1676 static void
1677 radv_queue_finish(struct radv_queue *queue)
1678 {
1679 if (queue->hw_ctx)
1680 queue->device->ws->ctx_destroy(queue->hw_ctx);
1681
1682 if (queue->initial_full_flush_preamble_cs)
1683 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1684 if (queue->initial_preamble_cs)
1685 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1686 if (queue->continue_preamble_cs)
1687 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1688 if (queue->descriptor_bo)
1689 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1690 if (queue->scratch_bo)
1691 queue->device->ws->buffer_destroy(queue->scratch_bo);
1692 if (queue->esgs_ring_bo)
1693 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1694 if (queue->gsvs_ring_bo)
1695 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1696 if (queue->tess_rings_bo)
1697 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1698 if (queue->compute_scratch_bo)
1699 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1700 }
1701
1702 static void
1703 radv_bo_list_init(struct radv_bo_list *bo_list)
1704 {
1705 pthread_mutex_init(&bo_list->mutex, NULL);
1706 bo_list->list.count = bo_list->capacity = 0;
1707 bo_list->list.bos = NULL;
1708 }
1709
1710 static void
1711 radv_bo_list_finish(struct radv_bo_list *bo_list)
1712 {
1713 free(bo_list->list.bos);
1714 pthread_mutex_destroy(&bo_list->mutex);
1715 }
1716
1717 static VkResult radv_bo_list_add(struct radv_device *device,
1718 struct radeon_winsys_bo *bo)
1719 {
1720 struct radv_bo_list *bo_list = &device->bo_list;
1721
1722 if (bo->is_local)
1723 return VK_SUCCESS;
1724
1725 if (unlikely(!device->use_global_bo_list))
1726 return VK_SUCCESS;
1727
1728 pthread_mutex_lock(&bo_list->mutex);
1729 if (bo_list->list.count == bo_list->capacity) {
1730 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1731 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1732
1733 if (!data) {
1734 pthread_mutex_unlock(&bo_list->mutex);
1735 return VK_ERROR_OUT_OF_HOST_MEMORY;
1736 }
1737
1738 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1739 bo_list->capacity = capacity;
1740 }
1741
1742 bo_list->list.bos[bo_list->list.count++] = bo;
1743 pthread_mutex_unlock(&bo_list->mutex);
1744 return VK_SUCCESS;
1745 }
1746
1747 static void radv_bo_list_remove(struct radv_device *device,
1748 struct radeon_winsys_bo *bo)
1749 {
1750 struct radv_bo_list *bo_list = &device->bo_list;
1751
1752 if (bo->is_local)
1753 return;
1754
1755 if (unlikely(!device->use_global_bo_list))
1756 return;
1757
1758 pthread_mutex_lock(&bo_list->mutex);
1759 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1760 if (bo_list->list.bos[i] == bo) {
1761 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1762 --bo_list->list.count;
1763 break;
1764 }
1765 }
1766 pthread_mutex_unlock(&bo_list->mutex);
1767 }
1768
1769 static void
1770 radv_device_init_gs_info(struct radv_device *device)
1771 {
1772 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1773 device->physical_device->rad_info.family);
1774 }
1775
1776 static int radv_get_device_extension_index(const char *name)
1777 {
1778 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1779 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1780 return i;
1781 }
1782 return -1;
1783 }
1784
1785 static int
1786 radv_get_int_debug_option(const char *name, int default_value)
1787 {
1788 const char *str;
1789 int result;
1790
1791 str = getenv(name);
1792 if (!str) {
1793 result = default_value;
1794 } else {
1795 char *endptr;
1796
1797 result = strtol(str, &endptr, 0);
1798 if (str == endptr) {
1799 /* No digits founs. */
1800 result = default_value;
1801 }
1802 }
1803
1804 return result;
1805 }
1806
1807 VkResult radv_CreateDevice(
1808 VkPhysicalDevice physicalDevice,
1809 const VkDeviceCreateInfo* pCreateInfo,
1810 const VkAllocationCallbacks* pAllocator,
1811 VkDevice* pDevice)
1812 {
1813 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1814 VkResult result;
1815 struct radv_device *device;
1816
1817 bool keep_shader_info = false;
1818
1819 /* Check enabled features */
1820 if (pCreateInfo->pEnabledFeatures) {
1821 VkPhysicalDeviceFeatures supported_features;
1822 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1823 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1824 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1825 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1826 for (uint32_t i = 0; i < num_features; i++) {
1827 if (enabled_feature[i] && !supported_feature[i])
1828 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1829 }
1830 }
1831
1832 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1833 sizeof(*device), 8,
1834 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1835 if (!device)
1836 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1837
1838 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1839 device->instance = physical_device->instance;
1840 device->physical_device = physical_device;
1841
1842 device->ws = physical_device->ws;
1843 if (pAllocator)
1844 device->alloc = *pAllocator;
1845 else
1846 device->alloc = physical_device->instance->alloc;
1847
1848 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1849 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1850 int index = radv_get_device_extension_index(ext_name);
1851 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1852 vk_free(&device->alloc, device);
1853 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1854 }
1855
1856 device->enabled_extensions.extensions[index] = true;
1857 }
1858
1859 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1860
1861 /* With update after bind we can't attach bo's to the command buffer
1862 * from the descriptor set anymore, so we have to use a global BO list.
1863 */
1864 device->use_global_bo_list =
1865 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1866 device->enabled_extensions.EXT_descriptor_indexing ||
1867 device->enabled_extensions.EXT_buffer_device_address;
1868
1869 mtx_init(&device->shader_slab_mutex, mtx_plain);
1870 list_inithead(&device->shader_slabs);
1871
1872 radv_bo_list_init(&device->bo_list);
1873
1874 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1875 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1876 uint32_t qfi = queue_create->queueFamilyIndex;
1877 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1878 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1879
1880 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1881
1882 device->queues[qfi] = vk_alloc(&device->alloc,
1883 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1884 if (!device->queues[qfi]) {
1885 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1886 goto fail;
1887 }
1888
1889 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1890
1891 device->queue_count[qfi] = queue_create->queueCount;
1892
1893 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1894 result = radv_queue_init(device, &device->queues[qfi][q],
1895 qfi, q, queue_create->flags,
1896 global_priority);
1897 if (result != VK_SUCCESS)
1898 goto fail;
1899 }
1900 }
1901
1902 /* TODO: Enable binning for GFX10. */
1903 device->pbb_allowed = device->physical_device->rad_info.chip_class == GFX9 &&
1904 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1905
1906 /* Disabled and not implemented for now. */
1907 device->dfsm_allowed = device->pbb_allowed &&
1908 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1909 device->physical_device->rad_info.family == CHIP_RAVEN2);
1910
1911 #ifdef ANDROID
1912 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1913 #endif
1914
1915 /* The maximum number of scratch waves. Scratch space isn't divided
1916 * evenly between CUs. The number is only a function of the number of CUs.
1917 * We can decrease the constant to decrease the scratch buffer size.
1918 *
1919 * sctx->scratch_waves must be >= the maximum possible size of
1920 * 1 threadgroup, so that the hw doesn't hang from being unable
1921 * to start any.
1922 *
1923 * The recommended value is 4 per CU at most. Higher numbers don't
1924 * bring much benefit, but they still occupy chip resources (think
1925 * async compute). I've seen ~2% performance difference between 4 and 32.
1926 */
1927 uint32_t max_threads_per_block = 2048;
1928 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1929 max_threads_per_block / 64);
1930
1931 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1932
1933 if (device->physical_device->rad_info.chip_class >= GFX7) {
1934 /* If the KMD allows it (there is a KMD hw register for it),
1935 * allow launching waves out-of-order.
1936 */
1937 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1938 }
1939
1940 radv_device_init_gs_info(device);
1941
1942 device->tess_offchip_block_dw_size =
1943 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1944 device->has_distributed_tess =
1945 device->physical_device->rad_info.chip_class >= GFX8 &&
1946 device->physical_device->rad_info.max_se >= 2;
1947
1948 if (getenv("RADV_TRACE_FILE")) {
1949 const char *filename = getenv("RADV_TRACE_FILE");
1950
1951 keep_shader_info = true;
1952
1953 if (!radv_init_trace(device))
1954 goto fail;
1955
1956 fprintf(stderr, "*****************************************************************************\n");
1957 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1958 fprintf(stderr, "*****************************************************************************\n");
1959
1960 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1961 radv_dump_enabled_options(device, stderr);
1962 }
1963
1964 device->keep_shader_info = keep_shader_info;
1965
1966 result = radv_device_init_meta(device);
1967 if (result != VK_SUCCESS)
1968 goto fail;
1969
1970 radv_device_init_msaa(device);
1971
1972 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1973 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1974 switch (family) {
1975 case RADV_QUEUE_GENERAL:
1976 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1977 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1978 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1979 break;
1980 case RADV_QUEUE_COMPUTE:
1981 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1982 radeon_emit(device->empty_cs[family], 0);
1983 break;
1984 }
1985 device->ws->cs_finalize(device->empty_cs[family]);
1986 }
1987
1988 if (device->physical_device->rad_info.chip_class >= GFX7)
1989 cik_create_gfx_config(device);
1990
1991 VkPipelineCacheCreateInfo ci;
1992 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1993 ci.pNext = NULL;
1994 ci.flags = 0;
1995 ci.pInitialData = NULL;
1996 ci.initialDataSize = 0;
1997 VkPipelineCache pc;
1998 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1999 &ci, NULL, &pc);
2000 if (result != VK_SUCCESS)
2001 goto fail_meta;
2002
2003 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2004
2005 device->force_aniso =
2006 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2007 if (device->force_aniso >= 0) {
2008 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2009 1 << util_logbase2(device->force_aniso));
2010 }
2011
2012 *pDevice = radv_device_to_handle(device);
2013 return VK_SUCCESS;
2014
2015 fail_meta:
2016 radv_device_finish_meta(device);
2017 fail:
2018 radv_bo_list_finish(&device->bo_list);
2019
2020 if (device->trace_bo)
2021 device->ws->buffer_destroy(device->trace_bo);
2022
2023 if (device->gfx_init)
2024 device->ws->buffer_destroy(device->gfx_init);
2025
2026 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2027 for (unsigned q = 0; q < device->queue_count[i]; q++)
2028 radv_queue_finish(&device->queues[i][q]);
2029 if (device->queue_count[i])
2030 vk_free(&device->alloc, device->queues[i]);
2031 }
2032
2033 vk_free(&device->alloc, device);
2034 return result;
2035 }
2036
2037 void radv_DestroyDevice(
2038 VkDevice _device,
2039 const VkAllocationCallbacks* pAllocator)
2040 {
2041 RADV_FROM_HANDLE(radv_device, device, _device);
2042
2043 if (!device)
2044 return;
2045
2046 if (device->trace_bo)
2047 device->ws->buffer_destroy(device->trace_bo);
2048
2049 if (device->gfx_init)
2050 device->ws->buffer_destroy(device->gfx_init);
2051
2052 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2053 for (unsigned q = 0; q < device->queue_count[i]; q++)
2054 radv_queue_finish(&device->queues[i][q]);
2055 if (device->queue_count[i])
2056 vk_free(&device->alloc, device->queues[i]);
2057 if (device->empty_cs[i])
2058 device->ws->cs_destroy(device->empty_cs[i]);
2059 }
2060 radv_device_finish_meta(device);
2061
2062 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2063 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2064
2065 radv_destroy_shader_slabs(device);
2066
2067 radv_bo_list_finish(&device->bo_list);
2068 vk_free(&device->alloc, device);
2069 }
2070
2071 VkResult radv_EnumerateInstanceLayerProperties(
2072 uint32_t* pPropertyCount,
2073 VkLayerProperties* pProperties)
2074 {
2075 if (pProperties == NULL) {
2076 *pPropertyCount = 0;
2077 return VK_SUCCESS;
2078 }
2079
2080 /* None supported at this time */
2081 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2082 }
2083
2084 VkResult radv_EnumerateDeviceLayerProperties(
2085 VkPhysicalDevice physicalDevice,
2086 uint32_t* pPropertyCount,
2087 VkLayerProperties* pProperties)
2088 {
2089 if (pProperties == NULL) {
2090 *pPropertyCount = 0;
2091 return VK_SUCCESS;
2092 }
2093
2094 /* None supported at this time */
2095 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2096 }
2097
2098 void radv_GetDeviceQueue2(
2099 VkDevice _device,
2100 const VkDeviceQueueInfo2* pQueueInfo,
2101 VkQueue* pQueue)
2102 {
2103 RADV_FROM_HANDLE(radv_device, device, _device);
2104 struct radv_queue *queue;
2105
2106 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2107 if (pQueueInfo->flags != queue->flags) {
2108 /* From the Vulkan 1.1.70 spec:
2109 *
2110 * "The queue returned by vkGetDeviceQueue2 must have the same
2111 * flags value from this structure as that used at device
2112 * creation time in a VkDeviceQueueCreateInfo instance. If no
2113 * matching flags were specified at device creation time then
2114 * pQueue will return VK_NULL_HANDLE."
2115 */
2116 *pQueue = VK_NULL_HANDLE;
2117 return;
2118 }
2119
2120 *pQueue = radv_queue_to_handle(queue);
2121 }
2122
2123 void radv_GetDeviceQueue(
2124 VkDevice _device,
2125 uint32_t queueFamilyIndex,
2126 uint32_t queueIndex,
2127 VkQueue* pQueue)
2128 {
2129 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2130 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2131 .queueFamilyIndex = queueFamilyIndex,
2132 .queueIndex = queueIndex
2133 };
2134
2135 radv_GetDeviceQueue2(_device, &info, pQueue);
2136 }
2137
2138 static void
2139 fill_geom_tess_rings(struct radv_queue *queue,
2140 uint32_t *map,
2141 bool add_sample_positions,
2142 uint32_t esgs_ring_size,
2143 struct radeon_winsys_bo *esgs_ring_bo,
2144 uint32_t gsvs_ring_size,
2145 struct radeon_winsys_bo *gsvs_ring_bo,
2146 uint32_t tess_factor_ring_size,
2147 uint32_t tess_offchip_ring_offset,
2148 uint32_t tess_offchip_ring_size,
2149 struct radeon_winsys_bo *tess_rings_bo)
2150 {
2151 uint32_t *desc = &map[4];
2152
2153 if (esgs_ring_bo) {
2154 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2155
2156 /* stride 0, num records - size, add tid, swizzle, elsize4,
2157 index stride 64 */
2158 desc[0] = esgs_va;
2159 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2160 S_008F04_STRIDE(0) |
2161 S_008F04_SWIZZLE_ENABLE(true);
2162 desc[2] = esgs_ring_size;
2163 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2164 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2165 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2166 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2167 S_008F0C_ELEMENT_SIZE(1) |
2168 S_008F0C_INDEX_STRIDE(3) |
2169 S_008F0C_ADD_TID_ENABLE(true);
2170
2171 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2172 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2173 S_008F0C_OOB_SELECT(2) |
2174 S_008F0C_RESOURCE_LEVEL(1);
2175 } else {
2176 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2177 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2178 }
2179
2180 /* GS entry for ES->GS ring */
2181 /* stride 0, num records - size, elsize0,
2182 index stride 0 */
2183 desc[4] = esgs_va;
2184 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2185 S_008F04_STRIDE(0) |
2186 S_008F04_SWIZZLE_ENABLE(false);
2187 desc[6] = esgs_ring_size;
2188 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2192 S_008F0C_ELEMENT_SIZE(0) |
2193 S_008F0C_INDEX_STRIDE(0) |
2194 S_008F0C_ADD_TID_ENABLE(false);
2195
2196 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2197 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2198 S_008F0C_OOB_SELECT(2) |
2199 S_008F0C_RESOURCE_LEVEL(1);
2200 } else {
2201 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2202 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2203 }
2204 }
2205
2206 desc += 8;
2207
2208 if (gsvs_ring_bo) {
2209 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2210
2211 /* VS entry for GS->VS ring */
2212 /* stride 0, num records - size, elsize0,
2213 index stride 0 */
2214 desc[0] = gsvs_va;
2215 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2216 S_008F04_STRIDE(0) |
2217 S_008F04_SWIZZLE_ENABLE(false);
2218 desc[2] = gsvs_ring_size;
2219 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2220 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2221 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2222 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2223 S_008F0C_ELEMENT_SIZE(0) |
2224 S_008F0C_INDEX_STRIDE(0) |
2225 S_008F0C_ADD_TID_ENABLE(false);
2226
2227 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2228 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2229 S_008F0C_OOB_SELECT(2) |
2230 S_008F0C_RESOURCE_LEVEL(1);
2231 } else {
2232 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2233 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2234 }
2235
2236 /* stride gsvs_itemsize, num records 64
2237 elsize 4, index stride 16 */
2238 /* shader will patch stride and desc[2] */
2239 desc[4] = gsvs_va;
2240 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2241 S_008F04_STRIDE(0) |
2242 S_008F04_SWIZZLE_ENABLE(true);
2243 desc[6] = 0;
2244 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2245 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2246 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2247 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2248 S_008F0C_ELEMENT_SIZE(1) |
2249 S_008F0C_INDEX_STRIDE(1) |
2250 S_008F0C_ADD_TID_ENABLE(true);
2251
2252 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2253 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2254 S_008F0C_OOB_SELECT(2) |
2255 S_008F0C_RESOURCE_LEVEL(1);
2256 } else {
2257 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2258 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2259 }
2260
2261 }
2262
2263 desc += 8;
2264
2265 if (tess_rings_bo) {
2266 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2267 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2268
2269 desc[0] = tess_va;
2270 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2271 S_008F04_STRIDE(0) |
2272 S_008F04_SWIZZLE_ENABLE(false);
2273 desc[2] = tess_factor_ring_size;
2274 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2278
2279 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2280 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2281 S_008F0C_OOB_SELECT(3) |
2282 S_008F0C_RESOURCE_LEVEL(1);
2283 } else {
2284 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2286 }
2287
2288 desc[4] = tess_offchip_va;
2289 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2290 S_008F04_STRIDE(0) |
2291 S_008F04_SWIZZLE_ENABLE(false);
2292 desc[6] = tess_offchip_ring_size;
2293 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2294 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2295 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2296 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2297
2298 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2299 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2300 S_008F0C_OOB_SELECT(3) |
2301 S_008F0C_RESOURCE_LEVEL(1);
2302 } else {
2303 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2304 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2305 }
2306 }
2307
2308 desc += 8;
2309
2310 if (add_sample_positions) {
2311 /* add sample positions after all rings */
2312 memcpy(desc, queue->device->sample_locations_1x, 8);
2313 desc += 2;
2314 memcpy(desc, queue->device->sample_locations_2x, 16);
2315 desc += 4;
2316 memcpy(desc, queue->device->sample_locations_4x, 32);
2317 desc += 8;
2318 memcpy(desc, queue->device->sample_locations_8x, 64);
2319 }
2320 }
2321
2322 static unsigned
2323 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2324 {
2325 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2326 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2327 device->physical_device->rad_info.family != CHIP_STONEY;
2328 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2329 unsigned max_offchip_buffers;
2330 unsigned offchip_granularity;
2331 unsigned hs_offchip_param;
2332
2333 /*
2334 * Per RadeonSI:
2335 * This must be one less than the maximum number due to a hw limitation.
2336 * Various hardware bugs need thGFX7
2337 *
2338 * Per AMDVLK:
2339 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2340 * Gfx7 should limit max_offchip_buffers to 508
2341 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2342 *
2343 * Follow AMDVLK here.
2344 */
2345 if (device->physical_device->rad_info.chip_class >= GFX10) {
2346 max_offchip_buffers_per_se = 256;
2347 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2348 device->physical_device->rad_info.chip_class == GFX7 ||
2349 device->physical_device->rad_info.chip_class == GFX6)
2350 --max_offchip_buffers_per_se;
2351
2352 max_offchip_buffers = max_offchip_buffers_per_se *
2353 device->physical_device->rad_info.max_se;
2354
2355 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2356 * around by setting 4K granularity.
2357 */
2358 if (device->tess_offchip_block_dw_size == 4096) {
2359 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2360 offchip_granularity = V_03093C_X_4K_DWORDS;
2361 } else {
2362 assert(device->tess_offchip_block_dw_size == 8192);
2363 offchip_granularity = V_03093C_X_8K_DWORDS;
2364 }
2365
2366 switch (device->physical_device->rad_info.chip_class) {
2367 case GFX6:
2368 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2369 break;
2370 case GFX7:
2371 case GFX8:
2372 case GFX9:
2373 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2374 break;
2375 case GFX10:
2376 break;
2377 default:
2378 break;
2379 }
2380
2381 *max_offchip_buffers_p = max_offchip_buffers;
2382 if (device->physical_device->rad_info.chip_class >= GFX7) {
2383 if (device->physical_device->rad_info.chip_class >= GFX8)
2384 --max_offchip_buffers;
2385 hs_offchip_param =
2386 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2387 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2388 } else {
2389 hs_offchip_param =
2390 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2391 }
2392 return hs_offchip_param;
2393 }
2394
2395 static void
2396 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2397 struct radeon_winsys_bo *esgs_ring_bo,
2398 uint32_t esgs_ring_size,
2399 struct radeon_winsys_bo *gsvs_ring_bo,
2400 uint32_t gsvs_ring_size)
2401 {
2402 if (!esgs_ring_bo && !gsvs_ring_bo)
2403 return;
2404
2405 if (esgs_ring_bo)
2406 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2407
2408 if (gsvs_ring_bo)
2409 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2410
2411 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2412 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2413 radeon_emit(cs, esgs_ring_size >> 8);
2414 radeon_emit(cs, gsvs_ring_size >> 8);
2415 } else {
2416 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2417 radeon_emit(cs, esgs_ring_size >> 8);
2418 radeon_emit(cs, gsvs_ring_size >> 8);
2419 }
2420 }
2421
2422 static void
2423 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2424 unsigned hs_offchip_param, unsigned tf_ring_size,
2425 struct radeon_winsys_bo *tess_rings_bo)
2426 {
2427 uint64_t tf_va;
2428
2429 if (!tess_rings_bo)
2430 return;
2431
2432 tf_va = radv_buffer_get_va(tess_rings_bo);
2433
2434 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2435
2436 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2437 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2438 S_030938_SIZE(tf_ring_size / 4));
2439 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2440 tf_va >> 8);
2441
2442 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2443 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2444 S_030984_BASE_HI(tf_va >> 40));
2445 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2446 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2447 S_030944_BASE_HI(tf_va >> 40));
2448 }
2449 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2450 hs_offchip_param);
2451 } else {
2452 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2453 S_008988_SIZE(tf_ring_size / 4));
2454 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2455 tf_va >> 8);
2456 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2457 hs_offchip_param);
2458 }
2459 }
2460
2461 static void
2462 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2463 struct radeon_winsys_bo *compute_scratch_bo)
2464 {
2465 uint64_t scratch_va;
2466
2467 if (!compute_scratch_bo)
2468 return;
2469
2470 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2471
2472 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2473
2474 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2475 radeon_emit(cs, scratch_va);
2476 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2477 S_008F04_SWIZZLE_ENABLE(1));
2478 }
2479
2480 static void
2481 radv_emit_global_shader_pointers(struct radv_queue *queue,
2482 struct radeon_cmdbuf *cs,
2483 struct radeon_winsys_bo *descriptor_bo)
2484 {
2485 uint64_t va;
2486
2487 if (!descriptor_bo)
2488 return;
2489
2490 va = radv_buffer_get_va(descriptor_bo);
2491
2492 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2493
2494 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2495 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2496 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2497 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2498 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2499
2500 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2501 radv_emit_shader_pointer(queue->device, cs, regs[i],
2502 va, true);
2503 }
2504 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2505 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2506 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2507 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2508 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2509
2510 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2511 radv_emit_shader_pointer(queue->device, cs, regs[i],
2512 va, true);
2513 }
2514 } else {
2515 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2516 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2517 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2518 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2519 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2520 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2521
2522 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2523 radv_emit_shader_pointer(queue->device, cs, regs[i],
2524 va, true);
2525 }
2526 }
2527 }
2528
2529 static void
2530 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2531 {
2532 struct radv_device *device = queue->device;
2533
2534 if (device->gfx_init) {
2535 uint64_t va = radv_buffer_get_va(device->gfx_init);
2536
2537 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2538 radeon_emit(cs, va);
2539 radeon_emit(cs, va >> 32);
2540 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2541
2542 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2543 } else {
2544 struct radv_physical_device *physical_device = device->physical_device;
2545 si_emit_graphics(physical_device, cs);
2546 }
2547 }
2548
2549 static void
2550 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2551 {
2552 struct radv_physical_device *physical_device = queue->device->physical_device;
2553 si_emit_compute(physical_device, cs);
2554 }
2555
2556 static VkResult
2557 radv_get_preamble_cs(struct radv_queue *queue,
2558 uint32_t scratch_size,
2559 uint32_t compute_scratch_size,
2560 uint32_t esgs_ring_size,
2561 uint32_t gsvs_ring_size,
2562 bool needs_tess_rings,
2563 bool needs_sample_positions,
2564 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2565 struct radeon_cmdbuf **initial_preamble_cs,
2566 struct radeon_cmdbuf **continue_preamble_cs)
2567 {
2568 struct radeon_winsys_bo *scratch_bo = NULL;
2569 struct radeon_winsys_bo *descriptor_bo = NULL;
2570 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2571 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2572 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2573 struct radeon_winsys_bo *tess_rings_bo = NULL;
2574 struct radeon_cmdbuf *dest_cs[3] = {0};
2575 bool add_tess_rings = false, add_sample_positions = false;
2576 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2577 unsigned max_offchip_buffers;
2578 unsigned hs_offchip_param = 0;
2579 unsigned tess_offchip_ring_offset;
2580 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2581 if (!queue->has_tess_rings) {
2582 if (needs_tess_rings)
2583 add_tess_rings = true;
2584 }
2585 if (!queue->has_sample_positions) {
2586 if (needs_sample_positions)
2587 add_sample_positions = true;
2588 }
2589 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2590 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2591 &max_offchip_buffers);
2592 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2593 tess_offchip_ring_size = max_offchip_buffers *
2594 queue->device->tess_offchip_block_dw_size * 4;
2595
2596 if (scratch_size <= queue->scratch_size &&
2597 compute_scratch_size <= queue->compute_scratch_size &&
2598 esgs_ring_size <= queue->esgs_ring_size &&
2599 gsvs_ring_size <= queue->gsvs_ring_size &&
2600 !add_tess_rings && !add_sample_positions &&
2601 queue->initial_preamble_cs) {
2602 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2603 *initial_preamble_cs = queue->initial_preamble_cs;
2604 *continue_preamble_cs = queue->continue_preamble_cs;
2605 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2606 *continue_preamble_cs = NULL;
2607 return VK_SUCCESS;
2608 }
2609
2610 if (scratch_size > queue->scratch_size) {
2611 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2612 scratch_size,
2613 4096,
2614 RADEON_DOMAIN_VRAM,
2615 ring_bo_flags,
2616 RADV_BO_PRIORITY_SCRATCH);
2617 if (!scratch_bo)
2618 goto fail;
2619 } else
2620 scratch_bo = queue->scratch_bo;
2621
2622 if (compute_scratch_size > queue->compute_scratch_size) {
2623 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2624 compute_scratch_size,
2625 4096,
2626 RADEON_DOMAIN_VRAM,
2627 ring_bo_flags,
2628 RADV_BO_PRIORITY_SCRATCH);
2629 if (!compute_scratch_bo)
2630 goto fail;
2631
2632 } else
2633 compute_scratch_bo = queue->compute_scratch_bo;
2634
2635 if (esgs_ring_size > queue->esgs_ring_size) {
2636 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2637 esgs_ring_size,
2638 4096,
2639 RADEON_DOMAIN_VRAM,
2640 ring_bo_flags,
2641 RADV_BO_PRIORITY_SCRATCH);
2642 if (!esgs_ring_bo)
2643 goto fail;
2644 } else {
2645 esgs_ring_bo = queue->esgs_ring_bo;
2646 esgs_ring_size = queue->esgs_ring_size;
2647 }
2648
2649 if (gsvs_ring_size > queue->gsvs_ring_size) {
2650 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2651 gsvs_ring_size,
2652 4096,
2653 RADEON_DOMAIN_VRAM,
2654 ring_bo_flags,
2655 RADV_BO_PRIORITY_SCRATCH);
2656 if (!gsvs_ring_bo)
2657 goto fail;
2658 } else {
2659 gsvs_ring_bo = queue->gsvs_ring_bo;
2660 gsvs_ring_size = queue->gsvs_ring_size;
2661 }
2662
2663 if (add_tess_rings) {
2664 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2665 tess_offchip_ring_offset + tess_offchip_ring_size,
2666 256,
2667 RADEON_DOMAIN_VRAM,
2668 ring_bo_flags,
2669 RADV_BO_PRIORITY_SCRATCH);
2670 if (!tess_rings_bo)
2671 goto fail;
2672 } else {
2673 tess_rings_bo = queue->tess_rings_bo;
2674 }
2675
2676 if (scratch_bo != queue->scratch_bo ||
2677 esgs_ring_bo != queue->esgs_ring_bo ||
2678 gsvs_ring_bo != queue->gsvs_ring_bo ||
2679 tess_rings_bo != queue->tess_rings_bo ||
2680 add_sample_positions) {
2681 uint32_t size = 0;
2682 if (gsvs_ring_bo || esgs_ring_bo ||
2683 tess_rings_bo || add_sample_positions) {
2684 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2685 if (add_sample_positions)
2686 size += 128; /* 64+32+16+8 = 120 bytes */
2687 }
2688 else if (scratch_bo)
2689 size = 8; /* 2 dword */
2690
2691 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2692 size,
2693 4096,
2694 RADEON_DOMAIN_VRAM,
2695 RADEON_FLAG_CPU_ACCESS |
2696 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2697 RADEON_FLAG_READ_ONLY,
2698 RADV_BO_PRIORITY_DESCRIPTOR);
2699 if (!descriptor_bo)
2700 goto fail;
2701 } else
2702 descriptor_bo = queue->descriptor_bo;
2703
2704 if (descriptor_bo != queue->descriptor_bo) {
2705 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2706
2707 if (scratch_bo) {
2708 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2709 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2710 S_008F04_SWIZZLE_ENABLE(1);
2711 map[0] = scratch_va;
2712 map[1] = rsrc1;
2713 }
2714
2715 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2716 fill_geom_tess_rings(queue, map, add_sample_positions,
2717 esgs_ring_size, esgs_ring_bo,
2718 gsvs_ring_size, gsvs_ring_bo,
2719 tess_factor_ring_size,
2720 tess_offchip_ring_offset,
2721 tess_offchip_ring_size,
2722 tess_rings_bo);
2723
2724 queue->device->ws->buffer_unmap(descriptor_bo);
2725 }
2726
2727 for(int i = 0; i < 3; ++i) {
2728 struct radeon_cmdbuf *cs = NULL;
2729 cs = queue->device->ws->cs_create(queue->device->ws,
2730 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2731 if (!cs)
2732 goto fail;
2733
2734 dest_cs[i] = cs;
2735
2736 if (scratch_bo)
2737 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2738
2739 /* Emit initial configuration. */
2740 switch (queue->queue_family_index) {
2741 case RADV_QUEUE_GENERAL:
2742 radv_init_graphics_state(cs, queue);
2743 break;
2744 case RADV_QUEUE_COMPUTE:
2745 radv_init_compute_state(cs, queue);
2746 break;
2747 case RADV_QUEUE_TRANSFER:
2748 break;
2749 }
2750
2751 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2752 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2753 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2754
2755 if (queue->device->physical_device->rad_info.chip_class < GFX10) {
2756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2757 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2758 }
2759 }
2760
2761 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2762 gsvs_ring_bo, gsvs_ring_size);
2763 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2764 tess_factor_ring_size, tess_rings_bo);
2765 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2766 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2767
2768 if (i == 0) {
2769 si_cs_emit_cache_flush(cs,
2770 queue->device->physical_device->rad_info.chip_class,
2771 NULL, 0,
2772 queue->queue_family_index == RING_COMPUTE &&
2773 queue->device->physical_device->rad_info.chip_class >= GFX7,
2774 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2775 RADV_CMD_FLAG_INV_ICACHE |
2776 RADV_CMD_FLAG_INV_SCACHE |
2777 RADV_CMD_FLAG_INV_VCACHE |
2778 RADV_CMD_FLAG_INV_L2 |
2779 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2780 } else if (i == 1) {
2781 si_cs_emit_cache_flush(cs,
2782 queue->device->physical_device->rad_info.chip_class,
2783 NULL, 0,
2784 queue->queue_family_index == RING_COMPUTE &&
2785 queue->device->physical_device->rad_info.chip_class >= GFX7,
2786 RADV_CMD_FLAG_INV_ICACHE |
2787 RADV_CMD_FLAG_INV_SCACHE |
2788 RADV_CMD_FLAG_INV_VCACHE |
2789 RADV_CMD_FLAG_INV_L2 |
2790 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2791 }
2792
2793 if (!queue->device->ws->cs_finalize(cs))
2794 goto fail;
2795 }
2796
2797 if (queue->initial_full_flush_preamble_cs)
2798 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2799
2800 if (queue->initial_preamble_cs)
2801 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2802
2803 if (queue->continue_preamble_cs)
2804 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2805
2806 queue->initial_full_flush_preamble_cs = dest_cs[0];
2807 queue->initial_preamble_cs = dest_cs[1];
2808 queue->continue_preamble_cs = dest_cs[2];
2809
2810 if (scratch_bo != queue->scratch_bo) {
2811 if (queue->scratch_bo)
2812 queue->device->ws->buffer_destroy(queue->scratch_bo);
2813 queue->scratch_bo = scratch_bo;
2814 queue->scratch_size = scratch_size;
2815 }
2816
2817 if (compute_scratch_bo != queue->compute_scratch_bo) {
2818 if (queue->compute_scratch_bo)
2819 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2820 queue->compute_scratch_bo = compute_scratch_bo;
2821 queue->compute_scratch_size = compute_scratch_size;
2822 }
2823
2824 if (esgs_ring_bo != queue->esgs_ring_bo) {
2825 if (queue->esgs_ring_bo)
2826 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2827 queue->esgs_ring_bo = esgs_ring_bo;
2828 queue->esgs_ring_size = esgs_ring_size;
2829 }
2830
2831 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2832 if (queue->gsvs_ring_bo)
2833 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2834 queue->gsvs_ring_bo = gsvs_ring_bo;
2835 queue->gsvs_ring_size = gsvs_ring_size;
2836 }
2837
2838 if (tess_rings_bo != queue->tess_rings_bo) {
2839 queue->tess_rings_bo = tess_rings_bo;
2840 queue->has_tess_rings = true;
2841 }
2842
2843 if (descriptor_bo != queue->descriptor_bo) {
2844 if (queue->descriptor_bo)
2845 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2846
2847 queue->descriptor_bo = descriptor_bo;
2848 }
2849
2850 if (add_sample_positions)
2851 queue->has_sample_positions = true;
2852
2853 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2854 *initial_preamble_cs = queue->initial_preamble_cs;
2855 *continue_preamble_cs = queue->continue_preamble_cs;
2856 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2857 *continue_preamble_cs = NULL;
2858 return VK_SUCCESS;
2859 fail:
2860 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2861 if (dest_cs[i])
2862 queue->device->ws->cs_destroy(dest_cs[i]);
2863 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2864 queue->device->ws->buffer_destroy(descriptor_bo);
2865 if (scratch_bo && scratch_bo != queue->scratch_bo)
2866 queue->device->ws->buffer_destroy(scratch_bo);
2867 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2868 queue->device->ws->buffer_destroy(compute_scratch_bo);
2869 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2870 queue->device->ws->buffer_destroy(esgs_ring_bo);
2871 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2872 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2873 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2874 queue->device->ws->buffer_destroy(tess_rings_bo);
2875 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2876 }
2877
2878 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2879 struct radv_winsys_sem_counts *counts,
2880 int num_sems,
2881 const VkSemaphore *sems,
2882 VkFence _fence,
2883 bool reset_temp)
2884 {
2885 int syncobj_idx = 0, sem_idx = 0;
2886
2887 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2888 return VK_SUCCESS;
2889
2890 for (uint32_t i = 0; i < num_sems; i++) {
2891 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2892
2893 if (sem->temp_syncobj || sem->syncobj)
2894 counts->syncobj_count++;
2895 else
2896 counts->sem_count++;
2897 }
2898
2899 if (_fence != VK_NULL_HANDLE) {
2900 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2901 if (fence->temp_syncobj || fence->syncobj)
2902 counts->syncobj_count++;
2903 }
2904
2905 if (counts->syncobj_count) {
2906 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2907 if (!counts->syncobj)
2908 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2909 }
2910
2911 if (counts->sem_count) {
2912 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2913 if (!counts->sem) {
2914 free(counts->syncobj);
2915 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2916 }
2917 }
2918
2919 for (uint32_t i = 0; i < num_sems; i++) {
2920 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2921
2922 if (sem->temp_syncobj) {
2923 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2924 }
2925 else if (sem->syncobj)
2926 counts->syncobj[syncobj_idx++] = sem->syncobj;
2927 else {
2928 assert(sem->sem);
2929 counts->sem[sem_idx++] = sem->sem;
2930 }
2931 }
2932
2933 if (_fence != VK_NULL_HANDLE) {
2934 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2935 if (fence->temp_syncobj)
2936 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2937 else if (fence->syncobj)
2938 counts->syncobj[syncobj_idx++] = fence->syncobj;
2939 }
2940
2941 return VK_SUCCESS;
2942 }
2943
2944 static void
2945 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2946 {
2947 free(sem_info->wait.syncobj);
2948 free(sem_info->wait.sem);
2949 free(sem_info->signal.syncobj);
2950 free(sem_info->signal.sem);
2951 }
2952
2953
2954 static void radv_free_temp_syncobjs(struct radv_device *device,
2955 int num_sems,
2956 const VkSemaphore *sems)
2957 {
2958 for (uint32_t i = 0; i < num_sems; i++) {
2959 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2960
2961 if (sem->temp_syncobj) {
2962 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2963 sem->temp_syncobj = 0;
2964 }
2965 }
2966 }
2967
2968 static VkResult
2969 radv_alloc_sem_info(struct radv_instance *instance,
2970 struct radv_winsys_sem_info *sem_info,
2971 int num_wait_sems,
2972 const VkSemaphore *wait_sems,
2973 int num_signal_sems,
2974 const VkSemaphore *signal_sems,
2975 VkFence fence)
2976 {
2977 VkResult ret;
2978 memset(sem_info, 0, sizeof(*sem_info));
2979
2980 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2981 if (ret)
2982 return ret;
2983 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2984 if (ret)
2985 radv_free_sem_info(sem_info);
2986
2987 /* caller can override these */
2988 sem_info->cs_emit_wait = true;
2989 sem_info->cs_emit_signal = true;
2990 return ret;
2991 }
2992
2993 /* Signals fence as soon as all the work currently put on queue is done. */
2994 static VkResult radv_signal_fence(struct radv_queue *queue,
2995 struct radv_fence *fence)
2996 {
2997 int ret;
2998 VkResult result;
2999 struct radv_winsys_sem_info sem_info;
3000
3001 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3002 radv_fence_to_handle(fence));
3003 if (result != VK_SUCCESS)
3004 return result;
3005
3006 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3007 &queue->device->empty_cs[queue->queue_family_index],
3008 1, NULL, NULL, &sem_info, NULL,
3009 false, fence->fence);
3010 radv_free_sem_info(&sem_info);
3011
3012 if (ret)
3013 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3014
3015 return VK_SUCCESS;
3016 }
3017
3018 VkResult radv_QueueSubmit(
3019 VkQueue _queue,
3020 uint32_t submitCount,
3021 const VkSubmitInfo* pSubmits,
3022 VkFence _fence)
3023 {
3024 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3025 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3026 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3027 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3028 int ret;
3029 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3030 uint32_t scratch_size = 0;
3031 uint32_t compute_scratch_size = 0;
3032 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3033 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3034 VkResult result;
3035 bool fence_emitted = false;
3036 bool tess_rings_needed = false;
3037 bool sample_positions_needed = false;
3038
3039 /* Do this first so failing to allocate scratch buffers can't result in
3040 * partially executed submissions. */
3041 for (uint32_t i = 0; i < submitCount; i++) {
3042 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3043 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3044 pSubmits[i].pCommandBuffers[j]);
3045
3046 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3047 compute_scratch_size = MAX2(compute_scratch_size,
3048 cmd_buffer->compute_scratch_size_needed);
3049 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3050 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3051 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3052 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3053 }
3054 }
3055
3056 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3057 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3058 sample_positions_needed, &initial_flush_preamble_cs,
3059 &initial_preamble_cs, &continue_preamble_cs);
3060 if (result != VK_SUCCESS)
3061 return result;
3062
3063 for (uint32_t i = 0; i < submitCount; i++) {
3064 struct radeon_cmdbuf **cs_array;
3065 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3066 bool can_patch = true;
3067 uint32_t advance;
3068 struct radv_winsys_sem_info sem_info;
3069
3070 result = radv_alloc_sem_info(queue->device->instance,
3071 &sem_info,
3072 pSubmits[i].waitSemaphoreCount,
3073 pSubmits[i].pWaitSemaphores,
3074 pSubmits[i].signalSemaphoreCount,
3075 pSubmits[i].pSignalSemaphores,
3076 _fence);
3077 if (result != VK_SUCCESS)
3078 return result;
3079
3080 if (!pSubmits[i].commandBufferCount) {
3081 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3082 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3083 &queue->device->empty_cs[queue->queue_family_index],
3084 1, NULL, NULL,
3085 &sem_info, NULL,
3086 false, base_fence);
3087 if (ret) {
3088 radv_loge("failed to submit CS %d\n", i);
3089 abort();
3090 }
3091 fence_emitted = true;
3092 }
3093 radv_free_sem_info(&sem_info);
3094 continue;
3095 }
3096
3097 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3098 (pSubmits[i].commandBufferCount));
3099
3100 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3101 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3102 pSubmits[i].pCommandBuffers[j]);
3103 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3104
3105 cs_array[j] = cmd_buffer->cs;
3106 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3107 can_patch = false;
3108
3109 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3110 }
3111
3112 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3113 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3114 const struct radv_winsys_bo_list *bo_list = NULL;
3115
3116 advance = MIN2(max_cs_submission,
3117 pSubmits[i].commandBufferCount - j);
3118
3119 if (queue->device->trace_bo)
3120 *queue->device->trace_id_ptr = 0;
3121
3122 sem_info.cs_emit_wait = j == 0;
3123 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3124
3125 if (unlikely(queue->device->use_global_bo_list)) {
3126 pthread_mutex_lock(&queue->device->bo_list.mutex);
3127 bo_list = &queue->device->bo_list.list;
3128 }
3129
3130 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3131 advance, initial_preamble, continue_preamble_cs,
3132 &sem_info, bo_list,
3133 can_patch, base_fence);
3134
3135 if (unlikely(queue->device->use_global_bo_list))
3136 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3137
3138 if (ret) {
3139 radv_loge("failed to submit CS %d\n", i);
3140 abort();
3141 }
3142 fence_emitted = true;
3143 if (queue->device->trace_bo) {
3144 radv_check_gpu_hangs(queue, cs_array[j]);
3145 }
3146 }
3147
3148 radv_free_temp_syncobjs(queue->device,
3149 pSubmits[i].waitSemaphoreCount,
3150 pSubmits[i].pWaitSemaphores);
3151 radv_free_sem_info(&sem_info);
3152 free(cs_array);
3153 }
3154
3155 if (fence) {
3156 if (!fence_emitted) {
3157 result = radv_signal_fence(queue, fence);
3158 if (result != VK_SUCCESS)
3159 return result;
3160 }
3161 }
3162
3163 return VK_SUCCESS;
3164 }
3165
3166 VkResult radv_QueueWaitIdle(
3167 VkQueue _queue)
3168 {
3169 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3170
3171 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3172 radv_queue_family_to_ring(queue->queue_family_index),
3173 queue->queue_idx);
3174 return VK_SUCCESS;
3175 }
3176
3177 VkResult radv_DeviceWaitIdle(
3178 VkDevice _device)
3179 {
3180 RADV_FROM_HANDLE(radv_device, device, _device);
3181
3182 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3183 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3184 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3185 }
3186 }
3187 return VK_SUCCESS;
3188 }
3189
3190 VkResult radv_EnumerateInstanceExtensionProperties(
3191 const char* pLayerName,
3192 uint32_t* pPropertyCount,
3193 VkExtensionProperties* pProperties)
3194 {
3195 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3196
3197 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3198 if (radv_supported_instance_extensions.extensions[i]) {
3199 vk_outarray_append(&out, prop) {
3200 *prop = radv_instance_extensions[i];
3201 }
3202 }
3203 }
3204
3205 return vk_outarray_status(&out);
3206 }
3207
3208 VkResult radv_EnumerateDeviceExtensionProperties(
3209 VkPhysicalDevice physicalDevice,
3210 const char* pLayerName,
3211 uint32_t* pPropertyCount,
3212 VkExtensionProperties* pProperties)
3213 {
3214 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3215 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3216
3217 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3218 if (device->supported_extensions.extensions[i]) {
3219 vk_outarray_append(&out, prop) {
3220 *prop = radv_device_extensions[i];
3221 }
3222 }
3223 }
3224
3225 return vk_outarray_status(&out);
3226 }
3227
3228 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3229 VkInstance _instance,
3230 const char* pName)
3231 {
3232 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3233
3234 return radv_lookup_entrypoint_checked(pName,
3235 instance ? instance->apiVersion : 0,
3236 instance ? &instance->enabled_extensions : NULL,
3237 NULL);
3238 }
3239
3240 /* The loader wants us to expose a second GetInstanceProcAddr function
3241 * to work around certain LD_PRELOAD issues seen in apps.
3242 */
3243 PUBLIC
3244 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3245 VkInstance instance,
3246 const char* pName);
3247
3248 PUBLIC
3249 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3250 VkInstance instance,
3251 const char* pName)
3252 {
3253 return radv_GetInstanceProcAddr(instance, pName);
3254 }
3255
3256 PUBLIC
3257 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3258 VkInstance _instance,
3259 const char* pName);
3260
3261 PUBLIC
3262 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3263 VkInstance _instance,
3264 const char* pName)
3265 {
3266 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3267
3268 return radv_lookup_physical_device_entrypoint_checked(pName,
3269 instance ? instance->apiVersion : 0,
3270 instance ? &instance->enabled_extensions : NULL);
3271 }
3272
3273 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3274 VkDevice _device,
3275 const char* pName)
3276 {
3277 RADV_FROM_HANDLE(radv_device, device, _device);
3278
3279 return radv_lookup_entrypoint_checked(pName,
3280 device->instance->apiVersion,
3281 &device->instance->enabled_extensions,
3282 &device->enabled_extensions);
3283 }
3284
3285 bool radv_get_memory_fd(struct radv_device *device,
3286 struct radv_device_memory *memory,
3287 int *pFD)
3288 {
3289 struct radeon_bo_metadata metadata;
3290
3291 if (memory->image) {
3292 radv_init_metadata(device, memory->image, &metadata);
3293 device->ws->buffer_set_metadata(memory->bo, &metadata);
3294 }
3295
3296 return device->ws->buffer_get_fd(device->ws, memory->bo,
3297 pFD);
3298 }
3299
3300 static VkResult radv_alloc_memory(struct radv_device *device,
3301 const VkMemoryAllocateInfo* pAllocateInfo,
3302 const VkAllocationCallbacks* pAllocator,
3303 VkDeviceMemory* pMem)
3304 {
3305 struct radv_device_memory *mem;
3306 VkResult result;
3307 enum radeon_bo_domain domain;
3308 uint32_t flags = 0;
3309 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3310
3311 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3312
3313 if (pAllocateInfo->allocationSize == 0) {
3314 /* Apparently, this is allowed */
3315 *pMem = VK_NULL_HANDLE;
3316 return VK_SUCCESS;
3317 }
3318
3319 const VkImportMemoryFdInfoKHR *import_info =
3320 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3321 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3322 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3323 const VkExportMemoryAllocateInfo *export_info =
3324 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3325 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3326 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3327
3328 const struct wsi_memory_allocate_info *wsi_info =
3329 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3330
3331 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3332 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3333 if (mem == NULL)
3334 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3335
3336 if (wsi_info && wsi_info->implicit_sync)
3337 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3338
3339 if (dedicate_info) {
3340 mem->image = radv_image_from_handle(dedicate_info->image);
3341 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3342 } else {
3343 mem->image = NULL;
3344 mem->buffer = NULL;
3345 }
3346
3347 float priority_float = 0.5;
3348 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3349 vk_find_struct_const(pAllocateInfo->pNext,
3350 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3351 if (priority_ext)
3352 priority_float = priority_ext->priority;
3353
3354 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3355 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3356
3357 mem->user_ptr = NULL;
3358
3359 if (import_info) {
3360 assert(import_info->handleType ==
3361 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3362 import_info->handleType ==
3363 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3364 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3365 priority, NULL, NULL);
3366 if (!mem->bo) {
3367 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3368 goto fail;
3369 } else {
3370 close(import_info->fd);
3371 }
3372 } else if (host_ptr_info) {
3373 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3374 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3375 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3376 pAllocateInfo->allocationSize,
3377 priority);
3378 if (!mem->bo) {
3379 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3380 goto fail;
3381 } else {
3382 mem->user_ptr = host_ptr_info->pHostPointer;
3383 }
3384 } else {
3385 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3386 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3387 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3388 domain = RADEON_DOMAIN_GTT;
3389 else
3390 domain = RADEON_DOMAIN_VRAM;
3391
3392 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3393 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3394 else
3395 flags |= RADEON_FLAG_CPU_ACCESS;
3396
3397 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3398 flags |= RADEON_FLAG_GTT_WC;
3399
3400 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3401 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3402 if (device->use_global_bo_list) {
3403 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3404 }
3405 }
3406
3407 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3408 domain, flags, priority);
3409
3410 if (!mem->bo) {
3411 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3412 goto fail;
3413 }
3414 mem->type_index = mem_type_index;
3415 }
3416
3417 result = radv_bo_list_add(device, mem->bo);
3418 if (result != VK_SUCCESS)
3419 goto fail_bo;
3420
3421 *pMem = radv_device_memory_to_handle(mem);
3422
3423 return VK_SUCCESS;
3424
3425 fail_bo:
3426 device->ws->buffer_destroy(mem->bo);
3427 fail:
3428 vk_free2(&device->alloc, pAllocator, mem);
3429
3430 return result;
3431 }
3432
3433 VkResult radv_AllocateMemory(
3434 VkDevice _device,
3435 const VkMemoryAllocateInfo* pAllocateInfo,
3436 const VkAllocationCallbacks* pAllocator,
3437 VkDeviceMemory* pMem)
3438 {
3439 RADV_FROM_HANDLE(radv_device, device, _device);
3440 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3441 }
3442
3443 void radv_FreeMemory(
3444 VkDevice _device,
3445 VkDeviceMemory _mem,
3446 const VkAllocationCallbacks* pAllocator)
3447 {
3448 RADV_FROM_HANDLE(radv_device, device, _device);
3449 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3450
3451 if (mem == NULL)
3452 return;
3453
3454 radv_bo_list_remove(device, mem->bo);
3455 device->ws->buffer_destroy(mem->bo);
3456 mem->bo = NULL;
3457
3458 vk_free2(&device->alloc, pAllocator, mem);
3459 }
3460
3461 VkResult radv_MapMemory(
3462 VkDevice _device,
3463 VkDeviceMemory _memory,
3464 VkDeviceSize offset,
3465 VkDeviceSize size,
3466 VkMemoryMapFlags flags,
3467 void** ppData)
3468 {
3469 RADV_FROM_HANDLE(radv_device, device, _device);
3470 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3471
3472 if (mem == NULL) {
3473 *ppData = NULL;
3474 return VK_SUCCESS;
3475 }
3476
3477 if (mem->user_ptr)
3478 *ppData = mem->user_ptr;
3479 else
3480 *ppData = device->ws->buffer_map(mem->bo);
3481
3482 if (*ppData) {
3483 *ppData += offset;
3484 return VK_SUCCESS;
3485 }
3486
3487 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3488 }
3489
3490 void radv_UnmapMemory(
3491 VkDevice _device,
3492 VkDeviceMemory _memory)
3493 {
3494 RADV_FROM_HANDLE(radv_device, device, _device);
3495 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3496
3497 if (mem == NULL)
3498 return;
3499
3500 if (mem->user_ptr == NULL)
3501 device->ws->buffer_unmap(mem->bo);
3502 }
3503
3504 VkResult radv_FlushMappedMemoryRanges(
3505 VkDevice _device,
3506 uint32_t memoryRangeCount,
3507 const VkMappedMemoryRange* pMemoryRanges)
3508 {
3509 return VK_SUCCESS;
3510 }
3511
3512 VkResult radv_InvalidateMappedMemoryRanges(
3513 VkDevice _device,
3514 uint32_t memoryRangeCount,
3515 const VkMappedMemoryRange* pMemoryRanges)
3516 {
3517 return VK_SUCCESS;
3518 }
3519
3520 void radv_GetBufferMemoryRequirements(
3521 VkDevice _device,
3522 VkBuffer _buffer,
3523 VkMemoryRequirements* pMemoryRequirements)
3524 {
3525 RADV_FROM_HANDLE(radv_device, device, _device);
3526 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3527
3528 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3529
3530 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3531 pMemoryRequirements->alignment = 4096;
3532 else
3533 pMemoryRequirements->alignment = 16;
3534
3535 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3536 }
3537
3538 void radv_GetBufferMemoryRequirements2(
3539 VkDevice device,
3540 const VkBufferMemoryRequirementsInfo2 *pInfo,
3541 VkMemoryRequirements2 *pMemoryRequirements)
3542 {
3543 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3544 &pMemoryRequirements->memoryRequirements);
3545 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3546 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3547 switch (ext->sType) {
3548 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3549 VkMemoryDedicatedRequirements *req =
3550 (VkMemoryDedicatedRequirements *) ext;
3551 req->requiresDedicatedAllocation = buffer->shareable;
3552 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3553 break;
3554 }
3555 default:
3556 break;
3557 }
3558 }
3559 }
3560
3561 void radv_GetImageMemoryRequirements(
3562 VkDevice _device,
3563 VkImage _image,
3564 VkMemoryRequirements* pMemoryRequirements)
3565 {
3566 RADV_FROM_HANDLE(radv_device, device, _device);
3567 RADV_FROM_HANDLE(radv_image, image, _image);
3568
3569 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3570
3571 pMemoryRequirements->size = image->size;
3572 pMemoryRequirements->alignment = image->alignment;
3573 }
3574
3575 void radv_GetImageMemoryRequirements2(
3576 VkDevice device,
3577 const VkImageMemoryRequirementsInfo2 *pInfo,
3578 VkMemoryRequirements2 *pMemoryRequirements)
3579 {
3580 radv_GetImageMemoryRequirements(device, pInfo->image,
3581 &pMemoryRequirements->memoryRequirements);
3582
3583 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3584
3585 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3586 switch (ext->sType) {
3587 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3588 VkMemoryDedicatedRequirements *req =
3589 (VkMemoryDedicatedRequirements *) ext;
3590 req->requiresDedicatedAllocation = image->shareable;
3591 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3592 break;
3593 }
3594 default:
3595 break;
3596 }
3597 }
3598 }
3599
3600 void radv_GetImageSparseMemoryRequirements(
3601 VkDevice device,
3602 VkImage image,
3603 uint32_t* pSparseMemoryRequirementCount,
3604 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3605 {
3606 stub();
3607 }
3608
3609 void radv_GetImageSparseMemoryRequirements2(
3610 VkDevice device,
3611 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3612 uint32_t* pSparseMemoryRequirementCount,
3613 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3614 {
3615 stub();
3616 }
3617
3618 void radv_GetDeviceMemoryCommitment(
3619 VkDevice device,
3620 VkDeviceMemory memory,
3621 VkDeviceSize* pCommittedMemoryInBytes)
3622 {
3623 *pCommittedMemoryInBytes = 0;
3624 }
3625
3626 VkResult radv_BindBufferMemory2(VkDevice device,
3627 uint32_t bindInfoCount,
3628 const VkBindBufferMemoryInfo *pBindInfos)
3629 {
3630 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3631 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3632 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3633
3634 if (mem) {
3635 buffer->bo = mem->bo;
3636 buffer->offset = pBindInfos[i].memoryOffset;
3637 } else {
3638 buffer->bo = NULL;
3639 }
3640 }
3641 return VK_SUCCESS;
3642 }
3643
3644 VkResult radv_BindBufferMemory(
3645 VkDevice device,
3646 VkBuffer buffer,
3647 VkDeviceMemory memory,
3648 VkDeviceSize memoryOffset)
3649 {
3650 const VkBindBufferMemoryInfo info = {
3651 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3652 .buffer = buffer,
3653 .memory = memory,
3654 .memoryOffset = memoryOffset
3655 };
3656
3657 return radv_BindBufferMemory2(device, 1, &info);
3658 }
3659
3660 VkResult radv_BindImageMemory2(VkDevice device,
3661 uint32_t bindInfoCount,
3662 const VkBindImageMemoryInfo *pBindInfos)
3663 {
3664 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3665 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3666 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3667
3668 if (mem) {
3669 image->bo = mem->bo;
3670 image->offset = pBindInfos[i].memoryOffset;
3671 } else {
3672 image->bo = NULL;
3673 image->offset = 0;
3674 }
3675 }
3676 return VK_SUCCESS;
3677 }
3678
3679
3680 VkResult radv_BindImageMemory(
3681 VkDevice device,
3682 VkImage image,
3683 VkDeviceMemory memory,
3684 VkDeviceSize memoryOffset)
3685 {
3686 const VkBindImageMemoryInfo info = {
3687 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3688 .image = image,
3689 .memory = memory,
3690 .memoryOffset = memoryOffset
3691 };
3692
3693 return radv_BindImageMemory2(device, 1, &info);
3694 }
3695
3696
3697 static void
3698 radv_sparse_buffer_bind_memory(struct radv_device *device,
3699 const VkSparseBufferMemoryBindInfo *bind)
3700 {
3701 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3702
3703 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3704 struct radv_device_memory *mem = NULL;
3705
3706 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3707 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3708
3709 device->ws->buffer_virtual_bind(buffer->bo,
3710 bind->pBinds[i].resourceOffset,
3711 bind->pBinds[i].size,
3712 mem ? mem->bo : NULL,
3713 bind->pBinds[i].memoryOffset);
3714 }
3715 }
3716
3717 static void
3718 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3719 const VkSparseImageOpaqueMemoryBindInfo *bind)
3720 {
3721 RADV_FROM_HANDLE(radv_image, image, bind->image);
3722
3723 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3724 struct radv_device_memory *mem = NULL;
3725
3726 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3727 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3728
3729 device->ws->buffer_virtual_bind(image->bo,
3730 bind->pBinds[i].resourceOffset,
3731 bind->pBinds[i].size,
3732 mem ? mem->bo : NULL,
3733 bind->pBinds[i].memoryOffset);
3734 }
3735 }
3736
3737 VkResult radv_QueueBindSparse(
3738 VkQueue _queue,
3739 uint32_t bindInfoCount,
3740 const VkBindSparseInfo* pBindInfo,
3741 VkFence _fence)
3742 {
3743 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3744 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3745 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3746 bool fence_emitted = false;
3747 VkResult result;
3748 int ret;
3749
3750 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3751 struct radv_winsys_sem_info sem_info;
3752 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3753 radv_sparse_buffer_bind_memory(queue->device,
3754 pBindInfo[i].pBufferBinds + j);
3755 }
3756
3757 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3758 radv_sparse_image_opaque_bind_memory(queue->device,
3759 pBindInfo[i].pImageOpaqueBinds + j);
3760 }
3761
3762 VkResult result;
3763 result = radv_alloc_sem_info(queue->device->instance,
3764 &sem_info,
3765 pBindInfo[i].waitSemaphoreCount,
3766 pBindInfo[i].pWaitSemaphores,
3767 pBindInfo[i].signalSemaphoreCount,
3768 pBindInfo[i].pSignalSemaphores,
3769 _fence);
3770 if (result != VK_SUCCESS)
3771 return result;
3772
3773 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3774 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3775 &queue->device->empty_cs[queue->queue_family_index],
3776 1, NULL, NULL,
3777 &sem_info, NULL,
3778 false, base_fence);
3779 if (ret) {
3780 radv_loge("failed to submit CS %d\n", i);
3781 abort();
3782 }
3783
3784 fence_emitted = true;
3785 }
3786
3787 radv_free_sem_info(&sem_info);
3788
3789 }
3790
3791 if (fence) {
3792 if (!fence_emitted) {
3793 result = radv_signal_fence(queue, fence);
3794 if (result != VK_SUCCESS)
3795 return result;
3796 }
3797 }
3798
3799 return VK_SUCCESS;
3800 }
3801
3802 VkResult radv_CreateFence(
3803 VkDevice _device,
3804 const VkFenceCreateInfo* pCreateInfo,
3805 const VkAllocationCallbacks* pAllocator,
3806 VkFence* pFence)
3807 {
3808 RADV_FROM_HANDLE(radv_device, device, _device);
3809 const VkExportFenceCreateInfo *export =
3810 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3811 VkExternalFenceHandleTypeFlags handleTypes =
3812 export ? export->handleTypes : 0;
3813
3814 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3815 sizeof(*fence), 8,
3816 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3817
3818 if (!fence)
3819 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3820
3821 fence->fence_wsi = NULL;
3822 fence->temp_syncobj = 0;
3823 if (device->always_use_syncobj || handleTypes) {
3824 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3825 if (ret) {
3826 vk_free2(&device->alloc, pAllocator, fence);
3827 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3828 }
3829 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3830 device->ws->signal_syncobj(device->ws, fence->syncobj);
3831 }
3832 fence->fence = NULL;
3833 } else {
3834 fence->fence = device->ws->create_fence();
3835 if (!fence->fence) {
3836 vk_free2(&device->alloc, pAllocator, fence);
3837 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3838 }
3839 fence->syncobj = 0;
3840 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3841 device->ws->signal_fence(fence->fence);
3842 }
3843
3844 *pFence = radv_fence_to_handle(fence);
3845
3846 return VK_SUCCESS;
3847 }
3848
3849 void radv_DestroyFence(
3850 VkDevice _device,
3851 VkFence _fence,
3852 const VkAllocationCallbacks* pAllocator)
3853 {
3854 RADV_FROM_HANDLE(radv_device, device, _device);
3855 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3856
3857 if (!fence)
3858 return;
3859
3860 if (fence->temp_syncobj)
3861 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3862 if (fence->syncobj)
3863 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3864 if (fence->fence)
3865 device->ws->destroy_fence(fence->fence);
3866 if (fence->fence_wsi)
3867 fence->fence_wsi->destroy(fence->fence_wsi);
3868 vk_free2(&device->alloc, pAllocator, fence);
3869 }
3870
3871
3872 uint64_t radv_get_current_time(void)
3873 {
3874 struct timespec tv;
3875 clock_gettime(CLOCK_MONOTONIC, &tv);
3876 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3877 }
3878
3879 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3880 {
3881 uint64_t current_time = radv_get_current_time();
3882
3883 timeout = MIN2(UINT64_MAX - current_time, timeout);
3884
3885 return current_time + timeout;
3886 }
3887
3888
3889 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3890 uint32_t fenceCount, const VkFence *pFences)
3891 {
3892 for (uint32_t i = 0; i < fenceCount; ++i) {
3893 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3894 if (fence->fence == NULL || fence->syncobj ||
3895 fence->temp_syncobj || fence->fence_wsi ||
3896 (!device->ws->is_fence_waitable(fence->fence)))
3897 return false;
3898 }
3899 return true;
3900 }
3901
3902 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3903 {
3904 for (uint32_t i = 0; i < fenceCount; ++i) {
3905 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3906 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3907 return false;
3908 }
3909 return true;
3910 }
3911
3912 VkResult radv_WaitForFences(
3913 VkDevice _device,
3914 uint32_t fenceCount,
3915 const VkFence* pFences,
3916 VkBool32 waitAll,
3917 uint64_t timeout)
3918 {
3919 RADV_FROM_HANDLE(radv_device, device, _device);
3920 timeout = radv_get_absolute_timeout(timeout);
3921
3922 if (device->always_use_syncobj &&
3923 radv_all_fences_syncobj(fenceCount, pFences))
3924 {
3925 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3926 if (!handles)
3927 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3928
3929 for (uint32_t i = 0; i < fenceCount; ++i) {
3930 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3931 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3932 }
3933
3934 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3935
3936 free(handles);
3937 return success ? VK_SUCCESS : VK_TIMEOUT;
3938 }
3939
3940 if (!waitAll && fenceCount > 1) {
3941 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3942 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3943 uint32_t wait_count = 0;
3944 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3945 if (!fences)
3946 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3947
3948 for (uint32_t i = 0; i < fenceCount; ++i) {
3949 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3950
3951 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3952 free(fences);
3953 return VK_SUCCESS;
3954 }
3955
3956 fences[wait_count++] = fence->fence;
3957 }
3958
3959 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3960 waitAll, timeout - radv_get_current_time());
3961
3962 free(fences);
3963 return success ? VK_SUCCESS : VK_TIMEOUT;
3964 }
3965
3966 while(radv_get_current_time() <= timeout) {
3967 for (uint32_t i = 0; i < fenceCount; ++i) {
3968 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3969 return VK_SUCCESS;
3970 }
3971 }
3972 return VK_TIMEOUT;
3973 }
3974
3975 for (uint32_t i = 0; i < fenceCount; ++i) {
3976 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3977 bool expired = false;
3978
3979 if (fence->temp_syncobj) {
3980 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3981 return VK_TIMEOUT;
3982 continue;
3983 }
3984
3985 if (fence->syncobj) {
3986 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3987 return VK_TIMEOUT;
3988 continue;
3989 }
3990
3991 if (fence->fence) {
3992 if (!device->ws->is_fence_waitable(fence->fence)) {
3993 while(!device->ws->is_fence_waitable(fence->fence) &&
3994 radv_get_current_time() <= timeout)
3995 /* Do nothing */;
3996 }
3997
3998 expired = device->ws->fence_wait(device->ws,
3999 fence->fence,
4000 true, timeout);
4001 if (!expired)
4002 return VK_TIMEOUT;
4003 }
4004
4005 if (fence->fence_wsi) {
4006 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4007 if (result != VK_SUCCESS)
4008 return result;
4009 }
4010 }
4011
4012 return VK_SUCCESS;
4013 }
4014
4015 VkResult radv_ResetFences(VkDevice _device,
4016 uint32_t fenceCount,
4017 const VkFence *pFences)
4018 {
4019 RADV_FROM_HANDLE(radv_device, device, _device);
4020
4021 for (unsigned i = 0; i < fenceCount; ++i) {
4022 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4023 if (fence->fence)
4024 device->ws->reset_fence(fence->fence);
4025
4026 /* Per spec, we first restore the permanent payload, and then reset, so
4027 * having a temp syncobj should not skip resetting the permanent syncobj. */
4028 if (fence->temp_syncobj) {
4029 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4030 fence->temp_syncobj = 0;
4031 }
4032
4033 if (fence->syncobj) {
4034 device->ws->reset_syncobj(device->ws, fence->syncobj);
4035 }
4036 }
4037
4038 return VK_SUCCESS;
4039 }
4040
4041 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4042 {
4043 RADV_FROM_HANDLE(radv_device, device, _device);
4044 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4045
4046 if (fence->temp_syncobj) {
4047 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4048 return success ? VK_SUCCESS : VK_NOT_READY;
4049 }
4050
4051 if (fence->syncobj) {
4052 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4053 return success ? VK_SUCCESS : VK_NOT_READY;
4054 }
4055
4056 if (fence->fence) {
4057 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4058 return VK_NOT_READY;
4059 }
4060 if (fence->fence_wsi) {
4061 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4062
4063 if (result != VK_SUCCESS) {
4064 if (result == VK_TIMEOUT)
4065 return VK_NOT_READY;
4066 return result;
4067 }
4068 }
4069 return VK_SUCCESS;
4070 }
4071
4072
4073 // Queue semaphore functions
4074
4075 VkResult radv_CreateSemaphore(
4076 VkDevice _device,
4077 const VkSemaphoreCreateInfo* pCreateInfo,
4078 const VkAllocationCallbacks* pAllocator,
4079 VkSemaphore* pSemaphore)
4080 {
4081 RADV_FROM_HANDLE(radv_device, device, _device);
4082 const VkExportSemaphoreCreateInfo *export =
4083 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4084 VkExternalSemaphoreHandleTypeFlags handleTypes =
4085 export ? export->handleTypes : 0;
4086
4087 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4088 sizeof(*sem), 8,
4089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4090 if (!sem)
4091 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4092
4093 sem->temp_syncobj = 0;
4094 /* create a syncobject if we are going to export this semaphore */
4095 if (device->always_use_syncobj || handleTypes) {
4096 assert (device->physical_device->rad_info.has_syncobj);
4097 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4098 if (ret) {
4099 vk_free2(&device->alloc, pAllocator, sem);
4100 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4101 }
4102 sem->sem = NULL;
4103 } else {
4104 sem->sem = device->ws->create_sem(device->ws);
4105 if (!sem->sem) {
4106 vk_free2(&device->alloc, pAllocator, sem);
4107 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4108 }
4109 sem->syncobj = 0;
4110 }
4111
4112 *pSemaphore = radv_semaphore_to_handle(sem);
4113 return VK_SUCCESS;
4114 }
4115
4116 void radv_DestroySemaphore(
4117 VkDevice _device,
4118 VkSemaphore _semaphore,
4119 const VkAllocationCallbacks* pAllocator)
4120 {
4121 RADV_FROM_HANDLE(radv_device, device, _device);
4122 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4123 if (!_semaphore)
4124 return;
4125
4126 if (sem->syncobj)
4127 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4128 else
4129 device->ws->destroy_sem(sem->sem);
4130 vk_free2(&device->alloc, pAllocator, sem);
4131 }
4132
4133 VkResult radv_CreateEvent(
4134 VkDevice _device,
4135 const VkEventCreateInfo* pCreateInfo,
4136 const VkAllocationCallbacks* pAllocator,
4137 VkEvent* pEvent)
4138 {
4139 RADV_FROM_HANDLE(radv_device, device, _device);
4140 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4141 sizeof(*event), 8,
4142 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4143
4144 if (!event)
4145 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4146
4147 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4148 RADEON_DOMAIN_GTT,
4149 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4150 RADV_BO_PRIORITY_FENCE);
4151 if (!event->bo) {
4152 vk_free2(&device->alloc, pAllocator, event);
4153 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4154 }
4155
4156 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4157
4158 *pEvent = radv_event_to_handle(event);
4159
4160 return VK_SUCCESS;
4161 }
4162
4163 void radv_DestroyEvent(
4164 VkDevice _device,
4165 VkEvent _event,
4166 const VkAllocationCallbacks* pAllocator)
4167 {
4168 RADV_FROM_HANDLE(radv_device, device, _device);
4169 RADV_FROM_HANDLE(radv_event, event, _event);
4170
4171 if (!event)
4172 return;
4173 device->ws->buffer_destroy(event->bo);
4174 vk_free2(&device->alloc, pAllocator, event);
4175 }
4176
4177 VkResult radv_GetEventStatus(
4178 VkDevice _device,
4179 VkEvent _event)
4180 {
4181 RADV_FROM_HANDLE(radv_event, event, _event);
4182
4183 if (*event->map == 1)
4184 return VK_EVENT_SET;
4185 return VK_EVENT_RESET;
4186 }
4187
4188 VkResult radv_SetEvent(
4189 VkDevice _device,
4190 VkEvent _event)
4191 {
4192 RADV_FROM_HANDLE(radv_event, event, _event);
4193 *event->map = 1;
4194
4195 return VK_SUCCESS;
4196 }
4197
4198 VkResult radv_ResetEvent(
4199 VkDevice _device,
4200 VkEvent _event)
4201 {
4202 RADV_FROM_HANDLE(radv_event, event, _event);
4203 *event->map = 0;
4204
4205 return VK_SUCCESS;
4206 }
4207
4208 VkResult radv_CreateBuffer(
4209 VkDevice _device,
4210 const VkBufferCreateInfo* pCreateInfo,
4211 const VkAllocationCallbacks* pAllocator,
4212 VkBuffer* pBuffer)
4213 {
4214 RADV_FROM_HANDLE(radv_device, device, _device);
4215 struct radv_buffer *buffer;
4216
4217 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4218
4219 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4220 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4221 if (buffer == NULL)
4222 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4223
4224 buffer->size = pCreateInfo->size;
4225 buffer->usage = pCreateInfo->usage;
4226 buffer->bo = NULL;
4227 buffer->offset = 0;
4228 buffer->flags = pCreateInfo->flags;
4229
4230 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4231 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4232
4233 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4234 buffer->bo = device->ws->buffer_create(device->ws,
4235 align64(buffer->size, 4096),
4236 4096, 0, RADEON_FLAG_VIRTUAL,
4237 RADV_BO_PRIORITY_VIRTUAL);
4238 if (!buffer->bo) {
4239 vk_free2(&device->alloc, pAllocator, buffer);
4240 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4241 }
4242 }
4243
4244 *pBuffer = radv_buffer_to_handle(buffer);
4245
4246 return VK_SUCCESS;
4247 }
4248
4249 void radv_DestroyBuffer(
4250 VkDevice _device,
4251 VkBuffer _buffer,
4252 const VkAllocationCallbacks* pAllocator)
4253 {
4254 RADV_FROM_HANDLE(radv_device, device, _device);
4255 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4256
4257 if (!buffer)
4258 return;
4259
4260 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4261 device->ws->buffer_destroy(buffer->bo);
4262
4263 vk_free2(&device->alloc, pAllocator, buffer);
4264 }
4265
4266 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4267 VkDevice device,
4268 const VkBufferDeviceAddressInfoEXT* pInfo)
4269 {
4270 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4271 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4272 }
4273
4274
4275 static inline unsigned
4276 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4277 {
4278 if (stencil)
4279 return plane->surface.u.legacy.stencil_tiling_index[level];
4280 else
4281 return plane->surface.u.legacy.tiling_index[level];
4282 }
4283
4284 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4285 {
4286 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4287 }
4288
4289 static uint32_t
4290 radv_init_dcc_control_reg(struct radv_device *device,
4291 struct radv_image_view *iview)
4292 {
4293 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4294 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4295 unsigned max_compressed_block_size;
4296 unsigned independent_128b_blocks;
4297 unsigned independent_64b_blocks;
4298
4299 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4300 return 0;
4301
4302 if (!device->physical_device->rad_info.has_dedicated_vram) {
4303 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4304 * dGPU and 64 for APU because all of our APUs to date use
4305 * DIMMs which have a request granularity size of 64B while all
4306 * other chips have a 32B request size.
4307 */
4308 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4309 }
4310
4311 if (device->physical_device->rad_info.chip_class >= GFX10) {
4312 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4313 independent_64b_blocks = 0;
4314 independent_128b_blocks = 1;
4315 } else {
4316 independent_128b_blocks = 0;
4317
4318 if (iview->image->info.samples > 1) {
4319 if (iview->image->planes[0].surface.bpe == 1)
4320 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4321 else if (iview->image->planes[0].surface.bpe == 2)
4322 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4323 }
4324
4325 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4326 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4327 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4328 /* If this DCC image is potentially going to be used in texture
4329 * fetches, we need some special settings.
4330 */
4331 independent_64b_blocks = 1;
4332 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4333 } else {
4334 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4335 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4336 * big as possible for better compression state.
4337 */
4338 independent_64b_blocks = 0;
4339 max_compressed_block_size = max_uncompressed_block_size;
4340 }
4341 }
4342
4343 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4344 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4345 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4346 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4347 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4348 }
4349
4350 static void
4351 radv_initialise_color_surface(struct radv_device *device,
4352 struct radv_color_buffer_info *cb,
4353 struct radv_image_view *iview)
4354 {
4355 const struct vk_format_description *desc;
4356 unsigned ntype, format, swap, endian;
4357 unsigned blend_clamp = 0, blend_bypass = 0;
4358 uint64_t va;
4359 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4360 const struct radeon_surf *surf = &plane->surface;
4361
4362 desc = vk_format_description(iview->vk_format);
4363
4364 memset(cb, 0, sizeof(*cb));
4365
4366 /* Intensity is implemented as Red, so treat it that way. */
4367 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4368
4369 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4370
4371 cb->cb_color_base = va >> 8;
4372
4373 if (device->physical_device->rad_info.chip_class >= GFX9) {
4374 struct gfx9_surf_meta_flags meta;
4375 if (iview->image->dcc_offset)
4376 meta = surf->u.gfx9.dcc;
4377 else
4378 meta = surf->u.gfx9.cmask;
4379
4380 if (device->physical_device->rad_info.chip_class >= GFX10) {
4381 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4382 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4383 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4384 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4385 } else {
4386 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4387 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4388 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4389 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4390 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4391 }
4392
4393 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4394 cb->cb_color_base |= surf->tile_swizzle;
4395 } else {
4396 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4397 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4398
4399 cb->cb_color_base += level_info->offset >> 8;
4400 if (level_info->mode == RADEON_SURF_MODE_2D)
4401 cb->cb_color_base |= surf->tile_swizzle;
4402
4403 pitch_tile_max = level_info->nblk_x / 8 - 1;
4404 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4405 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4406
4407 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4408 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4409 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4410
4411 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4412
4413 if (radv_image_has_fmask(iview->image)) {
4414 if (device->physical_device->rad_info.chip_class >= GFX7)
4415 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4416 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4417 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4418 } else {
4419 /* This must be set for fast clear to work without FMASK. */
4420 if (device->physical_device->rad_info.chip_class >= GFX7)
4421 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4422 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4423 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4424 }
4425 }
4426
4427 /* CMASK variables */
4428 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4429 va += iview->image->cmask.offset;
4430 cb->cb_color_cmask = va >> 8;
4431
4432 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4433 va += iview->image->dcc_offset;
4434
4435 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4436 device->physical_device->rad_info.chip_class <= GFX8)
4437 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4438
4439 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4440 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4441
4442 cb->cb_dcc_base = va >> 8;
4443 cb->cb_dcc_base |= dcc_tile_swizzle;
4444
4445 /* GFX10 field has the same base shift as the GFX6 field. */
4446 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4447 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4448 S_028C6C_SLICE_MAX_GFX10(max_slice);
4449
4450 if (iview->image->info.samples > 1) {
4451 unsigned log_samples = util_logbase2(iview->image->info.samples);
4452
4453 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4454 S_028C74_NUM_FRAGMENTS(log_samples);
4455 }
4456
4457 if (radv_image_has_fmask(iview->image)) {
4458 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4459 cb->cb_color_fmask = va >> 8;
4460 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4461 } else {
4462 cb->cb_color_fmask = cb->cb_color_base;
4463 }
4464
4465 ntype = radv_translate_color_numformat(iview->vk_format,
4466 desc,
4467 vk_format_get_first_non_void_channel(iview->vk_format));
4468 format = radv_translate_colorformat(iview->vk_format);
4469 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4470 radv_finishme("Illegal color\n");
4471 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4472 endian = radv_colorformat_endian_swap(format);
4473
4474 /* blend clamp should be set for all NORM/SRGB types */
4475 if (ntype == V_028C70_NUMBER_UNORM ||
4476 ntype == V_028C70_NUMBER_SNORM ||
4477 ntype == V_028C70_NUMBER_SRGB)
4478 blend_clamp = 1;
4479
4480 /* set blend bypass according to docs if SINT/UINT or
4481 8/24 COLOR variants */
4482 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4483 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4484 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4485 blend_clamp = 0;
4486 blend_bypass = 1;
4487 }
4488 #if 0
4489 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4490 (format == V_028C70_COLOR_8 ||
4491 format == V_028C70_COLOR_8_8 ||
4492 format == V_028C70_COLOR_8_8_8_8))
4493 ->color_is_int8 = true;
4494 #endif
4495 cb->cb_color_info = S_028C70_FORMAT(format) |
4496 S_028C70_COMP_SWAP(swap) |
4497 S_028C70_BLEND_CLAMP(blend_clamp) |
4498 S_028C70_BLEND_BYPASS(blend_bypass) |
4499 S_028C70_SIMPLE_FLOAT(1) |
4500 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4501 ntype != V_028C70_NUMBER_SNORM &&
4502 ntype != V_028C70_NUMBER_SRGB &&
4503 format != V_028C70_COLOR_8_24 &&
4504 format != V_028C70_COLOR_24_8) |
4505 S_028C70_NUMBER_TYPE(ntype) |
4506 S_028C70_ENDIAN(endian);
4507 if (radv_image_has_fmask(iview->image)) {
4508 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4509 if (device->physical_device->rad_info.chip_class == GFX6) {
4510 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4511 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4512 }
4513
4514 if (radv_image_is_tc_compat_cmask(iview->image)) {
4515 /* Allow the texture block to read FMASK directly
4516 * without decompressing it. This bit must be cleared
4517 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4518 * otherwise the operation doesn't happen.
4519 */
4520 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4521
4522 /* Set CMASK into a tiling format that allows the
4523 * texture block to read it.
4524 */
4525 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4526 }
4527 }
4528
4529 if (radv_image_has_cmask(iview->image) &&
4530 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4531 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4532
4533 if (radv_dcc_enabled(iview->image, iview->base_mip))
4534 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4535
4536 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4537
4538 /* This must be set for fast clear to work without FMASK. */
4539 if (!radv_image_has_fmask(iview->image) &&
4540 device->physical_device->rad_info.chip_class == GFX6) {
4541 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4542 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4543 }
4544
4545 if (device->physical_device->rad_info.chip_class >= GFX9) {
4546 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4547
4548 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4549 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4550 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4551 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4552
4553 if (device->physical_device->rad_info.chip_class >= GFX10) {
4554 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4555
4556 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4557 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4558 S_028EE0_RESOURCE_LEVEL(1);
4559 } else {
4560 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4561 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4562 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4563 }
4564
4565 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4566 S_028C68_MIP0_HEIGHT(height - 1) |
4567 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4568 }
4569 }
4570
4571 static unsigned
4572 radv_calc_decompress_on_z_planes(struct radv_device *device,
4573 struct radv_image_view *iview)
4574 {
4575 unsigned max_zplanes = 0;
4576
4577 assert(radv_image_is_tc_compat_htile(iview->image));
4578
4579 if (device->physical_device->rad_info.chip_class >= GFX9) {
4580 /* Default value for 32-bit depth surfaces. */
4581 max_zplanes = 4;
4582
4583 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4584 iview->image->info.samples > 1)
4585 max_zplanes = 2;
4586
4587 max_zplanes = max_zplanes + 1;
4588 } else {
4589 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4590 /* Do not enable Z plane compression for 16-bit depth
4591 * surfaces because isn't supported on GFX8. Only
4592 * 32-bit depth surfaces are supported by the hardware.
4593 * This allows to maintain shader compatibility and to
4594 * reduce the number of depth decompressions.
4595 */
4596 max_zplanes = 1;
4597 } else {
4598 if (iview->image->info.samples <= 1)
4599 max_zplanes = 5;
4600 else if (iview->image->info.samples <= 4)
4601 max_zplanes = 3;
4602 else
4603 max_zplanes = 2;
4604 }
4605 }
4606
4607 return max_zplanes;
4608 }
4609
4610 static void
4611 radv_initialise_ds_surface(struct radv_device *device,
4612 struct radv_ds_buffer_info *ds,
4613 struct radv_image_view *iview)
4614 {
4615 unsigned level = iview->base_mip;
4616 unsigned format, stencil_format;
4617 uint64_t va, s_offs, z_offs;
4618 bool stencil_only = false;
4619 const struct radv_image_plane *plane = &iview->image->planes[0];
4620 const struct radeon_surf *surf = &plane->surface;
4621
4622 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4623
4624 memset(ds, 0, sizeof(*ds));
4625 switch (iview->image->vk_format) {
4626 case VK_FORMAT_D24_UNORM_S8_UINT:
4627 case VK_FORMAT_X8_D24_UNORM_PACK32:
4628 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4629 ds->offset_scale = 2.0f;
4630 break;
4631 case VK_FORMAT_D16_UNORM:
4632 case VK_FORMAT_D16_UNORM_S8_UINT:
4633 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4634 ds->offset_scale = 4.0f;
4635 break;
4636 case VK_FORMAT_D32_SFLOAT:
4637 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4638 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4639 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4640 ds->offset_scale = 1.0f;
4641 break;
4642 case VK_FORMAT_S8_UINT:
4643 stencil_only = true;
4644 break;
4645 default:
4646 break;
4647 }
4648
4649 format = radv_translate_dbformat(iview->image->vk_format);
4650 stencil_format = surf->has_stencil ?
4651 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4652
4653 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4654 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4655 S_028008_SLICE_MAX(max_slice);
4656 if (device->physical_device->rad_info.chip_class >= GFX10) {
4657 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4658 S_028008_SLICE_MAX_HI(max_slice >> 11);
4659 }
4660
4661 ds->db_htile_data_base = 0;
4662 ds->db_htile_surface = 0;
4663
4664 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4665 s_offs = z_offs = va;
4666
4667 if (device->physical_device->rad_info.chip_class >= GFX9) {
4668 assert(surf->u.gfx9.surf_offset == 0);
4669 s_offs += surf->u.gfx9.stencil_offset;
4670
4671 ds->db_z_info = S_028038_FORMAT(format) |
4672 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4673 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4674 S_028038_MAXMIP(iview->image->info.levels - 1) |
4675 S_028038_ZRANGE_PRECISION(1);
4676 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4677 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4678
4679 if (device->physical_device->rad_info.chip_class == GFX9) {
4680 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4681 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4682 }
4683
4684 ds->db_depth_view |= S_028008_MIPID(level);
4685 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4686 S_02801C_Y_MAX(iview->image->info.height - 1);
4687
4688 if (radv_htile_enabled(iview->image, level)) {
4689 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4690
4691 if (radv_image_is_tc_compat_htile(iview->image)) {
4692 unsigned max_zplanes =
4693 radv_calc_decompress_on_z_planes(device, iview);
4694
4695 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4696
4697 if (device->physical_device->rad_info.chip_class >= GFX10) {
4698 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4699 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4700 } else {
4701 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4702 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4703 }
4704 }
4705
4706 if (!surf->has_stencil)
4707 /* Use all of the htile_buffer for depth if there's no stencil. */
4708 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4709 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4710 iview->image->htile_offset;
4711 ds->db_htile_data_base = va >> 8;
4712 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4713 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4714
4715 if (device->physical_device->rad_info.chip_class == GFX9) {
4716 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4717 }
4718 }
4719 } else {
4720 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4721
4722 if (stencil_only)
4723 level_info = &surf->u.legacy.stencil_level[level];
4724
4725 z_offs += surf->u.legacy.level[level].offset;
4726 s_offs += surf->u.legacy.stencil_level[level].offset;
4727
4728 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4729 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4730 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4731
4732 if (iview->image->info.samples > 1)
4733 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4734
4735 if (device->physical_device->rad_info.chip_class >= GFX7) {
4736 struct radeon_info *info = &device->physical_device->rad_info;
4737 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4738 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4739 unsigned macro_index = surf->u.legacy.macro_tile_index;
4740 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4741 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4742 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4743
4744 if (stencil_only)
4745 tile_mode = stencil_tile_mode;
4746
4747 ds->db_depth_info |=
4748 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4749 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4750 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4751 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4752 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4753 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4754 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4755 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4756 } else {
4757 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4758 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4759 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4760 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4761 if (stencil_only)
4762 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4763 }
4764
4765 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4766 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4767 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4768
4769 if (radv_htile_enabled(iview->image, level)) {
4770 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4771
4772 if (!surf->has_stencil &&
4773 !radv_image_is_tc_compat_htile(iview->image))
4774 /* Use all of the htile_buffer for depth if there's no stencil. */
4775 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4776
4777 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4778 iview->image->htile_offset;
4779 ds->db_htile_data_base = va >> 8;
4780 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4781
4782 if (radv_image_is_tc_compat_htile(iview->image)) {
4783 unsigned max_zplanes =
4784 radv_calc_decompress_on_z_planes(device, iview);
4785
4786 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4787 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4788 }
4789 }
4790 }
4791
4792 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4793 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4794 }
4795
4796 VkResult radv_CreateFramebuffer(
4797 VkDevice _device,
4798 const VkFramebufferCreateInfo* pCreateInfo,
4799 const VkAllocationCallbacks* pAllocator,
4800 VkFramebuffer* pFramebuffer)
4801 {
4802 RADV_FROM_HANDLE(radv_device, device, _device);
4803 struct radv_framebuffer *framebuffer;
4804
4805 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4806
4807 size_t size = sizeof(*framebuffer) +
4808 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4809 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4810 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4811 if (framebuffer == NULL)
4812 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4813
4814 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4815 framebuffer->width = pCreateInfo->width;
4816 framebuffer->height = pCreateInfo->height;
4817 framebuffer->layers = pCreateInfo->layers;
4818 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4819 VkImageView _iview = pCreateInfo->pAttachments[i];
4820 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4821 framebuffer->attachments[i].attachment = iview;
4822 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4823 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4824 } else {
4825 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4826 }
4827 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4828 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4829 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4830 }
4831
4832 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4833 return VK_SUCCESS;
4834 }
4835
4836 void radv_DestroyFramebuffer(
4837 VkDevice _device,
4838 VkFramebuffer _fb,
4839 const VkAllocationCallbacks* pAllocator)
4840 {
4841 RADV_FROM_HANDLE(radv_device, device, _device);
4842 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4843
4844 if (!fb)
4845 return;
4846 vk_free2(&device->alloc, pAllocator, fb);
4847 }
4848
4849 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4850 {
4851 switch (address_mode) {
4852 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4853 return V_008F30_SQ_TEX_WRAP;
4854 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4855 return V_008F30_SQ_TEX_MIRROR;
4856 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4857 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4858 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4859 return V_008F30_SQ_TEX_CLAMP_BORDER;
4860 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4861 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4862 default:
4863 unreachable("illegal tex wrap mode");
4864 break;
4865 }
4866 }
4867
4868 static unsigned
4869 radv_tex_compare(VkCompareOp op)
4870 {
4871 switch (op) {
4872 case VK_COMPARE_OP_NEVER:
4873 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4874 case VK_COMPARE_OP_LESS:
4875 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4876 case VK_COMPARE_OP_EQUAL:
4877 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4878 case VK_COMPARE_OP_LESS_OR_EQUAL:
4879 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4880 case VK_COMPARE_OP_GREATER:
4881 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4882 case VK_COMPARE_OP_NOT_EQUAL:
4883 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4884 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4885 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4886 case VK_COMPARE_OP_ALWAYS:
4887 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4888 default:
4889 unreachable("illegal compare mode");
4890 break;
4891 }
4892 }
4893
4894 static unsigned
4895 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4896 {
4897 switch (filter) {
4898 case VK_FILTER_NEAREST:
4899 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4900 V_008F38_SQ_TEX_XY_FILTER_POINT);
4901 case VK_FILTER_LINEAR:
4902 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4903 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4904 case VK_FILTER_CUBIC_IMG:
4905 default:
4906 fprintf(stderr, "illegal texture filter");
4907 return 0;
4908 }
4909 }
4910
4911 static unsigned
4912 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4913 {
4914 switch (mode) {
4915 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4916 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4917 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4918 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4919 default:
4920 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4921 }
4922 }
4923
4924 static unsigned
4925 radv_tex_bordercolor(VkBorderColor bcolor)
4926 {
4927 switch (bcolor) {
4928 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4929 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4930 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4931 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4932 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4933 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4934 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4935 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4936 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4937 default:
4938 break;
4939 }
4940 return 0;
4941 }
4942
4943 static unsigned
4944 radv_tex_aniso_filter(unsigned filter)
4945 {
4946 if (filter < 2)
4947 return 0;
4948 if (filter < 4)
4949 return 1;
4950 if (filter < 8)
4951 return 2;
4952 if (filter < 16)
4953 return 3;
4954 return 4;
4955 }
4956
4957 static unsigned
4958 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4959 {
4960 switch (mode) {
4961 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4962 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4963 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4964 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4965 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4966 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4967 default:
4968 break;
4969 }
4970 return 0;
4971 }
4972
4973 static uint32_t
4974 radv_get_max_anisotropy(struct radv_device *device,
4975 const VkSamplerCreateInfo *pCreateInfo)
4976 {
4977 if (device->force_aniso >= 0)
4978 return device->force_aniso;
4979
4980 if (pCreateInfo->anisotropyEnable &&
4981 pCreateInfo->maxAnisotropy > 1.0f)
4982 return (uint32_t)pCreateInfo->maxAnisotropy;
4983
4984 return 0;
4985 }
4986
4987 static void
4988 radv_init_sampler(struct radv_device *device,
4989 struct radv_sampler *sampler,
4990 const VkSamplerCreateInfo *pCreateInfo)
4991 {
4992 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4993 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4994 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
4995 device->physical_device->rad_info.chip_class == GFX9;
4996 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4997
4998 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4999 vk_find_struct_const(pCreateInfo->pNext,
5000 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5001 if (sampler_reduction)
5002 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5003
5004 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5005 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5006 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5007 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5008 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5009 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5010 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5011 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5012 S_008F30_DISABLE_CUBE_WRAP(0) |
5013 S_008F30_COMPAT_MODE(compat_mode) |
5014 S_008F30_FILTER_MODE(filter_mode));
5015 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5016 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5017 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5018 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5019 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5020 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5021 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5022 S_008F38_MIP_POINT_PRECLAMP(0));
5023 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5024 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5025
5026 if (device->physical_device->rad_info.chip_class >= GFX10) {
5027 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5028 } else {
5029 sampler->state[2] |=
5030 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5031 S_008F38_FILTER_PREC_FIX(1) |
5032 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5033 }
5034 }
5035
5036 VkResult radv_CreateSampler(
5037 VkDevice _device,
5038 const VkSamplerCreateInfo* pCreateInfo,
5039 const VkAllocationCallbacks* pAllocator,
5040 VkSampler* pSampler)
5041 {
5042 RADV_FROM_HANDLE(radv_device, device, _device);
5043 struct radv_sampler *sampler;
5044
5045 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5046 vk_find_struct_const(pCreateInfo->pNext,
5047 SAMPLER_YCBCR_CONVERSION_INFO);
5048
5049 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5050
5051 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5052 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5053 if (!sampler)
5054 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5055
5056 radv_init_sampler(device, sampler, pCreateInfo);
5057
5058 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5059 *pSampler = radv_sampler_to_handle(sampler);
5060
5061 return VK_SUCCESS;
5062 }
5063
5064 void radv_DestroySampler(
5065 VkDevice _device,
5066 VkSampler _sampler,
5067 const VkAllocationCallbacks* pAllocator)
5068 {
5069 RADV_FROM_HANDLE(radv_device, device, _device);
5070 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5071
5072 if (!sampler)
5073 return;
5074 vk_free2(&device->alloc, pAllocator, sampler);
5075 }
5076
5077 /* vk_icd.h does not declare this function, so we declare it here to
5078 * suppress Wmissing-prototypes.
5079 */
5080 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5081 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5082
5083 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5084 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5085 {
5086 /* For the full details on loader interface versioning, see
5087 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5088 * What follows is a condensed summary, to help you navigate the large and
5089 * confusing official doc.
5090 *
5091 * - Loader interface v0 is incompatible with later versions. We don't
5092 * support it.
5093 *
5094 * - In loader interface v1:
5095 * - The first ICD entrypoint called by the loader is
5096 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5097 * entrypoint.
5098 * - The ICD must statically expose no other Vulkan symbol unless it is
5099 * linked with -Bsymbolic.
5100 * - Each dispatchable Vulkan handle created by the ICD must be
5101 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5102 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5103 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5104 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5105 * such loader-managed surfaces.
5106 *
5107 * - Loader interface v2 differs from v1 in:
5108 * - The first ICD entrypoint called by the loader is
5109 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5110 * statically expose this entrypoint.
5111 *
5112 * - Loader interface v3 differs from v2 in:
5113 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5114 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5115 * because the loader no longer does so.
5116 */
5117 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5118 return VK_SUCCESS;
5119 }
5120
5121 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5122 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5123 int *pFD)
5124 {
5125 RADV_FROM_HANDLE(radv_device, device, _device);
5126 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5127
5128 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5129
5130 /* At the moment, we support only the below handle types. */
5131 assert(pGetFdInfo->handleType ==
5132 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5133 pGetFdInfo->handleType ==
5134 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5135
5136 bool ret = radv_get_memory_fd(device, memory, pFD);
5137 if (ret == false)
5138 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5139 return VK_SUCCESS;
5140 }
5141
5142 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5143 VkExternalMemoryHandleTypeFlagBits handleType,
5144 int fd,
5145 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5146 {
5147 RADV_FROM_HANDLE(radv_device, device, _device);
5148
5149 switch (handleType) {
5150 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5151 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5152 return VK_SUCCESS;
5153
5154 default:
5155 /* The valid usage section for this function says:
5156 *
5157 * "handleType must not be one of the handle types defined as
5158 * opaque."
5159 *
5160 * So opaque handle types fall into the default "unsupported" case.
5161 */
5162 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5163 }
5164 }
5165
5166 static VkResult radv_import_opaque_fd(struct radv_device *device,
5167 int fd,
5168 uint32_t *syncobj)
5169 {
5170 uint32_t syncobj_handle = 0;
5171 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5172 if (ret != 0)
5173 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5174
5175 if (*syncobj)
5176 device->ws->destroy_syncobj(device->ws, *syncobj);
5177
5178 *syncobj = syncobj_handle;
5179 close(fd);
5180
5181 return VK_SUCCESS;
5182 }
5183
5184 static VkResult radv_import_sync_fd(struct radv_device *device,
5185 int fd,
5186 uint32_t *syncobj)
5187 {
5188 /* If we create a syncobj we do it locally so that if we have an error, we don't
5189 * leave a syncobj in an undetermined state in the fence. */
5190 uint32_t syncobj_handle = *syncobj;
5191 if (!syncobj_handle) {
5192 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5193 if (ret) {
5194 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5195 }
5196 }
5197
5198 if (fd == -1) {
5199 device->ws->signal_syncobj(device->ws, syncobj_handle);
5200 } else {
5201 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5202 if (ret != 0)
5203 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5204 }
5205
5206 *syncobj = syncobj_handle;
5207 if (fd != -1)
5208 close(fd);
5209
5210 return VK_SUCCESS;
5211 }
5212
5213 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5214 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5215 {
5216 RADV_FROM_HANDLE(radv_device, device, _device);
5217 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5218 uint32_t *syncobj_dst = NULL;
5219
5220 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5221 syncobj_dst = &sem->temp_syncobj;
5222 } else {
5223 syncobj_dst = &sem->syncobj;
5224 }
5225
5226 switch(pImportSemaphoreFdInfo->handleType) {
5227 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5228 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5229 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5230 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5231 default:
5232 unreachable("Unhandled semaphore handle type");
5233 }
5234 }
5235
5236 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5237 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5238 int *pFd)
5239 {
5240 RADV_FROM_HANDLE(radv_device, device, _device);
5241 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5242 int ret;
5243 uint32_t syncobj_handle;
5244
5245 if (sem->temp_syncobj)
5246 syncobj_handle = sem->temp_syncobj;
5247 else
5248 syncobj_handle = sem->syncobj;
5249
5250 switch(pGetFdInfo->handleType) {
5251 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5252 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5253 break;
5254 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5255 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5256 if (!ret) {
5257 if (sem->temp_syncobj) {
5258 close (sem->temp_syncobj);
5259 sem->temp_syncobj = 0;
5260 } else {
5261 device->ws->reset_syncobj(device->ws, syncobj_handle);
5262 }
5263 }
5264 break;
5265 default:
5266 unreachable("Unhandled semaphore handle type");
5267 }
5268
5269 if (ret)
5270 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5271 return VK_SUCCESS;
5272 }
5273
5274 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5275 VkPhysicalDevice physicalDevice,
5276 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5277 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5278 {
5279 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5280
5281 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5282 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5283 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5284 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5285 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5286 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5287 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5288 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5289 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5290 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5291 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5292 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5293 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5294 } else {
5295 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5296 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5297 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5298 }
5299 }
5300
5301 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5302 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5303 {
5304 RADV_FROM_HANDLE(radv_device, device, _device);
5305 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5306 uint32_t *syncobj_dst = NULL;
5307
5308
5309 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5310 syncobj_dst = &fence->temp_syncobj;
5311 } else {
5312 syncobj_dst = &fence->syncobj;
5313 }
5314
5315 switch(pImportFenceFdInfo->handleType) {
5316 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5317 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5318 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5319 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5320 default:
5321 unreachable("Unhandled fence handle type");
5322 }
5323 }
5324
5325 VkResult radv_GetFenceFdKHR(VkDevice _device,
5326 const VkFenceGetFdInfoKHR *pGetFdInfo,
5327 int *pFd)
5328 {
5329 RADV_FROM_HANDLE(radv_device, device, _device);
5330 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5331 int ret;
5332 uint32_t syncobj_handle;
5333
5334 if (fence->temp_syncobj)
5335 syncobj_handle = fence->temp_syncobj;
5336 else
5337 syncobj_handle = fence->syncobj;
5338
5339 switch(pGetFdInfo->handleType) {
5340 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5341 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5342 break;
5343 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5344 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5345 if (!ret) {
5346 if (fence->temp_syncobj) {
5347 close (fence->temp_syncobj);
5348 fence->temp_syncobj = 0;
5349 } else {
5350 device->ws->reset_syncobj(device->ws, syncobj_handle);
5351 }
5352 }
5353 break;
5354 default:
5355 unreachable("Unhandled fence handle type");
5356 }
5357
5358 if (ret)
5359 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5360 return VK_SUCCESS;
5361 }
5362
5363 void radv_GetPhysicalDeviceExternalFenceProperties(
5364 VkPhysicalDevice physicalDevice,
5365 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5366 VkExternalFenceProperties *pExternalFenceProperties)
5367 {
5368 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5369
5370 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5371 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5372 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5373 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5374 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5375 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5376 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5377 } else {
5378 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5379 pExternalFenceProperties->compatibleHandleTypes = 0;
5380 pExternalFenceProperties->externalFenceFeatures = 0;
5381 }
5382 }
5383
5384 VkResult
5385 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5386 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5387 const VkAllocationCallbacks* pAllocator,
5388 VkDebugReportCallbackEXT* pCallback)
5389 {
5390 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5391 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5392 pCreateInfo, pAllocator, &instance->alloc,
5393 pCallback);
5394 }
5395
5396 void
5397 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5398 VkDebugReportCallbackEXT _callback,
5399 const VkAllocationCallbacks* pAllocator)
5400 {
5401 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5402 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5403 _callback, pAllocator, &instance->alloc);
5404 }
5405
5406 void
5407 radv_DebugReportMessageEXT(VkInstance _instance,
5408 VkDebugReportFlagsEXT flags,
5409 VkDebugReportObjectTypeEXT objectType,
5410 uint64_t object,
5411 size_t location,
5412 int32_t messageCode,
5413 const char* pLayerPrefix,
5414 const char* pMessage)
5415 {
5416 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5417 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5418 object, location, messageCode, pLayerPrefix, pMessage);
5419 }
5420
5421 void
5422 radv_GetDeviceGroupPeerMemoryFeatures(
5423 VkDevice device,
5424 uint32_t heapIndex,
5425 uint32_t localDeviceIndex,
5426 uint32_t remoteDeviceIndex,
5427 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5428 {
5429 assert(localDeviceIndex == remoteDeviceIndex);
5430
5431 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5432 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5433 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5434 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5435 }
5436
5437 static const VkTimeDomainEXT radv_time_domains[] = {
5438 VK_TIME_DOMAIN_DEVICE_EXT,
5439 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5440 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5441 };
5442
5443 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5444 VkPhysicalDevice physicalDevice,
5445 uint32_t *pTimeDomainCount,
5446 VkTimeDomainEXT *pTimeDomains)
5447 {
5448 int d;
5449 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5450
5451 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5452 vk_outarray_append(&out, i) {
5453 *i = radv_time_domains[d];
5454 }
5455 }
5456
5457 return vk_outarray_status(&out);
5458 }
5459
5460 static uint64_t
5461 radv_clock_gettime(clockid_t clock_id)
5462 {
5463 struct timespec current;
5464 int ret;
5465
5466 ret = clock_gettime(clock_id, &current);
5467 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5468 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5469 if (ret < 0)
5470 return 0;
5471
5472 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5473 }
5474
5475 VkResult radv_GetCalibratedTimestampsEXT(
5476 VkDevice _device,
5477 uint32_t timestampCount,
5478 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5479 uint64_t *pTimestamps,
5480 uint64_t *pMaxDeviation)
5481 {
5482 RADV_FROM_HANDLE(radv_device, device, _device);
5483 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5484 int d;
5485 uint64_t begin, end;
5486 uint64_t max_clock_period = 0;
5487
5488 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5489
5490 for (d = 0; d < timestampCount; d++) {
5491 switch (pTimestampInfos[d].timeDomain) {
5492 case VK_TIME_DOMAIN_DEVICE_EXT:
5493 pTimestamps[d] = device->ws->query_value(device->ws,
5494 RADEON_TIMESTAMP);
5495 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5496 max_clock_period = MAX2(max_clock_period, device_period);
5497 break;
5498 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5499 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5500 max_clock_period = MAX2(max_clock_period, 1);
5501 break;
5502
5503 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5504 pTimestamps[d] = begin;
5505 break;
5506 default:
5507 pTimestamps[d] = 0;
5508 break;
5509 }
5510 }
5511
5512 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5513
5514 /*
5515 * The maximum deviation is the sum of the interval over which we
5516 * perform the sampling and the maximum period of any sampled
5517 * clock. That's because the maximum skew between any two sampled
5518 * clock edges is when the sampled clock with the largest period is
5519 * sampled at the end of that period but right at the beginning of the
5520 * sampling interval and some other clock is sampled right at the
5521 * begining of its sampling period and right at the end of the
5522 * sampling interval. Let's assume the GPU has the longest clock
5523 * period and that the application is sampling GPU and monotonic:
5524 *
5525 * s e
5526 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5527 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5528 *
5529 * g
5530 * 0 1 2 3
5531 * GPU -----_____-----_____-----_____-----_____
5532 *
5533 * m
5534 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5535 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5536 *
5537 * Interval <----------------->
5538 * Deviation <-------------------------->
5539 *
5540 * s = read(raw) 2
5541 * g = read(GPU) 1
5542 * m = read(monotonic) 2
5543 * e = read(raw) b
5544 *
5545 * We round the sample interval up by one tick to cover sampling error
5546 * in the interval clock
5547 */
5548
5549 uint64_t sample_interval = end - begin + 1;
5550
5551 *pMaxDeviation = sample_interval + max_clock_period;
5552
5553 return VK_SUCCESS;
5554 }
5555
5556 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5557 VkPhysicalDevice physicalDevice,
5558 VkSampleCountFlagBits samples,
5559 VkMultisamplePropertiesEXT* pMultisampleProperties)
5560 {
5561 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5562 VK_SAMPLE_COUNT_4_BIT |
5563 VK_SAMPLE_COUNT_8_BIT)) {
5564 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5565 } else {
5566 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5567 }
5568 }