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radv: Enable VK_KHR_shader_draw_parameters.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "util/strtod.h"
37
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable;
48
49 static int
50 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
51 {
52 Dl_info info;
53 struct stat st;
54 if (!dladdr(ptr, &info) || !info.dli_fname) {
55 return -1;
56 }
57 if (stat(info.dli_fname, &st)) {
58 return -1;
59 }
60 *timestamp = st.st_mtim.tv_sec;
61 return 0;
62 }
63
64 static int
65 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
66 {
67 uint32_t mesa_timestamp, llvm_timestamp;
68 uint16_t f = family;
69 memset(uuid, 0, VK_UUID_SIZE);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
72 return -1;
73
74 memcpy(uuid, &mesa_timestamp, 4);
75 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
76 memcpy((char*)uuid + 8, &f, 2);
77 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
78 return 0;
79 }
80
81 static const VkExtensionProperties instance_extensions[] = {
82 {
83 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
84 .specVersion = 25,
85 },
86 #ifdef VK_USE_PLATFORM_XCB_KHR
87 {
88 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
89 .specVersion = 6,
90 },
91 #endif
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
93 {
94 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
95 .specVersion = 6,
96 },
97 #endif
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
99 {
100 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
101 .specVersion = 5,
102 },
103 #endif
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
117 .specVersion = 68,
118 },
119 {
120 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 };
132
133 static VkResult
134 radv_extensions_register(struct radv_instance *instance,
135 struct radv_extensions *extensions,
136 const VkExtensionProperties *new_ext,
137 uint32_t num_ext)
138 {
139 size_t new_size;
140 VkExtensionProperties *new_ptr;
141
142 assert(new_ext && num_ext > 0);
143
144 if (!new_ext)
145 return VK_ERROR_INITIALIZATION_FAILED;
146
147 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
148 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
149 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
150
151 /* Old array continues to be valid, update nothing */
152 if (!new_ptr)
153 return VK_ERROR_OUT_OF_HOST_MEMORY;
154
155 memcpy(&new_ptr[extensions->num_ext], new_ext,
156 num_ext * sizeof(VkExtensionProperties));
157 extensions->ext_array = new_ptr;
158 extensions->num_ext += num_ext;
159
160 return VK_SUCCESS;
161 }
162
163 static void
164 radv_extensions_finish(struct radv_instance *instance,
165 struct radv_extensions *extensions)
166 {
167 assert(extensions);
168
169 if (!extensions)
170 radv_loge("Attemted to free invalid extension struct\n");
171
172 if (extensions->ext_array)
173 vk_free(&instance->alloc, extensions->ext_array);
174 }
175
176 static bool
177 is_extension_enabled(const VkExtensionProperties *extensions,
178 size_t num_ext,
179 const char *name)
180 {
181 assert(extensions && name);
182
183 for (uint32_t i = 0; i < num_ext; i++) {
184 if (strcmp(name, extensions[i].extensionName) == 0)
185 return true;
186 }
187
188 return false;
189 }
190
191 static VkResult
192 radv_physical_device_init(struct radv_physical_device *device,
193 struct radv_instance *instance,
194 const char *path)
195 {
196 VkResult result;
197 drmVersionPtr version;
198 int fd;
199
200 fd = open(path, O_RDWR | O_CLOEXEC);
201 if (fd < 0)
202 return VK_ERROR_INCOMPATIBLE_DRIVER;
203
204 version = drmGetVersion(fd);
205 if (!version) {
206 close(fd);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
208 "failed to get version %s: %m", path);
209 }
210
211 if (strcmp(version->name, "amdgpu")) {
212 drmFreeVersion(version);
213 close(fd);
214 return VK_ERROR_INCOMPATIBLE_DRIVER;
215 }
216 drmFreeVersion(version);
217
218 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
219 device->instance = instance;
220 assert(strlen(path) < ARRAY_SIZE(device->path));
221 strncpy(device->path, path, ARRAY_SIZE(device->path));
222
223 device->ws = radv_amdgpu_winsys_create(fd);
224 if (!device->ws) {
225 result = VK_ERROR_INCOMPATIBLE_DRIVER;
226 goto fail;
227 }
228 device->ws->query_info(device->ws, &device->rad_info);
229 result = radv_init_wsi(device);
230 if (result != VK_SUCCESS) {
231 device->ws->destroy(device->ws);
232 goto fail;
233 }
234
235 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
236 radv_finish_wsi(device);
237 device->ws->destroy(device->ws);
238 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
239 "cannot generate UUID");
240 goto fail;
241 }
242
243 result = radv_extensions_register(instance,
244 &device->extensions,
245 common_device_extensions,
246 ARRAY_SIZE(common_device_extensions));
247 if (result != VK_SUCCESS)
248 goto fail;
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251 device->name = device->rad_info.name;
252 close(fd);
253 return VK_SUCCESS;
254
255 fail:
256 close(fd);
257 return result;
258 }
259
260 static void
261 radv_physical_device_finish(struct radv_physical_device *device)
262 {
263 radv_extensions_finish(device->instance, &device->extensions);
264 radv_finish_wsi(device);
265 device->ws->destroy(device->ws);
266 }
267
268
269 static void *
270 default_alloc_func(void *pUserData, size_t size, size_t align,
271 VkSystemAllocationScope allocationScope)
272 {
273 return malloc(size);
274 }
275
276 static void *
277 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
278 size_t align, VkSystemAllocationScope allocationScope)
279 {
280 return realloc(pOriginal, size);
281 }
282
283 static void
284 default_free_func(void *pUserData, void *pMemory)
285 {
286 free(pMemory);
287 }
288
289 static const VkAllocationCallbacks default_alloc = {
290 .pUserData = NULL,
291 .pfnAllocation = default_alloc_func,
292 .pfnReallocation = default_realloc_func,
293 .pfnFree = default_free_func,
294 };
295
296 static const struct debug_control radv_debug_options[] = {
297 {"fastclears", RADV_DEBUG_FAST_CLEARS},
298 {"nodcc", RADV_DEBUG_NO_DCC},
299 {"shaders", RADV_DEBUG_DUMP_SHADERS},
300 {"nocache", RADV_DEBUG_NO_CACHE},
301 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
302 {"nohiz", RADV_DEBUG_NO_HIZ},
303 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
304 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
305 {NULL, 0}
306 };
307
308 VkResult radv_CreateInstance(
309 const VkInstanceCreateInfo* pCreateInfo,
310 const VkAllocationCallbacks* pAllocator,
311 VkInstance* pInstance)
312 {
313 struct radv_instance *instance;
314
315 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
316
317 uint32_t client_version;
318 if (pCreateInfo->pApplicationInfo &&
319 pCreateInfo->pApplicationInfo->apiVersion != 0) {
320 client_version = pCreateInfo->pApplicationInfo->apiVersion;
321 } else {
322 client_version = VK_MAKE_VERSION(1, 0, 0);
323 }
324
325 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
326 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
327 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
328 "Client requested version %d.%d.%d",
329 VK_VERSION_MAJOR(client_version),
330 VK_VERSION_MINOR(client_version),
331 VK_VERSION_PATCH(client_version));
332 }
333
334 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
335 if (!is_extension_enabled(instance_extensions,
336 ARRAY_SIZE(instance_extensions),
337 pCreateInfo->ppEnabledExtensionNames[i]))
338 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
339 }
340
341 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
343 if (!instance)
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
345
346 memset(instance, 0, sizeof(*instance));
347
348 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
349
350 if (pAllocator)
351 instance->alloc = *pAllocator;
352 else
353 instance->alloc = default_alloc;
354
355 instance->apiVersion = client_version;
356 instance->physicalDeviceCount = -1;
357
358 _mesa_locale_init();
359
360 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
361
362 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
363 radv_debug_options);
364
365 *pInstance = radv_instance_to_handle(instance);
366
367 return VK_SUCCESS;
368 }
369
370 void radv_DestroyInstance(
371 VkInstance _instance,
372 const VkAllocationCallbacks* pAllocator)
373 {
374 RADV_FROM_HANDLE(radv_instance, instance, _instance);
375
376 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
377 radv_physical_device_finish(instance->physicalDevices + i);
378 }
379
380 VG(VALGRIND_DESTROY_MEMPOOL(instance));
381
382 _mesa_locale_fini();
383
384 vk_free(&instance->alloc, instance);
385 }
386
387 VkResult radv_EnumeratePhysicalDevices(
388 VkInstance _instance,
389 uint32_t* pPhysicalDeviceCount,
390 VkPhysicalDevice* pPhysicalDevices)
391 {
392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
393 VkResult result;
394
395 if (instance->physicalDeviceCount < 0) {
396 char path[20];
397 instance->physicalDeviceCount = 0;
398 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
399 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
400 result = radv_physical_device_init(instance->physicalDevices +
401 instance->physicalDeviceCount,
402 instance, path);
403 if (result == VK_SUCCESS)
404 ++instance->physicalDeviceCount;
405 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
406 return result;
407 }
408 }
409
410 if (!pPhysicalDevices) {
411 *pPhysicalDeviceCount = instance->physicalDeviceCount;
412 } else {
413 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
414 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
415 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
416 }
417
418 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
419 : VK_SUCCESS;
420 }
421
422 void radv_GetPhysicalDeviceFeatures(
423 VkPhysicalDevice physicalDevice,
424 VkPhysicalDeviceFeatures* pFeatures)
425 {
426 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
427
428 memset(pFeatures, 0, sizeof(*pFeatures));
429
430 *pFeatures = (VkPhysicalDeviceFeatures) {
431 .robustBufferAccess = true,
432 .fullDrawIndexUint32 = true,
433 .imageCubeArray = true,
434 .independentBlend = true,
435 .geometryShader = true,
436 .tessellationShader = false,
437 .sampleRateShading = false,
438 .dualSrcBlend = true,
439 .logicOp = true,
440 .multiDrawIndirect = true,
441 .drawIndirectFirstInstance = true,
442 .depthClamp = true,
443 .depthBiasClamp = true,
444 .fillModeNonSolid = true,
445 .depthBounds = true,
446 .wideLines = true,
447 .largePoints = true,
448 .alphaToOne = true,
449 .multiViewport = true,
450 .samplerAnisotropy = true,
451 .textureCompressionETC2 = false,
452 .textureCompressionASTC_LDR = false,
453 .textureCompressionBC = true,
454 .occlusionQueryPrecise = true,
455 .pipelineStatisticsQuery = false,
456 .vertexPipelineStoresAndAtomics = true,
457 .fragmentStoresAndAtomics = true,
458 .shaderTessellationAndGeometryPointSize = true,
459 .shaderImageGatherExtended = true,
460 .shaderStorageImageExtendedFormats = true,
461 .shaderStorageImageMultisample = false,
462 .shaderUniformBufferArrayDynamicIndexing = true,
463 .shaderSampledImageArrayDynamicIndexing = true,
464 .shaderStorageBufferArrayDynamicIndexing = true,
465 .shaderStorageImageArrayDynamicIndexing = true,
466 .shaderStorageImageReadWithoutFormat = false,
467 .shaderStorageImageWriteWithoutFormat = false,
468 .shaderClipDistance = true,
469 .shaderCullDistance = true,
470 .shaderFloat64 = true,
471 .shaderInt64 = false,
472 .shaderInt16 = false,
473 .alphaToOne = true,
474 .variableMultisampleRate = false,
475 .inheritedQueries = false,
476 };
477 }
478
479 void radv_GetPhysicalDeviceFeatures2KHR(
480 VkPhysicalDevice physicalDevice,
481 VkPhysicalDeviceFeatures2KHR *pFeatures)
482 {
483 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
484 }
485
486 void radv_GetPhysicalDeviceProperties(
487 VkPhysicalDevice physicalDevice,
488 VkPhysicalDeviceProperties* pProperties)
489 {
490 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
491 VkSampleCountFlags sample_counts = 0xf;
492 VkPhysicalDeviceLimits limits = {
493 .maxImageDimension1D = (1 << 14),
494 .maxImageDimension2D = (1 << 14),
495 .maxImageDimension3D = (1 << 11),
496 .maxImageDimensionCube = (1 << 14),
497 .maxImageArrayLayers = (1 << 11),
498 .maxTexelBufferElements = 128 * 1024 * 1024,
499 .maxUniformBufferRange = UINT32_MAX,
500 .maxStorageBufferRange = UINT32_MAX,
501 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
502 .maxMemoryAllocationCount = UINT32_MAX,
503 .maxSamplerAllocationCount = 64 * 1024,
504 .bufferImageGranularity = 64, /* A cache line */
505 .sparseAddressSpaceSize = 0,
506 .maxBoundDescriptorSets = MAX_SETS,
507 .maxPerStageDescriptorSamplers = 64,
508 .maxPerStageDescriptorUniformBuffers = 64,
509 .maxPerStageDescriptorStorageBuffers = 64,
510 .maxPerStageDescriptorSampledImages = 64,
511 .maxPerStageDescriptorStorageImages = 64,
512 .maxPerStageDescriptorInputAttachments = 64,
513 .maxPerStageResources = 128,
514 .maxDescriptorSetSamplers = 256,
515 .maxDescriptorSetUniformBuffers = 256,
516 .maxDescriptorSetUniformBuffersDynamic = 256,
517 .maxDescriptorSetStorageBuffers = 256,
518 .maxDescriptorSetStorageBuffersDynamic = 256,
519 .maxDescriptorSetSampledImages = 256,
520 .maxDescriptorSetStorageImages = 256,
521 .maxDescriptorSetInputAttachments = 256,
522 .maxVertexInputAttributes = 32,
523 .maxVertexInputBindings = 32,
524 .maxVertexInputAttributeOffset = 2047,
525 .maxVertexInputBindingStride = 2048,
526 .maxVertexOutputComponents = 128,
527 .maxTessellationGenerationLevel = 0,
528 .maxTessellationPatchSize = 0,
529 .maxTessellationControlPerVertexInputComponents = 0,
530 .maxTessellationControlPerVertexOutputComponents = 0,
531 .maxTessellationControlPerPatchOutputComponents = 0,
532 .maxTessellationControlTotalOutputComponents = 0,
533 .maxTessellationEvaluationInputComponents = 0,
534 .maxTessellationEvaluationOutputComponents = 0,
535 .maxGeometryShaderInvocations = 32,
536 .maxGeometryInputComponents = 64,
537 .maxGeometryOutputComponents = 128,
538 .maxGeometryOutputVertices = 256,
539 .maxGeometryTotalOutputComponents = 1024,
540 .maxFragmentInputComponents = 128,
541 .maxFragmentOutputAttachments = 8,
542 .maxFragmentDualSrcAttachments = 1,
543 .maxFragmentCombinedOutputResources = 8,
544 .maxComputeSharedMemorySize = 32768,
545 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
546 .maxComputeWorkGroupInvocations = 2048,
547 .maxComputeWorkGroupSize = {
548 2048,
549 2048,
550 2048
551 },
552 .subPixelPrecisionBits = 4 /* FIXME */,
553 .subTexelPrecisionBits = 4 /* FIXME */,
554 .mipmapPrecisionBits = 4 /* FIXME */,
555 .maxDrawIndexedIndexValue = UINT32_MAX,
556 .maxDrawIndirectCount = UINT32_MAX,
557 .maxSamplerLodBias = 16,
558 .maxSamplerAnisotropy = 16,
559 .maxViewports = MAX_VIEWPORTS,
560 .maxViewportDimensions = { (1 << 14), (1 << 14) },
561 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
562 .viewportSubPixelBits = 13, /* We take a float? */
563 .minMemoryMapAlignment = 4096, /* A page */
564 .minTexelBufferOffsetAlignment = 1,
565 .minUniformBufferOffsetAlignment = 4,
566 .minStorageBufferOffsetAlignment = 4,
567 .minTexelOffset = -32,
568 .maxTexelOffset = 31,
569 .minTexelGatherOffset = -32,
570 .maxTexelGatherOffset = 31,
571 .minInterpolationOffset = -2,
572 .maxInterpolationOffset = 2,
573 .subPixelInterpolationOffsetBits = 8,
574 .maxFramebufferWidth = (1 << 14),
575 .maxFramebufferHeight = (1 << 14),
576 .maxFramebufferLayers = (1 << 10),
577 .framebufferColorSampleCounts = sample_counts,
578 .framebufferDepthSampleCounts = sample_counts,
579 .framebufferStencilSampleCounts = sample_counts,
580 .framebufferNoAttachmentsSampleCounts = sample_counts,
581 .maxColorAttachments = MAX_RTS,
582 .sampledImageColorSampleCounts = sample_counts,
583 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
584 .sampledImageDepthSampleCounts = sample_counts,
585 .sampledImageStencilSampleCounts = sample_counts,
586 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
587 .maxSampleMaskWords = 1,
588 .timestampComputeAndGraphics = false,
589 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
590 .maxClipDistances = 8,
591 .maxCullDistances = 8,
592 .maxCombinedClipAndCullDistances = 8,
593 .discreteQueuePriorities = 1,
594 .pointSizeRange = { 0.125, 255.875 },
595 .lineWidthRange = { 0.0, 7.9921875 },
596 .pointSizeGranularity = (1.0 / 8.0),
597 .lineWidthGranularity = (1.0 / 128.0),
598 .strictLines = false, /* FINISHME */
599 .standardSampleLocations = true,
600 .optimalBufferCopyOffsetAlignment = 128,
601 .optimalBufferCopyRowPitchAlignment = 128,
602 .nonCoherentAtomSize = 64,
603 };
604
605 *pProperties = (VkPhysicalDeviceProperties) {
606 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
607 .driverVersion = 1,
608 .vendorID = 0x1002,
609 .deviceID = pdevice->rad_info.pci_id,
610 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
611 .limits = limits,
612 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
613 };
614
615 strcpy(pProperties->deviceName, pdevice->name);
616 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
617 }
618
619 void radv_GetPhysicalDeviceProperties2KHR(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceProperties2KHR *pProperties)
622 {
623 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
624 }
625
626 void radv_GetPhysicalDeviceQueueFamilyProperties(
627 VkPhysicalDevice physicalDevice,
628 uint32_t* pCount,
629 VkQueueFamilyProperties* pQueueFamilyProperties)
630 {
631 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
632 int num_queue_families = 1;
633 int idx;
634 if (pdevice->rad_info.compute_rings > 0 &&
635 pdevice->rad_info.chip_class >= CIK &&
636 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
637 num_queue_families++;
638
639 if (pQueueFamilyProperties == NULL) {
640 *pCount = num_queue_families;
641 return;
642 }
643
644 if (!*pCount)
645 return;
646
647 idx = 0;
648 if (*pCount >= 1) {
649 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
650 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
651 VK_QUEUE_COMPUTE_BIT |
652 VK_QUEUE_TRANSFER_BIT,
653 .queueCount = 1,
654 .timestampValidBits = 64,
655 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
656 };
657 idx++;
658 }
659
660 if (pdevice->rad_info.compute_rings > 0 &&
661 pdevice->rad_info.chip_class >= CIK &&
662 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
663 if (*pCount > idx) {
664 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
665 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
666 .queueCount = pdevice->rad_info.compute_rings,
667 .timestampValidBits = 64,
668 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
669 };
670 idx++;
671 }
672 }
673 *pCount = idx;
674 }
675
676 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
677 VkPhysicalDevice physicalDevice,
678 uint32_t* pCount,
679 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
680 {
681 return radv_GetPhysicalDeviceQueueFamilyProperties(physicalDevice,
682 pCount,
683 &pQueueFamilyProperties->queueFamilyProperties);
684 }
685
686 void radv_GetPhysicalDeviceMemoryProperties(
687 VkPhysicalDevice physicalDevice,
688 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
689 {
690 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
691
692 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
693
694 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
695 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
696 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
697 .heapIndex = RADV_MEM_HEAP_VRAM,
698 };
699 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
700 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
701 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
702 .heapIndex = RADV_MEM_HEAP_GTT,
703 };
704 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
705 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
706 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
707 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
708 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
709 };
710 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
711 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
712 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
713 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
714 .heapIndex = RADV_MEM_HEAP_GTT,
715 };
716
717 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
718
719 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
720 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
721 .size = physical_device->rad_info.vram_size -
722 physical_device->rad_info.visible_vram_size,
723 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
724 };
725 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
726 .size = physical_device->rad_info.visible_vram_size,
727 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
728 };
729 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
730 .size = physical_device->rad_info.gart_size,
731 .flags = 0,
732 };
733 }
734
735 void radv_GetPhysicalDeviceMemoryProperties2KHR(
736 VkPhysicalDevice physicalDevice,
737 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
738 {
739 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
740 &pMemoryProperties->memoryProperties);
741 }
742
743 static int
744 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
745 int queue_family_index, int idx)
746 {
747 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
748 queue->device = device;
749 queue->queue_family_index = queue_family_index;
750 queue->queue_idx = idx;
751
752 queue->hw_ctx = device->ws->ctx_create(device->ws);
753 if (!queue->hw_ctx)
754 return VK_ERROR_OUT_OF_HOST_MEMORY;
755
756 return VK_SUCCESS;
757 }
758
759 static void
760 radv_queue_finish(struct radv_queue *queue)
761 {
762 if (queue->hw_ctx)
763 queue->device->ws->ctx_destroy(queue->hw_ctx);
764
765 if (queue->preamble_cs)
766 queue->device->ws->cs_destroy(queue->preamble_cs);
767 if (queue->descriptor_bo)
768 queue->device->ws->buffer_destroy(queue->descriptor_bo);
769 if (queue->scratch_bo)
770 queue->device->ws->buffer_destroy(queue->scratch_bo);
771 if (queue->esgs_ring_bo)
772 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
773 if (queue->gsvs_ring_bo)
774 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
775 if (queue->compute_scratch_bo)
776 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
777 }
778
779 static void
780 radv_device_init_gs_info(struct radv_device *device)
781 {
782 switch (device->physical_device->rad_info.family) {
783 case CHIP_OLAND:
784 case CHIP_HAINAN:
785 case CHIP_KAVERI:
786 case CHIP_KABINI:
787 case CHIP_MULLINS:
788 case CHIP_ICELAND:
789 case CHIP_CARRIZO:
790 case CHIP_STONEY:
791 device->gs_table_depth = 16;
792 return;
793 case CHIP_TAHITI:
794 case CHIP_PITCAIRN:
795 case CHIP_VERDE:
796 case CHIP_BONAIRE:
797 case CHIP_HAWAII:
798 case CHIP_TONGA:
799 case CHIP_FIJI:
800 case CHIP_POLARIS10:
801 case CHIP_POLARIS11:
802 device->gs_table_depth = 32;
803 return;
804 default:
805 unreachable("unknown GPU");
806 }
807 }
808
809 VkResult radv_CreateDevice(
810 VkPhysicalDevice physicalDevice,
811 const VkDeviceCreateInfo* pCreateInfo,
812 const VkAllocationCallbacks* pAllocator,
813 VkDevice* pDevice)
814 {
815 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
816 VkResult result;
817 struct radv_device *device;
818
819 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
820 if (!is_extension_enabled(physical_device->extensions.ext_array,
821 physical_device->extensions.num_ext,
822 pCreateInfo->ppEnabledExtensionNames[i]))
823 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
824 }
825
826 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
827 sizeof(*device), 8,
828 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
829 if (!device)
830 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
831
832 memset(device, 0, sizeof(*device));
833
834 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
835 device->instance = physical_device->instance;
836 device->physical_device = physical_device;
837
838 device->debug_flags = device->instance->debug_flags;
839
840 device->ws = physical_device->ws;
841 if (pAllocator)
842 device->alloc = *pAllocator;
843 else
844 device->alloc = physical_device->instance->alloc;
845
846 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
847 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
848 uint32_t qfi = queue_create->queueFamilyIndex;
849
850 device->queues[qfi] = vk_alloc(&device->alloc,
851 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
852 if (!device->queues[qfi]) {
853 result = VK_ERROR_OUT_OF_HOST_MEMORY;
854 goto fail;
855 }
856
857 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
858
859 device->queue_count[qfi] = queue_create->queueCount;
860
861 for (unsigned q = 0; q < queue_create->queueCount; q++) {
862 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
863 if (result != VK_SUCCESS)
864 goto fail;
865 }
866 }
867
868 #if HAVE_LLVM < 0x0400
869 device->llvm_supports_spill = false;
870 #else
871 device->llvm_supports_spill = true;
872 #endif
873
874 /* The maximum number of scratch waves. Scratch space isn't divided
875 * evenly between CUs. The number is only a function of the number of CUs.
876 * We can decrease the constant to decrease the scratch buffer size.
877 *
878 * sctx->scratch_waves must be >= the maximum posible size of
879 * 1 threadgroup, so that the hw doesn't hang from being unable
880 * to start any.
881 *
882 * The recommended value is 4 per CU at most. Higher numbers don't
883 * bring much benefit, but they still occupy chip resources (think
884 * async compute). I've seen ~2% performance difference between 4 and 32.
885 */
886 uint32_t max_threads_per_block = 2048;
887 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
888 max_threads_per_block / 64);
889
890 radv_device_init_gs_info(device);
891
892 result = radv_device_init_meta(device);
893 if (result != VK_SUCCESS)
894 goto fail;
895
896 radv_device_init_msaa(device);
897
898 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
899 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
900 switch (family) {
901 case RADV_QUEUE_GENERAL:
902 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
903 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
904 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
905 break;
906 case RADV_QUEUE_COMPUTE:
907 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
908 radeon_emit(device->empty_cs[family], 0);
909 break;
910 }
911 device->ws->cs_finalize(device->empty_cs[family]);
912 }
913
914 if (getenv("RADV_TRACE_FILE")) {
915 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
916 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
917 if (!device->trace_bo)
918 goto fail;
919
920 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
921 if (!device->trace_id_ptr)
922 goto fail;
923 }
924
925 *pDevice = radv_device_to_handle(device);
926 return VK_SUCCESS;
927
928 fail:
929 if (device->trace_bo)
930 device->ws->buffer_destroy(device->trace_bo);
931
932 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
933 for (unsigned q = 0; q < device->queue_count[i]; q++)
934 radv_queue_finish(&device->queues[i][q]);
935 if (device->queue_count[i])
936 vk_free(&device->alloc, device->queues[i]);
937 }
938
939 vk_free(&device->alloc, device);
940 return result;
941 }
942
943 void radv_DestroyDevice(
944 VkDevice _device,
945 const VkAllocationCallbacks* pAllocator)
946 {
947 RADV_FROM_HANDLE(radv_device, device, _device);
948
949 if (device->trace_bo)
950 device->ws->buffer_destroy(device->trace_bo);
951
952 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
953 for (unsigned q = 0; q < device->queue_count[i]; q++)
954 radv_queue_finish(&device->queues[i][q]);
955 if (device->queue_count[i])
956 vk_free(&device->alloc, device->queues[i]);
957 }
958 radv_device_finish_meta(device);
959
960 vk_free(&device->alloc, device);
961 }
962
963 VkResult radv_EnumerateInstanceExtensionProperties(
964 const char* pLayerName,
965 uint32_t* pPropertyCount,
966 VkExtensionProperties* pProperties)
967 {
968 if (pProperties == NULL) {
969 *pPropertyCount = ARRAY_SIZE(instance_extensions);
970 return VK_SUCCESS;
971 }
972
973 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
974 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
975
976 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
977 return VK_INCOMPLETE;
978
979 return VK_SUCCESS;
980 }
981
982 VkResult radv_EnumerateDeviceExtensionProperties(
983 VkPhysicalDevice physicalDevice,
984 const char* pLayerName,
985 uint32_t* pPropertyCount,
986 VkExtensionProperties* pProperties)
987 {
988 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
989
990 if (pProperties == NULL) {
991 *pPropertyCount = pdevice->extensions.num_ext;
992 return VK_SUCCESS;
993 }
994
995 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
996 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
997
998 if (*pPropertyCount < pdevice->extensions.num_ext)
999 return VK_INCOMPLETE;
1000
1001 return VK_SUCCESS;
1002 }
1003
1004 VkResult radv_EnumerateInstanceLayerProperties(
1005 uint32_t* pPropertyCount,
1006 VkLayerProperties* pProperties)
1007 {
1008 if (pProperties == NULL) {
1009 *pPropertyCount = 0;
1010 return VK_SUCCESS;
1011 }
1012
1013 /* None supported at this time */
1014 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1015 }
1016
1017 VkResult radv_EnumerateDeviceLayerProperties(
1018 VkPhysicalDevice physicalDevice,
1019 uint32_t* pPropertyCount,
1020 VkLayerProperties* pProperties)
1021 {
1022 if (pProperties == NULL) {
1023 *pPropertyCount = 0;
1024 return VK_SUCCESS;
1025 }
1026
1027 /* None supported at this time */
1028 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1029 }
1030
1031 void radv_GetDeviceQueue(
1032 VkDevice _device,
1033 uint32_t queueFamilyIndex,
1034 uint32_t queueIndex,
1035 VkQueue* pQueue)
1036 {
1037 RADV_FROM_HANDLE(radv_device, device, _device);
1038
1039 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1040 }
1041
1042 static void radv_dump_trace(struct radv_device *device,
1043 struct radeon_winsys_cs *cs)
1044 {
1045 const char *filename = getenv("RADV_TRACE_FILE");
1046 FILE *f = fopen(filename, "w");
1047 if (!f) {
1048 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1049 return;
1050 }
1051
1052 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1053 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1054 fclose(f);
1055 }
1056
1057 static void
1058 fill_geom_rings(struct radv_queue *queue,
1059 uint32_t *map,
1060 uint32_t esgs_ring_size,
1061 struct radeon_winsys_bo *esgs_ring_bo,
1062 uint32_t gsvs_ring_size,
1063 struct radeon_winsys_bo *gsvs_ring_bo)
1064 {
1065 uint64_t esgs_va = 0, gsvs_va = 0;
1066 uint32_t *desc = &map[4];
1067
1068 if (esgs_ring_bo)
1069 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1070 if (gsvs_ring_bo)
1071 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1072
1073 /* stride 0, num records - size, add tid, swizzle, elsize4,
1074 index stride 64 */
1075 desc[0] = esgs_va;
1076 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1077 S_008F04_STRIDE(0) |
1078 S_008F04_SWIZZLE_ENABLE(true);
1079 desc[2] = esgs_ring_size;
1080 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1081 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1082 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1083 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1084 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1085 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1086 S_008F0C_ELEMENT_SIZE(1) |
1087 S_008F0C_INDEX_STRIDE(3) |
1088 S_008F0C_ADD_TID_ENABLE(true);
1089
1090 desc += 4;
1091 /* GS entry for ES->GS ring */
1092 /* stride 0, num records - size, elsize0,
1093 index stride 0 */
1094 desc[0] = esgs_va;
1095 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1096 S_008F04_STRIDE(0) |
1097 S_008F04_SWIZZLE_ENABLE(false);
1098 desc[2] = esgs_ring_size;
1099 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1100 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1101 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1102 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1103 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1104 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1105 S_008F0C_ELEMENT_SIZE(0) |
1106 S_008F0C_INDEX_STRIDE(0) |
1107 S_008F0C_ADD_TID_ENABLE(false);
1108
1109 desc += 4;
1110 /* VS entry for GS->VS ring */
1111 /* stride 0, num records - size, elsize0,
1112 index stride 0 */
1113 desc[0] = gsvs_va;
1114 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1115 S_008F04_STRIDE(0) |
1116 S_008F04_SWIZZLE_ENABLE(false);
1117 desc[2] = gsvs_ring_size;
1118 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1119 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1120 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1121 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1122 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1123 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1124 S_008F0C_ELEMENT_SIZE(0) |
1125 S_008F0C_INDEX_STRIDE(0) |
1126 S_008F0C_ADD_TID_ENABLE(false);
1127 desc += 4;
1128
1129 /* stride gsvs_itemsize, num records 64
1130 elsize 4, index stride 16 */
1131 /* shader will patch stride and desc[2] */
1132 desc[0] = gsvs_va;
1133 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1134 S_008F04_STRIDE(0) |
1135 S_008F04_SWIZZLE_ENABLE(true);
1136 desc[2] = 0;
1137 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1138 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1139 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1140 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1141 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1143 S_008F0C_ELEMENT_SIZE(1) |
1144 S_008F0C_INDEX_STRIDE(1) |
1145 S_008F0C_ADD_TID_ENABLE(true);
1146 }
1147
1148 static VkResult
1149 radv_get_preamble_cs(struct radv_queue *queue,
1150 uint32_t scratch_size,
1151 uint32_t compute_scratch_size,
1152 uint32_t esgs_ring_size,
1153 uint32_t gsvs_ring_size,
1154 struct radeon_winsys_cs **preamble_cs)
1155 {
1156 struct radeon_winsys_bo *scratch_bo = NULL;
1157 struct radeon_winsys_bo *descriptor_bo = NULL;
1158 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1159 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1160 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1161 struct radeon_winsys_cs *cs = NULL;
1162
1163 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size) {
1164 *preamble_cs = NULL;
1165 return VK_SUCCESS;
1166 }
1167
1168 if (scratch_size <= queue->scratch_size &&
1169 compute_scratch_size <= queue->compute_scratch_size &&
1170 esgs_ring_size <= queue->esgs_ring_size &&
1171 gsvs_ring_size <= queue->gsvs_ring_size) {
1172 *preamble_cs = queue->preamble_cs;
1173 return VK_SUCCESS;
1174 }
1175
1176 if (scratch_size > queue->scratch_size) {
1177 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1178 scratch_size,
1179 4096,
1180 RADEON_DOMAIN_VRAM,
1181 RADEON_FLAG_NO_CPU_ACCESS);
1182 if (!scratch_bo)
1183 goto fail;
1184 } else
1185 scratch_bo = queue->scratch_bo;
1186
1187 if (compute_scratch_size > queue->compute_scratch_size) {
1188 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1189 compute_scratch_size,
1190 4096,
1191 RADEON_DOMAIN_VRAM,
1192 RADEON_FLAG_NO_CPU_ACCESS);
1193 if (!compute_scratch_bo)
1194 goto fail;
1195
1196 } else
1197 compute_scratch_bo = queue->compute_scratch_bo;
1198
1199 if (esgs_ring_size > queue->esgs_ring_size) {
1200 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1201 esgs_ring_size,
1202 4096,
1203 RADEON_DOMAIN_VRAM,
1204 RADEON_FLAG_NO_CPU_ACCESS);
1205 if (!esgs_ring_bo)
1206 goto fail;
1207 } else {
1208 esgs_ring_bo = queue->esgs_ring_bo;
1209 esgs_ring_size = queue->esgs_ring_size;
1210 }
1211
1212 if (gsvs_ring_size > queue->gsvs_ring_size) {
1213 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1214 gsvs_ring_size,
1215 4096,
1216 RADEON_DOMAIN_VRAM,
1217 RADEON_FLAG_NO_CPU_ACCESS);
1218 if (!gsvs_ring_bo)
1219 goto fail;
1220 } else {
1221 gsvs_ring_bo = queue->gsvs_ring_bo;
1222 gsvs_ring_size = queue->gsvs_ring_size;
1223 }
1224
1225 if (scratch_bo != queue->scratch_bo ||
1226 esgs_ring_bo != queue->esgs_ring_bo ||
1227 gsvs_ring_bo != queue->gsvs_ring_bo) {
1228 uint32_t size = 0;
1229 if (gsvs_ring_bo || esgs_ring_bo)
1230 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1231 else if (scratch_bo)
1232 size = 8; /* 2 dword */
1233
1234 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1235 size,
1236 4096,
1237 RADEON_DOMAIN_VRAM,
1238 RADEON_FLAG_CPU_ACCESS);
1239 if (!descriptor_bo)
1240 goto fail;
1241 } else
1242 descriptor_bo = queue->descriptor_bo;
1243
1244 cs = queue->device->ws->cs_create(queue->device->ws,
1245 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1246 if (!cs)
1247 goto fail;
1248
1249
1250 if (scratch_bo)
1251 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1252
1253 if (esgs_ring_bo)
1254 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1255
1256 if (gsvs_ring_bo)
1257 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1258
1259 if (descriptor_bo)
1260 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1261
1262 if (descriptor_bo != queue->descriptor_bo) {
1263 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1264
1265 if (scratch_bo) {
1266 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1267 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1268 S_008F04_SWIZZLE_ENABLE(1);
1269 map[0] = scratch_va;
1270 map[1] = rsrc1;
1271 }
1272
1273 if (esgs_ring_bo || gsvs_ring_bo)
1274 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1275
1276 queue->device->ws->buffer_unmap(descriptor_bo);
1277 }
1278
1279 if (esgs_ring_bo || gsvs_ring_bo) {
1280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1281 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1282 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1283 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1284
1285 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1286 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1287 radeon_emit(cs, esgs_ring_size >> 8);
1288 radeon_emit(cs, gsvs_ring_size >> 8);
1289 } else {
1290 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1291 radeon_emit(cs, esgs_ring_size >> 8);
1292 radeon_emit(cs, gsvs_ring_size >> 8);
1293 }
1294 }
1295
1296 if (descriptor_bo) {
1297 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1298 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1299 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1300 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1301 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1302 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1303
1304 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1305
1306 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1307 radeon_set_sh_reg_seq(cs, regs[i], 2);
1308 radeon_emit(cs, va);
1309 radeon_emit(cs, va >> 32);
1310 }
1311 }
1312
1313 if (compute_scratch_bo) {
1314 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1315 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1316 S_008F04_SWIZZLE_ENABLE(1);
1317
1318 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1319
1320 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1321 radeon_emit(cs, scratch_va);
1322 radeon_emit(cs, rsrc1);
1323 }
1324
1325 if (!queue->device->ws->cs_finalize(cs))
1326 goto fail;
1327
1328 if (queue->preamble_cs)
1329 queue->device->ws->cs_destroy(queue->preamble_cs);
1330
1331 queue->preamble_cs = cs;
1332
1333 if (scratch_bo != queue->scratch_bo) {
1334 if (queue->scratch_bo)
1335 queue->device->ws->buffer_destroy(queue->scratch_bo);
1336 queue->scratch_bo = scratch_bo;
1337 queue->scratch_size = scratch_size;
1338 }
1339
1340 if (compute_scratch_bo != queue->compute_scratch_bo) {
1341 if (queue->compute_scratch_bo)
1342 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1343 queue->compute_scratch_bo = compute_scratch_bo;
1344 queue->compute_scratch_size = compute_scratch_size;
1345 }
1346
1347 if (esgs_ring_bo != queue->esgs_ring_bo) {
1348 if (queue->esgs_ring_bo)
1349 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1350 queue->esgs_ring_bo = esgs_ring_bo;
1351 queue->esgs_ring_size = esgs_ring_size;
1352 }
1353
1354 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1355 if (queue->gsvs_ring_bo)
1356 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1357 queue->gsvs_ring_bo = gsvs_ring_bo;
1358 queue->gsvs_ring_size = gsvs_ring_size;
1359 }
1360
1361 if (descriptor_bo != queue->descriptor_bo) {
1362 if (queue->descriptor_bo)
1363 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1364
1365 queue->descriptor_bo = descriptor_bo;
1366 }
1367
1368 *preamble_cs = cs;
1369 return VK_SUCCESS;
1370 fail:
1371 if (cs)
1372 queue->device->ws->cs_destroy(cs);
1373 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1374 queue->device->ws->buffer_destroy(descriptor_bo);
1375 if (scratch_bo && scratch_bo != queue->scratch_bo)
1376 queue->device->ws->buffer_destroy(scratch_bo);
1377 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1378 queue->device->ws->buffer_destroy(compute_scratch_bo);
1379 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1380 queue->device->ws->buffer_destroy(esgs_ring_bo);
1381 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1382 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1383 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1384 }
1385
1386 VkResult radv_QueueSubmit(
1387 VkQueue _queue,
1388 uint32_t submitCount,
1389 const VkSubmitInfo* pSubmits,
1390 VkFence _fence)
1391 {
1392 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1393 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1394 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1395 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1396 int ret;
1397 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1398 uint32_t scratch_size = 0;
1399 uint32_t compute_scratch_size = 0;
1400 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1401 struct radeon_winsys_cs *preamble_cs = NULL;
1402 VkResult result;
1403
1404 /* Do this first so failing to allocate scratch buffers can't result in
1405 * partially executed submissions. */
1406 for (uint32_t i = 0; i < submitCount; i++) {
1407 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1408 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1409 pSubmits[i].pCommandBuffers[j]);
1410
1411 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1412 compute_scratch_size = MAX2(compute_scratch_size,
1413 cmd_buffer->compute_scratch_size_needed);
1414 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1415 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1416 }
1417 }
1418
1419 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size, esgs_ring_size, gsvs_ring_size, &preamble_cs);
1420 if (result != VK_SUCCESS)
1421 return result;
1422
1423 for (uint32_t i = 0; i < submitCount; i++) {
1424 struct radeon_winsys_cs **cs_array;
1425 bool can_patch = true;
1426 uint32_t advance;
1427
1428 if (!pSubmits[i].commandBufferCount)
1429 continue;
1430
1431 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1432 pSubmits[i].commandBufferCount);
1433
1434 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1435 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1436 pSubmits[i].pCommandBuffers[j]);
1437 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1438
1439 cs_array[j] = cmd_buffer->cs;
1440 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1441 can_patch = false;
1442 }
1443
1444 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1445 advance = MIN2(max_cs_submission,
1446 pSubmits[i].commandBufferCount - j);
1447 bool b = j == 0;
1448 bool e = j + advance == pSubmits[i].commandBufferCount;
1449
1450 if (queue->device->trace_bo)
1451 *queue->device->trace_id_ptr = 0;
1452
1453 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1454 advance, preamble_cs,
1455 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1456 b ? pSubmits[i].waitSemaphoreCount : 0,
1457 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1458 e ? pSubmits[i].signalSemaphoreCount : 0,
1459 can_patch, base_fence);
1460
1461 if (ret) {
1462 radv_loge("failed to submit CS %d\n", i);
1463 abort();
1464 }
1465 if (queue->device->trace_bo) {
1466 bool success = queue->device->ws->ctx_wait_idle(
1467 queue->hw_ctx,
1468 radv_queue_family_to_ring(
1469 queue->queue_family_index),
1470 queue->queue_idx);
1471
1472 if (!success) { /* Hang */
1473 radv_dump_trace(queue->device, cs_array[j]);
1474 abort();
1475 }
1476 }
1477 }
1478 free(cs_array);
1479 }
1480
1481 if (fence) {
1482 if (!submitCount)
1483 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1484 &queue->device->empty_cs[queue->queue_family_index],
1485 1, NULL, NULL, 0, NULL, 0,
1486 false, base_fence);
1487
1488 fence->submitted = true;
1489 }
1490
1491 return VK_SUCCESS;
1492 }
1493
1494 VkResult radv_QueueWaitIdle(
1495 VkQueue _queue)
1496 {
1497 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1498
1499 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1500 radv_queue_family_to_ring(queue->queue_family_index),
1501 queue->queue_idx);
1502 return VK_SUCCESS;
1503 }
1504
1505 VkResult radv_DeviceWaitIdle(
1506 VkDevice _device)
1507 {
1508 RADV_FROM_HANDLE(radv_device, device, _device);
1509
1510 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1511 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1512 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1513 }
1514 }
1515 return VK_SUCCESS;
1516 }
1517
1518 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1519 VkInstance instance,
1520 const char* pName)
1521 {
1522 return radv_lookup_entrypoint(pName);
1523 }
1524
1525 /* The loader wants us to expose a second GetInstanceProcAddr function
1526 * to work around certain LD_PRELOAD issues seen in apps.
1527 */
1528 PUBLIC
1529 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1530 VkInstance instance,
1531 const char* pName);
1532
1533 PUBLIC
1534 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1535 VkInstance instance,
1536 const char* pName)
1537 {
1538 return radv_GetInstanceProcAddr(instance, pName);
1539 }
1540
1541 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1542 VkDevice device,
1543 const char* pName)
1544 {
1545 return radv_lookup_entrypoint(pName);
1546 }
1547
1548 VkResult radv_AllocateMemory(
1549 VkDevice _device,
1550 const VkMemoryAllocateInfo* pAllocateInfo,
1551 const VkAllocationCallbacks* pAllocator,
1552 VkDeviceMemory* pMem)
1553 {
1554 RADV_FROM_HANDLE(radv_device, device, _device);
1555 struct radv_device_memory *mem;
1556 VkResult result;
1557 enum radeon_bo_domain domain;
1558 uint32_t flags = 0;
1559 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1560
1561 if (pAllocateInfo->allocationSize == 0) {
1562 /* Apparently, this is allowed */
1563 *pMem = VK_NULL_HANDLE;
1564 return VK_SUCCESS;
1565 }
1566
1567 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1568 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1569 if (mem == NULL)
1570 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1571
1572 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1573 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1574 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1575 domain = RADEON_DOMAIN_GTT;
1576 else
1577 domain = RADEON_DOMAIN_VRAM;
1578
1579 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1580 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1581 else
1582 flags |= RADEON_FLAG_CPU_ACCESS;
1583
1584 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1585 flags |= RADEON_FLAG_GTT_WC;
1586
1587 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1588 domain, flags);
1589
1590 if (!mem->bo) {
1591 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1592 goto fail;
1593 }
1594 mem->type_index = pAllocateInfo->memoryTypeIndex;
1595
1596 *pMem = radv_device_memory_to_handle(mem);
1597
1598 return VK_SUCCESS;
1599
1600 fail:
1601 vk_free2(&device->alloc, pAllocator, mem);
1602
1603 return result;
1604 }
1605
1606 void radv_FreeMemory(
1607 VkDevice _device,
1608 VkDeviceMemory _mem,
1609 const VkAllocationCallbacks* pAllocator)
1610 {
1611 RADV_FROM_HANDLE(radv_device, device, _device);
1612 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1613
1614 if (mem == NULL)
1615 return;
1616
1617 device->ws->buffer_destroy(mem->bo);
1618 mem->bo = NULL;
1619
1620 vk_free2(&device->alloc, pAllocator, mem);
1621 }
1622
1623 VkResult radv_MapMemory(
1624 VkDevice _device,
1625 VkDeviceMemory _memory,
1626 VkDeviceSize offset,
1627 VkDeviceSize size,
1628 VkMemoryMapFlags flags,
1629 void** ppData)
1630 {
1631 RADV_FROM_HANDLE(radv_device, device, _device);
1632 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1633
1634 if (mem == NULL) {
1635 *ppData = NULL;
1636 return VK_SUCCESS;
1637 }
1638
1639 *ppData = device->ws->buffer_map(mem->bo);
1640 if (*ppData) {
1641 *ppData += offset;
1642 return VK_SUCCESS;
1643 }
1644
1645 return VK_ERROR_MEMORY_MAP_FAILED;
1646 }
1647
1648 void radv_UnmapMemory(
1649 VkDevice _device,
1650 VkDeviceMemory _memory)
1651 {
1652 RADV_FROM_HANDLE(radv_device, device, _device);
1653 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1654
1655 if (mem == NULL)
1656 return;
1657
1658 device->ws->buffer_unmap(mem->bo);
1659 }
1660
1661 VkResult radv_FlushMappedMemoryRanges(
1662 VkDevice _device,
1663 uint32_t memoryRangeCount,
1664 const VkMappedMemoryRange* pMemoryRanges)
1665 {
1666 return VK_SUCCESS;
1667 }
1668
1669 VkResult radv_InvalidateMappedMemoryRanges(
1670 VkDevice _device,
1671 uint32_t memoryRangeCount,
1672 const VkMappedMemoryRange* pMemoryRanges)
1673 {
1674 return VK_SUCCESS;
1675 }
1676
1677 void radv_GetBufferMemoryRequirements(
1678 VkDevice device,
1679 VkBuffer _buffer,
1680 VkMemoryRequirements* pMemoryRequirements)
1681 {
1682 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1683
1684 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1685
1686 pMemoryRequirements->size = buffer->size;
1687 pMemoryRequirements->alignment = 16;
1688 }
1689
1690 void radv_GetImageMemoryRequirements(
1691 VkDevice device,
1692 VkImage _image,
1693 VkMemoryRequirements* pMemoryRequirements)
1694 {
1695 RADV_FROM_HANDLE(radv_image, image, _image);
1696
1697 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1698
1699 pMemoryRequirements->size = image->size;
1700 pMemoryRequirements->alignment = image->alignment;
1701 }
1702
1703 void radv_GetImageSparseMemoryRequirements(
1704 VkDevice device,
1705 VkImage image,
1706 uint32_t* pSparseMemoryRequirementCount,
1707 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1708 {
1709 stub();
1710 }
1711
1712 void radv_GetDeviceMemoryCommitment(
1713 VkDevice device,
1714 VkDeviceMemory memory,
1715 VkDeviceSize* pCommittedMemoryInBytes)
1716 {
1717 *pCommittedMemoryInBytes = 0;
1718 }
1719
1720 VkResult radv_BindBufferMemory(
1721 VkDevice device,
1722 VkBuffer _buffer,
1723 VkDeviceMemory _memory,
1724 VkDeviceSize memoryOffset)
1725 {
1726 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1727 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1728
1729 if (mem) {
1730 buffer->bo = mem->bo;
1731 buffer->offset = memoryOffset;
1732 } else {
1733 buffer->bo = NULL;
1734 buffer->offset = 0;
1735 }
1736
1737 return VK_SUCCESS;
1738 }
1739
1740 VkResult radv_BindImageMemory(
1741 VkDevice device,
1742 VkImage _image,
1743 VkDeviceMemory _memory,
1744 VkDeviceSize memoryOffset)
1745 {
1746 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1747 RADV_FROM_HANDLE(radv_image, image, _image);
1748
1749 if (mem) {
1750 image->bo = mem->bo;
1751 image->offset = memoryOffset;
1752 } else {
1753 image->bo = NULL;
1754 image->offset = 0;
1755 }
1756
1757 return VK_SUCCESS;
1758 }
1759
1760 VkResult radv_QueueBindSparse(
1761 VkQueue queue,
1762 uint32_t bindInfoCount,
1763 const VkBindSparseInfo* pBindInfo,
1764 VkFence fence)
1765 {
1766 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1767 }
1768
1769 VkResult radv_CreateFence(
1770 VkDevice _device,
1771 const VkFenceCreateInfo* pCreateInfo,
1772 const VkAllocationCallbacks* pAllocator,
1773 VkFence* pFence)
1774 {
1775 RADV_FROM_HANDLE(radv_device, device, _device);
1776 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1777 sizeof(*fence), 8,
1778 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1779
1780 if (!fence)
1781 return VK_ERROR_OUT_OF_HOST_MEMORY;
1782
1783 memset(fence, 0, sizeof(*fence));
1784 fence->submitted = false;
1785 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1786 fence->fence = device->ws->create_fence();
1787 if (!fence->fence) {
1788 vk_free2(&device->alloc, pAllocator, fence);
1789 return VK_ERROR_OUT_OF_HOST_MEMORY;
1790 }
1791
1792 *pFence = radv_fence_to_handle(fence);
1793
1794 return VK_SUCCESS;
1795 }
1796
1797 void radv_DestroyFence(
1798 VkDevice _device,
1799 VkFence _fence,
1800 const VkAllocationCallbacks* pAllocator)
1801 {
1802 RADV_FROM_HANDLE(radv_device, device, _device);
1803 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1804
1805 if (!fence)
1806 return;
1807 device->ws->destroy_fence(fence->fence);
1808 vk_free2(&device->alloc, pAllocator, fence);
1809 }
1810
1811 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1812 {
1813 uint64_t current_time;
1814 struct timespec tv;
1815
1816 clock_gettime(CLOCK_MONOTONIC, &tv);
1817 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1818
1819 timeout = MIN2(UINT64_MAX - current_time, timeout);
1820
1821 return current_time + timeout;
1822 }
1823
1824 VkResult radv_WaitForFences(
1825 VkDevice _device,
1826 uint32_t fenceCount,
1827 const VkFence* pFences,
1828 VkBool32 waitAll,
1829 uint64_t timeout)
1830 {
1831 RADV_FROM_HANDLE(radv_device, device, _device);
1832 timeout = radv_get_absolute_timeout(timeout);
1833
1834 if (!waitAll && fenceCount > 1) {
1835 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1836 }
1837
1838 for (uint32_t i = 0; i < fenceCount; ++i) {
1839 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1840 bool expired = false;
1841
1842 if (fence->signalled)
1843 continue;
1844
1845 if (!fence->submitted)
1846 return VK_TIMEOUT;
1847
1848 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1849 if (!expired)
1850 return VK_TIMEOUT;
1851
1852 fence->signalled = true;
1853 }
1854
1855 return VK_SUCCESS;
1856 }
1857
1858 VkResult radv_ResetFences(VkDevice device,
1859 uint32_t fenceCount,
1860 const VkFence *pFences)
1861 {
1862 for (unsigned i = 0; i < fenceCount; ++i) {
1863 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1864 fence->submitted = fence->signalled = false;
1865 }
1866
1867 return VK_SUCCESS;
1868 }
1869
1870 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1871 {
1872 RADV_FROM_HANDLE(radv_device, device, _device);
1873 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1874
1875 if (fence->signalled)
1876 return VK_SUCCESS;
1877 if (!fence->submitted)
1878 return VK_NOT_READY;
1879
1880 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1881 return VK_NOT_READY;
1882
1883 return VK_SUCCESS;
1884 }
1885
1886
1887 // Queue semaphore functions
1888
1889 VkResult radv_CreateSemaphore(
1890 VkDevice _device,
1891 const VkSemaphoreCreateInfo* pCreateInfo,
1892 const VkAllocationCallbacks* pAllocator,
1893 VkSemaphore* pSemaphore)
1894 {
1895 RADV_FROM_HANDLE(radv_device, device, _device);
1896 struct radeon_winsys_sem *sem;
1897
1898 sem = device->ws->create_sem(device->ws);
1899 if (!sem)
1900 return VK_ERROR_OUT_OF_HOST_MEMORY;
1901
1902 *pSemaphore = (VkSemaphore)sem;
1903 return VK_SUCCESS;
1904 }
1905
1906 void radv_DestroySemaphore(
1907 VkDevice _device,
1908 VkSemaphore _semaphore,
1909 const VkAllocationCallbacks* pAllocator)
1910 {
1911 RADV_FROM_HANDLE(radv_device, device, _device);
1912 struct radeon_winsys_sem *sem;
1913 if (!_semaphore)
1914 return;
1915
1916 sem = (struct radeon_winsys_sem *)_semaphore;
1917 device->ws->destroy_sem(sem);
1918 }
1919
1920 VkResult radv_CreateEvent(
1921 VkDevice _device,
1922 const VkEventCreateInfo* pCreateInfo,
1923 const VkAllocationCallbacks* pAllocator,
1924 VkEvent* pEvent)
1925 {
1926 RADV_FROM_HANDLE(radv_device, device, _device);
1927 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1928 sizeof(*event), 8,
1929 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1930
1931 if (!event)
1932 return VK_ERROR_OUT_OF_HOST_MEMORY;
1933
1934 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1935 RADEON_DOMAIN_GTT,
1936 RADEON_FLAG_CPU_ACCESS);
1937 if (!event->bo) {
1938 vk_free2(&device->alloc, pAllocator, event);
1939 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1940 }
1941
1942 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1943
1944 *pEvent = radv_event_to_handle(event);
1945
1946 return VK_SUCCESS;
1947 }
1948
1949 void radv_DestroyEvent(
1950 VkDevice _device,
1951 VkEvent _event,
1952 const VkAllocationCallbacks* pAllocator)
1953 {
1954 RADV_FROM_HANDLE(radv_device, device, _device);
1955 RADV_FROM_HANDLE(radv_event, event, _event);
1956
1957 if (!event)
1958 return;
1959 device->ws->buffer_destroy(event->bo);
1960 vk_free2(&device->alloc, pAllocator, event);
1961 }
1962
1963 VkResult radv_GetEventStatus(
1964 VkDevice _device,
1965 VkEvent _event)
1966 {
1967 RADV_FROM_HANDLE(radv_event, event, _event);
1968
1969 if (*event->map == 1)
1970 return VK_EVENT_SET;
1971 return VK_EVENT_RESET;
1972 }
1973
1974 VkResult radv_SetEvent(
1975 VkDevice _device,
1976 VkEvent _event)
1977 {
1978 RADV_FROM_HANDLE(radv_event, event, _event);
1979 *event->map = 1;
1980
1981 return VK_SUCCESS;
1982 }
1983
1984 VkResult radv_ResetEvent(
1985 VkDevice _device,
1986 VkEvent _event)
1987 {
1988 RADV_FROM_HANDLE(radv_event, event, _event);
1989 *event->map = 0;
1990
1991 return VK_SUCCESS;
1992 }
1993
1994 VkResult radv_CreateBuffer(
1995 VkDevice _device,
1996 const VkBufferCreateInfo* pCreateInfo,
1997 const VkAllocationCallbacks* pAllocator,
1998 VkBuffer* pBuffer)
1999 {
2000 RADV_FROM_HANDLE(radv_device, device, _device);
2001 struct radv_buffer *buffer;
2002
2003 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2004
2005 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2006 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2007 if (buffer == NULL)
2008 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2009
2010 buffer->size = pCreateInfo->size;
2011 buffer->usage = pCreateInfo->usage;
2012 buffer->bo = NULL;
2013 buffer->offset = 0;
2014
2015 *pBuffer = radv_buffer_to_handle(buffer);
2016
2017 return VK_SUCCESS;
2018 }
2019
2020 void radv_DestroyBuffer(
2021 VkDevice _device,
2022 VkBuffer _buffer,
2023 const VkAllocationCallbacks* pAllocator)
2024 {
2025 RADV_FROM_HANDLE(radv_device, device, _device);
2026 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2027
2028 if (!buffer)
2029 return;
2030
2031 vk_free2(&device->alloc, pAllocator, buffer);
2032 }
2033
2034 static inline unsigned
2035 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2036 {
2037 if (stencil)
2038 return image->surface.stencil_tiling_index[level];
2039 else
2040 return image->surface.tiling_index[level];
2041 }
2042
2043 static void
2044 radv_initialise_color_surface(struct radv_device *device,
2045 struct radv_color_buffer_info *cb,
2046 struct radv_image_view *iview)
2047 {
2048 const struct vk_format_description *desc;
2049 unsigned ntype, format, swap, endian;
2050 unsigned blend_clamp = 0, blend_bypass = 0;
2051 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2052 uint64_t va;
2053 const struct radeon_surf *surf = &iview->image->surface;
2054 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2055
2056 desc = vk_format_description(iview->vk_format);
2057
2058 memset(cb, 0, sizeof(*cb));
2059
2060 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2061 va += level_info->offset;
2062 cb->cb_color_base = va >> 8;
2063
2064 /* CMASK variables */
2065 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2066 va += iview->image->cmask.offset;
2067 cb->cb_color_cmask = va >> 8;
2068 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2069
2070 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2071 va += iview->image->dcc_offset;
2072 cb->cb_dcc_base = va >> 8;
2073
2074 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2075 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2076 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2077
2078 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2079 pitch_tile_max = level_info->nblk_x / 8 - 1;
2080 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2081 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2082
2083 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2084 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2085
2086 /* Intensity is implemented as Red, so treat it that way. */
2087 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2088 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2089
2090 if (iview->image->samples > 1) {
2091 unsigned log_samples = util_logbase2(iview->image->samples);
2092
2093 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2094 S_028C74_NUM_FRAGMENTS(log_samples);
2095 }
2096
2097 if (iview->image->fmask.size) {
2098 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2099 if (device->physical_device->rad_info.chip_class >= CIK)
2100 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2101 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2102 cb->cb_color_fmask = va >> 8;
2103 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2104 } else {
2105 /* This must be set for fast clear to work without FMASK. */
2106 if (device->physical_device->rad_info.chip_class >= CIK)
2107 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2108 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2109 cb->cb_color_fmask = cb->cb_color_base;
2110 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2111 }
2112
2113 ntype = radv_translate_color_numformat(iview->vk_format,
2114 desc,
2115 vk_format_get_first_non_void_channel(iview->vk_format));
2116 format = radv_translate_colorformat(iview->vk_format);
2117 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2118 radv_finishme("Illegal color\n");
2119 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2120 endian = radv_colorformat_endian_swap(format);
2121
2122 /* blend clamp should be set for all NORM/SRGB types */
2123 if (ntype == V_028C70_NUMBER_UNORM ||
2124 ntype == V_028C70_NUMBER_SNORM ||
2125 ntype == V_028C70_NUMBER_SRGB)
2126 blend_clamp = 1;
2127
2128 /* set blend bypass according to docs if SINT/UINT or
2129 8/24 COLOR variants */
2130 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2131 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2132 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2133 blend_clamp = 0;
2134 blend_bypass = 1;
2135 }
2136 #if 0
2137 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2138 (format == V_028C70_COLOR_8 ||
2139 format == V_028C70_COLOR_8_8 ||
2140 format == V_028C70_COLOR_8_8_8_8))
2141 ->color_is_int8 = true;
2142 #endif
2143 cb->cb_color_info = S_028C70_FORMAT(format) |
2144 S_028C70_COMP_SWAP(swap) |
2145 S_028C70_BLEND_CLAMP(blend_clamp) |
2146 S_028C70_BLEND_BYPASS(blend_bypass) |
2147 S_028C70_SIMPLE_FLOAT(1) |
2148 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2149 ntype != V_028C70_NUMBER_SNORM &&
2150 ntype != V_028C70_NUMBER_SRGB &&
2151 format != V_028C70_COLOR_8_24 &&
2152 format != V_028C70_COLOR_24_8) |
2153 S_028C70_NUMBER_TYPE(ntype) |
2154 S_028C70_ENDIAN(endian);
2155 if (iview->image->samples > 1)
2156 if (iview->image->fmask.size)
2157 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2158
2159 if (iview->image->cmask.size &&
2160 (device->debug_flags & RADV_DEBUG_FAST_CLEARS))
2161 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2162
2163 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2164 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2165
2166 if (device->physical_device->rad_info.chip_class >= VI) {
2167 unsigned max_uncompressed_block_size = 2;
2168 if (iview->image->samples > 1) {
2169 if (iview->image->surface.bpe == 1)
2170 max_uncompressed_block_size = 0;
2171 else if (iview->image->surface.bpe == 2)
2172 max_uncompressed_block_size = 1;
2173 }
2174
2175 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2176 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2177 }
2178
2179 /* This must be set for fast clear to work without FMASK. */
2180 if (!iview->image->fmask.size &&
2181 device->physical_device->rad_info.chip_class == SI) {
2182 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2183 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2184 }
2185 }
2186
2187 static void
2188 radv_initialise_ds_surface(struct radv_device *device,
2189 struct radv_ds_buffer_info *ds,
2190 struct radv_image_view *iview)
2191 {
2192 unsigned level = iview->base_mip;
2193 unsigned format;
2194 uint64_t va, s_offs, z_offs;
2195 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2196 memset(ds, 0, sizeof(*ds));
2197 switch (iview->vk_format) {
2198 case VK_FORMAT_D24_UNORM_S8_UINT:
2199 case VK_FORMAT_X8_D24_UNORM_PACK32:
2200 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2201 ds->offset_scale = 2.0f;
2202 break;
2203 case VK_FORMAT_D16_UNORM:
2204 case VK_FORMAT_D16_UNORM_S8_UINT:
2205 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2206 ds->offset_scale = 4.0f;
2207 break;
2208 case VK_FORMAT_D32_SFLOAT:
2209 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2210 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2211 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2212 ds->offset_scale = 1.0f;
2213 break;
2214 default:
2215 break;
2216 }
2217
2218 format = radv_translate_dbformat(iview->vk_format);
2219 if (format == V_028040_Z_INVALID) {
2220 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2221 }
2222
2223 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2224 s_offs = z_offs = va;
2225 z_offs += iview->image->surface.level[level].offset;
2226 s_offs += iview->image->surface.stencil_level[level].offset;
2227
2228 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2229 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2230 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2231 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2232 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2233
2234 if (iview->image->samples > 1)
2235 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2236
2237 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2238 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2239 else
2240 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2241
2242 if (device->physical_device->rad_info.chip_class >= CIK) {
2243 struct radeon_info *info = &device->physical_device->rad_info;
2244 unsigned tiling_index = iview->image->surface.tiling_index[level];
2245 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2246 unsigned macro_index = iview->image->surface.macro_tile_index;
2247 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2248 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2249 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2250
2251 ds->db_depth_info |=
2252 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2253 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2254 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2255 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2256 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2257 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2258 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2259 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2260 } else {
2261 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2262 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2263 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2264 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2265 }
2266
2267 if (iview->image->htile.size && !level) {
2268 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2269 S_028040_ALLOW_EXPCLEAR(1);
2270
2271 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2272 /* Workaround: For a not yet understood reason, the
2273 * combination of MSAA, fast stencil clear and stencil
2274 * decompress messes with subsequent stencil buffer
2275 * uses. Problem was reproduced on Verde, Bonaire,
2276 * Tonga, and Carrizo.
2277 *
2278 * Disabling EXPCLEAR works around the problem.
2279 *
2280 * Check piglit's arb_texture_multisample-stencil-clear
2281 * test if you want to try changing this.
2282 */
2283 if (iview->image->samples <= 1)
2284 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2285 } else
2286 /* Use all of the htile_buffer for depth if there's no stencil. */
2287 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2288
2289 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2290 iview->image->htile.offset;
2291 ds->db_htile_data_base = va >> 8;
2292 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2293 } else {
2294 ds->db_htile_data_base = 0;
2295 ds->db_htile_surface = 0;
2296 }
2297
2298 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2299 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2300
2301 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2302 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2303 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2304 }
2305
2306 VkResult radv_CreateFramebuffer(
2307 VkDevice _device,
2308 const VkFramebufferCreateInfo* pCreateInfo,
2309 const VkAllocationCallbacks* pAllocator,
2310 VkFramebuffer* pFramebuffer)
2311 {
2312 RADV_FROM_HANDLE(radv_device, device, _device);
2313 struct radv_framebuffer *framebuffer;
2314
2315 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2316
2317 size_t size = sizeof(*framebuffer) +
2318 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2319 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2320 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2321 if (framebuffer == NULL)
2322 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2323
2324 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2325 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2326 VkImageView _iview = pCreateInfo->pAttachments[i];
2327 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2328 framebuffer->attachments[i].attachment = iview;
2329 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2330 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2331 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2332 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2333 }
2334 }
2335
2336 framebuffer->width = pCreateInfo->width;
2337 framebuffer->height = pCreateInfo->height;
2338 framebuffer->layers = pCreateInfo->layers;
2339
2340 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2341 return VK_SUCCESS;
2342 }
2343
2344 void radv_DestroyFramebuffer(
2345 VkDevice _device,
2346 VkFramebuffer _fb,
2347 const VkAllocationCallbacks* pAllocator)
2348 {
2349 RADV_FROM_HANDLE(radv_device, device, _device);
2350 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2351
2352 if (!fb)
2353 return;
2354 vk_free2(&device->alloc, pAllocator, fb);
2355 }
2356
2357 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2358 {
2359 switch (address_mode) {
2360 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2361 return V_008F30_SQ_TEX_WRAP;
2362 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2363 return V_008F30_SQ_TEX_MIRROR;
2364 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2365 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2366 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2367 return V_008F30_SQ_TEX_CLAMP_BORDER;
2368 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2369 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2370 default:
2371 unreachable("illegal tex wrap mode");
2372 break;
2373 }
2374 }
2375
2376 static unsigned
2377 radv_tex_compare(VkCompareOp op)
2378 {
2379 switch (op) {
2380 case VK_COMPARE_OP_NEVER:
2381 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2382 case VK_COMPARE_OP_LESS:
2383 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2384 case VK_COMPARE_OP_EQUAL:
2385 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2386 case VK_COMPARE_OP_LESS_OR_EQUAL:
2387 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2388 case VK_COMPARE_OP_GREATER:
2389 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2390 case VK_COMPARE_OP_NOT_EQUAL:
2391 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2392 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2393 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2394 case VK_COMPARE_OP_ALWAYS:
2395 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2396 default:
2397 unreachable("illegal compare mode");
2398 break;
2399 }
2400 }
2401
2402 static unsigned
2403 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2404 {
2405 switch (filter) {
2406 case VK_FILTER_NEAREST:
2407 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2408 V_008F38_SQ_TEX_XY_FILTER_POINT);
2409 case VK_FILTER_LINEAR:
2410 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2411 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2412 case VK_FILTER_CUBIC_IMG:
2413 default:
2414 fprintf(stderr, "illegal texture filter");
2415 return 0;
2416 }
2417 }
2418
2419 static unsigned
2420 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2421 {
2422 switch (mode) {
2423 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2424 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2425 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2426 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2427 default:
2428 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2429 }
2430 }
2431
2432 static unsigned
2433 radv_tex_bordercolor(VkBorderColor bcolor)
2434 {
2435 switch (bcolor) {
2436 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2437 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2438 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2439 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2440 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2441 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2442 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2443 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2444 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2445 default:
2446 break;
2447 }
2448 return 0;
2449 }
2450
2451 static unsigned
2452 radv_tex_aniso_filter(unsigned filter)
2453 {
2454 if (filter < 2)
2455 return 0;
2456 if (filter < 4)
2457 return 1;
2458 if (filter < 8)
2459 return 2;
2460 if (filter < 16)
2461 return 3;
2462 return 4;
2463 }
2464
2465 static void
2466 radv_init_sampler(struct radv_device *device,
2467 struct radv_sampler *sampler,
2468 const VkSamplerCreateInfo *pCreateInfo)
2469 {
2470 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2471 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2472 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2473 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2474
2475 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2476 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2477 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2478 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2479 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2480 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2481 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2482 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2483 S_008F30_DISABLE_CUBE_WRAP(0) |
2484 S_008F30_COMPAT_MODE(is_vi));
2485 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2486 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2487 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2488 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2489 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2490 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2491 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2492 S_008F38_MIP_POINT_PRECLAMP(1) |
2493 S_008F38_DISABLE_LSB_CEIL(1) |
2494 S_008F38_FILTER_PREC_FIX(1) |
2495 S_008F38_ANISO_OVERRIDE(is_vi));
2496 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2497 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2498 }
2499
2500 VkResult radv_CreateSampler(
2501 VkDevice _device,
2502 const VkSamplerCreateInfo* pCreateInfo,
2503 const VkAllocationCallbacks* pAllocator,
2504 VkSampler* pSampler)
2505 {
2506 RADV_FROM_HANDLE(radv_device, device, _device);
2507 struct radv_sampler *sampler;
2508
2509 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2510
2511 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2512 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2513 if (!sampler)
2514 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2515
2516 radv_init_sampler(device, sampler, pCreateInfo);
2517 *pSampler = radv_sampler_to_handle(sampler);
2518
2519 return VK_SUCCESS;
2520 }
2521
2522 void radv_DestroySampler(
2523 VkDevice _device,
2524 VkSampler _sampler,
2525 const VkAllocationCallbacks* pAllocator)
2526 {
2527 RADV_FROM_HANDLE(radv_device, device, _device);
2528 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2529
2530 if (!sampler)
2531 return;
2532 vk_free2(&device->alloc, pAllocator, sampler);
2533 }
2534
2535
2536 /* vk_icd.h does not declare this function, so we declare it here to
2537 * suppress Wmissing-prototypes.
2538 */
2539 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2540 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2541
2542 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2543 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2544 {
2545 /* For the full details on loader interface versioning, see
2546 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2547 * What follows is a condensed summary, to help you navigate the large and
2548 * confusing official doc.
2549 *
2550 * - Loader interface v0 is incompatible with later versions. We don't
2551 * support it.
2552 *
2553 * - In loader interface v1:
2554 * - The first ICD entrypoint called by the loader is
2555 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2556 * entrypoint.
2557 * - The ICD must statically expose no other Vulkan symbol unless it is
2558 * linked with -Bsymbolic.
2559 * - Each dispatchable Vulkan handle created by the ICD must be
2560 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2561 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2562 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2563 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2564 * such loader-managed surfaces.
2565 *
2566 * - Loader interface v2 differs from v1 in:
2567 * - The first ICD entrypoint called by the loader is
2568 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2569 * statically expose this entrypoint.
2570 *
2571 * - Loader interface v3 differs from v2 in:
2572 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2573 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2574 * because the loader no longer does so.
2575 */
2576 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2577 return VK_SUCCESS;
2578 }