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radv: initialize the per-queue descriptor BO only once
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 radv_physical_device_init_mem_types(device);
373 radv_fill_device_extension_table(device, &device->supported_extensions);
374
375 device->bus_info = *drm_device->businfo.pci;
376
377 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
378 ac_print_gpu_info(&device->rad_info);
379
380 /* The WSI is structured as a layer on top of the driver, so this has
381 * to be the last part of initialization (at least until we get other
382 * semi-layers).
383 */
384 result = radv_init_wsi(device);
385 if (result != VK_SUCCESS) {
386 device->ws->destroy(device->ws);
387 vk_error(instance, result);
388 goto fail;
389 }
390
391 return VK_SUCCESS;
392
393 fail:
394 close(fd);
395 if (master_fd != -1)
396 close(master_fd);
397 return result;
398 }
399
400 static void
401 radv_physical_device_finish(struct radv_physical_device *device)
402 {
403 radv_finish_wsi(device);
404 device->ws->destroy(device->ws);
405 disk_cache_destroy(device->disk_cache);
406 close(device->local_fd);
407 if (device->master_fd != -1)
408 close(device->master_fd);
409 }
410
411 static void *
412 default_alloc_func(void *pUserData, size_t size, size_t align,
413 VkSystemAllocationScope allocationScope)
414 {
415 return malloc(size);
416 }
417
418 static void *
419 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
420 size_t align, VkSystemAllocationScope allocationScope)
421 {
422 return realloc(pOriginal, size);
423 }
424
425 static void
426 default_free_func(void *pUserData, void *pMemory)
427 {
428 free(pMemory);
429 }
430
431 static const VkAllocationCallbacks default_alloc = {
432 .pUserData = NULL,
433 .pfnAllocation = default_alloc_func,
434 .pfnReallocation = default_realloc_func,
435 .pfnFree = default_free_func,
436 };
437
438 static const struct debug_control radv_debug_options[] = {
439 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
440 {"nodcc", RADV_DEBUG_NO_DCC},
441 {"shaders", RADV_DEBUG_DUMP_SHADERS},
442 {"nocache", RADV_DEBUG_NO_CACHE},
443 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
444 {"nohiz", RADV_DEBUG_NO_HIZ},
445 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
446 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
447 {"allbos", RADV_DEBUG_ALL_BOS},
448 {"noibs", RADV_DEBUG_NO_IBS},
449 {"spirv", RADV_DEBUG_DUMP_SPIRV},
450 {"vmfaults", RADV_DEBUG_VM_FAULTS},
451 {"zerovram", RADV_DEBUG_ZERO_VRAM},
452 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
453 {"nosisched", RADV_DEBUG_NO_SISCHED},
454 {"preoptir", RADV_DEBUG_PREOPTIR},
455 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
456 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
457 {"info", RADV_DEBUG_INFO},
458 {"errors", RADV_DEBUG_ERRORS},
459 {"startup", RADV_DEBUG_STARTUP},
460 {"checkir", RADV_DEBUG_CHECKIR},
461 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
462 {"nobinning", RADV_DEBUG_NOBINNING},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {"localbos", RADV_PERFTEST_LOCAL_BOS},
477 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
478 {NULL, 0}
479 };
480
481 const char *
482 radv_get_perftest_option_name(int id)
483 {
484 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
485 return radv_perftest_options[id].string;
486 }
487
488 static void
489 radv_handle_per_app_options(struct radv_instance *instance,
490 const VkApplicationInfo *info)
491 {
492 const char *name = info ? info->pApplicationName : NULL;
493
494 if (!name)
495 return;
496
497 if (!strcmp(name, "Talos - Linux - 32bit") ||
498 !strcmp(name, "Talos - Linux - 64bit")) {
499 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
500 /* Force enable LLVM sisched for Talos because it looks
501 * safe and it gives few more FPS.
502 */
503 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
504 }
505 } else if (!strcmp(name, "DOOM_VFR")) {
506 /* Work around a Doom VFR game bug */
507 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
508 }
509 }
510
511 static int radv_get_instance_extension_index(const char *name)
512 {
513 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
514 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
515 return i;
516 }
517 return -1;
518 }
519
520
521 VkResult radv_CreateInstance(
522 const VkInstanceCreateInfo* pCreateInfo,
523 const VkAllocationCallbacks* pAllocator,
524 VkInstance* pInstance)
525 {
526 struct radv_instance *instance;
527 VkResult result;
528
529 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
530
531 uint32_t client_version;
532 if (pCreateInfo->pApplicationInfo &&
533 pCreateInfo->pApplicationInfo->apiVersion != 0) {
534 client_version = pCreateInfo->pApplicationInfo->apiVersion;
535 } else {
536 radv_EnumerateInstanceVersion(&client_version);
537 }
538
539 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
540 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
541 if (!instance)
542 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
543
544 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
545
546 if (pAllocator)
547 instance->alloc = *pAllocator;
548 else
549 instance->alloc = default_alloc;
550
551 instance->apiVersion = client_version;
552 instance->physicalDeviceCount = -1;
553
554 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
555 radv_debug_options);
556
557 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
558 radv_perftest_options);
559
560
561 if (instance->debug_flags & RADV_DEBUG_STARTUP)
562 radv_logi("Created an instance");
563
564 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
565 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
566 int index = radv_get_instance_extension_index(ext_name);
567
568 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
569 vk_free2(&default_alloc, pAllocator, instance);
570 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
571 }
572
573 instance->enabled_extensions.extensions[index] = true;
574 }
575
576 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
577 if (result != VK_SUCCESS) {
578 vk_free2(&default_alloc, pAllocator, instance);
579 return vk_error(instance, result);
580 }
581
582 _mesa_locale_init();
583
584 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
585
586 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
587
588 *pInstance = radv_instance_to_handle(instance);
589
590 return VK_SUCCESS;
591 }
592
593 void radv_DestroyInstance(
594 VkInstance _instance,
595 const VkAllocationCallbacks* pAllocator)
596 {
597 RADV_FROM_HANDLE(radv_instance, instance, _instance);
598
599 if (!instance)
600 return;
601
602 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
603 radv_physical_device_finish(instance->physicalDevices + i);
604 }
605
606 VG(VALGRIND_DESTROY_MEMPOOL(instance));
607
608 _mesa_locale_fini();
609
610 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
611
612 vk_free(&instance->alloc, instance);
613 }
614
615 static VkResult
616 radv_enumerate_devices(struct radv_instance *instance)
617 {
618 /* TODO: Check for more devices ? */
619 drmDevicePtr devices[8];
620 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
621 int max_devices;
622
623 instance->physicalDeviceCount = 0;
624
625 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
626
627 if (instance->debug_flags & RADV_DEBUG_STARTUP)
628 radv_logi("Found %d drm nodes", max_devices);
629
630 if (max_devices < 1)
631 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
632
633 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
634 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
635 devices[i]->bustype == DRM_BUS_PCI &&
636 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
637
638 result = radv_physical_device_init(instance->physicalDevices +
639 instance->physicalDeviceCount,
640 instance,
641 devices[i]);
642 if (result == VK_SUCCESS)
643 ++instance->physicalDeviceCount;
644 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
645 break;
646 }
647 }
648 drmFreeDevices(devices, max_devices);
649
650 return result;
651 }
652
653 VkResult radv_EnumeratePhysicalDevices(
654 VkInstance _instance,
655 uint32_t* pPhysicalDeviceCount,
656 VkPhysicalDevice* pPhysicalDevices)
657 {
658 RADV_FROM_HANDLE(radv_instance, instance, _instance);
659 VkResult result;
660
661 if (instance->physicalDeviceCount < 0) {
662 result = radv_enumerate_devices(instance);
663 if (result != VK_SUCCESS &&
664 result != VK_ERROR_INCOMPATIBLE_DRIVER)
665 return result;
666 }
667
668 if (!pPhysicalDevices) {
669 *pPhysicalDeviceCount = instance->physicalDeviceCount;
670 } else {
671 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
672 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
673 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
674 }
675
676 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
677 : VK_SUCCESS;
678 }
679
680 VkResult radv_EnumeratePhysicalDeviceGroups(
681 VkInstance _instance,
682 uint32_t* pPhysicalDeviceGroupCount,
683 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
684 {
685 RADV_FROM_HANDLE(radv_instance, instance, _instance);
686 VkResult result;
687
688 if (instance->physicalDeviceCount < 0) {
689 result = radv_enumerate_devices(instance);
690 if (result != VK_SUCCESS &&
691 result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 return result;
693 }
694
695 if (!pPhysicalDeviceGroupProperties) {
696 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
697 } else {
698 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
699 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
700 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
701 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
702 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
703 }
704 }
705 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
706 : VK_SUCCESS;
707 }
708
709 void radv_GetPhysicalDeviceFeatures(
710 VkPhysicalDevice physicalDevice,
711 VkPhysicalDeviceFeatures* pFeatures)
712 {
713 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
714 memset(pFeatures, 0, sizeof(*pFeatures));
715
716 *pFeatures = (VkPhysicalDeviceFeatures) {
717 .robustBufferAccess = true,
718 .fullDrawIndexUint32 = true,
719 .imageCubeArray = true,
720 .independentBlend = true,
721 .geometryShader = true,
722 .tessellationShader = true,
723 .sampleRateShading = true,
724 .dualSrcBlend = true,
725 .logicOp = true,
726 .multiDrawIndirect = true,
727 .drawIndirectFirstInstance = true,
728 .depthClamp = true,
729 .depthBiasClamp = true,
730 .fillModeNonSolid = true,
731 .depthBounds = true,
732 .wideLines = true,
733 .largePoints = true,
734 .alphaToOne = true,
735 .multiViewport = true,
736 .samplerAnisotropy = true,
737 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
738 pdevice->rad_info.family == CHIP_STONEY,
739 .textureCompressionASTC_LDR = false,
740 .textureCompressionBC = true,
741 .occlusionQueryPrecise = true,
742 .pipelineStatisticsQuery = true,
743 .vertexPipelineStoresAndAtomics = true,
744 .fragmentStoresAndAtomics = true,
745 .shaderTessellationAndGeometryPointSize = true,
746 .shaderImageGatherExtended = true,
747 .shaderStorageImageExtendedFormats = true,
748 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
749 .shaderUniformBufferArrayDynamicIndexing = true,
750 .shaderSampledImageArrayDynamicIndexing = true,
751 .shaderStorageBufferArrayDynamicIndexing = true,
752 .shaderStorageImageArrayDynamicIndexing = true,
753 .shaderStorageImageReadWithoutFormat = true,
754 .shaderStorageImageWriteWithoutFormat = true,
755 .shaderClipDistance = true,
756 .shaderCullDistance = true,
757 .shaderFloat64 = true,
758 .shaderInt64 = true,
759 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
760 .sparseBinding = true,
761 .variableMultisampleRate = true,
762 .inheritedQueries = true,
763 };
764 }
765
766 void radv_GetPhysicalDeviceFeatures2(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures2 *pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 vk_foreach_struct(ext, pFeatures->pNext) {
772 switch (ext->sType) {
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
774 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
775 features->variablePointersStorageBuffer = true;
776 features->variablePointers = true;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
780 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
781 features->multiview = true;
782 features->multiviewGeometryShader = true;
783 features->multiviewTessellationShader = true;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
787 VkPhysicalDeviceShaderDrawParameterFeatures *features =
788 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
789 features->shaderDrawParameters = true;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
793 VkPhysicalDeviceProtectedMemoryFeatures *features =
794 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
795 features->protectedMemory = false;
796 break;
797 }
798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
799 VkPhysicalDevice16BitStorageFeatures *features =
800 (VkPhysicalDevice16BitStorageFeatures*)ext;
801 bool enabled = pdevice->rad_info.chip_class >= VI;
802 features->storageBuffer16BitAccess = enabled;
803 features->uniformAndStorageBuffer16BitAccess = enabled;
804 features->storagePushConstant16 = enabled;
805 features->storageInputOutput16 = enabled;
806 break;
807 }
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
809 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
810 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
811 features->samplerYcbcrConversion = false;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
815 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
816 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
817 features->shaderInputAttachmentArrayDynamicIndexing = true;
818 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
819 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
820 features->shaderUniformBufferArrayNonUniformIndexing = false;
821 features->shaderSampledImageArrayNonUniformIndexing = false;
822 features->shaderStorageBufferArrayNonUniformIndexing = false;
823 features->shaderStorageImageArrayNonUniformIndexing = false;
824 features->shaderInputAttachmentArrayNonUniformIndexing = false;
825 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
826 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
827 features->descriptorBindingUniformBufferUpdateAfterBind = true;
828 features->descriptorBindingSampledImageUpdateAfterBind = true;
829 features->descriptorBindingStorageImageUpdateAfterBind = true;
830 features->descriptorBindingStorageBufferUpdateAfterBind = true;
831 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
832 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingUpdateUnusedWhilePending = true;
834 features->descriptorBindingPartiallyBound = true;
835 features->descriptorBindingVariableDescriptorCount = true;
836 features->runtimeDescriptorArray = true;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
840 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
841 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
842 features->conditionalRendering = true;
843 features->inheritedConditionalRendering = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
847 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
848 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
849 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
850 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
854 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
855 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
856 features->transformFeedback = true;
857 features->geometryStreams = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
861 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
862 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
863 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
864 break;
865 }
866 default:
867 break;
868 }
869 }
870 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
871 }
872
873 void radv_GetPhysicalDeviceProperties(
874 VkPhysicalDevice physicalDevice,
875 VkPhysicalDeviceProperties* pProperties)
876 {
877 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
878 VkSampleCountFlags sample_counts = 0xf;
879
880 /* make sure that the entire descriptor set is addressable with a signed
881 * 32-bit int. So the sum of all limits scaled by descriptor size has to
882 * be at most 2 GiB. the combined image & samples object count as one of
883 * both. This limit is for the pipeline layout, not for the set layout, but
884 * there is no set limit, so we just set a pipeline limit. I don't think
885 * any app is going to hit this soon. */
886 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
887 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
888 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
889 32 /* sampler, largest when combined with image */ +
890 64 /* sampled image */ +
891 64 /* storage image */);
892
893 VkPhysicalDeviceLimits limits = {
894 .maxImageDimension1D = (1 << 14),
895 .maxImageDimension2D = (1 << 14),
896 .maxImageDimension3D = (1 << 11),
897 .maxImageDimensionCube = (1 << 14),
898 .maxImageArrayLayers = (1 << 11),
899 .maxTexelBufferElements = 128 * 1024 * 1024,
900 .maxUniformBufferRange = UINT32_MAX,
901 .maxStorageBufferRange = UINT32_MAX,
902 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
903 .maxMemoryAllocationCount = UINT32_MAX,
904 .maxSamplerAllocationCount = 64 * 1024,
905 .bufferImageGranularity = 64, /* A cache line */
906 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
907 .maxBoundDescriptorSets = MAX_SETS,
908 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
909 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
910 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
911 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
912 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
913 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
914 .maxPerStageResources = max_descriptor_set_size,
915 .maxDescriptorSetSamplers = max_descriptor_set_size,
916 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
917 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
918 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
919 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
920 .maxDescriptorSetSampledImages = max_descriptor_set_size,
921 .maxDescriptorSetStorageImages = max_descriptor_set_size,
922 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
923 .maxVertexInputAttributes = 32,
924 .maxVertexInputBindings = 32,
925 .maxVertexInputAttributeOffset = 2047,
926 .maxVertexInputBindingStride = 2048,
927 .maxVertexOutputComponents = 128,
928 .maxTessellationGenerationLevel = 64,
929 .maxTessellationPatchSize = 32,
930 .maxTessellationControlPerVertexInputComponents = 128,
931 .maxTessellationControlPerVertexOutputComponents = 128,
932 .maxTessellationControlPerPatchOutputComponents = 120,
933 .maxTessellationControlTotalOutputComponents = 4096,
934 .maxTessellationEvaluationInputComponents = 128,
935 .maxTessellationEvaluationOutputComponents = 128,
936 .maxGeometryShaderInvocations = 127,
937 .maxGeometryInputComponents = 64,
938 .maxGeometryOutputComponents = 128,
939 .maxGeometryOutputVertices = 256,
940 .maxGeometryTotalOutputComponents = 1024,
941 .maxFragmentInputComponents = 128,
942 .maxFragmentOutputAttachments = 8,
943 .maxFragmentDualSrcAttachments = 1,
944 .maxFragmentCombinedOutputResources = 8,
945 .maxComputeSharedMemorySize = 32768,
946 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
947 .maxComputeWorkGroupInvocations = 2048,
948 .maxComputeWorkGroupSize = {
949 2048,
950 2048,
951 2048
952 },
953 .subPixelPrecisionBits = 8,
954 .subTexelPrecisionBits = 8,
955 .mipmapPrecisionBits = 8,
956 .maxDrawIndexedIndexValue = UINT32_MAX,
957 .maxDrawIndirectCount = UINT32_MAX,
958 .maxSamplerLodBias = 16,
959 .maxSamplerAnisotropy = 16,
960 .maxViewports = MAX_VIEWPORTS,
961 .maxViewportDimensions = { (1 << 14), (1 << 14) },
962 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
963 .viewportSubPixelBits = 8,
964 .minMemoryMapAlignment = 4096, /* A page */
965 .minTexelBufferOffsetAlignment = 1,
966 .minUniformBufferOffsetAlignment = 4,
967 .minStorageBufferOffsetAlignment = 4,
968 .minTexelOffset = -32,
969 .maxTexelOffset = 31,
970 .minTexelGatherOffset = -32,
971 .maxTexelGatherOffset = 31,
972 .minInterpolationOffset = -2,
973 .maxInterpolationOffset = 2,
974 .subPixelInterpolationOffsetBits = 8,
975 .maxFramebufferWidth = (1 << 14),
976 .maxFramebufferHeight = (1 << 14),
977 .maxFramebufferLayers = (1 << 10),
978 .framebufferColorSampleCounts = sample_counts,
979 .framebufferDepthSampleCounts = sample_counts,
980 .framebufferStencilSampleCounts = sample_counts,
981 .framebufferNoAttachmentsSampleCounts = sample_counts,
982 .maxColorAttachments = MAX_RTS,
983 .sampledImageColorSampleCounts = sample_counts,
984 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
985 .sampledImageDepthSampleCounts = sample_counts,
986 .sampledImageStencilSampleCounts = sample_counts,
987 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
988 .maxSampleMaskWords = 1,
989 .timestampComputeAndGraphics = true,
990 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
991 .maxClipDistances = 8,
992 .maxCullDistances = 8,
993 .maxCombinedClipAndCullDistances = 8,
994 .discreteQueuePriorities = 2,
995 .pointSizeRange = { 0.125, 255.875 },
996 .lineWidthRange = { 0.0, 7.9921875 },
997 .pointSizeGranularity = (1.0 / 8.0),
998 .lineWidthGranularity = (1.0 / 128.0),
999 .strictLines = false, /* FINISHME */
1000 .standardSampleLocations = true,
1001 .optimalBufferCopyOffsetAlignment = 128,
1002 .optimalBufferCopyRowPitchAlignment = 128,
1003 .nonCoherentAtomSize = 64,
1004 };
1005
1006 *pProperties = (VkPhysicalDeviceProperties) {
1007 .apiVersion = radv_physical_device_api_version(pdevice),
1008 .driverVersion = vk_get_driver_version(),
1009 .vendorID = ATI_VENDOR_ID,
1010 .deviceID = pdevice->rad_info.pci_id,
1011 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1012 .limits = limits,
1013 .sparseProperties = {0},
1014 };
1015
1016 strcpy(pProperties->deviceName, pdevice->name);
1017 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1018 }
1019
1020 void radv_GetPhysicalDeviceProperties2(
1021 VkPhysicalDevice physicalDevice,
1022 VkPhysicalDeviceProperties2 *pProperties)
1023 {
1024 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1025 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1026
1027 vk_foreach_struct(ext, pProperties->pNext) {
1028 switch (ext->sType) {
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1030 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1031 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1032 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1036 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1037 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1038 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1039 properties->deviceLUIDValid = false;
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1043 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1044 properties->maxMultiviewViewCount = MAX_VIEWS;
1045 properties->maxMultiviewInstanceIndex = INT_MAX;
1046 break;
1047 }
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1049 VkPhysicalDevicePointClippingProperties *properties =
1050 (VkPhysicalDevicePointClippingProperties*)ext;
1051 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1055 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1056 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1057 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1061 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1062 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1063 properties->minImportedHostPointerAlignment = 4096;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1067 VkPhysicalDeviceSubgroupProperties *properties =
1068 (VkPhysicalDeviceSubgroupProperties*)ext;
1069 properties->subgroupSize = 64;
1070 properties->supportedStages = VK_SHADER_STAGE_ALL;
1071 properties->supportedOperations =
1072 VK_SUBGROUP_FEATURE_BASIC_BIT |
1073 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1074 VK_SUBGROUP_FEATURE_QUAD_BIT |
1075 VK_SUBGROUP_FEATURE_VOTE_BIT;
1076 if (pdevice->rad_info.chip_class >= VI) {
1077 properties->supportedOperations |=
1078 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1079 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1080 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1081 }
1082 properties->quadOperationsInAllStages = true;
1083 break;
1084 }
1085 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1086 VkPhysicalDeviceMaintenance3Properties *properties =
1087 (VkPhysicalDeviceMaintenance3Properties*)ext;
1088 /* Make sure everything is addressable by a signed 32-bit int, and
1089 * our largest descriptors are 96 bytes. */
1090 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1091 /* Our buffer size fields allow only this much */
1092 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1093 break;
1094 }
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1096 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1097 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1098 /* GFX6-8 only support single channel min/max filter. */
1099 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1100 properties->filterMinmaxSingleComponentFormats = true;
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1104 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1105 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1106
1107 /* Shader engines. */
1108 properties->shaderEngineCount =
1109 pdevice->rad_info.max_se;
1110 properties->shaderArraysPerEngineCount =
1111 pdevice->rad_info.max_sh_per_se;
1112 properties->computeUnitsPerShaderArray =
1113 pdevice->rad_info.num_good_cu_per_sh;
1114 properties->simdPerComputeUnit = 4;
1115 properties->wavefrontsPerSimd =
1116 pdevice->rad_info.family == CHIP_TONGA ||
1117 pdevice->rad_info.family == CHIP_ICELAND ||
1118 pdevice->rad_info.family == CHIP_POLARIS10 ||
1119 pdevice->rad_info.family == CHIP_POLARIS11 ||
1120 pdevice->rad_info.family == CHIP_POLARIS12 ||
1121 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1122 properties->wavefrontSize = 64;
1123
1124 /* SGPR. */
1125 properties->sgprsPerSimd =
1126 radv_get_num_physical_sgprs(pdevice);
1127 properties->minSgprAllocation =
1128 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1129 properties->maxSgprAllocation =
1130 pdevice->rad_info.family == CHIP_TONGA ||
1131 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1132 properties->sgprAllocationGranularity =
1133 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1134
1135 /* VGPR. */
1136 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1137 properties->minVgprAllocation = 4;
1138 properties->maxVgprAllocation = 256;
1139 properties->vgprAllocationGranularity = 4;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1143 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1144 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1145 properties->maxVertexAttribDivisor = UINT32_MAX;
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1149 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1150 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1151 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1152 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1153 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1154 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1155 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1156 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1157 properties->robustBufferAccessUpdateAfterBind = false;
1158 properties->quadDivergentImplicitLod = false;
1159
1160 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1161 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1162 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1163 32 /* sampler, largest when combined with image */ +
1164 64 /* sampled image */ +
1165 64 /* storage image */);
1166 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1167 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1168 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1169 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1170 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1171 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1172 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1173 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1174 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1175 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1176 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1177 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1178 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1179 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1180 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1181 break;
1182 }
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1184 VkPhysicalDeviceProtectedMemoryProperties *properties =
1185 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1186 properties->protectedNoFault = false;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1190 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1191 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1192 properties->primitiveOverestimationSize = 0;
1193 properties->maxExtraPrimitiveOverestimationSize = 0;
1194 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1195 properties->primitiveUnderestimation = VK_FALSE;
1196 properties->conservativePointAndLineRasterization = VK_FALSE;
1197 properties->degenerateTrianglesRasterized = VK_FALSE;
1198 properties->degenerateLinesRasterized = VK_FALSE;
1199 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1200 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1201 break;
1202 }
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1204 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1205 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1206 properties->pciDomain = pdevice->bus_info.domain;
1207 properties->pciBus = pdevice->bus_info.bus;
1208 properties->pciDevice = pdevice->bus_info.dev;
1209 properties->pciFunction = pdevice->bus_info.func;
1210 break;
1211 }
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1213 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1214 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1215
1216 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1217 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1218 strcpy(driver_props->driverName, "radv");
1219
1220 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1221 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1222 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1223 " (LLVM %d.%d.%d)",
1224 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1225 MESA_LLVM_VERSION_PATCH);
1226
1227 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1228 .major = 1,
1229 .minor = 1,
1230 .subminor = 2,
1231 .patch = 0,
1232 };
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1236 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1237 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1238 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1239 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1240 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1241 properties->maxTransformFeedbackStreamDataSize = 512;
1242 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1243 properties->maxTransformFeedbackBufferDataStride = 512;
1244 properties->transformFeedbackQueries = true;
1245 properties->transformFeedbackStreamsLinesTriangles = false;
1246 properties->transformFeedbackRasterizationStreamSelect = false;
1247 properties->transformFeedbackDraw = true;
1248 break;
1249 }
1250 default:
1251 break;
1252 }
1253 }
1254 }
1255
1256 static void radv_get_physical_device_queue_family_properties(
1257 struct radv_physical_device* pdevice,
1258 uint32_t* pCount,
1259 VkQueueFamilyProperties** pQueueFamilyProperties)
1260 {
1261 int num_queue_families = 1;
1262 int idx;
1263 if (pdevice->rad_info.num_compute_rings > 0 &&
1264 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1265 num_queue_families++;
1266
1267 if (pQueueFamilyProperties == NULL) {
1268 *pCount = num_queue_families;
1269 return;
1270 }
1271
1272 if (!*pCount)
1273 return;
1274
1275 idx = 0;
1276 if (*pCount >= 1) {
1277 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1278 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1279 VK_QUEUE_COMPUTE_BIT |
1280 VK_QUEUE_TRANSFER_BIT |
1281 VK_QUEUE_SPARSE_BINDING_BIT,
1282 .queueCount = 1,
1283 .timestampValidBits = 64,
1284 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1285 };
1286 idx++;
1287 }
1288
1289 if (pdevice->rad_info.num_compute_rings > 0 &&
1290 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1291 if (*pCount > idx) {
1292 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1293 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1294 VK_QUEUE_TRANSFER_BIT |
1295 VK_QUEUE_SPARSE_BINDING_BIT,
1296 .queueCount = pdevice->rad_info.num_compute_rings,
1297 .timestampValidBits = 64,
1298 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1299 };
1300 idx++;
1301 }
1302 }
1303 *pCount = idx;
1304 }
1305
1306 void radv_GetPhysicalDeviceQueueFamilyProperties(
1307 VkPhysicalDevice physicalDevice,
1308 uint32_t* pCount,
1309 VkQueueFamilyProperties* pQueueFamilyProperties)
1310 {
1311 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1312 if (!pQueueFamilyProperties) {
1313 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1314 return;
1315 }
1316 VkQueueFamilyProperties *properties[] = {
1317 pQueueFamilyProperties + 0,
1318 pQueueFamilyProperties + 1,
1319 pQueueFamilyProperties + 2,
1320 };
1321 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1322 assert(*pCount <= 3);
1323 }
1324
1325 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1326 VkPhysicalDevice physicalDevice,
1327 uint32_t* pCount,
1328 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1329 {
1330 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1331 if (!pQueueFamilyProperties) {
1332 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1333 return;
1334 }
1335 VkQueueFamilyProperties *properties[] = {
1336 &pQueueFamilyProperties[0].queueFamilyProperties,
1337 &pQueueFamilyProperties[1].queueFamilyProperties,
1338 &pQueueFamilyProperties[2].queueFamilyProperties,
1339 };
1340 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1341 assert(*pCount <= 3);
1342 }
1343
1344 void radv_GetPhysicalDeviceMemoryProperties(
1345 VkPhysicalDevice physicalDevice,
1346 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1347 {
1348 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1349
1350 *pMemoryProperties = physical_device->memory_properties;
1351 }
1352
1353 static void
1354 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1355 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1356 {
1357 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1358 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1359 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1360 uint64_t vram_size = radv_get_vram_size(device);
1361 uint64_t gtt_size = device->rad_info.gart_size;
1362 uint64_t heap_budget, heap_usage;
1363
1364 /* For all memory heaps, the computation of budget is as follow:
1365 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1366 *
1367 * The Vulkan spec 1.1.97 says that the budget should include any
1368 * currently allocated device memory.
1369 *
1370 * Note that the application heap usages are not really accurate (eg.
1371 * in presence of shared buffers).
1372 */
1373 if (vram_size) {
1374 heap_usage = device->ws->query_value(device->ws,
1375 RADEON_ALLOCATED_VRAM);
1376
1377 heap_budget = vram_size -
1378 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1379 heap_usage;
1380
1381 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1382 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1383 }
1384
1385 if (visible_vram_size) {
1386 heap_usage = device->ws->query_value(device->ws,
1387 RADEON_ALLOCATED_VRAM_VIS);
1388
1389 heap_budget = visible_vram_size -
1390 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1391 heap_usage;
1392
1393 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1394 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1395 }
1396
1397 if (gtt_size) {
1398 heap_usage = device->ws->query_value(device->ws,
1399 RADEON_ALLOCATED_GTT);
1400
1401 heap_budget = gtt_size -
1402 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1403 heap_usage;
1404
1405 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1406 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1407 }
1408
1409 /* The heapBudget and heapUsage values must be zero for array elements
1410 * greater than or equal to
1411 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1412 */
1413 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1414 memoryBudget->heapBudget[i] = 0;
1415 memoryBudget->heapUsage[i] = 0;
1416 }
1417 }
1418
1419 void radv_GetPhysicalDeviceMemoryProperties2(
1420 VkPhysicalDevice physicalDevice,
1421 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1422 {
1423 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1424 &pMemoryProperties->memoryProperties);
1425
1426 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1427 vk_find_struct(pMemoryProperties->pNext,
1428 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1429 if (memory_budget)
1430 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1431 }
1432
1433 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1434 VkDevice _device,
1435 VkExternalMemoryHandleTypeFlagBits handleType,
1436 const void *pHostPointer,
1437 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1438 {
1439 RADV_FROM_HANDLE(radv_device, device, _device);
1440
1441 switch (handleType)
1442 {
1443 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1444 const struct radv_physical_device *physical_device = device->physical_device;
1445 uint32_t memoryTypeBits = 0;
1446 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1447 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1448 memoryTypeBits = (1 << i);
1449 break;
1450 }
1451 }
1452 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1453 return VK_SUCCESS;
1454 }
1455 default:
1456 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1457 }
1458 }
1459
1460 static enum radeon_ctx_priority
1461 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1462 {
1463 /* Default to MEDIUM when a specific global priority isn't requested */
1464 if (!pObj)
1465 return RADEON_CTX_PRIORITY_MEDIUM;
1466
1467 switch(pObj->globalPriority) {
1468 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1469 return RADEON_CTX_PRIORITY_REALTIME;
1470 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1471 return RADEON_CTX_PRIORITY_HIGH;
1472 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1473 return RADEON_CTX_PRIORITY_MEDIUM;
1474 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1475 return RADEON_CTX_PRIORITY_LOW;
1476 default:
1477 unreachable("Illegal global priority value");
1478 return RADEON_CTX_PRIORITY_INVALID;
1479 }
1480 }
1481
1482 static int
1483 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1484 uint32_t queue_family_index, int idx,
1485 VkDeviceQueueCreateFlags flags,
1486 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1487 {
1488 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1489 queue->device = device;
1490 queue->queue_family_index = queue_family_index;
1491 queue->queue_idx = idx;
1492 queue->priority = radv_get_queue_global_priority(global_priority);
1493 queue->flags = flags;
1494
1495 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1496 if (!queue->hw_ctx)
1497 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1498
1499 return VK_SUCCESS;
1500 }
1501
1502 static void
1503 radv_queue_finish(struct radv_queue *queue)
1504 {
1505 if (queue->hw_ctx)
1506 queue->device->ws->ctx_destroy(queue->hw_ctx);
1507
1508 if (queue->initial_full_flush_preamble_cs)
1509 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1510 if (queue->initial_preamble_cs)
1511 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1512 if (queue->continue_preamble_cs)
1513 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1514 if (queue->descriptor_bo)
1515 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1516 if (queue->scratch_bo)
1517 queue->device->ws->buffer_destroy(queue->scratch_bo);
1518 if (queue->esgs_ring_bo)
1519 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1520 if (queue->gsvs_ring_bo)
1521 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1522 if (queue->tess_rings_bo)
1523 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1524 if (queue->compute_scratch_bo)
1525 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1526 }
1527
1528 static void
1529 radv_bo_list_init(struct radv_bo_list *bo_list)
1530 {
1531 pthread_mutex_init(&bo_list->mutex, NULL);
1532 bo_list->list.count = bo_list->capacity = 0;
1533 bo_list->list.bos = NULL;
1534 }
1535
1536 static void
1537 radv_bo_list_finish(struct radv_bo_list *bo_list)
1538 {
1539 free(bo_list->list.bos);
1540 pthread_mutex_destroy(&bo_list->mutex);
1541 }
1542
1543 static VkResult radv_bo_list_add(struct radv_device *device,
1544 struct radeon_winsys_bo *bo)
1545 {
1546 struct radv_bo_list *bo_list = &device->bo_list;
1547
1548 if (unlikely(!device->use_global_bo_list))
1549 return VK_SUCCESS;
1550
1551 pthread_mutex_lock(&bo_list->mutex);
1552 if (bo_list->list.count == bo_list->capacity) {
1553 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1554 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1555
1556 if (!data) {
1557 pthread_mutex_unlock(&bo_list->mutex);
1558 return VK_ERROR_OUT_OF_HOST_MEMORY;
1559 }
1560
1561 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1562 bo_list->capacity = capacity;
1563 }
1564
1565 bo_list->list.bos[bo_list->list.count++] = bo;
1566 pthread_mutex_unlock(&bo_list->mutex);
1567 return VK_SUCCESS;
1568 }
1569
1570 static void radv_bo_list_remove(struct radv_device *device,
1571 struct radeon_winsys_bo *bo)
1572 {
1573 struct radv_bo_list *bo_list = &device->bo_list;
1574
1575 if (unlikely(!device->use_global_bo_list))
1576 return;
1577
1578 pthread_mutex_lock(&bo_list->mutex);
1579 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1580 if (bo_list->list.bos[i] == bo) {
1581 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1582 --bo_list->list.count;
1583 break;
1584 }
1585 }
1586 pthread_mutex_unlock(&bo_list->mutex);
1587 }
1588
1589 static void
1590 radv_device_init_gs_info(struct radv_device *device)
1591 {
1592 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1593 device->physical_device->rad_info.family);
1594 }
1595
1596 static int radv_get_device_extension_index(const char *name)
1597 {
1598 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1599 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1600 return i;
1601 }
1602 return -1;
1603 }
1604
1605 static int
1606 radv_get_int_debug_option(const char *name, int default_value)
1607 {
1608 const char *str;
1609 int result;
1610
1611 str = getenv(name);
1612 if (!str) {
1613 result = default_value;
1614 } else {
1615 char *endptr;
1616
1617 result = strtol(str, &endptr, 0);
1618 if (str == endptr) {
1619 /* No digits founs. */
1620 result = default_value;
1621 }
1622 }
1623
1624 return result;
1625 }
1626
1627 VkResult radv_CreateDevice(
1628 VkPhysicalDevice physicalDevice,
1629 const VkDeviceCreateInfo* pCreateInfo,
1630 const VkAllocationCallbacks* pAllocator,
1631 VkDevice* pDevice)
1632 {
1633 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1634 VkResult result;
1635 struct radv_device *device;
1636
1637 bool keep_shader_info = false;
1638
1639 /* Check enabled features */
1640 if (pCreateInfo->pEnabledFeatures) {
1641 VkPhysicalDeviceFeatures supported_features;
1642 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1643 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1644 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1645 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1646 for (uint32_t i = 0; i < num_features; i++) {
1647 if (enabled_feature[i] && !supported_feature[i])
1648 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1649 }
1650 }
1651
1652 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1653 sizeof(*device), 8,
1654 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1655 if (!device)
1656 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1657
1658 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1659 device->instance = physical_device->instance;
1660 device->physical_device = physical_device;
1661
1662 device->ws = physical_device->ws;
1663 if (pAllocator)
1664 device->alloc = *pAllocator;
1665 else
1666 device->alloc = physical_device->instance->alloc;
1667
1668 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1669 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1670 int index = radv_get_device_extension_index(ext_name);
1671 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1672 vk_free(&device->alloc, device);
1673 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1674 }
1675
1676 device->enabled_extensions.extensions[index] = true;
1677 }
1678
1679 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1680
1681 /* With update after bind we can't attach bo's to the command buffer
1682 * from the descriptor set anymore, so we have to use a global BO list.
1683 */
1684 device->use_global_bo_list =
1685 device->enabled_extensions.EXT_descriptor_indexing;
1686
1687 mtx_init(&device->shader_slab_mutex, mtx_plain);
1688 list_inithead(&device->shader_slabs);
1689
1690 radv_bo_list_init(&device->bo_list);
1691
1692 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1693 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1694 uint32_t qfi = queue_create->queueFamilyIndex;
1695 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1696 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1697
1698 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1699
1700 device->queues[qfi] = vk_alloc(&device->alloc,
1701 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1702 if (!device->queues[qfi]) {
1703 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1704 goto fail;
1705 }
1706
1707 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1708
1709 device->queue_count[qfi] = queue_create->queueCount;
1710
1711 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1712 result = radv_queue_init(device, &device->queues[qfi][q],
1713 qfi, q, queue_create->flags,
1714 global_priority);
1715 if (result != VK_SUCCESS)
1716 goto fail;
1717 }
1718 }
1719
1720 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1721 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1722
1723 /* Disabled and not implemented for now. */
1724 device->dfsm_allowed = device->pbb_allowed &&
1725 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1726 device->physical_device->rad_info.family == CHIP_RAVEN2);
1727
1728 #ifdef ANDROID
1729 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1730 #endif
1731
1732 /* The maximum number of scratch waves. Scratch space isn't divided
1733 * evenly between CUs. The number is only a function of the number of CUs.
1734 * We can decrease the constant to decrease the scratch buffer size.
1735 *
1736 * sctx->scratch_waves must be >= the maximum possible size of
1737 * 1 threadgroup, so that the hw doesn't hang from being unable
1738 * to start any.
1739 *
1740 * The recommended value is 4 per CU at most. Higher numbers don't
1741 * bring much benefit, but they still occupy chip resources (think
1742 * async compute). I've seen ~2% performance difference between 4 and 32.
1743 */
1744 uint32_t max_threads_per_block = 2048;
1745 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1746 max_threads_per_block / 64);
1747
1748 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1749
1750 if (device->physical_device->rad_info.chip_class >= CIK) {
1751 /* If the KMD allows it (there is a KMD hw register for it),
1752 * allow launching waves out-of-order.
1753 */
1754 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1755 }
1756
1757 radv_device_init_gs_info(device);
1758
1759 device->tess_offchip_block_dw_size =
1760 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1761 device->has_distributed_tess =
1762 device->physical_device->rad_info.chip_class >= VI &&
1763 device->physical_device->rad_info.max_se >= 2;
1764
1765 if (getenv("RADV_TRACE_FILE")) {
1766 const char *filename = getenv("RADV_TRACE_FILE");
1767
1768 keep_shader_info = true;
1769
1770 if (!radv_init_trace(device))
1771 goto fail;
1772
1773 fprintf(stderr, "*****************************************************************************\n");
1774 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1775 fprintf(stderr, "*****************************************************************************\n");
1776
1777 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1778 radv_dump_enabled_options(device, stderr);
1779 }
1780
1781 device->keep_shader_info = keep_shader_info;
1782
1783 result = radv_device_init_meta(device);
1784 if (result != VK_SUCCESS)
1785 goto fail;
1786
1787 radv_device_init_msaa(device);
1788
1789 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1790 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1791 switch (family) {
1792 case RADV_QUEUE_GENERAL:
1793 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1794 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1795 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1796 break;
1797 case RADV_QUEUE_COMPUTE:
1798 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1799 radeon_emit(device->empty_cs[family], 0);
1800 break;
1801 }
1802 device->ws->cs_finalize(device->empty_cs[family]);
1803 }
1804
1805 if (device->physical_device->rad_info.chip_class >= CIK)
1806 cik_create_gfx_config(device);
1807
1808 VkPipelineCacheCreateInfo ci;
1809 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1810 ci.pNext = NULL;
1811 ci.flags = 0;
1812 ci.pInitialData = NULL;
1813 ci.initialDataSize = 0;
1814 VkPipelineCache pc;
1815 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1816 &ci, NULL, &pc);
1817 if (result != VK_SUCCESS)
1818 goto fail_meta;
1819
1820 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1821
1822 device->force_aniso =
1823 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1824 if (device->force_aniso >= 0) {
1825 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1826 1 << util_logbase2(device->force_aniso));
1827 }
1828
1829 *pDevice = radv_device_to_handle(device);
1830 return VK_SUCCESS;
1831
1832 fail_meta:
1833 radv_device_finish_meta(device);
1834 fail:
1835 radv_bo_list_finish(&device->bo_list);
1836
1837 if (device->trace_bo)
1838 device->ws->buffer_destroy(device->trace_bo);
1839
1840 if (device->gfx_init)
1841 device->ws->buffer_destroy(device->gfx_init);
1842
1843 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1844 for (unsigned q = 0; q < device->queue_count[i]; q++)
1845 radv_queue_finish(&device->queues[i][q]);
1846 if (device->queue_count[i])
1847 vk_free(&device->alloc, device->queues[i]);
1848 }
1849
1850 vk_free(&device->alloc, device);
1851 return result;
1852 }
1853
1854 void radv_DestroyDevice(
1855 VkDevice _device,
1856 const VkAllocationCallbacks* pAllocator)
1857 {
1858 RADV_FROM_HANDLE(radv_device, device, _device);
1859
1860 if (!device)
1861 return;
1862
1863 if (device->trace_bo)
1864 device->ws->buffer_destroy(device->trace_bo);
1865
1866 if (device->gfx_init)
1867 device->ws->buffer_destroy(device->gfx_init);
1868
1869 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1870 for (unsigned q = 0; q < device->queue_count[i]; q++)
1871 radv_queue_finish(&device->queues[i][q]);
1872 if (device->queue_count[i])
1873 vk_free(&device->alloc, device->queues[i]);
1874 if (device->empty_cs[i])
1875 device->ws->cs_destroy(device->empty_cs[i]);
1876 }
1877 radv_device_finish_meta(device);
1878
1879 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1880 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1881
1882 radv_destroy_shader_slabs(device);
1883
1884 radv_bo_list_finish(&device->bo_list);
1885 vk_free(&device->alloc, device);
1886 }
1887
1888 VkResult radv_EnumerateInstanceLayerProperties(
1889 uint32_t* pPropertyCount,
1890 VkLayerProperties* pProperties)
1891 {
1892 if (pProperties == NULL) {
1893 *pPropertyCount = 0;
1894 return VK_SUCCESS;
1895 }
1896
1897 /* None supported at this time */
1898 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1899 }
1900
1901 VkResult radv_EnumerateDeviceLayerProperties(
1902 VkPhysicalDevice physicalDevice,
1903 uint32_t* pPropertyCount,
1904 VkLayerProperties* pProperties)
1905 {
1906 if (pProperties == NULL) {
1907 *pPropertyCount = 0;
1908 return VK_SUCCESS;
1909 }
1910
1911 /* None supported at this time */
1912 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1913 }
1914
1915 void radv_GetDeviceQueue2(
1916 VkDevice _device,
1917 const VkDeviceQueueInfo2* pQueueInfo,
1918 VkQueue* pQueue)
1919 {
1920 RADV_FROM_HANDLE(radv_device, device, _device);
1921 struct radv_queue *queue;
1922
1923 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1924 if (pQueueInfo->flags != queue->flags) {
1925 /* From the Vulkan 1.1.70 spec:
1926 *
1927 * "The queue returned by vkGetDeviceQueue2 must have the same
1928 * flags value from this structure as that used at device
1929 * creation time in a VkDeviceQueueCreateInfo instance. If no
1930 * matching flags were specified at device creation time then
1931 * pQueue will return VK_NULL_HANDLE."
1932 */
1933 *pQueue = VK_NULL_HANDLE;
1934 return;
1935 }
1936
1937 *pQueue = radv_queue_to_handle(queue);
1938 }
1939
1940 void radv_GetDeviceQueue(
1941 VkDevice _device,
1942 uint32_t queueFamilyIndex,
1943 uint32_t queueIndex,
1944 VkQueue* pQueue)
1945 {
1946 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1947 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1948 .queueFamilyIndex = queueFamilyIndex,
1949 .queueIndex = queueIndex
1950 };
1951
1952 radv_GetDeviceQueue2(_device, &info, pQueue);
1953 }
1954
1955 static void
1956 fill_geom_tess_rings(struct radv_queue *queue,
1957 uint32_t *map,
1958 bool add_sample_positions,
1959 uint32_t esgs_ring_size,
1960 struct radeon_winsys_bo *esgs_ring_bo,
1961 uint32_t gsvs_ring_size,
1962 struct radeon_winsys_bo *gsvs_ring_bo,
1963 uint32_t tess_factor_ring_size,
1964 uint32_t tess_offchip_ring_offset,
1965 uint32_t tess_offchip_ring_size,
1966 struct radeon_winsys_bo *tess_rings_bo)
1967 {
1968 uint32_t *desc = &map[4];
1969
1970 if (esgs_ring_bo) {
1971 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
1972
1973 /* stride 0, num records - size, add tid, swizzle, elsize4,
1974 index stride 64 */
1975 desc[0] = esgs_va;
1976 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1977 S_008F04_STRIDE(0) |
1978 S_008F04_SWIZZLE_ENABLE(true);
1979 desc[2] = esgs_ring_size;
1980 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1981 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1982 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1983 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1984 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1985 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1986 S_008F0C_ELEMENT_SIZE(1) |
1987 S_008F0C_INDEX_STRIDE(3) |
1988 S_008F0C_ADD_TID_ENABLE(true);
1989
1990 /* GS entry for ES->GS ring */
1991 /* stride 0, num records - size, elsize0,
1992 index stride 0 */
1993 desc[4] = esgs_va;
1994 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1995 S_008F04_STRIDE(0) |
1996 S_008F04_SWIZZLE_ENABLE(false);
1997 desc[6] = esgs_ring_size;
1998 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1999 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2000 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2001 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2002 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2003 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2004 S_008F0C_ELEMENT_SIZE(0) |
2005 S_008F0C_INDEX_STRIDE(0) |
2006 S_008F0C_ADD_TID_ENABLE(false);
2007 }
2008
2009 desc += 8;
2010
2011 if (gsvs_ring_bo) {
2012 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2013
2014 /* VS entry for GS->VS ring */
2015 /* stride 0, num records - size, elsize0,
2016 index stride 0 */
2017 desc[0] = gsvs_va;
2018 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2019 S_008F04_STRIDE(0) |
2020 S_008F04_SWIZZLE_ENABLE(false);
2021 desc[2] = gsvs_ring_size;
2022 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2023 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2024 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2025 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2026 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2027 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2028 S_008F0C_ELEMENT_SIZE(0) |
2029 S_008F0C_INDEX_STRIDE(0) |
2030 S_008F0C_ADD_TID_ENABLE(false);
2031
2032 /* stride gsvs_itemsize, num records 64
2033 elsize 4, index stride 16 */
2034 /* shader will patch stride and desc[2] */
2035 desc[4] = gsvs_va;
2036 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2037 S_008F04_STRIDE(0) |
2038 S_008F04_SWIZZLE_ENABLE(true);
2039 desc[6] = 0;
2040 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2041 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2042 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2043 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2044 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2045 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2046 S_008F0C_ELEMENT_SIZE(1) |
2047 S_008F0C_INDEX_STRIDE(1) |
2048 S_008F0C_ADD_TID_ENABLE(true);
2049 }
2050
2051 desc += 8;
2052
2053 if (tess_rings_bo) {
2054 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2055 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2056
2057 desc[0] = tess_va;
2058 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2059 S_008F04_STRIDE(0) |
2060 S_008F04_SWIZZLE_ENABLE(false);
2061 desc[2] = tess_factor_ring_size;
2062 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2063 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2064 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2065 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2066 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2067 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2068 S_008F0C_ELEMENT_SIZE(0) |
2069 S_008F0C_INDEX_STRIDE(0) |
2070 S_008F0C_ADD_TID_ENABLE(false);
2071
2072 desc[4] = tess_offchip_va;
2073 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2074 S_008F04_STRIDE(0) |
2075 S_008F04_SWIZZLE_ENABLE(false);
2076 desc[6] = tess_offchip_ring_size;
2077 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2078 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2079 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2080 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2081 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2082 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2083 S_008F0C_ELEMENT_SIZE(0) |
2084 S_008F0C_INDEX_STRIDE(0) |
2085 S_008F0C_ADD_TID_ENABLE(false);
2086 }
2087
2088 desc += 8;
2089
2090 if (add_sample_positions) {
2091 /* add sample positions after all rings */
2092 memcpy(desc, queue->device->sample_locations_1x, 8);
2093 desc += 2;
2094 memcpy(desc, queue->device->sample_locations_2x, 16);
2095 desc += 4;
2096 memcpy(desc, queue->device->sample_locations_4x, 32);
2097 desc += 8;
2098 memcpy(desc, queue->device->sample_locations_8x, 64);
2099 }
2100 }
2101
2102 static unsigned
2103 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2104 {
2105 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2106 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2107 device->physical_device->rad_info.family != CHIP_STONEY;
2108 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2109 unsigned max_offchip_buffers;
2110 unsigned offchip_granularity;
2111 unsigned hs_offchip_param;
2112
2113 /*
2114 * Per RadeonSI:
2115 * This must be one less than the maximum number due to a hw limitation.
2116 * Various hardware bugs in SI, CIK, and GFX9 need this.
2117 *
2118 * Per AMDVLK:
2119 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2120 * Gfx7 should limit max_offchip_buffers to 508
2121 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2122 *
2123 * Follow AMDVLK here.
2124 */
2125 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2126 device->physical_device->rad_info.chip_class == CIK ||
2127 device->physical_device->rad_info.chip_class == SI)
2128 --max_offchip_buffers_per_se;
2129
2130 max_offchip_buffers = max_offchip_buffers_per_se *
2131 device->physical_device->rad_info.max_se;
2132
2133 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2134 * around by setting 4K granularity.
2135 */
2136 if (device->tess_offchip_block_dw_size == 4096) {
2137 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2138 offchip_granularity = V_03093C_X_4K_DWORDS;
2139 } else {
2140 assert(device->tess_offchip_block_dw_size == 8192);
2141 offchip_granularity = V_03093C_X_8K_DWORDS;
2142 }
2143
2144 switch (device->physical_device->rad_info.chip_class) {
2145 case SI:
2146 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2147 break;
2148 case CIK:
2149 case VI:
2150 case GFX9:
2151 default:
2152 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2153 break;
2154 }
2155
2156 *max_offchip_buffers_p = max_offchip_buffers;
2157 if (device->physical_device->rad_info.chip_class >= CIK) {
2158 if (device->physical_device->rad_info.chip_class >= VI)
2159 --max_offchip_buffers;
2160 hs_offchip_param =
2161 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2162 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2163 } else {
2164 hs_offchip_param =
2165 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2166 }
2167 return hs_offchip_param;
2168 }
2169
2170 static void
2171 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2172 struct radeon_winsys_bo *esgs_ring_bo,
2173 uint32_t esgs_ring_size,
2174 struct radeon_winsys_bo *gsvs_ring_bo,
2175 uint32_t gsvs_ring_size)
2176 {
2177 if (!esgs_ring_bo && !gsvs_ring_bo)
2178 return;
2179
2180 if (esgs_ring_bo)
2181 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2182
2183 if (gsvs_ring_bo)
2184 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2185
2186 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2187 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2188 radeon_emit(cs, esgs_ring_size >> 8);
2189 radeon_emit(cs, gsvs_ring_size >> 8);
2190 } else {
2191 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2192 radeon_emit(cs, esgs_ring_size >> 8);
2193 radeon_emit(cs, gsvs_ring_size >> 8);
2194 }
2195 }
2196
2197 static void
2198 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2199 unsigned hs_offchip_param, unsigned tf_ring_size,
2200 struct radeon_winsys_bo *tess_rings_bo)
2201 {
2202 uint64_t tf_va;
2203
2204 if (!tess_rings_bo)
2205 return;
2206
2207 tf_va = radv_buffer_get_va(tess_rings_bo);
2208
2209 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2210
2211 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2212 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2213 S_030938_SIZE(tf_ring_size / 4));
2214 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2215 tf_va >> 8);
2216 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2217 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2218 S_030944_BASE_HI(tf_va >> 40));
2219 }
2220 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2221 hs_offchip_param);
2222 } else {
2223 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2224 S_008988_SIZE(tf_ring_size / 4));
2225 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2226 tf_va >> 8);
2227 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2228 hs_offchip_param);
2229 }
2230 }
2231
2232 static void
2233 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2234 struct radeon_winsys_bo *compute_scratch_bo)
2235 {
2236 uint64_t scratch_va;
2237
2238 if (!compute_scratch_bo)
2239 return;
2240
2241 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2242
2243 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2244
2245 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2246 radeon_emit(cs, scratch_va);
2247 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2248 S_008F04_SWIZZLE_ENABLE(1));
2249 }
2250
2251 static void
2252 radv_emit_global_shader_pointers(struct radv_queue *queue,
2253 struct radeon_cmdbuf *cs,
2254 struct radeon_winsys_bo *descriptor_bo)
2255 {
2256 uint64_t va;
2257
2258 if (!descriptor_bo)
2259 return;
2260
2261 va = radv_buffer_get_va(descriptor_bo);
2262
2263 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2264
2265 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2266 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2267 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2268 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2269 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2270
2271 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2272 radv_emit_shader_pointer(queue->device, cs, regs[i],
2273 va, true);
2274 }
2275 } else {
2276 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2277 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2278 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2279 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2280 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2281 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2282
2283 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2284 radv_emit_shader_pointer(queue->device, cs, regs[i],
2285 va, true);
2286 }
2287 }
2288 }
2289
2290 static void
2291 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2292 {
2293 struct radv_device *device = queue->device;
2294
2295 if (device->gfx_init) {
2296 uint64_t va = radv_buffer_get_va(device->gfx_init);
2297
2298 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2299 radeon_emit(cs, va);
2300 radeon_emit(cs, va >> 32);
2301 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2302
2303 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2304 } else {
2305 struct radv_physical_device *physical_device = device->physical_device;
2306 si_emit_graphics(physical_device, cs);
2307 }
2308 }
2309
2310 static void
2311 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2312 {
2313 struct radv_physical_device *physical_device = queue->device->physical_device;
2314 si_emit_compute(physical_device, cs);
2315 }
2316
2317 static VkResult
2318 radv_get_preamble_cs(struct radv_queue *queue,
2319 uint32_t scratch_size,
2320 uint32_t compute_scratch_size,
2321 uint32_t esgs_ring_size,
2322 uint32_t gsvs_ring_size,
2323 bool needs_tess_rings,
2324 bool needs_sample_positions,
2325 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2326 struct radeon_cmdbuf **initial_preamble_cs,
2327 struct radeon_cmdbuf **continue_preamble_cs)
2328 {
2329 struct radeon_winsys_bo *scratch_bo = NULL;
2330 struct radeon_winsys_bo *descriptor_bo = NULL;
2331 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2332 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2333 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2334 struct radeon_winsys_bo *tess_rings_bo = NULL;
2335 struct radeon_cmdbuf *dest_cs[3] = {0};
2336 bool add_tess_rings = false, add_sample_positions = false;
2337 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2338 unsigned max_offchip_buffers;
2339 unsigned hs_offchip_param = 0;
2340 unsigned tess_offchip_ring_offset;
2341 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2342 if (!queue->has_tess_rings) {
2343 if (needs_tess_rings)
2344 add_tess_rings = true;
2345 }
2346 if (!queue->has_sample_positions) {
2347 if (needs_sample_positions)
2348 add_sample_positions = true;
2349 }
2350 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2351 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2352 &max_offchip_buffers);
2353 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2354 tess_offchip_ring_size = max_offchip_buffers *
2355 queue->device->tess_offchip_block_dw_size * 4;
2356
2357 if (scratch_size <= queue->scratch_size &&
2358 compute_scratch_size <= queue->compute_scratch_size &&
2359 esgs_ring_size <= queue->esgs_ring_size &&
2360 gsvs_ring_size <= queue->gsvs_ring_size &&
2361 !add_tess_rings && !add_sample_positions &&
2362 queue->initial_preamble_cs) {
2363 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2364 *initial_preamble_cs = queue->initial_preamble_cs;
2365 *continue_preamble_cs = queue->continue_preamble_cs;
2366 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2367 *continue_preamble_cs = NULL;
2368 return VK_SUCCESS;
2369 }
2370
2371 if (scratch_size > queue->scratch_size) {
2372 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2373 scratch_size,
2374 4096,
2375 RADEON_DOMAIN_VRAM,
2376 ring_bo_flags);
2377 if (!scratch_bo)
2378 goto fail;
2379 } else
2380 scratch_bo = queue->scratch_bo;
2381
2382 if (compute_scratch_size > queue->compute_scratch_size) {
2383 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2384 compute_scratch_size,
2385 4096,
2386 RADEON_DOMAIN_VRAM,
2387 ring_bo_flags);
2388 if (!compute_scratch_bo)
2389 goto fail;
2390
2391 } else
2392 compute_scratch_bo = queue->compute_scratch_bo;
2393
2394 if (esgs_ring_size > queue->esgs_ring_size) {
2395 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2396 esgs_ring_size,
2397 4096,
2398 RADEON_DOMAIN_VRAM,
2399 ring_bo_flags);
2400 if (!esgs_ring_bo)
2401 goto fail;
2402 } else {
2403 esgs_ring_bo = queue->esgs_ring_bo;
2404 esgs_ring_size = queue->esgs_ring_size;
2405 }
2406
2407 if (gsvs_ring_size > queue->gsvs_ring_size) {
2408 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2409 gsvs_ring_size,
2410 4096,
2411 RADEON_DOMAIN_VRAM,
2412 ring_bo_flags);
2413 if (!gsvs_ring_bo)
2414 goto fail;
2415 } else {
2416 gsvs_ring_bo = queue->gsvs_ring_bo;
2417 gsvs_ring_size = queue->gsvs_ring_size;
2418 }
2419
2420 if (add_tess_rings) {
2421 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2422 tess_offchip_ring_offset + tess_offchip_ring_size,
2423 256,
2424 RADEON_DOMAIN_VRAM,
2425 ring_bo_flags);
2426 if (!tess_rings_bo)
2427 goto fail;
2428 } else {
2429 tess_rings_bo = queue->tess_rings_bo;
2430 }
2431
2432 if (scratch_bo != queue->scratch_bo ||
2433 esgs_ring_bo != queue->esgs_ring_bo ||
2434 gsvs_ring_bo != queue->gsvs_ring_bo ||
2435 tess_rings_bo != queue->tess_rings_bo ||
2436 add_sample_positions) {
2437 uint32_t size = 0;
2438 if (gsvs_ring_bo || esgs_ring_bo ||
2439 tess_rings_bo || add_sample_positions) {
2440 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2441 if (add_sample_positions)
2442 size += 128; /* 64+32+16+8 = 120 bytes */
2443 }
2444 else if (scratch_bo)
2445 size = 8; /* 2 dword */
2446
2447 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2448 size,
2449 4096,
2450 RADEON_DOMAIN_VRAM,
2451 RADEON_FLAG_CPU_ACCESS |
2452 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2453 RADEON_FLAG_READ_ONLY);
2454 if (!descriptor_bo)
2455 goto fail;
2456 } else
2457 descriptor_bo = queue->descriptor_bo;
2458
2459 if (descriptor_bo != queue->descriptor_bo) {
2460 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2461
2462 if (scratch_bo) {
2463 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2464 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2465 S_008F04_SWIZZLE_ENABLE(1);
2466 map[0] = scratch_va;
2467 map[1] = rsrc1;
2468 }
2469
2470 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2471 fill_geom_tess_rings(queue, map, add_sample_positions,
2472 esgs_ring_size, esgs_ring_bo,
2473 gsvs_ring_size, gsvs_ring_bo,
2474 tess_factor_ring_size,
2475 tess_offchip_ring_offset,
2476 tess_offchip_ring_size,
2477 tess_rings_bo);
2478
2479 queue->device->ws->buffer_unmap(descriptor_bo);
2480 }
2481
2482 for(int i = 0; i < 3; ++i) {
2483 struct radeon_cmdbuf *cs = NULL;
2484 cs = queue->device->ws->cs_create(queue->device->ws,
2485 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2486 if (!cs)
2487 goto fail;
2488
2489 dest_cs[i] = cs;
2490
2491 if (scratch_bo)
2492 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2493
2494 /* Emit initial configuration. */
2495 switch (queue->queue_family_index) {
2496 case RADV_QUEUE_GENERAL:
2497 radv_init_graphics_state(cs, queue);
2498 break;
2499 case RADV_QUEUE_COMPUTE:
2500 radv_init_compute_state(cs, queue);
2501 break;
2502 case RADV_QUEUE_TRANSFER:
2503 break;
2504 }
2505
2506 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2507 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2508 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2509 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2510 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2511 }
2512
2513 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2514 gsvs_ring_bo, gsvs_ring_size);
2515 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2516 tess_factor_ring_size, tess_rings_bo);
2517 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2518 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2519
2520 if (i == 0) {
2521 si_cs_emit_cache_flush(cs,
2522 queue->device->physical_device->rad_info.chip_class,
2523 NULL, 0,
2524 queue->queue_family_index == RING_COMPUTE &&
2525 queue->device->physical_device->rad_info.chip_class >= CIK,
2526 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2527 RADV_CMD_FLAG_INV_ICACHE |
2528 RADV_CMD_FLAG_INV_SMEM_L1 |
2529 RADV_CMD_FLAG_INV_VMEM_L1 |
2530 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2531 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2532 } else if (i == 1) {
2533 si_cs_emit_cache_flush(cs,
2534 queue->device->physical_device->rad_info.chip_class,
2535 NULL, 0,
2536 queue->queue_family_index == RING_COMPUTE &&
2537 queue->device->physical_device->rad_info.chip_class >= CIK,
2538 RADV_CMD_FLAG_INV_ICACHE |
2539 RADV_CMD_FLAG_INV_SMEM_L1 |
2540 RADV_CMD_FLAG_INV_VMEM_L1 |
2541 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2542 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2543 }
2544
2545 if (!queue->device->ws->cs_finalize(cs))
2546 goto fail;
2547 }
2548
2549 if (queue->initial_full_flush_preamble_cs)
2550 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2551
2552 if (queue->initial_preamble_cs)
2553 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2554
2555 if (queue->continue_preamble_cs)
2556 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2557
2558 queue->initial_full_flush_preamble_cs = dest_cs[0];
2559 queue->initial_preamble_cs = dest_cs[1];
2560 queue->continue_preamble_cs = dest_cs[2];
2561
2562 if (scratch_bo != queue->scratch_bo) {
2563 if (queue->scratch_bo)
2564 queue->device->ws->buffer_destroy(queue->scratch_bo);
2565 queue->scratch_bo = scratch_bo;
2566 queue->scratch_size = scratch_size;
2567 }
2568
2569 if (compute_scratch_bo != queue->compute_scratch_bo) {
2570 if (queue->compute_scratch_bo)
2571 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2572 queue->compute_scratch_bo = compute_scratch_bo;
2573 queue->compute_scratch_size = compute_scratch_size;
2574 }
2575
2576 if (esgs_ring_bo != queue->esgs_ring_bo) {
2577 if (queue->esgs_ring_bo)
2578 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2579 queue->esgs_ring_bo = esgs_ring_bo;
2580 queue->esgs_ring_size = esgs_ring_size;
2581 }
2582
2583 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2584 if (queue->gsvs_ring_bo)
2585 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2586 queue->gsvs_ring_bo = gsvs_ring_bo;
2587 queue->gsvs_ring_size = gsvs_ring_size;
2588 }
2589
2590 if (tess_rings_bo != queue->tess_rings_bo) {
2591 queue->tess_rings_bo = tess_rings_bo;
2592 queue->has_tess_rings = true;
2593 }
2594
2595 if (descriptor_bo != queue->descriptor_bo) {
2596 if (queue->descriptor_bo)
2597 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2598
2599 queue->descriptor_bo = descriptor_bo;
2600 }
2601
2602 if (add_sample_positions)
2603 queue->has_sample_positions = true;
2604
2605 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2606 *initial_preamble_cs = queue->initial_preamble_cs;
2607 *continue_preamble_cs = queue->continue_preamble_cs;
2608 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2609 *continue_preamble_cs = NULL;
2610 return VK_SUCCESS;
2611 fail:
2612 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2613 if (dest_cs[i])
2614 queue->device->ws->cs_destroy(dest_cs[i]);
2615 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2616 queue->device->ws->buffer_destroy(descriptor_bo);
2617 if (scratch_bo && scratch_bo != queue->scratch_bo)
2618 queue->device->ws->buffer_destroy(scratch_bo);
2619 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2620 queue->device->ws->buffer_destroy(compute_scratch_bo);
2621 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2622 queue->device->ws->buffer_destroy(esgs_ring_bo);
2623 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2624 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2625 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2626 queue->device->ws->buffer_destroy(tess_rings_bo);
2627 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2628 }
2629
2630 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2631 struct radv_winsys_sem_counts *counts,
2632 int num_sems,
2633 const VkSemaphore *sems,
2634 VkFence _fence,
2635 bool reset_temp)
2636 {
2637 int syncobj_idx = 0, sem_idx = 0;
2638
2639 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2640 return VK_SUCCESS;
2641
2642 for (uint32_t i = 0; i < num_sems; i++) {
2643 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2644
2645 if (sem->temp_syncobj || sem->syncobj)
2646 counts->syncobj_count++;
2647 else
2648 counts->sem_count++;
2649 }
2650
2651 if (_fence != VK_NULL_HANDLE) {
2652 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2653 if (fence->temp_syncobj || fence->syncobj)
2654 counts->syncobj_count++;
2655 }
2656
2657 if (counts->syncobj_count) {
2658 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2659 if (!counts->syncobj)
2660 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2661 }
2662
2663 if (counts->sem_count) {
2664 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2665 if (!counts->sem) {
2666 free(counts->syncobj);
2667 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2668 }
2669 }
2670
2671 for (uint32_t i = 0; i < num_sems; i++) {
2672 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2673
2674 if (sem->temp_syncobj) {
2675 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2676 }
2677 else if (sem->syncobj)
2678 counts->syncobj[syncobj_idx++] = sem->syncobj;
2679 else {
2680 assert(sem->sem);
2681 counts->sem[sem_idx++] = sem->sem;
2682 }
2683 }
2684
2685 if (_fence != VK_NULL_HANDLE) {
2686 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2687 if (fence->temp_syncobj)
2688 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2689 else if (fence->syncobj)
2690 counts->syncobj[syncobj_idx++] = fence->syncobj;
2691 }
2692
2693 return VK_SUCCESS;
2694 }
2695
2696 static void
2697 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2698 {
2699 free(sem_info->wait.syncobj);
2700 free(sem_info->wait.sem);
2701 free(sem_info->signal.syncobj);
2702 free(sem_info->signal.sem);
2703 }
2704
2705
2706 static void radv_free_temp_syncobjs(struct radv_device *device,
2707 int num_sems,
2708 const VkSemaphore *sems)
2709 {
2710 for (uint32_t i = 0; i < num_sems; i++) {
2711 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2712
2713 if (sem->temp_syncobj) {
2714 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2715 sem->temp_syncobj = 0;
2716 }
2717 }
2718 }
2719
2720 static VkResult
2721 radv_alloc_sem_info(struct radv_instance *instance,
2722 struct radv_winsys_sem_info *sem_info,
2723 int num_wait_sems,
2724 const VkSemaphore *wait_sems,
2725 int num_signal_sems,
2726 const VkSemaphore *signal_sems,
2727 VkFence fence)
2728 {
2729 VkResult ret;
2730 memset(sem_info, 0, sizeof(*sem_info));
2731
2732 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2733 if (ret)
2734 return ret;
2735 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2736 if (ret)
2737 radv_free_sem_info(sem_info);
2738
2739 /* caller can override these */
2740 sem_info->cs_emit_wait = true;
2741 sem_info->cs_emit_signal = true;
2742 return ret;
2743 }
2744
2745 /* Signals fence as soon as all the work currently put on queue is done. */
2746 static VkResult radv_signal_fence(struct radv_queue *queue,
2747 struct radv_fence *fence)
2748 {
2749 int ret;
2750 VkResult result;
2751 struct radv_winsys_sem_info sem_info;
2752
2753 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2754 radv_fence_to_handle(fence));
2755 if (result != VK_SUCCESS)
2756 return result;
2757
2758 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2759 &queue->device->empty_cs[queue->queue_family_index],
2760 1, NULL, NULL, &sem_info, NULL,
2761 false, fence->fence);
2762 radv_free_sem_info(&sem_info);
2763
2764 if (ret)
2765 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2766
2767 return VK_SUCCESS;
2768 }
2769
2770 VkResult radv_QueueSubmit(
2771 VkQueue _queue,
2772 uint32_t submitCount,
2773 const VkSubmitInfo* pSubmits,
2774 VkFence _fence)
2775 {
2776 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2777 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2778 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2779 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2780 int ret;
2781 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2782 uint32_t scratch_size = 0;
2783 uint32_t compute_scratch_size = 0;
2784 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2785 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2786 VkResult result;
2787 bool fence_emitted = false;
2788 bool tess_rings_needed = false;
2789 bool sample_positions_needed = false;
2790
2791 /* Do this first so failing to allocate scratch buffers can't result in
2792 * partially executed submissions. */
2793 for (uint32_t i = 0; i < submitCount; i++) {
2794 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2795 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2796 pSubmits[i].pCommandBuffers[j]);
2797
2798 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2799 compute_scratch_size = MAX2(compute_scratch_size,
2800 cmd_buffer->compute_scratch_size_needed);
2801 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2802 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2803 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2804 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2805 }
2806 }
2807
2808 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2809 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2810 sample_positions_needed, &initial_flush_preamble_cs,
2811 &initial_preamble_cs, &continue_preamble_cs);
2812 if (result != VK_SUCCESS)
2813 return result;
2814
2815 for (uint32_t i = 0; i < submitCount; i++) {
2816 struct radeon_cmdbuf **cs_array;
2817 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2818 bool can_patch = true;
2819 uint32_t advance;
2820 struct radv_winsys_sem_info sem_info;
2821
2822 result = radv_alloc_sem_info(queue->device->instance,
2823 &sem_info,
2824 pSubmits[i].waitSemaphoreCount,
2825 pSubmits[i].pWaitSemaphores,
2826 pSubmits[i].signalSemaphoreCount,
2827 pSubmits[i].pSignalSemaphores,
2828 _fence);
2829 if (result != VK_SUCCESS)
2830 return result;
2831
2832 if (!pSubmits[i].commandBufferCount) {
2833 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2834 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2835 &queue->device->empty_cs[queue->queue_family_index],
2836 1, NULL, NULL,
2837 &sem_info, NULL,
2838 false, base_fence);
2839 if (ret) {
2840 radv_loge("failed to submit CS %d\n", i);
2841 abort();
2842 }
2843 fence_emitted = true;
2844 }
2845 radv_free_sem_info(&sem_info);
2846 continue;
2847 }
2848
2849 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2850 (pSubmits[i].commandBufferCount));
2851
2852 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2853 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2854 pSubmits[i].pCommandBuffers[j]);
2855 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2856
2857 cs_array[j] = cmd_buffer->cs;
2858 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2859 can_patch = false;
2860
2861 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2862 }
2863
2864 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2865 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2866 const struct radv_winsys_bo_list *bo_list = NULL;
2867
2868 advance = MIN2(max_cs_submission,
2869 pSubmits[i].commandBufferCount - j);
2870
2871 if (queue->device->trace_bo)
2872 *queue->device->trace_id_ptr = 0;
2873
2874 sem_info.cs_emit_wait = j == 0;
2875 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2876
2877 if (unlikely(queue->device->use_global_bo_list)) {
2878 pthread_mutex_lock(&queue->device->bo_list.mutex);
2879 bo_list = &queue->device->bo_list.list;
2880 }
2881
2882 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2883 advance, initial_preamble, continue_preamble_cs,
2884 &sem_info, bo_list,
2885 can_patch, base_fence);
2886
2887 if (unlikely(queue->device->use_global_bo_list))
2888 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2889
2890 if (ret) {
2891 radv_loge("failed to submit CS %d\n", i);
2892 abort();
2893 }
2894 fence_emitted = true;
2895 if (queue->device->trace_bo) {
2896 radv_check_gpu_hangs(queue, cs_array[j]);
2897 }
2898 }
2899
2900 radv_free_temp_syncobjs(queue->device,
2901 pSubmits[i].waitSemaphoreCount,
2902 pSubmits[i].pWaitSemaphores);
2903 radv_free_sem_info(&sem_info);
2904 free(cs_array);
2905 }
2906
2907 if (fence) {
2908 if (!fence_emitted) {
2909 result = radv_signal_fence(queue, fence);
2910 if (result != VK_SUCCESS)
2911 return result;
2912 }
2913 fence->submitted = true;
2914 }
2915
2916 return VK_SUCCESS;
2917 }
2918
2919 VkResult radv_QueueWaitIdle(
2920 VkQueue _queue)
2921 {
2922 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2923
2924 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2925 radv_queue_family_to_ring(queue->queue_family_index),
2926 queue->queue_idx);
2927 return VK_SUCCESS;
2928 }
2929
2930 VkResult radv_DeviceWaitIdle(
2931 VkDevice _device)
2932 {
2933 RADV_FROM_HANDLE(radv_device, device, _device);
2934
2935 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2936 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2937 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2938 }
2939 }
2940 return VK_SUCCESS;
2941 }
2942
2943 VkResult radv_EnumerateInstanceExtensionProperties(
2944 const char* pLayerName,
2945 uint32_t* pPropertyCount,
2946 VkExtensionProperties* pProperties)
2947 {
2948 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2949
2950 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2951 if (radv_supported_instance_extensions.extensions[i]) {
2952 vk_outarray_append(&out, prop) {
2953 *prop = radv_instance_extensions[i];
2954 }
2955 }
2956 }
2957
2958 return vk_outarray_status(&out);
2959 }
2960
2961 VkResult radv_EnumerateDeviceExtensionProperties(
2962 VkPhysicalDevice physicalDevice,
2963 const char* pLayerName,
2964 uint32_t* pPropertyCount,
2965 VkExtensionProperties* pProperties)
2966 {
2967 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2968 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2969
2970 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2971 if (device->supported_extensions.extensions[i]) {
2972 vk_outarray_append(&out, prop) {
2973 *prop = radv_device_extensions[i];
2974 }
2975 }
2976 }
2977
2978 return vk_outarray_status(&out);
2979 }
2980
2981 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2982 VkInstance _instance,
2983 const char* pName)
2984 {
2985 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2986
2987 return radv_lookup_entrypoint_checked(pName,
2988 instance ? instance->apiVersion : 0,
2989 instance ? &instance->enabled_extensions : NULL,
2990 NULL);
2991 }
2992
2993 /* The loader wants us to expose a second GetInstanceProcAddr function
2994 * to work around certain LD_PRELOAD issues seen in apps.
2995 */
2996 PUBLIC
2997 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2998 VkInstance instance,
2999 const char* pName);
3000
3001 PUBLIC
3002 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3003 VkInstance instance,
3004 const char* pName)
3005 {
3006 return radv_GetInstanceProcAddr(instance, pName);
3007 }
3008
3009 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3010 VkDevice _device,
3011 const char* pName)
3012 {
3013 RADV_FROM_HANDLE(radv_device, device, _device);
3014
3015 return radv_lookup_entrypoint_checked(pName,
3016 device->instance->apiVersion,
3017 &device->instance->enabled_extensions,
3018 &device->enabled_extensions);
3019 }
3020
3021 bool radv_get_memory_fd(struct radv_device *device,
3022 struct radv_device_memory *memory,
3023 int *pFD)
3024 {
3025 struct radeon_bo_metadata metadata;
3026
3027 if (memory->image) {
3028 radv_init_metadata(device, memory->image, &metadata);
3029 device->ws->buffer_set_metadata(memory->bo, &metadata);
3030 }
3031
3032 return device->ws->buffer_get_fd(device->ws, memory->bo,
3033 pFD);
3034 }
3035
3036 static VkResult radv_alloc_memory(struct radv_device *device,
3037 const VkMemoryAllocateInfo* pAllocateInfo,
3038 const VkAllocationCallbacks* pAllocator,
3039 VkDeviceMemory* pMem)
3040 {
3041 struct radv_device_memory *mem;
3042 VkResult result;
3043 enum radeon_bo_domain domain;
3044 uint32_t flags = 0;
3045 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3046
3047 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3048
3049 if (pAllocateInfo->allocationSize == 0) {
3050 /* Apparently, this is allowed */
3051 *pMem = VK_NULL_HANDLE;
3052 return VK_SUCCESS;
3053 }
3054
3055 const VkImportMemoryFdInfoKHR *import_info =
3056 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3057 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3058 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3059 const VkExportMemoryAllocateInfo *export_info =
3060 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3061 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3062 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3063
3064 const struct wsi_memory_allocate_info *wsi_info =
3065 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3066
3067 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3068 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3069 if (mem == NULL)
3070 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3071
3072 if (wsi_info && wsi_info->implicit_sync)
3073 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3074
3075 if (dedicate_info) {
3076 mem->image = radv_image_from_handle(dedicate_info->image);
3077 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3078 } else {
3079 mem->image = NULL;
3080 mem->buffer = NULL;
3081 }
3082
3083 mem->user_ptr = NULL;
3084
3085 if (import_info) {
3086 assert(import_info->handleType ==
3087 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3088 import_info->handleType ==
3089 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3090 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3091 NULL, NULL);
3092 if (!mem->bo) {
3093 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3094 goto fail;
3095 } else {
3096 close(import_info->fd);
3097 }
3098 } else if (host_ptr_info) {
3099 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3100 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3101 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3102 pAllocateInfo->allocationSize);
3103 if (!mem->bo) {
3104 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3105 goto fail;
3106 } else {
3107 mem->user_ptr = host_ptr_info->pHostPointer;
3108 }
3109 } else {
3110 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3111 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3112 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3113 domain = RADEON_DOMAIN_GTT;
3114 else
3115 domain = RADEON_DOMAIN_VRAM;
3116
3117 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3118 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3119 else
3120 flags |= RADEON_FLAG_CPU_ACCESS;
3121
3122 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3123 flags |= RADEON_FLAG_GTT_WC;
3124
3125 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3126 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3127
3128 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3129 domain, flags);
3130
3131 if (!mem->bo) {
3132 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3133 goto fail;
3134 }
3135 mem->type_index = mem_type_index;
3136 }
3137
3138 result = radv_bo_list_add(device, mem->bo);
3139 if (result != VK_SUCCESS)
3140 goto fail_bo;
3141
3142 *pMem = radv_device_memory_to_handle(mem);
3143
3144 return VK_SUCCESS;
3145
3146 fail_bo:
3147 device->ws->buffer_destroy(mem->bo);
3148 fail:
3149 vk_free2(&device->alloc, pAllocator, mem);
3150
3151 return result;
3152 }
3153
3154 VkResult radv_AllocateMemory(
3155 VkDevice _device,
3156 const VkMemoryAllocateInfo* pAllocateInfo,
3157 const VkAllocationCallbacks* pAllocator,
3158 VkDeviceMemory* pMem)
3159 {
3160 RADV_FROM_HANDLE(radv_device, device, _device);
3161 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3162 }
3163
3164 void radv_FreeMemory(
3165 VkDevice _device,
3166 VkDeviceMemory _mem,
3167 const VkAllocationCallbacks* pAllocator)
3168 {
3169 RADV_FROM_HANDLE(radv_device, device, _device);
3170 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3171
3172 if (mem == NULL)
3173 return;
3174
3175 radv_bo_list_remove(device, mem->bo);
3176 device->ws->buffer_destroy(mem->bo);
3177 mem->bo = NULL;
3178
3179 vk_free2(&device->alloc, pAllocator, mem);
3180 }
3181
3182 VkResult radv_MapMemory(
3183 VkDevice _device,
3184 VkDeviceMemory _memory,
3185 VkDeviceSize offset,
3186 VkDeviceSize size,
3187 VkMemoryMapFlags flags,
3188 void** ppData)
3189 {
3190 RADV_FROM_HANDLE(radv_device, device, _device);
3191 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3192
3193 if (mem == NULL) {
3194 *ppData = NULL;
3195 return VK_SUCCESS;
3196 }
3197
3198 if (mem->user_ptr)
3199 *ppData = mem->user_ptr;
3200 else
3201 *ppData = device->ws->buffer_map(mem->bo);
3202
3203 if (*ppData) {
3204 *ppData += offset;
3205 return VK_SUCCESS;
3206 }
3207
3208 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3209 }
3210
3211 void radv_UnmapMemory(
3212 VkDevice _device,
3213 VkDeviceMemory _memory)
3214 {
3215 RADV_FROM_HANDLE(radv_device, device, _device);
3216 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3217
3218 if (mem == NULL)
3219 return;
3220
3221 if (mem->user_ptr == NULL)
3222 device->ws->buffer_unmap(mem->bo);
3223 }
3224
3225 VkResult radv_FlushMappedMemoryRanges(
3226 VkDevice _device,
3227 uint32_t memoryRangeCount,
3228 const VkMappedMemoryRange* pMemoryRanges)
3229 {
3230 return VK_SUCCESS;
3231 }
3232
3233 VkResult radv_InvalidateMappedMemoryRanges(
3234 VkDevice _device,
3235 uint32_t memoryRangeCount,
3236 const VkMappedMemoryRange* pMemoryRanges)
3237 {
3238 return VK_SUCCESS;
3239 }
3240
3241 void radv_GetBufferMemoryRequirements(
3242 VkDevice _device,
3243 VkBuffer _buffer,
3244 VkMemoryRequirements* pMemoryRequirements)
3245 {
3246 RADV_FROM_HANDLE(radv_device, device, _device);
3247 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3248
3249 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3250
3251 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3252 pMemoryRequirements->alignment = 4096;
3253 else
3254 pMemoryRequirements->alignment = 16;
3255
3256 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3257 }
3258
3259 void radv_GetBufferMemoryRequirements2(
3260 VkDevice device,
3261 const VkBufferMemoryRequirementsInfo2 *pInfo,
3262 VkMemoryRequirements2 *pMemoryRequirements)
3263 {
3264 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3265 &pMemoryRequirements->memoryRequirements);
3266 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3267 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3268 switch (ext->sType) {
3269 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3270 VkMemoryDedicatedRequirements *req =
3271 (VkMemoryDedicatedRequirements *) ext;
3272 req->requiresDedicatedAllocation = buffer->shareable;
3273 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3274 break;
3275 }
3276 default:
3277 break;
3278 }
3279 }
3280 }
3281
3282 void radv_GetImageMemoryRequirements(
3283 VkDevice _device,
3284 VkImage _image,
3285 VkMemoryRequirements* pMemoryRequirements)
3286 {
3287 RADV_FROM_HANDLE(radv_device, device, _device);
3288 RADV_FROM_HANDLE(radv_image, image, _image);
3289
3290 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3291
3292 pMemoryRequirements->size = image->size;
3293 pMemoryRequirements->alignment = image->alignment;
3294 }
3295
3296 void radv_GetImageMemoryRequirements2(
3297 VkDevice device,
3298 const VkImageMemoryRequirementsInfo2 *pInfo,
3299 VkMemoryRequirements2 *pMemoryRequirements)
3300 {
3301 radv_GetImageMemoryRequirements(device, pInfo->image,
3302 &pMemoryRequirements->memoryRequirements);
3303
3304 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3305
3306 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3307 switch (ext->sType) {
3308 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3309 VkMemoryDedicatedRequirements *req =
3310 (VkMemoryDedicatedRequirements *) ext;
3311 req->requiresDedicatedAllocation = image->shareable;
3312 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3313 break;
3314 }
3315 default:
3316 break;
3317 }
3318 }
3319 }
3320
3321 void radv_GetImageSparseMemoryRequirements(
3322 VkDevice device,
3323 VkImage image,
3324 uint32_t* pSparseMemoryRequirementCount,
3325 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3326 {
3327 stub();
3328 }
3329
3330 void radv_GetImageSparseMemoryRequirements2(
3331 VkDevice device,
3332 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3333 uint32_t* pSparseMemoryRequirementCount,
3334 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3335 {
3336 stub();
3337 }
3338
3339 void radv_GetDeviceMemoryCommitment(
3340 VkDevice device,
3341 VkDeviceMemory memory,
3342 VkDeviceSize* pCommittedMemoryInBytes)
3343 {
3344 *pCommittedMemoryInBytes = 0;
3345 }
3346
3347 VkResult radv_BindBufferMemory2(VkDevice device,
3348 uint32_t bindInfoCount,
3349 const VkBindBufferMemoryInfo *pBindInfos)
3350 {
3351 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3352 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3353 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3354
3355 if (mem) {
3356 buffer->bo = mem->bo;
3357 buffer->offset = pBindInfos[i].memoryOffset;
3358 } else {
3359 buffer->bo = NULL;
3360 }
3361 }
3362 return VK_SUCCESS;
3363 }
3364
3365 VkResult radv_BindBufferMemory(
3366 VkDevice device,
3367 VkBuffer buffer,
3368 VkDeviceMemory memory,
3369 VkDeviceSize memoryOffset)
3370 {
3371 const VkBindBufferMemoryInfo info = {
3372 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3373 .buffer = buffer,
3374 .memory = memory,
3375 .memoryOffset = memoryOffset
3376 };
3377
3378 return radv_BindBufferMemory2(device, 1, &info);
3379 }
3380
3381 VkResult radv_BindImageMemory2(VkDevice device,
3382 uint32_t bindInfoCount,
3383 const VkBindImageMemoryInfo *pBindInfos)
3384 {
3385 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3386 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3387 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3388
3389 if (mem) {
3390 image->bo = mem->bo;
3391 image->offset = pBindInfos[i].memoryOffset;
3392 } else {
3393 image->bo = NULL;
3394 image->offset = 0;
3395 }
3396 }
3397 return VK_SUCCESS;
3398 }
3399
3400
3401 VkResult radv_BindImageMemory(
3402 VkDevice device,
3403 VkImage image,
3404 VkDeviceMemory memory,
3405 VkDeviceSize memoryOffset)
3406 {
3407 const VkBindImageMemoryInfo info = {
3408 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3409 .image = image,
3410 .memory = memory,
3411 .memoryOffset = memoryOffset
3412 };
3413
3414 return radv_BindImageMemory2(device, 1, &info);
3415 }
3416
3417
3418 static void
3419 radv_sparse_buffer_bind_memory(struct radv_device *device,
3420 const VkSparseBufferMemoryBindInfo *bind)
3421 {
3422 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3423
3424 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3425 struct radv_device_memory *mem = NULL;
3426
3427 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3428 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3429
3430 device->ws->buffer_virtual_bind(buffer->bo,
3431 bind->pBinds[i].resourceOffset,
3432 bind->pBinds[i].size,
3433 mem ? mem->bo : NULL,
3434 bind->pBinds[i].memoryOffset);
3435 }
3436 }
3437
3438 static void
3439 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3440 const VkSparseImageOpaqueMemoryBindInfo *bind)
3441 {
3442 RADV_FROM_HANDLE(radv_image, image, bind->image);
3443
3444 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3445 struct radv_device_memory *mem = NULL;
3446
3447 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3448 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3449
3450 device->ws->buffer_virtual_bind(image->bo,
3451 bind->pBinds[i].resourceOffset,
3452 bind->pBinds[i].size,
3453 mem ? mem->bo : NULL,
3454 bind->pBinds[i].memoryOffset);
3455 }
3456 }
3457
3458 VkResult radv_QueueBindSparse(
3459 VkQueue _queue,
3460 uint32_t bindInfoCount,
3461 const VkBindSparseInfo* pBindInfo,
3462 VkFence _fence)
3463 {
3464 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3465 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3466 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3467 bool fence_emitted = false;
3468 VkResult result;
3469 int ret;
3470
3471 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3472 struct radv_winsys_sem_info sem_info;
3473 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3474 radv_sparse_buffer_bind_memory(queue->device,
3475 pBindInfo[i].pBufferBinds + j);
3476 }
3477
3478 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3479 radv_sparse_image_opaque_bind_memory(queue->device,
3480 pBindInfo[i].pImageOpaqueBinds + j);
3481 }
3482
3483 VkResult result;
3484 result = radv_alloc_sem_info(queue->device->instance,
3485 &sem_info,
3486 pBindInfo[i].waitSemaphoreCount,
3487 pBindInfo[i].pWaitSemaphores,
3488 pBindInfo[i].signalSemaphoreCount,
3489 pBindInfo[i].pSignalSemaphores,
3490 _fence);
3491 if (result != VK_SUCCESS)
3492 return result;
3493
3494 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3495 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3496 &queue->device->empty_cs[queue->queue_family_index],
3497 1, NULL, NULL,
3498 &sem_info, NULL,
3499 false, base_fence);
3500 if (ret) {
3501 radv_loge("failed to submit CS %d\n", i);
3502 abort();
3503 }
3504
3505 fence_emitted = true;
3506 if (fence)
3507 fence->submitted = true;
3508 }
3509
3510 radv_free_sem_info(&sem_info);
3511
3512 }
3513
3514 if (fence) {
3515 if (!fence_emitted) {
3516 result = radv_signal_fence(queue, fence);
3517 if (result != VK_SUCCESS)
3518 return result;
3519 }
3520 fence->submitted = true;
3521 }
3522
3523 return VK_SUCCESS;
3524 }
3525
3526 VkResult radv_CreateFence(
3527 VkDevice _device,
3528 const VkFenceCreateInfo* pCreateInfo,
3529 const VkAllocationCallbacks* pAllocator,
3530 VkFence* pFence)
3531 {
3532 RADV_FROM_HANDLE(radv_device, device, _device);
3533 const VkExportFenceCreateInfo *export =
3534 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3535 VkExternalFenceHandleTypeFlags handleTypes =
3536 export ? export->handleTypes : 0;
3537
3538 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3539 sizeof(*fence), 8,
3540 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3541
3542 if (!fence)
3543 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3544
3545 fence->fence_wsi = NULL;
3546 fence->submitted = false;
3547 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3548 fence->temp_syncobj = 0;
3549 if (device->always_use_syncobj || handleTypes) {
3550 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3551 if (ret) {
3552 vk_free2(&device->alloc, pAllocator, fence);
3553 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3554 }
3555 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3556 device->ws->signal_syncobj(device->ws, fence->syncobj);
3557 }
3558 fence->fence = NULL;
3559 } else {
3560 fence->fence = device->ws->create_fence();
3561 if (!fence->fence) {
3562 vk_free2(&device->alloc, pAllocator, fence);
3563 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3564 }
3565 fence->syncobj = 0;
3566 }
3567
3568 *pFence = radv_fence_to_handle(fence);
3569
3570 return VK_SUCCESS;
3571 }
3572
3573 void radv_DestroyFence(
3574 VkDevice _device,
3575 VkFence _fence,
3576 const VkAllocationCallbacks* pAllocator)
3577 {
3578 RADV_FROM_HANDLE(radv_device, device, _device);
3579 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3580
3581 if (!fence)
3582 return;
3583
3584 if (fence->temp_syncobj)
3585 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3586 if (fence->syncobj)
3587 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3588 if (fence->fence)
3589 device->ws->destroy_fence(fence->fence);
3590 if (fence->fence_wsi)
3591 fence->fence_wsi->destroy(fence->fence_wsi);
3592 vk_free2(&device->alloc, pAllocator, fence);
3593 }
3594
3595
3596 static uint64_t radv_get_current_time()
3597 {
3598 struct timespec tv;
3599 clock_gettime(CLOCK_MONOTONIC, &tv);
3600 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3601 }
3602
3603 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3604 {
3605 uint64_t current_time = radv_get_current_time();
3606
3607 timeout = MIN2(UINT64_MAX - current_time, timeout);
3608
3609 return current_time + timeout;
3610 }
3611
3612
3613 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3614 {
3615 for (uint32_t i = 0; i < fenceCount; ++i) {
3616 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3617 if (fence->fence == NULL || fence->syncobj ||
3618 fence->temp_syncobj ||
3619 (!fence->signalled && !fence->submitted))
3620 return false;
3621 }
3622 return true;
3623 }
3624
3625 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3626 {
3627 for (uint32_t i = 0; i < fenceCount; ++i) {
3628 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3629 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3630 return false;
3631 }
3632 return true;
3633 }
3634
3635 VkResult radv_WaitForFences(
3636 VkDevice _device,
3637 uint32_t fenceCount,
3638 const VkFence* pFences,
3639 VkBool32 waitAll,
3640 uint64_t timeout)
3641 {
3642 RADV_FROM_HANDLE(radv_device, device, _device);
3643 timeout = radv_get_absolute_timeout(timeout);
3644
3645 if (device->always_use_syncobj &&
3646 radv_all_fences_syncobj(fenceCount, pFences))
3647 {
3648 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3649 if (!handles)
3650 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3651
3652 for (uint32_t i = 0; i < fenceCount; ++i) {
3653 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3654 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3655 }
3656
3657 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3658
3659 free(handles);
3660 return success ? VK_SUCCESS : VK_TIMEOUT;
3661 }
3662
3663 if (!waitAll && fenceCount > 1) {
3664 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3665 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3666 uint32_t wait_count = 0;
3667 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3668 if (!fences)
3669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3670
3671 for (uint32_t i = 0; i < fenceCount; ++i) {
3672 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3673
3674 if (fence->signalled) {
3675 free(fences);
3676 return VK_SUCCESS;
3677 }
3678
3679 fences[wait_count++] = fence->fence;
3680 }
3681
3682 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3683 waitAll, timeout - radv_get_current_time());
3684
3685 free(fences);
3686 return success ? VK_SUCCESS : VK_TIMEOUT;
3687 }
3688
3689 while(radv_get_current_time() <= timeout) {
3690 for (uint32_t i = 0; i < fenceCount; ++i) {
3691 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3692 return VK_SUCCESS;
3693 }
3694 }
3695 return VK_TIMEOUT;
3696 }
3697
3698 for (uint32_t i = 0; i < fenceCount; ++i) {
3699 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3700 bool expired = false;
3701
3702 if (fence->temp_syncobj) {
3703 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3704 return VK_TIMEOUT;
3705 continue;
3706 }
3707
3708 if (fence->syncobj) {
3709 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3710 return VK_TIMEOUT;
3711 continue;
3712 }
3713
3714 if (fence->signalled)
3715 continue;
3716
3717 if (fence->fence) {
3718 if (!fence->submitted) {
3719 while(radv_get_current_time() <= timeout &&
3720 !fence->submitted)
3721 /* Do nothing */;
3722
3723 if (!fence->submitted)
3724 return VK_TIMEOUT;
3725
3726 /* Recheck as it may have been set by
3727 * submitting operations. */
3728
3729 if (fence->signalled)
3730 continue;
3731 }
3732
3733 expired = device->ws->fence_wait(device->ws,
3734 fence->fence,
3735 true, timeout);
3736 if (!expired)
3737 return VK_TIMEOUT;
3738 }
3739
3740 if (fence->fence_wsi) {
3741 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3742 if (result != VK_SUCCESS)
3743 return result;
3744 }
3745
3746 fence->signalled = true;
3747 }
3748
3749 return VK_SUCCESS;
3750 }
3751
3752 VkResult radv_ResetFences(VkDevice _device,
3753 uint32_t fenceCount,
3754 const VkFence *pFences)
3755 {
3756 RADV_FROM_HANDLE(radv_device, device, _device);
3757
3758 for (unsigned i = 0; i < fenceCount; ++i) {
3759 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3760 fence->submitted = fence->signalled = false;
3761
3762 /* Per spec, we first restore the permanent payload, and then reset, so
3763 * having a temp syncobj should not skip resetting the permanent syncobj. */
3764 if (fence->temp_syncobj) {
3765 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3766 fence->temp_syncobj = 0;
3767 }
3768
3769 if (fence->syncobj) {
3770 device->ws->reset_syncobj(device->ws, fence->syncobj);
3771 }
3772 }
3773
3774 return VK_SUCCESS;
3775 }
3776
3777 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3778 {
3779 RADV_FROM_HANDLE(radv_device, device, _device);
3780 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3781
3782 if (fence->temp_syncobj) {
3783 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3784 return success ? VK_SUCCESS : VK_NOT_READY;
3785 }
3786
3787 if (fence->syncobj) {
3788 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3789 return success ? VK_SUCCESS : VK_NOT_READY;
3790 }
3791
3792 if (fence->signalled)
3793 return VK_SUCCESS;
3794 if (!fence->submitted)
3795 return VK_NOT_READY;
3796 if (fence->fence) {
3797 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3798 return VK_NOT_READY;
3799 }
3800 if (fence->fence_wsi) {
3801 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3802
3803 if (result != VK_SUCCESS) {
3804 if (result == VK_TIMEOUT)
3805 return VK_NOT_READY;
3806 return result;
3807 }
3808 }
3809 return VK_SUCCESS;
3810 }
3811
3812
3813 // Queue semaphore functions
3814
3815 VkResult radv_CreateSemaphore(
3816 VkDevice _device,
3817 const VkSemaphoreCreateInfo* pCreateInfo,
3818 const VkAllocationCallbacks* pAllocator,
3819 VkSemaphore* pSemaphore)
3820 {
3821 RADV_FROM_HANDLE(radv_device, device, _device);
3822 const VkExportSemaphoreCreateInfo *export =
3823 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3824 VkExternalSemaphoreHandleTypeFlags handleTypes =
3825 export ? export->handleTypes : 0;
3826
3827 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3828 sizeof(*sem), 8,
3829 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3830 if (!sem)
3831 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3832
3833 sem->temp_syncobj = 0;
3834 /* create a syncobject if we are going to export this semaphore */
3835 if (device->always_use_syncobj || handleTypes) {
3836 assert (device->physical_device->rad_info.has_syncobj);
3837 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3838 if (ret) {
3839 vk_free2(&device->alloc, pAllocator, sem);
3840 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3841 }
3842 sem->sem = NULL;
3843 } else {
3844 sem->sem = device->ws->create_sem(device->ws);
3845 if (!sem->sem) {
3846 vk_free2(&device->alloc, pAllocator, sem);
3847 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3848 }
3849 sem->syncobj = 0;
3850 }
3851
3852 *pSemaphore = radv_semaphore_to_handle(sem);
3853 return VK_SUCCESS;
3854 }
3855
3856 void radv_DestroySemaphore(
3857 VkDevice _device,
3858 VkSemaphore _semaphore,
3859 const VkAllocationCallbacks* pAllocator)
3860 {
3861 RADV_FROM_HANDLE(radv_device, device, _device);
3862 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3863 if (!_semaphore)
3864 return;
3865
3866 if (sem->syncobj)
3867 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3868 else
3869 device->ws->destroy_sem(sem->sem);
3870 vk_free2(&device->alloc, pAllocator, sem);
3871 }
3872
3873 VkResult radv_CreateEvent(
3874 VkDevice _device,
3875 const VkEventCreateInfo* pCreateInfo,
3876 const VkAllocationCallbacks* pAllocator,
3877 VkEvent* pEvent)
3878 {
3879 RADV_FROM_HANDLE(radv_device, device, _device);
3880 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3881 sizeof(*event), 8,
3882 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3883
3884 if (!event)
3885 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3886
3887 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3888 RADEON_DOMAIN_GTT,
3889 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3890 if (!event->bo) {
3891 vk_free2(&device->alloc, pAllocator, event);
3892 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3893 }
3894
3895 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3896
3897 *pEvent = radv_event_to_handle(event);
3898
3899 return VK_SUCCESS;
3900 }
3901
3902 void radv_DestroyEvent(
3903 VkDevice _device,
3904 VkEvent _event,
3905 const VkAllocationCallbacks* pAllocator)
3906 {
3907 RADV_FROM_HANDLE(radv_device, device, _device);
3908 RADV_FROM_HANDLE(radv_event, event, _event);
3909
3910 if (!event)
3911 return;
3912 device->ws->buffer_destroy(event->bo);
3913 vk_free2(&device->alloc, pAllocator, event);
3914 }
3915
3916 VkResult radv_GetEventStatus(
3917 VkDevice _device,
3918 VkEvent _event)
3919 {
3920 RADV_FROM_HANDLE(radv_event, event, _event);
3921
3922 if (*event->map == 1)
3923 return VK_EVENT_SET;
3924 return VK_EVENT_RESET;
3925 }
3926
3927 VkResult radv_SetEvent(
3928 VkDevice _device,
3929 VkEvent _event)
3930 {
3931 RADV_FROM_HANDLE(radv_event, event, _event);
3932 *event->map = 1;
3933
3934 return VK_SUCCESS;
3935 }
3936
3937 VkResult radv_ResetEvent(
3938 VkDevice _device,
3939 VkEvent _event)
3940 {
3941 RADV_FROM_HANDLE(radv_event, event, _event);
3942 *event->map = 0;
3943
3944 return VK_SUCCESS;
3945 }
3946
3947 VkResult radv_CreateBuffer(
3948 VkDevice _device,
3949 const VkBufferCreateInfo* pCreateInfo,
3950 const VkAllocationCallbacks* pAllocator,
3951 VkBuffer* pBuffer)
3952 {
3953 RADV_FROM_HANDLE(radv_device, device, _device);
3954 struct radv_buffer *buffer;
3955
3956 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3957
3958 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3960 if (buffer == NULL)
3961 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3962
3963 buffer->size = pCreateInfo->size;
3964 buffer->usage = pCreateInfo->usage;
3965 buffer->bo = NULL;
3966 buffer->offset = 0;
3967 buffer->flags = pCreateInfo->flags;
3968
3969 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3970 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
3971
3972 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3973 buffer->bo = device->ws->buffer_create(device->ws,
3974 align64(buffer->size, 4096),
3975 4096, 0, RADEON_FLAG_VIRTUAL);
3976 if (!buffer->bo) {
3977 vk_free2(&device->alloc, pAllocator, buffer);
3978 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3979 }
3980 }
3981
3982 *pBuffer = radv_buffer_to_handle(buffer);
3983
3984 return VK_SUCCESS;
3985 }
3986
3987 void radv_DestroyBuffer(
3988 VkDevice _device,
3989 VkBuffer _buffer,
3990 const VkAllocationCallbacks* pAllocator)
3991 {
3992 RADV_FROM_HANDLE(radv_device, device, _device);
3993 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3994
3995 if (!buffer)
3996 return;
3997
3998 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3999 device->ws->buffer_destroy(buffer->bo);
4000
4001 vk_free2(&device->alloc, pAllocator, buffer);
4002 }
4003
4004 static inline unsigned
4005 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4006 {
4007 if (stencil)
4008 return image->surface.u.legacy.stencil_tiling_index[level];
4009 else
4010 return image->surface.u.legacy.tiling_index[level];
4011 }
4012
4013 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4014 {
4015 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4016 }
4017
4018 static uint32_t
4019 radv_init_dcc_control_reg(struct radv_device *device,
4020 struct radv_image_view *iview)
4021 {
4022 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4023 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4024 unsigned max_compressed_block_size;
4025 unsigned independent_64b_blocks;
4026
4027 if (!radv_image_has_dcc(iview->image))
4028 return 0;
4029
4030 if (iview->image->info.samples > 1) {
4031 if (iview->image->surface.bpe == 1)
4032 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4033 else if (iview->image->surface.bpe == 2)
4034 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4035 }
4036
4037 if (!device->physical_device->rad_info.has_dedicated_vram) {
4038 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4039 * dGPU and 64 for APU because all of our APUs to date use
4040 * DIMMs which have a request granularity size of 64B while all
4041 * other chips have a 32B request size.
4042 */
4043 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4044 }
4045
4046 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4047 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4048 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4049 /* If this DCC image is potentially going to be used in texture
4050 * fetches, we need some special settings.
4051 */
4052 independent_64b_blocks = 1;
4053 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4054 } else {
4055 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4056 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4057 * big as possible for better compression state.
4058 */
4059 independent_64b_blocks = 0;
4060 max_compressed_block_size = max_uncompressed_block_size;
4061 }
4062
4063 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4064 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4065 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4066 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4067 }
4068
4069 static void
4070 radv_initialise_color_surface(struct radv_device *device,
4071 struct radv_color_buffer_info *cb,
4072 struct radv_image_view *iview)
4073 {
4074 const struct vk_format_description *desc;
4075 unsigned ntype, format, swap, endian;
4076 unsigned blend_clamp = 0, blend_bypass = 0;
4077 uint64_t va;
4078 const struct radeon_surf *surf = &iview->image->surface;
4079
4080 desc = vk_format_description(iview->vk_format);
4081
4082 memset(cb, 0, sizeof(*cb));
4083
4084 /* Intensity is implemented as Red, so treat it that way. */
4085 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4086
4087 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4088
4089 cb->cb_color_base = va >> 8;
4090
4091 if (device->physical_device->rad_info.chip_class >= GFX9) {
4092 struct gfx9_surf_meta_flags meta;
4093 if (iview->image->dcc_offset)
4094 meta = iview->image->surface.u.gfx9.dcc;
4095 else
4096 meta = iview->image->surface.u.gfx9.cmask;
4097
4098 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4099 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4100 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4101 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4102
4103 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4104 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4105 } else {
4106 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4107 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4108
4109 cb->cb_color_base += level_info->offset >> 8;
4110 if (level_info->mode == RADEON_SURF_MODE_2D)
4111 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4112
4113 pitch_tile_max = level_info->nblk_x / 8 - 1;
4114 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4115 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4116
4117 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4118 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4119 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4120
4121 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4122
4123 if (radv_image_has_fmask(iview->image)) {
4124 if (device->physical_device->rad_info.chip_class >= CIK)
4125 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4126 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4127 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4128 } else {
4129 /* This must be set for fast clear to work without FMASK. */
4130 if (device->physical_device->rad_info.chip_class >= CIK)
4131 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4132 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4133 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4134 }
4135 }
4136
4137 /* CMASK variables */
4138 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4139 va += iview->image->cmask.offset;
4140 cb->cb_color_cmask = va >> 8;
4141
4142 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4143 va += iview->image->dcc_offset;
4144 cb->cb_dcc_base = va >> 8;
4145 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4146
4147 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4148 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4149 S_028C6C_SLICE_MAX(max_slice);
4150
4151 if (iview->image->info.samples > 1) {
4152 unsigned log_samples = util_logbase2(iview->image->info.samples);
4153
4154 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4155 S_028C74_NUM_FRAGMENTS(log_samples);
4156 }
4157
4158 if (radv_image_has_fmask(iview->image)) {
4159 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4160 cb->cb_color_fmask = va >> 8;
4161 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4162 } else {
4163 cb->cb_color_fmask = cb->cb_color_base;
4164 }
4165
4166 ntype = radv_translate_color_numformat(iview->vk_format,
4167 desc,
4168 vk_format_get_first_non_void_channel(iview->vk_format));
4169 format = radv_translate_colorformat(iview->vk_format);
4170 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4171 radv_finishme("Illegal color\n");
4172 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4173 endian = radv_colorformat_endian_swap(format);
4174
4175 /* blend clamp should be set for all NORM/SRGB types */
4176 if (ntype == V_028C70_NUMBER_UNORM ||
4177 ntype == V_028C70_NUMBER_SNORM ||
4178 ntype == V_028C70_NUMBER_SRGB)
4179 blend_clamp = 1;
4180
4181 /* set blend bypass according to docs if SINT/UINT or
4182 8/24 COLOR variants */
4183 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4184 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4185 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4186 blend_clamp = 0;
4187 blend_bypass = 1;
4188 }
4189 #if 0
4190 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4191 (format == V_028C70_COLOR_8 ||
4192 format == V_028C70_COLOR_8_8 ||
4193 format == V_028C70_COLOR_8_8_8_8))
4194 ->color_is_int8 = true;
4195 #endif
4196 cb->cb_color_info = S_028C70_FORMAT(format) |
4197 S_028C70_COMP_SWAP(swap) |
4198 S_028C70_BLEND_CLAMP(blend_clamp) |
4199 S_028C70_BLEND_BYPASS(blend_bypass) |
4200 S_028C70_SIMPLE_FLOAT(1) |
4201 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4202 ntype != V_028C70_NUMBER_SNORM &&
4203 ntype != V_028C70_NUMBER_SRGB &&
4204 format != V_028C70_COLOR_8_24 &&
4205 format != V_028C70_COLOR_24_8) |
4206 S_028C70_NUMBER_TYPE(ntype) |
4207 S_028C70_ENDIAN(endian);
4208 if (radv_image_has_fmask(iview->image)) {
4209 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4210 if (device->physical_device->rad_info.chip_class == SI) {
4211 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4212 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4213 }
4214 }
4215
4216 if (radv_image_has_cmask(iview->image) &&
4217 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4218 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4219
4220 if (radv_dcc_enabled(iview->image, iview->base_mip))
4221 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4222
4223 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4224
4225 /* This must be set for fast clear to work without FMASK. */
4226 if (!radv_image_has_fmask(iview->image) &&
4227 device->physical_device->rad_info.chip_class == SI) {
4228 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4229 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4230 }
4231
4232 if (device->physical_device->rad_info.chip_class >= GFX9) {
4233 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4234 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4235
4236 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4237 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4238 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4239 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4240 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4241 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4242 }
4243 }
4244
4245 static unsigned
4246 radv_calc_decompress_on_z_planes(struct radv_device *device,
4247 struct radv_image_view *iview)
4248 {
4249 unsigned max_zplanes = 0;
4250
4251 assert(radv_image_is_tc_compat_htile(iview->image));
4252
4253 if (device->physical_device->rad_info.chip_class >= GFX9) {
4254 /* Default value for 32-bit depth surfaces. */
4255 max_zplanes = 4;
4256
4257 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4258 iview->image->info.samples > 1)
4259 max_zplanes = 2;
4260
4261 max_zplanes = max_zplanes + 1;
4262 } else {
4263 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4264 /* Do not enable Z plane compression for 16-bit depth
4265 * surfaces because isn't supported on GFX8. Only
4266 * 32-bit depth surfaces are supported by the hardware.
4267 * This allows to maintain shader compatibility and to
4268 * reduce the number of depth decompressions.
4269 */
4270 max_zplanes = 1;
4271 } else {
4272 if (iview->image->info.samples <= 1)
4273 max_zplanes = 5;
4274 else if (iview->image->info.samples <= 4)
4275 max_zplanes = 3;
4276 else
4277 max_zplanes = 2;
4278 }
4279 }
4280
4281 return max_zplanes;
4282 }
4283
4284 static void
4285 radv_initialise_ds_surface(struct radv_device *device,
4286 struct radv_ds_buffer_info *ds,
4287 struct radv_image_view *iview)
4288 {
4289 unsigned level = iview->base_mip;
4290 unsigned format, stencil_format;
4291 uint64_t va, s_offs, z_offs;
4292 bool stencil_only = false;
4293 memset(ds, 0, sizeof(*ds));
4294 switch (iview->image->vk_format) {
4295 case VK_FORMAT_D24_UNORM_S8_UINT:
4296 case VK_FORMAT_X8_D24_UNORM_PACK32:
4297 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4298 ds->offset_scale = 2.0f;
4299 break;
4300 case VK_FORMAT_D16_UNORM:
4301 case VK_FORMAT_D16_UNORM_S8_UINT:
4302 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4303 ds->offset_scale = 4.0f;
4304 break;
4305 case VK_FORMAT_D32_SFLOAT:
4306 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4307 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4308 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4309 ds->offset_scale = 1.0f;
4310 break;
4311 case VK_FORMAT_S8_UINT:
4312 stencil_only = true;
4313 break;
4314 default:
4315 break;
4316 }
4317
4318 format = radv_translate_dbformat(iview->image->vk_format);
4319 stencil_format = iview->image->surface.has_stencil ?
4320 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4321
4322 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4323 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4324 S_028008_SLICE_MAX(max_slice);
4325
4326 ds->db_htile_data_base = 0;
4327 ds->db_htile_surface = 0;
4328
4329 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4330 s_offs = z_offs = va;
4331
4332 if (device->physical_device->rad_info.chip_class >= GFX9) {
4333 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4334 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4335
4336 ds->db_z_info = S_028038_FORMAT(format) |
4337 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4338 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4339 S_028038_MAXMIP(iview->image->info.levels - 1) |
4340 S_028038_ZRANGE_PRECISION(1);
4341 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4342 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4343
4344 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4345 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4346 ds->db_depth_view |= S_028008_MIPID(level);
4347
4348 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4349 S_02801C_Y_MAX(iview->image->info.height - 1);
4350
4351 if (radv_htile_enabled(iview->image, level)) {
4352 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4353
4354 if (radv_image_is_tc_compat_htile(iview->image)) {
4355 unsigned max_zplanes =
4356 radv_calc_decompress_on_z_planes(device, iview);
4357
4358 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4359 S_028038_ITERATE_FLUSH(1);
4360 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4361 }
4362
4363 if (!iview->image->surface.has_stencil)
4364 /* Use all of the htile_buffer for depth if there's no stencil. */
4365 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4366 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4367 iview->image->htile_offset;
4368 ds->db_htile_data_base = va >> 8;
4369 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4370 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4371 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4372 }
4373 } else {
4374 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4375
4376 if (stencil_only)
4377 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4378
4379 z_offs += iview->image->surface.u.legacy.level[level].offset;
4380 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4381
4382 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4383 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4384 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4385
4386 if (iview->image->info.samples > 1)
4387 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4388
4389 if (device->physical_device->rad_info.chip_class >= CIK) {
4390 struct radeon_info *info = &device->physical_device->rad_info;
4391 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4392 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4393 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4394 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4395 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4396 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4397
4398 if (stencil_only)
4399 tile_mode = stencil_tile_mode;
4400
4401 ds->db_depth_info |=
4402 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4403 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4404 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4405 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4406 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4407 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4408 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4409 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4410 } else {
4411 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4412 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4413 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4414 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4415 if (stencil_only)
4416 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4417 }
4418
4419 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4420 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4421 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4422
4423 if (radv_htile_enabled(iview->image, level)) {
4424 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4425
4426 if (!iview->image->surface.has_stencil &&
4427 !radv_image_is_tc_compat_htile(iview->image))
4428 /* Use all of the htile_buffer for depth if there's no stencil. */
4429 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4430
4431 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4432 iview->image->htile_offset;
4433 ds->db_htile_data_base = va >> 8;
4434 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4435
4436 if (radv_image_is_tc_compat_htile(iview->image)) {
4437 unsigned max_zplanes =
4438 radv_calc_decompress_on_z_planes(device, iview);
4439
4440 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4441 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4442 }
4443 }
4444 }
4445
4446 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4447 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4448 }
4449
4450 VkResult radv_CreateFramebuffer(
4451 VkDevice _device,
4452 const VkFramebufferCreateInfo* pCreateInfo,
4453 const VkAllocationCallbacks* pAllocator,
4454 VkFramebuffer* pFramebuffer)
4455 {
4456 RADV_FROM_HANDLE(radv_device, device, _device);
4457 struct radv_framebuffer *framebuffer;
4458
4459 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4460
4461 size_t size = sizeof(*framebuffer) +
4462 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4463 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4464 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4465 if (framebuffer == NULL)
4466 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4467
4468 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4469 framebuffer->width = pCreateInfo->width;
4470 framebuffer->height = pCreateInfo->height;
4471 framebuffer->layers = pCreateInfo->layers;
4472 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4473 VkImageView _iview = pCreateInfo->pAttachments[i];
4474 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4475 framebuffer->attachments[i].attachment = iview;
4476 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4477 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4478 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4479 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4480 }
4481 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4482 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4483 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4484 }
4485
4486 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4487 return VK_SUCCESS;
4488 }
4489
4490 void radv_DestroyFramebuffer(
4491 VkDevice _device,
4492 VkFramebuffer _fb,
4493 const VkAllocationCallbacks* pAllocator)
4494 {
4495 RADV_FROM_HANDLE(radv_device, device, _device);
4496 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4497
4498 if (!fb)
4499 return;
4500 vk_free2(&device->alloc, pAllocator, fb);
4501 }
4502
4503 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4504 {
4505 switch (address_mode) {
4506 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4507 return V_008F30_SQ_TEX_WRAP;
4508 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4509 return V_008F30_SQ_TEX_MIRROR;
4510 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4511 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4512 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4513 return V_008F30_SQ_TEX_CLAMP_BORDER;
4514 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4515 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4516 default:
4517 unreachable("illegal tex wrap mode");
4518 break;
4519 }
4520 }
4521
4522 static unsigned
4523 radv_tex_compare(VkCompareOp op)
4524 {
4525 switch (op) {
4526 case VK_COMPARE_OP_NEVER:
4527 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4528 case VK_COMPARE_OP_LESS:
4529 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4530 case VK_COMPARE_OP_EQUAL:
4531 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4532 case VK_COMPARE_OP_LESS_OR_EQUAL:
4533 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4534 case VK_COMPARE_OP_GREATER:
4535 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4536 case VK_COMPARE_OP_NOT_EQUAL:
4537 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4538 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4539 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4540 case VK_COMPARE_OP_ALWAYS:
4541 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4542 default:
4543 unreachable("illegal compare mode");
4544 break;
4545 }
4546 }
4547
4548 static unsigned
4549 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4550 {
4551 switch (filter) {
4552 case VK_FILTER_NEAREST:
4553 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4554 V_008F38_SQ_TEX_XY_FILTER_POINT);
4555 case VK_FILTER_LINEAR:
4556 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4557 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4558 case VK_FILTER_CUBIC_IMG:
4559 default:
4560 fprintf(stderr, "illegal texture filter");
4561 return 0;
4562 }
4563 }
4564
4565 static unsigned
4566 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4567 {
4568 switch (mode) {
4569 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4570 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4571 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4572 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4573 default:
4574 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4575 }
4576 }
4577
4578 static unsigned
4579 radv_tex_bordercolor(VkBorderColor bcolor)
4580 {
4581 switch (bcolor) {
4582 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4583 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4584 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4585 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4586 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4587 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4588 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4589 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4590 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4591 default:
4592 break;
4593 }
4594 return 0;
4595 }
4596
4597 static unsigned
4598 radv_tex_aniso_filter(unsigned filter)
4599 {
4600 if (filter < 2)
4601 return 0;
4602 if (filter < 4)
4603 return 1;
4604 if (filter < 8)
4605 return 2;
4606 if (filter < 16)
4607 return 3;
4608 return 4;
4609 }
4610
4611 static unsigned
4612 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4613 {
4614 switch (mode) {
4615 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4616 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4617 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4618 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4619 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4620 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4621 default:
4622 break;
4623 }
4624 return 0;
4625 }
4626
4627 static uint32_t
4628 radv_get_max_anisotropy(struct radv_device *device,
4629 const VkSamplerCreateInfo *pCreateInfo)
4630 {
4631 if (device->force_aniso >= 0)
4632 return device->force_aniso;
4633
4634 if (pCreateInfo->anisotropyEnable &&
4635 pCreateInfo->maxAnisotropy > 1.0f)
4636 return (uint32_t)pCreateInfo->maxAnisotropy;
4637
4638 return 0;
4639 }
4640
4641 static void
4642 radv_init_sampler(struct radv_device *device,
4643 struct radv_sampler *sampler,
4644 const VkSamplerCreateInfo *pCreateInfo)
4645 {
4646 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4647 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4648 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4649 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4650
4651 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4652 vk_find_struct_const(pCreateInfo->pNext,
4653 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4654 if (sampler_reduction)
4655 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4656
4657 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4658 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4659 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4660 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4661 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4662 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4663 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4664 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4665 S_008F30_DISABLE_CUBE_WRAP(0) |
4666 S_008F30_COMPAT_MODE(is_vi) |
4667 S_008F30_FILTER_MODE(filter_mode));
4668 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4669 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4670 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4671 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4672 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4673 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4674 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4675 S_008F38_MIP_POINT_PRECLAMP(0) |
4676 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4677 S_008F38_FILTER_PREC_FIX(1) |
4678 S_008F38_ANISO_OVERRIDE(is_vi));
4679 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4680 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4681 }
4682
4683 VkResult radv_CreateSampler(
4684 VkDevice _device,
4685 const VkSamplerCreateInfo* pCreateInfo,
4686 const VkAllocationCallbacks* pAllocator,
4687 VkSampler* pSampler)
4688 {
4689 RADV_FROM_HANDLE(radv_device, device, _device);
4690 struct radv_sampler *sampler;
4691
4692 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4693
4694 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4695 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4696 if (!sampler)
4697 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4698
4699 radv_init_sampler(device, sampler, pCreateInfo);
4700 *pSampler = radv_sampler_to_handle(sampler);
4701
4702 return VK_SUCCESS;
4703 }
4704
4705 void radv_DestroySampler(
4706 VkDevice _device,
4707 VkSampler _sampler,
4708 const VkAllocationCallbacks* pAllocator)
4709 {
4710 RADV_FROM_HANDLE(radv_device, device, _device);
4711 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4712
4713 if (!sampler)
4714 return;
4715 vk_free2(&device->alloc, pAllocator, sampler);
4716 }
4717
4718 /* vk_icd.h does not declare this function, so we declare it here to
4719 * suppress Wmissing-prototypes.
4720 */
4721 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4722 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4723
4724 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4725 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4726 {
4727 /* For the full details on loader interface versioning, see
4728 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4729 * What follows is a condensed summary, to help you navigate the large and
4730 * confusing official doc.
4731 *
4732 * - Loader interface v0 is incompatible with later versions. We don't
4733 * support it.
4734 *
4735 * - In loader interface v1:
4736 * - The first ICD entrypoint called by the loader is
4737 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4738 * entrypoint.
4739 * - The ICD must statically expose no other Vulkan symbol unless it is
4740 * linked with -Bsymbolic.
4741 * - Each dispatchable Vulkan handle created by the ICD must be
4742 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4743 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4744 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4745 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4746 * such loader-managed surfaces.
4747 *
4748 * - Loader interface v2 differs from v1 in:
4749 * - The first ICD entrypoint called by the loader is
4750 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4751 * statically expose this entrypoint.
4752 *
4753 * - Loader interface v3 differs from v2 in:
4754 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4755 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4756 * because the loader no longer does so.
4757 */
4758 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4759 return VK_SUCCESS;
4760 }
4761
4762 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4763 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4764 int *pFD)
4765 {
4766 RADV_FROM_HANDLE(radv_device, device, _device);
4767 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4768
4769 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4770
4771 /* At the moment, we support only the below handle types. */
4772 assert(pGetFdInfo->handleType ==
4773 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4774 pGetFdInfo->handleType ==
4775 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4776
4777 bool ret = radv_get_memory_fd(device, memory, pFD);
4778 if (ret == false)
4779 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4780 return VK_SUCCESS;
4781 }
4782
4783 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4784 VkExternalMemoryHandleTypeFlagBits handleType,
4785 int fd,
4786 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4787 {
4788 RADV_FROM_HANDLE(radv_device, device, _device);
4789
4790 switch (handleType) {
4791 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4792 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4793 return VK_SUCCESS;
4794
4795 default:
4796 /* The valid usage section for this function says:
4797 *
4798 * "handleType must not be one of the handle types defined as
4799 * opaque."
4800 *
4801 * So opaque handle types fall into the default "unsupported" case.
4802 */
4803 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4804 }
4805 }
4806
4807 static VkResult radv_import_opaque_fd(struct radv_device *device,
4808 int fd,
4809 uint32_t *syncobj)
4810 {
4811 uint32_t syncobj_handle = 0;
4812 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4813 if (ret != 0)
4814 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4815
4816 if (*syncobj)
4817 device->ws->destroy_syncobj(device->ws, *syncobj);
4818
4819 *syncobj = syncobj_handle;
4820 close(fd);
4821
4822 return VK_SUCCESS;
4823 }
4824
4825 static VkResult radv_import_sync_fd(struct radv_device *device,
4826 int fd,
4827 uint32_t *syncobj)
4828 {
4829 /* If we create a syncobj we do it locally so that if we have an error, we don't
4830 * leave a syncobj in an undetermined state in the fence. */
4831 uint32_t syncobj_handle = *syncobj;
4832 if (!syncobj_handle) {
4833 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4834 if (ret) {
4835 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4836 }
4837 }
4838
4839 if (fd == -1) {
4840 device->ws->signal_syncobj(device->ws, syncobj_handle);
4841 } else {
4842 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4843 if (ret != 0)
4844 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4845 }
4846
4847 *syncobj = syncobj_handle;
4848 if (fd != -1)
4849 close(fd);
4850
4851 return VK_SUCCESS;
4852 }
4853
4854 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4855 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4856 {
4857 RADV_FROM_HANDLE(radv_device, device, _device);
4858 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4859 uint32_t *syncobj_dst = NULL;
4860
4861 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4862 syncobj_dst = &sem->temp_syncobj;
4863 } else {
4864 syncobj_dst = &sem->syncobj;
4865 }
4866
4867 switch(pImportSemaphoreFdInfo->handleType) {
4868 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4869 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4870 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4871 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4872 default:
4873 unreachable("Unhandled semaphore handle type");
4874 }
4875 }
4876
4877 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4878 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4879 int *pFd)
4880 {
4881 RADV_FROM_HANDLE(radv_device, device, _device);
4882 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4883 int ret;
4884 uint32_t syncobj_handle;
4885
4886 if (sem->temp_syncobj)
4887 syncobj_handle = sem->temp_syncobj;
4888 else
4889 syncobj_handle = sem->syncobj;
4890
4891 switch(pGetFdInfo->handleType) {
4892 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4893 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4894 break;
4895 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4896 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4897 if (!ret) {
4898 if (sem->temp_syncobj) {
4899 close (sem->temp_syncobj);
4900 sem->temp_syncobj = 0;
4901 } else {
4902 device->ws->reset_syncobj(device->ws, syncobj_handle);
4903 }
4904 }
4905 break;
4906 default:
4907 unreachable("Unhandled semaphore handle type");
4908 }
4909
4910 if (ret)
4911 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4912 return VK_SUCCESS;
4913 }
4914
4915 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4916 VkPhysicalDevice physicalDevice,
4917 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4918 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4919 {
4920 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4921
4922 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4923 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4924 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4925 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4926 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4927 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4928 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4929 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4930 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4931 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4932 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4933 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4934 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4935 } else {
4936 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4937 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4938 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4939 }
4940 }
4941
4942 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4943 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4944 {
4945 RADV_FROM_HANDLE(radv_device, device, _device);
4946 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4947 uint32_t *syncobj_dst = NULL;
4948
4949
4950 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
4951 syncobj_dst = &fence->temp_syncobj;
4952 } else {
4953 syncobj_dst = &fence->syncobj;
4954 }
4955
4956 switch(pImportFenceFdInfo->handleType) {
4957 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
4958 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4959 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
4960 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4961 default:
4962 unreachable("Unhandled fence handle type");
4963 }
4964 }
4965
4966 VkResult radv_GetFenceFdKHR(VkDevice _device,
4967 const VkFenceGetFdInfoKHR *pGetFdInfo,
4968 int *pFd)
4969 {
4970 RADV_FROM_HANDLE(radv_device, device, _device);
4971 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4972 int ret;
4973 uint32_t syncobj_handle;
4974
4975 if (fence->temp_syncobj)
4976 syncobj_handle = fence->temp_syncobj;
4977 else
4978 syncobj_handle = fence->syncobj;
4979
4980 switch(pGetFdInfo->handleType) {
4981 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
4982 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4983 break;
4984 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
4985 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4986 if (!ret) {
4987 if (fence->temp_syncobj) {
4988 close (fence->temp_syncobj);
4989 fence->temp_syncobj = 0;
4990 } else {
4991 device->ws->reset_syncobj(device->ws, syncobj_handle);
4992 }
4993 }
4994 break;
4995 default:
4996 unreachable("Unhandled fence handle type");
4997 }
4998
4999 if (ret)
5000 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5001 return VK_SUCCESS;
5002 }
5003
5004 void radv_GetPhysicalDeviceExternalFenceProperties(
5005 VkPhysicalDevice physicalDevice,
5006 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5007 VkExternalFenceProperties *pExternalFenceProperties)
5008 {
5009 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5010
5011 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5012 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5013 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5014 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5015 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5016 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5017 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5018 } else {
5019 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5020 pExternalFenceProperties->compatibleHandleTypes = 0;
5021 pExternalFenceProperties->externalFenceFeatures = 0;
5022 }
5023 }
5024
5025 VkResult
5026 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5027 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5028 const VkAllocationCallbacks* pAllocator,
5029 VkDebugReportCallbackEXT* pCallback)
5030 {
5031 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5032 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5033 pCreateInfo, pAllocator, &instance->alloc,
5034 pCallback);
5035 }
5036
5037 void
5038 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5039 VkDebugReportCallbackEXT _callback,
5040 const VkAllocationCallbacks* pAllocator)
5041 {
5042 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5043 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5044 _callback, pAllocator, &instance->alloc);
5045 }
5046
5047 void
5048 radv_DebugReportMessageEXT(VkInstance _instance,
5049 VkDebugReportFlagsEXT flags,
5050 VkDebugReportObjectTypeEXT objectType,
5051 uint64_t object,
5052 size_t location,
5053 int32_t messageCode,
5054 const char* pLayerPrefix,
5055 const char* pMessage)
5056 {
5057 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5058 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5059 object, location, messageCode, pLayerPrefix, pMessage);
5060 }
5061
5062 void
5063 radv_GetDeviceGroupPeerMemoryFeatures(
5064 VkDevice device,
5065 uint32_t heapIndex,
5066 uint32_t localDeviceIndex,
5067 uint32_t remoteDeviceIndex,
5068 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5069 {
5070 assert(localDeviceIndex == remoteDeviceIndex);
5071
5072 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5073 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5074 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5075 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5076 }
5077
5078 static const VkTimeDomainEXT radv_time_domains[] = {
5079 VK_TIME_DOMAIN_DEVICE_EXT,
5080 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5081 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5082 };
5083
5084 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5085 VkPhysicalDevice physicalDevice,
5086 uint32_t *pTimeDomainCount,
5087 VkTimeDomainEXT *pTimeDomains)
5088 {
5089 int d;
5090 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5091
5092 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5093 vk_outarray_append(&out, i) {
5094 *i = radv_time_domains[d];
5095 }
5096 }
5097
5098 return vk_outarray_status(&out);
5099 }
5100
5101 static uint64_t
5102 radv_clock_gettime(clockid_t clock_id)
5103 {
5104 struct timespec current;
5105 int ret;
5106
5107 ret = clock_gettime(clock_id, &current);
5108 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5109 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5110 if (ret < 0)
5111 return 0;
5112
5113 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5114 }
5115
5116 VkResult radv_GetCalibratedTimestampsEXT(
5117 VkDevice _device,
5118 uint32_t timestampCount,
5119 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5120 uint64_t *pTimestamps,
5121 uint64_t *pMaxDeviation)
5122 {
5123 RADV_FROM_HANDLE(radv_device, device, _device);
5124 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5125 int d;
5126 uint64_t begin, end;
5127 uint64_t max_clock_period = 0;
5128
5129 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5130
5131 for (d = 0; d < timestampCount; d++) {
5132 switch (pTimestampInfos[d].timeDomain) {
5133 case VK_TIME_DOMAIN_DEVICE_EXT:
5134 pTimestamps[d] = device->ws->query_value(device->ws,
5135 RADEON_TIMESTAMP);
5136 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5137 max_clock_period = MAX2(max_clock_period, device_period);
5138 break;
5139 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5140 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5141 max_clock_period = MAX2(max_clock_period, 1);
5142 break;
5143
5144 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5145 pTimestamps[d] = begin;
5146 break;
5147 default:
5148 pTimestamps[d] = 0;
5149 break;
5150 }
5151 }
5152
5153 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5154
5155 /*
5156 * The maximum deviation is the sum of the interval over which we
5157 * perform the sampling and the maximum period of any sampled
5158 * clock. That's because the maximum skew between any two sampled
5159 * clock edges is when the sampled clock with the largest period is
5160 * sampled at the end of that period but right at the beginning of the
5161 * sampling interval and some other clock is sampled right at the
5162 * begining of its sampling period and right at the end of the
5163 * sampling interval. Let's assume the GPU has the longest clock
5164 * period and that the application is sampling GPU and monotonic:
5165 *
5166 * s e
5167 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5168 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5169 *
5170 * g
5171 * 0 1 2 3
5172 * GPU -----_____-----_____-----_____-----_____
5173 *
5174 * m
5175 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5176 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5177 *
5178 * Interval <----------------->
5179 * Deviation <-------------------------->
5180 *
5181 * s = read(raw) 2
5182 * g = read(GPU) 1
5183 * m = read(monotonic) 2
5184 * e = read(raw) b
5185 *
5186 * We round the sample interval up by one tick to cover sampling error
5187 * in the interval clock
5188 */
5189
5190 uint64_t sample_interval = end - begin + 1;
5191
5192 *pMaxDeviation = sample_interval + max_clock_period;
5193
5194 return VK_SUCCESS;
5195 }