projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Support v3 of VK_EXT_vertex_attribute_divisor.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void *));
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 } else if (!strcmp(name, "DOOM_VFR")) {
484 /* Work around a Doom VFR game bug */
485 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
486 }
487 }
488
489 static int radv_get_instance_extension_index(const char *name)
490 {
491 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
492 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
493 return i;
494 }
495 return -1;
496 }
497
498
499 VkResult radv_CreateInstance(
500 const VkInstanceCreateInfo* pCreateInfo,
501 const VkAllocationCallbacks* pAllocator,
502 VkInstance* pInstance)
503 {
504 struct radv_instance *instance;
505 VkResult result;
506
507 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
508
509 uint32_t client_version;
510 if (pCreateInfo->pApplicationInfo &&
511 pCreateInfo->pApplicationInfo->apiVersion != 0) {
512 client_version = pCreateInfo->pApplicationInfo->apiVersion;
513 } else {
514 radv_EnumerateInstanceVersion(&client_version);
515 }
516
517 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
518 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
519 if (!instance)
520 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
521
522 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
523
524 if (pAllocator)
525 instance->alloc = *pAllocator;
526 else
527 instance->alloc = default_alloc;
528
529 instance->apiVersion = client_version;
530 instance->physicalDeviceCount = -1;
531
532 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
533 radv_debug_options);
534
535 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
536 radv_perftest_options);
537
538
539 if (instance->debug_flags & RADV_DEBUG_STARTUP)
540 radv_logi("Created an instance");
541
542 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
543 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
544 int index = radv_get_instance_extension_index(ext_name);
545
546 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
547 vk_free2(&default_alloc, pAllocator, instance);
548 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
549 }
550
551 instance->enabled_extensions.extensions[index] = true;
552 }
553
554 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
555 if (result != VK_SUCCESS) {
556 vk_free2(&default_alloc, pAllocator, instance);
557 return vk_error(instance, result);
558 }
559
560 _mesa_locale_init();
561
562 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
563
564 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
565
566 *pInstance = radv_instance_to_handle(instance);
567
568 return VK_SUCCESS;
569 }
570
571 void radv_DestroyInstance(
572 VkInstance _instance,
573 const VkAllocationCallbacks* pAllocator)
574 {
575 RADV_FROM_HANDLE(radv_instance, instance, _instance);
576
577 if (!instance)
578 return;
579
580 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
581 radv_physical_device_finish(instance->physicalDevices + i);
582 }
583
584 VG(VALGRIND_DESTROY_MEMPOOL(instance));
585
586 _mesa_locale_fini();
587
588 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
589
590 vk_free(&instance->alloc, instance);
591 }
592
593 static VkResult
594 radv_enumerate_devices(struct radv_instance *instance)
595 {
596 /* TODO: Check for more devices ? */
597 drmDevicePtr devices[8];
598 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
599 int max_devices;
600
601 instance->physicalDeviceCount = 0;
602
603 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
604
605 if (instance->debug_flags & RADV_DEBUG_STARTUP)
606 radv_logi("Found %d drm nodes", max_devices);
607
608 if (max_devices < 1)
609 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
610
611 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
612 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
613 devices[i]->bustype == DRM_BUS_PCI &&
614 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
615
616 result = radv_physical_device_init(instance->physicalDevices +
617 instance->physicalDeviceCount,
618 instance,
619 devices[i]);
620 if (result == VK_SUCCESS)
621 ++instance->physicalDeviceCount;
622 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
623 break;
624 }
625 }
626 drmFreeDevices(devices, max_devices);
627
628 return result;
629 }
630
631 VkResult radv_EnumeratePhysicalDevices(
632 VkInstance _instance,
633 uint32_t* pPhysicalDeviceCount,
634 VkPhysicalDevice* pPhysicalDevices)
635 {
636 RADV_FROM_HANDLE(radv_instance, instance, _instance);
637 VkResult result;
638
639 if (instance->physicalDeviceCount < 0) {
640 result = radv_enumerate_devices(instance);
641 if (result != VK_SUCCESS &&
642 result != VK_ERROR_INCOMPATIBLE_DRIVER)
643 return result;
644 }
645
646 if (!pPhysicalDevices) {
647 *pPhysicalDeviceCount = instance->physicalDeviceCount;
648 } else {
649 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
650 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
651 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
652 }
653
654 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
655 : VK_SUCCESS;
656 }
657
658 VkResult radv_EnumeratePhysicalDeviceGroups(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceGroupCount,
661 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDeviceGroupProperties) {
674 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
678 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
679 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
680 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
681 }
682 }
683 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
684 : VK_SUCCESS;
685 }
686
687 void radv_GetPhysicalDeviceFeatures(
688 VkPhysicalDevice physicalDevice,
689 VkPhysicalDeviceFeatures* pFeatures)
690 {
691 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
692 memset(pFeatures, 0, sizeof(*pFeatures));
693
694 *pFeatures = (VkPhysicalDeviceFeatures) {
695 .robustBufferAccess = true,
696 .fullDrawIndexUint32 = true,
697 .imageCubeArray = true,
698 .independentBlend = true,
699 .geometryShader = true,
700 .tessellationShader = true,
701 .sampleRateShading = true,
702 .dualSrcBlend = true,
703 .logicOp = true,
704 .multiDrawIndirect = true,
705 .drawIndirectFirstInstance = true,
706 .depthClamp = true,
707 .depthBiasClamp = true,
708 .fillModeNonSolid = true,
709 .depthBounds = true,
710 .wideLines = true,
711 .largePoints = true,
712 .alphaToOne = true,
713 .multiViewport = true,
714 .samplerAnisotropy = true,
715 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
716 pdevice->rad_info.family == CHIP_STONEY,
717 .textureCompressionASTC_LDR = false,
718 .textureCompressionBC = true,
719 .occlusionQueryPrecise = true,
720 .pipelineStatisticsQuery = true,
721 .vertexPipelineStoresAndAtomics = true,
722 .fragmentStoresAndAtomics = true,
723 .shaderTessellationAndGeometryPointSize = true,
724 .shaderImageGatherExtended = true,
725 .shaderStorageImageExtendedFormats = true,
726 .shaderStorageImageMultisample = false,
727 .shaderUniformBufferArrayDynamicIndexing = true,
728 .shaderSampledImageArrayDynamicIndexing = true,
729 .shaderStorageBufferArrayDynamicIndexing = true,
730 .shaderStorageImageArrayDynamicIndexing = true,
731 .shaderStorageImageReadWithoutFormat = true,
732 .shaderStorageImageWriteWithoutFormat = true,
733 .shaderClipDistance = true,
734 .shaderCullDistance = true,
735 .shaderFloat64 = true,
736 .shaderInt64 = true,
737 .shaderInt16 = false,
738 .sparseBinding = true,
739 .variableMultisampleRate = true,
740 .inheritedQueries = true,
741 };
742 }
743
744 void radv_GetPhysicalDeviceFeatures2(
745 VkPhysicalDevice physicalDevice,
746 VkPhysicalDeviceFeatures2KHR *pFeatures)
747 {
748 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
749 vk_foreach_struct(ext, pFeatures->pNext) {
750 switch (ext->sType) {
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
752 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
753 features->variablePointersStorageBuffer = true;
754 features->variablePointers = false;
755 break;
756 }
757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
758 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
759 features->multiview = true;
760 features->multiviewGeometryShader = true;
761 features->multiviewTessellationShader = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
765 VkPhysicalDeviceShaderDrawParameterFeatures *features =
766 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
767 features->shaderDrawParameters = true;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
771 VkPhysicalDeviceProtectedMemoryFeatures *features =
772 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
773 features->protectedMemory = false;
774 break;
775 }
776 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
777 VkPhysicalDevice16BitStorageFeatures *features =
778 (VkPhysicalDevice16BitStorageFeatures*)ext;
779 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
780 features->storageBuffer16BitAccess = enabled;
781 features->uniformAndStorageBuffer16BitAccess = enabled;
782 features->storagePushConstant16 = enabled;
783 features->storageInputOutput16 = enabled;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
787 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
788 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
789 features->samplerYcbcrConversion = false;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
793 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
794 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
795 features->shaderInputAttachmentArrayDynamicIndexing = true;
796 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
797 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
798 features->shaderUniformBufferArrayNonUniformIndexing = false;
799 features->shaderSampledImageArrayNonUniformIndexing = false;
800 features->shaderStorageBufferArrayNonUniformIndexing = false;
801 features->shaderStorageImageArrayNonUniformIndexing = false;
802 features->shaderInputAttachmentArrayNonUniformIndexing = false;
803 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
804 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
805 features->descriptorBindingUniformBufferUpdateAfterBind = true;
806 features->descriptorBindingSampledImageUpdateAfterBind = true;
807 features->descriptorBindingStorageImageUpdateAfterBind = true;
808 features->descriptorBindingStorageBufferUpdateAfterBind = true;
809 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
810 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
811 features->descriptorBindingUpdateUnusedWhilePending = true;
812 features->descriptorBindingPartiallyBound = true;
813 features->descriptorBindingVariableDescriptorCount = true;
814 features->runtimeDescriptorArray = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
818 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
819 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
820 features->conditionalRendering = true;
821 features->inheritedConditionalRendering = false;
822 break;
823 }
824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
825 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
826 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
827 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
828 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
829 break;
830 }
831 default:
832 break;
833 }
834 }
835 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
836 }
837
838 void radv_GetPhysicalDeviceProperties(
839 VkPhysicalDevice physicalDevice,
840 VkPhysicalDeviceProperties* pProperties)
841 {
842 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
843 VkSampleCountFlags sample_counts = 0xf;
844
845 /* make sure that the entire descriptor set is addressable with a signed
846 * 32-bit int. So the sum of all limits scaled by descriptor size has to
847 * be at most 2 GiB. the combined image & samples object count as one of
848 * both. This limit is for the pipeline layout, not for the set layout, but
849 * there is no set limit, so we just set a pipeline limit. I don't think
850 * any app is going to hit this soon. */
851 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
852 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
853 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
854 32 /* sampler, largest when combined with image */ +
855 64 /* sampled image */ +
856 64 /* storage image */);
857
858 VkPhysicalDeviceLimits limits = {
859 .maxImageDimension1D = (1 << 14),
860 .maxImageDimension2D = (1 << 14),
861 .maxImageDimension3D = (1 << 11),
862 .maxImageDimensionCube = (1 << 14),
863 .maxImageArrayLayers = (1 << 11),
864 .maxTexelBufferElements = 128 * 1024 * 1024,
865 .maxUniformBufferRange = UINT32_MAX,
866 .maxStorageBufferRange = UINT32_MAX,
867 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
868 .maxMemoryAllocationCount = UINT32_MAX,
869 .maxSamplerAllocationCount = 64 * 1024,
870 .bufferImageGranularity = 64, /* A cache line */
871 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
872 .maxBoundDescriptorSets = MAX_SETS,
873 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
874 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
875 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
876 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
877 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
878 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
879 .maxPerStageResources = max_descriptor_set_size,
880 .maxDescriptorSetSamplers = max_descriptor_set_size,
881 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
882 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
883 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
884 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
885 .maxDescriptorSetSampledImages = max_descriptor_set_size,
886 .maxDescriptorSetStorageImages = max_descriptor_set_size,
887 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
888 .maxVertexInputAttributes = 32,
889 .maxVertexInputBindings = 32,
890 .maxVertexInputAttributeOffset = 2047,
891 .maxVertexInputBindingStride = 2048,
892 .maxVertexOutputComponents = 128,
893 .maxTessellationGenerationLevel = 64,
894 .maxTessellationPatchSize = 32,
895 .maxTessellationControlPerVertexInputComponents = 128,
896 .maxTessellationControlPerVertexOutputComponents = 128,
897 .maxTessellationControlPerPatchOutputComponents = 120,
898 .maxTessellationControlTotalOutputComponents = 4096,
899 .maxTessellationEvaluationInputComponents = 128,
900 .maxTessellationEvaluationOutputComponents = 128,
901 .maxGeometryShaderInvocations = 127,
902 .maxGeometryInputComponents = 64,
903 .maxGeometryOutputComponents = 128,
904 .maxGeometryOutputVertices = 256,
905 .maxGeometryTotalOutputComponents = 1024,
906 .maxFragmentInputComponents = 128,
907 .maxFragmentOutputAttachments = 8,
908 .maxFragmentDualSrcAttachments = 1,
909 .maxFragmentCombinedOutputResources = 8,
910 .maxComputeSharedMemorySize = 32768,
911 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
912 .maxComputeWorkGroupInvocations = 2048,
913 .maxComputeWorkGroupSize = {
914 2048,
915 2048,
916 2048
917 },
918 .subPixelPrecisionBits = 4 /* FIXME */,
919 .subTexelPrecisionBits = 4 /* FIXME */,
920 .mipmapPrecisionBits = 4 /* FIXME */,
921 .maxDrawIndexedIndexValue = UINT32_MAX,
922 .maxDrawIndirectCount = UINT32_MAX,
923 .maxSamplerLodBias = 16,
924 .maxSamplerAnisotropy = 16,
925 .maxViewports = MAX_VIEWPORTS,
926 .maxViewportDimensions = { (1 << 14), (1 << 14) },
927 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
928 .viewportSubPixelBits = 8,
929 .minMemoryMapAlignment = 4096, /* A page */
930 .minTexelBufferOffsetAlignment = 1,
931 .minUniformBufferOffsetAlignment = 4,
932 .minStorageBufferOffsetAlignment = 4,
933 .minTexelOffset = -32,
934 .maxTexelOffset = 31,
935 .minTexelGatherOffset = -32,
936 .maxTexelGatherOffset = 31,
937 .minInterpolationOffset = -2,
938 .maxInterpolationOffset = 2,
939 .subPixelInterpolationOffsetBits = 8,
940 .maxFramebufferWidth = (1 << 14),
941 .maxFramebufferHeight = (1 << 14),
942 .maxFramebufferLayers = (1 << 10),
943 .framebufferColorSampleCounts = sample_counts,
944 .framebufferDepthSampleCounts = sample_counts,
945 .framebufferStencilSampleCounts = sample_counts,
946 .framebufferNoAttachmentsSampleCounts = sample_counts,
947 .maxColorAttachments = MAX_RTS,
948 .sampledImageColorSampleCounts = sample_counts,
949 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
950 .sampledImageDepthSampleCounts = sample_counts,
951 .sampledImageStencilSampleCounts = sample_counts,
952 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
953 .maxSampleMaskWords = 1,
954 .timestampComputeAndGraphics = true,
955 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
956 .maxClipDistances = 8,
957 .maxCullDistances = 8,
958 .maxCombinedClipAndCullDistances = 8,
959 .discreteQueuePriorities = 1,
960 .pointSizeRange = { 0.125, 255.875 },
961 .lineWidthRange = { 0.0, 7.9921875 },
962 .pointSizeGranularity = (1.0 / 8.0),
963 .lineWidthGranularity = (1.0 / 128.0),
964 .strictLines = false, /* FINISHME */
965 .standardSampleLocations = true,
966 .optimalBufferCopyOffsetAlignment = 128,
967 .optimalBufferCopyRowPitchAlignment = 128,
968 .nonCoherentAtomSize = 64,
969 };
970
971 *pProperties = (VkPhysicalDeviceProperties) {
972 .apiVersion = radv_physical_device_api_version(pdevice),
973 .driverVersion = vk_get_driver_version(),
974 .vendorID = ATI_VENDOR_ID,
975 .deviceID = pdevice->rad_info.pci_id,
976 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
977 .limits = limits,
978 .sparseProperties = {0},
979 };
980
981 strcpy(pProperties->deviceName, pdevice->name);
982 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
983 }
984
985 void radv_GetPhysicalDeviceProperties2(
986 VkPhysicalDevice physicalDevice,
987 VkPhysicalDeviceProperties2KHR *pProperties)
988 {
989 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
990 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
991
992 vk_foreach_struct(ext, pProperties->pNext) {
993 switch (ext->sType) {
994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
995 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
996 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
997 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
998 break;
999 }
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1001 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1002 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1003 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1004 properties->deviceLUIDValid = false;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1008 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1009 properties->maxMultiviewViewCount = MAX_VIEWS;
1010 properties->maxMultiviewInstanceIndex = INT_MAX;
1011 break;
1012 }
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1014 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1015 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1016 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1020 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1021 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1022 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1023 break;
1024 }
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1026 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1027 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1028 properties->minImportedHostPointerAlignment = 4096;
1029 break;
1030 }
1031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1032 VkPhysicalDeviceSubgroupProperties *properties =
1033 (VkPhysicalDeviceSubgroupProperties*)ext;
1034 properties->subgroupSize = 64;
1035 properties->supportedStages = VK_SHADER_STAGE_ALL;
1036 properties->supportedOperations =
1037 VK_SUBGROUP_FEATURE_BASIC_BIT |
1038 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1039 VK_SUBGROUP_FEATURE_QUAD_BIT |
1040 VK_SUBGROUP_FEATURE_VOTE_BIT;
1041 if (pdevice->rad_info.chip_class >= VI) {
1042 properties->supportedOperations |=
1043 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1044 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1045 }
1046 properties->quadOperationsInAllStages = true;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1050 VkPhysicalDeviceMaintenance3Properties *properties =
1051 (VkPhysicalDeviceMaintenance3Properties*)ext;
1052 /* Make sure everything is addressable by a signed 32-bit int, and
1053 * our largest descriptors are 96 bytes. */
1054 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1055 /* Our buffer size fields allow only this much */
1056 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1057 break;
1058 }
1059 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1060 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1061 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1062 /* GFX6-8 only support single channel min/max filter. */
1063 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1064 properties->filterMinmaxSingleComponentFormats = true;
1065 break;
1066 }
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1068 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1069 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1070
1071 /* Shader engines. */
1072 properties->shaderEngineCount =
1073 pdevice->rad_info.max_se;
1074 properties->shaderArraysPerEngineCount =
1075 pdevice->rad_info.max_sh_per_se;
1076 properties->computeUnitsPerShaderArray =
1077 pdevice->rad_info.num_good_compute_units /
1078 (pdevice->rad_info.max_se *
1079 pdevice->rad_info.max_sh_per_se);
1080 properties->simdPerComputeUnit = 4;
1081 properties->wavefrontsPerSimd =
1082 pdevice->rad_info.family == CHIP_TONGA ||
1083 pdevice->rad_info.family == CHIP_ICELAND ||
1084 pdevice->rad_info.family == CHIP_POLARIS10 ||
1085 pdevice->rad_info.family == CHIP_POLARIS11 ||
1086 pdevice->rad_info.family == CHIP_POLARIS12 ||
1087 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1088 properties->wavefrontSize = 64;
1089
1090 /* SGPR. */
1091 properties->sgprsPerSimd =
1092 radv_get_num_physical_sgprs(pdevice);
1093 properties->minSgprAllocation =
1094 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1095 properties->maxSgprAllocation =
1096 pdevice->rad_info.family == CHIP_TONGA ||
1097 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1098 properties->sgprAllocationGranularity =
1099 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1100
1101 /* VGPR. */
1102 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1103 properties->minVgprAllocation = 4;
1104 properties->maxVgprAllocation = 256;
1105 properties->vgprAllocationGranularity = 4;
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1109 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1110 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1111 properties->maxVertexAttribDivisor = UINT32_MAX;
1112 break;
1113 }
1114 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1115 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1116 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1117 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1118 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1119 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1120 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1121 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1122 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1123 properties->robustBufferAccessUpdateAfterBind = false;
1124 properties->quadDivergentImplicitLod = false;
1125
1126 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1127 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1128 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1129 32 /* sampler, largest when combined with image */ +
1130 64 /* sampled image */ +
1131 64 /* storage image */);
1132 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1133 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1134 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1135 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1136 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1137 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1138 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1139 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1140 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1141 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1142 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1143 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1144 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1145 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1146 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1147 break;
1148 }
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1150 VkPhysicalDeviceProtectedMemoryProperties *properties =
1151 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1152 properties->protectedNoFault = false;
1153 break;
1154 }
1155 default:
1156 break;
1157 }
1158 }
1159 }
1160
1161 static void radv_get_physical_device_queue_family_properties(
1162 struct radv_physical_device* pdevice,
1163 uint32_t* pCount,
1164 VkQueueFamilyProperties** pQueueFamilyProperties)
1165 {
1166 int num_queue_families = 1;
1167 int idx;
1168 if (pdevice->rad_info.num_compute_rings > 0 &&
1169 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1170 num_queue_families++;
1171
1172 if (pQueueFamilyProperties == NULL) {
1173 *pCount = num_queue_families;
1174 return;
1175 }
1176
1177 if (!*pCount)
1178 return;
1179
1180 idx = 0;
1181 if (*pCount >= 1) {
1182 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1183 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1184 VK_QUEUE_COMPUTE_BIT |
1185 VK_QUEUE_TRANSFER_BIT |
1186 VK_QUEUE_SPARSE_BINDING_BIT,
1187 .queueCount = 1,
1188 .timestampValidBits = 64,
1189 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1190 };
1191 idx++;
1192 }
1193
1194 if (pdevice->rad_info.num_compute_rings > 0 &&
1195 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1196 if (*pCount > idx) {
1197 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1198 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1199 VK_QUEUE_TRANSFER_BIT |
1200 VK_QUEUE_SPARSE_BINDING_BIT,
1201 .queueCount = pdevice->rad_info.num_compute_rings,
1202 .timestampValidBits = 64,
1203 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1204 };
1205 idx++;
1206 }
1207 }
1208 *pCount = idx;
1209 }
1210
1211 void radv_GetPhysicalDeviceQueueFamilyProperties(
1212 VkPhysicalDevice physicalDevice,
1213 uint32_t* pCount,
1214 VkQueueFamilyProperties* pQueueFamilyProperties)
1215 {
1216 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1217 if (!pQueueFamilyProperties) {
1218 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1219 return;
1220 }
1221 VkQueueFamilyProperties *properties[] = {
1222 pQueueFamilyProperties + 0,
1223 pQueueFamilyProperties + 1,
1224 pQueueFamilyProperties + 2,
1225 };
1226 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1227 assert(*pCount <= 3);
1228 }
1229
1230 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1231 VkPhysicalDevice physicalDevice,
1232 uint32_t* pCount,
1233 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1234 {
1235 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1236 if (!pQueueFamilyProperties) {
1237 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1238 return;
1239 }
1240 VkQueueFamilyProperties *properties[] = {
1241 &pQueueFamilyProperties[0].queueFamilyProperties,
1242 &pQueueFamilyProperties[1].queueFamilyProperties,
1243 &pQueueFamilyProperties[2].queueFamilyProperties,
1244 };
1245 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1246 assert(*pCount <= 3);
1247 }
1248
1249 void radv_GetPhysicalDeviceMemoryProperties(
1250 VkPhysicalDevice physicalDevice,
1251 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1252 {
1253 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1254
1255 *pMemoryProperties = physical_device->memory_properties;
1256 }
1257
1258 void radv_GetPhysicalDeviceMemoryProperties2(
1259 VkPhysicalDevice physicalDevice,
1260 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1261 {
1262 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1263 &pMemoryProperties->memoryProperties);
1264 }
1265
1266 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1267 VkDevice _device,
1268 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1269 const void *pHostPointer,
1270 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1271 {
1272 RADV_FROM_HANDLE(radv_device, device, _device);
1273
1274 switch (handleType)
1275 {
1276 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1277 const struct radv_physical_device *physical_device = device->physical_device;
1278 uint32_t memoryTypeBits = 0;
1279 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1280 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1281 memoryTypeBits = (1 << i);
1282 break;
1283 }
1284 }
1285 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1286 return VK_SUCCESS;
1287 }
1288 default:
1289 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1290 }
1291 }
1292
1293 static enum radeon_ctx_priority
1294 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1295 {
1296 /* Default to MEDIUM when a specific global priority isn't requested */
1297 if (!pObj)
1298 return RADEON_CTX_PRIORITY_MEDIUM;
1299
1300 switch(pObj->globalPriority) {
1301 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1302 return RADEON_CTX_PRIORITY_REALTIME;
1303 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1304 return RADEON_CTX_PRIORITY_HIGH;
1305 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1306 return RADEON_CTX_PRIORITY_MEDIUM;
1307 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1308 return RADEON_CTX_PRIORITY_LOW;
1309 default:
1310 unreachable("Illegal global priority value");
1311 return RADEON_CTX_PRIORITY_INVALID;
1312 }
1313 }
1314
1315 static int
1316 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1317 uint32_t queue_family_index, int idx,
1318 VkDeviceQueueCreateFlags flags,
1319 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1320 {
1321 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1322 queue->device = device;
1323 queue->queue_family_index = queue_family_index;
1324 queue->queue_idx = idx;
1325 queue->priority = radv_get_queue_global_priority(global_priority);
1326 queue->flags = flags;
1327
1328 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1329 if (!queue->hw_ctx)
1330 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1331
1332 return VK_SUCCESS;
1333 }
1334
1335 static void
1336 radv_queue_finish(struct radv_queue *queue)
1337 {
1338 if (queue->hw_ctx)
1339 queue->device->ws->ctx_destroy(queue->hw_ctx);
1340
1341 if (queue->initial_full_flush_preamble_cs)
1342 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1343 if (queue->initial_preamble_cs)
1344 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1345 if (queue->continue_preamble_cs)
1346 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1347 if (queue->descriptor_bo)
1348 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1349 if (queue->scratch_bo)
1350 queue->device->ws->buffer_destroy(queue->scratch_bo);
1351 if (queue->esgs_ring_bo)
1352 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1353 if (queue->gsvs_ring_bo)
1354 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1355 if (queue->tess_rings_bo)
1356 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1357 if (queue->compute_scratch_bo)
1358 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1359 }
1360
1361 static void
1362 radv_bo_list_init(struct radv_bo_list *bo_list)
1363 {
1364 pthread_mutex_init(&bo_list->mutex, NULL);
1365 bo_list->list.count = bo_list->capacity = 0;
1366 bo_list->list.bos = NULL;
1367 }
1368
1369 static void
1370 radv_bo_list_finish(struct radv_bo_list *bo_list)
1371 {
1372 free(bo_list->list.bos);
1373 pthread_mutex_destroy(&bo_list->mutex);
1374 }
1375
1376 static VkResult radv_bo_list_add(struct radv_device *device,
1377 struct radeon_winsys_bo *bo)
1378 {
1379 struct radv_bo_list *bo_list = &device->bo_list;
1380
1381 if (unlikely(!device->use_global_bo_list))
1382 return VK_SUCCESS;
1383
1384 pthread_mutex_lock(&bo_list->mutex);
1385 if (bo_list->list.count == bo_list->capacity) {
1386 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1387 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1388
1389 if (!data) {
1390 pthread_mutex_unlock(&bo_list->mutex);
1391 return VK_ERROR_OUT_OF_HOST_MEMORY;
1392 }
1393
1394 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1395 bo_list->capacity = capacity;
1396 }
1397
1398 bo_list->list.bos[bo_list->list.count++] = bo;
1399 pthread_mutex_unlock(&bo_list->mutex);
1400 return VK_SUCCESS;
1401 }
1402
1403 static void radv_bo_list_remove(struct radv_device *device,
1404 struct radeon_winsys_bo *bo)
1405 {
1406 struct radv_bo_list *bo_list = &device->bo_list;
1407
1408 if (unlikely(!device->use_global_bo_list))
1409 return;
1410
1411 pthread_mutex_lock(&bo_list->mutex);
1412 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1413 if (bo_list->list.bos[i] == bo) {
1414 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1415 --bo_list->list.count;
1416 break;
1417 }
1418 }
1419 pthread_mutex_unlock(&bo_list->mutex);
1420 }
1421
1422 static void
1423 radv_device_init_gs_info(struct radv_device *device)
1424 {
1425 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1426 device->physical_device->rad_info.family);
1427 }
1428
1429 static int radv_get_device_extension_index(const char *name)
1430 {
1431 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1432 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1433 return i;
1434 }
1435 return -1;
1436 }
1437
1438 VkResult radv_CreateDevice(
1439 VkPhysicalDevice physicalDevice,
1440 const VkDeviceCreateInfo* pCreateInfo,
1441 const VkAllocationCallbacks* pAllocator,
1442 VkDevice* pDevice)
1443 {
1444 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1445 VkResult result;
1446 struct radv_device *device;
1447
1448 bool keep_shader_info = false;
1449
1450 /* Check enabled features */
1451 if (pCreateInfo->pEnabledFeatures) {
1452 VkPhysicalDeviceFeatures supported_features;
1453 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1454 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1455 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1456 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1457 for (uint32_t i = 0; i < num_features; i++) {
1458 if (enabled_feature[i] && !supported_feature[i])
1459 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1460 }
1461 }
1462
1463 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1464 sizeof(*device), 8,
1465 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1466 if (!device)
1467 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1468
1469 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1470 device->instance = physical_device->instance;
1471 device->physical_device = physical_device;
1472
1473 device->ws = physical_device->ws;
1474 if (pAllocator)
1475 device->alloc = *pAllocator;
1476 else
1477 device->alloc = physical_device->instance->alloc;
1478
1479 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1480 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1481 int index = radv_get_device_extension_index(ext_name);
1482 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1483 vk_free(&device->alloc, device);
1484 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1485 }
1486
1487 device->enabled_extensions.extensions[index] = true;
1488 }
1489
1490 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1491
1492 /* With update after bind we can't attach bo's to the command buffer
1493 * from the descriptor set anymore, so we have to use a global BO list.
1494 */
1495 device->use_global_bo_list =
1496 device->enabled_extensions.EXT_descriptor_indexing;
1497
1498 mtx_init(&device->shader_slab_mutex, mtx_plain);
1499 list_inithead(&device->shader_slabs);
1500
1501 radv_bo_list_init(&device->bo_list);
1502
1503 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1504 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1505 uint32_t qfi = queue_create->queueFamilyIndex;
1506 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1507 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1508
1509 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1510
1511 device->queues[qfi] = vk_alloc(&device->alloc,
1512 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1513 if (!device->queues[qfi]) {
1514 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1515 goto fail;
1516 }
1517
1518 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1519
1520 device->queue_count[qfi] = queue_create->queueCount;
1521
1522 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1523 result = radv_queue_init(device, &device->queues[qfi][q],
1524 qfi, q, queue_create->flags,
1525 global_priority);
1526 if (result != VK_SUCCESS)
1527 goto fail;
1528 }
1529 }
1530
1531 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1532 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1533 device->physical_device->rad_info.family == CHIP_RAVEN);
1534
1535 /* Disabled and not implemented for now. */
1536 device->dfsm_allowed = device->pbb_allowed &&
1537 device->physical_device->rad_info.family == CHIP_RAVEN;
1538
1539 #ifdef ANDROID
1540 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1541 #endif
1542
1543 /* The maximum number of scratch waves. Scratch space isn't divided
1544 * evenly between CUs. The number is only a function of the number of CUs.
1545 * We can decrease the constant to decrease the scratch buffer size.
1546 *
1547 * sctx->scratch_waves must be >= the maximum possible size of
1548 * 1 threadgroup, so that the hw doesn't hang from being unable
1549 * to start any.
1550 *
1551 * The recommended value is 4 per CU at most. Higher numbers don't
1552 * bring much benefit, but they still occupy chip resources (think
1553 * async compute). I've seen ~2% performance difference between 4 and 32.
1554 */
1555 uint32_t max_threads_per_block = 2048;
1556 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1557 max_threads_per_block / 64);
1558
1559 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1560
1561 if (device->physical_device->rad_info.chip_class >= CIK) {
1562 /* If the KMD allows it (there is a KMD hw register for it),
1563 * allow launching waves out-of-order.
1564 */
1565 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1566 }
1567
1568 radv_device_init_gs_info(device);
1569
1570 device->tess_offchip_block_dw_size =
1571 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1572 device->has_distributed_tess =
1573 device->physical_device->rad_info.chip_class >= VI &&
1574 device->physical_device->rad_info.max_se >= 2;
1575
1576 if (getenv("RADV_TRACE_FILE")) {
1577 const char *filename = getenv("RADV_TRACE_FILE");
1578
1579 keep_shader_info = true;
1580
1581 if (!radv_init_trace(device))
1582 goto fail;
1583
1584 fprintf(stderr, "*****************************************************************************\n");
1585 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1586 fprintf(stderr, "*****************************************************************************\n");
1587
1588 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1589 radv_dump_enabled_options(device, stderr);
1590 }
1591
1592 device->keep_shader_info = keep_shader_info;
1593
1594 result = radv_device_init_meta(device);
1595 if (result != VK_SUCCESS)
1596 goto fail;
1597
1598 radv_device_init_msaa(device);
1599
1600 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1601 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1602 switch (family) {
1603 case RADV_QUEUE_GENERAL:
1604 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1605 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1606 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1607 break;
1608 case RADV_QUEUE_COMPUTE:
1609 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1610 radeon_emit(device->empty_cs[family], 0);
1611 break;
1612 }
1613 device->ws->cs_finalize(device->empty_cs[family]);
1614 }
1615
1616 if (device->physical_device->rad_info.chip_class >= CIK)
1617 cik_create_gfx_config(device);
1618
1619 VkPipelineCacheCreateInfo ci;
1620 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1621 ci.pNext = NULL;
1622 ci.flags = 0;
1623 ci.pInitialData = NULL;
1624 ci.initialDataSize = 0;
1625 VkPipelineCache pc;
1626 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1627 &ci, NULL, &pc);
1628 if (result != VK_SUCCESS)
1629 goto fail_meta;
1630
1631 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1632
1633 *pDevice = radv_device_to_handle(device);
1634 return VK_SUCCESS;
1635
1636 fail_meta:
1637 radv_device_finish_meta(device);
1638 fail:
1639 radv_bo_list_finish(&device->bo_list);
1640
1641 if (device->trace_bo)
1642 device->ws->buffer_destroy(device->trace_bo);
1643
1644 if (device->gfx_init)
1645 device->ws->buffer_destroy(device->gfx_init);
1646
1647 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1648 for (unsigned q = 0; q < device->queue_count[i]; q++)
1649 radv_queue_finish(&device->queues[i][q]);
1650 if (device->queue_count[i])
1651 vk_free(&device->alloc, device->queues[i]);
1652 }
1653
1654 vk_free(&device->alloc, device);
1655 return result;
1656 }
1657
1658 void radv_DestroyDevice(
1659 VkDevice _device,
1660 const VkAllocationCallbacks* pAllocator)
1661 {
1662 RADV_FROM_HANDLE(radv_device, device, _device);
1663
1664 if (!device)
1665 return;
1666
1667 if (device->trace_bo)
1668 device->ws->buffer_destroy(device->trace_bo);
1669
1670 if (device->gfx_init)
1671 device->ws->buffer_destroy(device->gfx_init);
1672
1673 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1674 for (unsigned q = 0; q < device->queue_count[i]; q++)
1675 radv_queue_finish(&device->queues[i][q]);
1676 if (device->queue_count[i])
1677 vk_free(&device->alloc, device->queues[i]);
1678 if (device->empty_cs[i])
1679 device->ws->cs_destroy(device->empty_cs[i]);
1680 }
1681 radv_device_finish_meta(device);
1682
1683 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1684 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1685
1686 radv_destroy_shader_slabs(device);
1687
1688 radv_bo_list_finish(&device->bo_list);
1689 vk_free(&device->alloc, device);
1690 }
1691
1692 VkResult radv_EnumerateInstanceLayerProperties(
1693 uint32_t* pPropertyCount,
1694 VkLayerProperties* pProperties)
1695 {
1696 if (pProperties == NULL) {
1697 *pPropertyCount = 0;
1698 return VK_SUCCESS;
1699 }
1700
1701 /* None supported at this time */
1702 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1703 }
1704
1705 VkResult radv_EnumerateDeviceLayerProperties(
1706 VkPhysicalDevice physicalDevice,
1707 uint32_t* pPropertyCount,
1708 VkLayerProperties* pProperties)
1709 {
1710 if (pProperties == NULL) {
1711 *pPropertyCount = 0;
1712 return VK_SUCCESS;
1713 }
1714
1715 /* None supported at this time */
1716 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1717 }
1718
1719 void radv_GetDeviceQueue2(
1720 VkDevice _device,
1721 const VkDeviceQueueInfo2* pQueueInfo,
1722 VkQueue* pQueue)
1723 {
1724 RADV_FROM_HANDLE(radv_device, device, _device);
1725 struct radv_queue *queue;
1726
1727 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1728 if (pQueueInfo->flags != queue->flags) {
1729 /* From the Vulkan 1.1.70 spec:
1730 *
1731 * "The queue returned by vkGetDeviceQueue2 must have the same
1732 * flags value from this structure as that used at device
1733 * creation time in a VkDeviceQueueCreateInfo instance. If no
1734 * matching flags were specified at device creation time then
1735 * pQueue will return VK_NULL_HANDLE."
1736 */
1737 *pQueue = VK_NULL_HANDLE;
1738 return;
1739 }
1740
1741 *pQueue = radv_queue_to_handle(queue);
1742 }
1743
1744 void radv_GetDeviceQueue(
1745 VkDevice _device,
1746 uint32_t queueFamilyIndex,
1747 uint32_t queueIndex,
1748 VkQueue* pQueue)
1749 {
1750 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1751 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1752 .queueFamilyIndex = queueFamilyIndex,
1753 .queueIndex = queueIndex
1754 };
1755
1756 radv_GetDeviceQueue2(_device, &info, pQueue);
1757 }
1758
1759 static void
1760 fill_geom_tess_rings(struct radv_queue *queue,
1761 uint32_t *map,
1762 bool add_sample_positions,
1763 uint32_t esgs_ring_size,
1764 struct radeon_winsys_bo *esgs_ring_bo,
1765 uint32_t gsvs_ring_size,
1766 struct radeon_winsys_bo *gsvs_ring_bo,
1767 uint32_t tess_factor_ring_size,
1768 uint32_t tess_offchip_ring_offset,
1769 uint32_t tess_offchip_ring_size,
1770 struct radeon_winsys_bo *tess_rings_bo)
1771 {
1772 uint64_t esgs_va = 0, gsvs_va = 0;
1773 uint64_t tess_va = 0, tess_offchip_va = 0;
1774 uint32_t *desc = &map[4];
1775
1776 if (esgs_ring_bo)
1777 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1778 if (gsvs_ring_bo)
1779 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1780 if (tess_rings_bo) {
1781 tess_va = radv_buffer_get_va(tess_rings_bo);
1782 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1783 }
1784
1785 /* stride 0, num records - size, add tid, swizzle, elsize4,
1786 index stride 64 */
1787 desc[0] = esgs_va;
1788 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1789 S_008F04_STRIDE(0) |
1790 S_008F04_SWIZZLE_ENABLE(true);
1791 desc[2] = esgs_ring_size;
1792 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1793 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1794 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1795 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1796 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1797 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1798 S_008F0C_ELEMENT_SIZE(1) |
1799 S_008F0C_INDEX_STRIDE(3) |
1800 S_008F0C_ADD_TID_ENABLE(true);
1801
1802 desc += 4;
1803 /* GS entry for ES->GS ring */
1804 /* stride 0, num records - size, elsize0,
1805 index stride 0 */
1806 desc[0] = esgs_va;
1807 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1808 S_008F04_STRIDE(0) |
1809 S_008F04_SWIZZLE_ENABLE(false);
1810 desc[2] = esgs_ring_size;
1811 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1812 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1813 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1814 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1815 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1816 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1817 S_008F0C_ELEMENT_SIZE(0) |
1818 S_008F0C_INDEX_STRIDE(0) |
1819 S_008F0C_ADD_TID_ENABLE(false);
1820
1821 desc += 4;
1822 /* VS entry for GS->VS ring */
1823 /* stride 0, num records - size, elsize0,
1824 index stride 0 */
1825 desc[0] = gsvs_va;
1826 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1827 S_008F04_STRIDE(0) |
1828 S_008F04_SWIZZLE_ENABLE(false);
1829 desc[2] = gsvs_ring_size;
1830 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1831 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1832 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1833 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1834 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1835 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1836 S_008F0C_ELEMENT_SIZE(0) |
1837 S_008F0C_INDEX_STRIDE(0) |
1838 S_008F0C_ADD_TID_ENABLE(false);
1839 desc += 4;
1840
1841 /* stride gsvs_itemsize, num records 64
1842 elsize 4, index stride 16 */
1843 /* shader will patch stride and desc[2] */
1844 desc[0] = gsvs_va;
1845 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1846 S_008F04_STRIDE(0) |
1847 S_008F04_SWIZZLE_ENABLE(true);
1848 desc[2] = 0;
1849 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1850 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1851 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1852 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1853 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1854 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1855 S_008F0C_ELEMENT_SIZE(1) |
1856 S_008F0C_INDEX_STRIDE(1) |
1857 S_008F0C_ADD_TID_ENABLE(true);
1858 desc += 4;
1859
1860 desc[0] = tess_va;
1861 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1862 S_008F04_STRIDE(0) |
1863 S_008F04_SWIZZLE_ENABLE(false);
1864 desc[2] = tess_factor_ring_size;
1865 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1866 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1867 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1868 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1869 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1870 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1871 S_008F0C_ELEMENT_SIZE(0) |
1872 S_008F0C_INDEX_STRIDE(0) |
1873 S_008F0C_ADD_TID_ENABLE(false);
1874 desc += 4;
1875
1876 desc[0] = tess_offchip_va;
1877 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1878 S_008F04_STRIDE(0) |
1879 S_008F04_SWIZZLE_ENABLE(false);
1880 desc[2] = tess_offchip_ring_size;
1881 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1882 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1883 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1884 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1885 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1886 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1887 S_008F0C_ELEMENT_SIZE(0) |
1888 S_008F0C_INDEX_STRIDE(0) |
1889 S_008F0C_ADD_TID_ENABLE(false);
1890 desc += 4;
1891
1892 /* add sample positions after all rings */
1893 memcpy(desc, queue->device->sample_locations_1x, 8);
1894 desc += 2;
1895 memcpy(desc, queue->device->sample_locations_2x, 16);
1896 desc += 4;
1897 memcpy(desc, queue->device->sample_locations_4x, 32);
1898 desc += 8;
1899 memcpy(desc, queue->device->sample_locations_8x, 64);
1900 desc += 16;
1901 memcpy(desc, queue->device->sample_locations_16x, 128);
1902 }
1903
1904 static unsigned
1905 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1906 {
1907 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1908 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1909 device->physical_device->rad_info.family != CHIP_STONEY;
1910 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1911 unsigned max_offchip_buffers;
1912 unsigned offchip_granularity;
1913 unsigned hs_offchip_param;
1914
1915 /*
1916 * Per RadeonSI:
1917 * This must be one less than the maximum number due to a hw limitation.
1918 * Various hardware bugs in SI, CIK, and GFX9 need this.
1919 *
1920 * Per AMDVLK:
1921 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1922 * Gfx7 should limit max_offchip_buffers to 508
1923 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1924 *
1925 * Follow AMDVLK here.
1926 */
1927 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1928 device->physical_device->rad_info.chip_class == CIK ||
1929 device->physical_device->rad_info.chip_class == SI)
1930 --max_offchip_buffers_per_se;
1931
1932 max_offchip_buffers = max_offchip_buffers_per_se *
1933 device->physical_device->rad_info.max_se;
1934
1935 switch (device->tess_offchip_block_dw_size) {
1936 default:
1937 assert(0);
1938 /* fall through */
1939 case 8192:
1940 offchip_granularity = V_03093C_X_8K_DWORDS;
1941 break;
1942 case 4096:
1943 offchip_granularity = V_03093C_X_4K_DWORDS;
1944 break;
1945 }
1946
1947 switch (device->physical_device->rad_info.chip_class) {
1948 case SI:
1949 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1950 break;
1951 case CIK:
1952 case VI:
1953 case GFX9:
1954 default:
1955 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1956 break;
1957 }
1958
1959 *max_offchip_buffers_p = max_offchip_buffers;
1960 if (device->physical_device->rad_info.chip_class >= CIK) {
1961 if (device->physical_device->rad_info.chip_class >= VI)
1962 --max_offchip_buffers;
1963 hs_offchip_param =
1964 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1965 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1966 } else {
1967 hs_offchip_param =
1968 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1969 }
1970 return hs_offchip_param;
1971 }
1972
1973 static void
1974 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1975 struct radeon_winsys_bo *esgs_ring_bo,
1976 uint32_t esgs_ring_size,
1977 struct radeon_winsys_bo *gsvs_ring_bo,
1978 uint32_t gsvs_ring_size)
1979 {
1980 if (!esgs_ring_bo && !gsvs_ring_bo)
1981 return;
1982
1983 if (esgs_ring_bo)
1984 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1985
1986 if (gsvs_ring_bo)
1987 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1988
1989 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1990 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1991 radeon_emit(cs, esgs_ring_size >> 8);
1992 radeon_emit(cs, gsvs_ring_size >> 8);
1993 } else {
1994 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1995 radeon_emit(cs, esgs_ring_size >> 8);
1996 radeon_emit(cs, gsvs_ring_size >> 8);
1997 }
1998 }
1999
2000 static void
2001 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2002 unsigned hs_offchip_param, unsigned tf_ring_size,
2003 struct radeon_winsys_bo *tess_rings_bo)
2004 {
2005 uint64_t tf_va;
2006
2007 if (!tess_rings_bo)
2008 return;
2009
2010 tf_va = radv_buffer_get_va(tess_rings_bo);
2011
2012 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2013
2014 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2015 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2016 S_030938_SIZE(tf_ring_size / 4));
2017 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2018 tf_va >> 8);
2019 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2020 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2021 S_030944_BASE_HI(tf_va >> 40));
2022 }
2023 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2024 hs_offchip_param);
2025 } else {
2026 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2027 S_008988_SIZE(tf_ring_size / 4));
2028 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2029 tf_va >> 8);
2030 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2031 hs_offchip_param);
2032 }
2033 }
2034
2035 static void
2036 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2037 struct radeon_winsys_bo *compute_scratch_bo)
2038 {
2039 uint64_t scratch_va;
2040
2041 if (!compute_scratch_bo)
2042 return;
2043
2044 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2045
2046 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2047
2048 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2049 radeon_emit(cs, scratch_va);
2050 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2051 S_008F04_SWIZZLE_ENABLE(1));
2052 }
2053
2054 static void
2055 radv_emit_global_shader_pointers(struct radv_queue *queue,
2056 struct radeon_cmdbuf *cs,
2057 struct radeon_winsys_bo *descriptor_bo)
2058 {
2059 uint64_t va;
2060
2061 if (!descriptor_bo)
2062 return;
2063
2064 va = radv_buffer_get_va(descriptor_bo);
2065
2066 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2067
2068 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2069 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2070 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2071 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2072 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2073
2074 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2075 radv_emit_shader_pointer(queue->device, cs, regs[i],
2076 va, true);
2077 }
2078 } else {
2079 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2080 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2081 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2082 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2083 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2084 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2085
2086 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2087 radv_emit_shader_pointer(queue->device, cs, regs[i],
2088 va, true);
2089 }
2090 }
2091 }
2092
2093 static VkResult
2094 radv_get_preamble_cs(struct radv_queue *queue,
2095 uint32_t scratch_size,
2096 uint32_t compute_scratch_size,
2097 uint32_t esgs_ring_size,
2098 uint32_t gsvs_ring_size,
2099 bool needs_tess_rings,
2100 bool needs_sample_positions,
2101 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2102 struct radeon_cmdbuf **initial_preamble_cs,
2103 struct radeon_cmdbuf **continue_preamble_cs)
2104 {
2105 struct radeon_winsys_bo *scratch_bo = NULL;
2106 struct radeon_winsys_bo *descriptor_bo = NULL;
2107 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2108 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2109 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2110 struct radeon_winsys_bo *tess_rings_bo = NULL;
2111 struct radeon_cmdbuf *dest_cs[3] = {0};
2112 bool add_tess_rings = false, add_sample_positions = false;
2113 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2114 unsigned max_offchip_buffers;
2115 unsigned hs_offchip_param = 0;
2116 unsigned tess_offchip_ring_offset;
2117 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2118 if (!queue->has_tess_rings) {
2119 if (needs_tess_rings)
2120 add_tess_rings = true;
2121 }
2122 if (!queue->has_sample_positions) {
2123 if (needs_sample_positions)
2124 add_sample_positions = true;
2125 }
2126 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2127 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2128 &max_offchip_buffers);
2129 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2130 tess_offchip_ring_size = max_offchip_buffers *
2131 queue->device->tess_offchip_block_dw_size * 4;
2132
2133 if (scratch_size <= queue->scratch_size &&
2134 compute_scratch_size <= queue->compute_scratch_size &&
2135 esgs_ring_size <= queue->esgs_ring_size &&
2136 gsvs_ring_size <= queue->gsvs_ring_size &&
2137 !add_tess_rings && !add_sample_positions &&
2138 queue->initial_preamble_cs) {
2139 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2140 *initial_preamble_cs = queue->initial_preamble_cs;
2141 *continue_preamble_cs = queue->continue_preamble_cs;
2142 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2143 *continue_preamble_cs = NULL;
2144 return VK_SUCCESS;
2145 }
2146
2147 if (scratch_size > queue->scratch_size) {
2148 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2149 scratch_size,
2150 4096,
2151 RADEON_DOMAIN_VRAM,
2152 ring_bo_flags);
2153 if (!scratch_bo)
2154 goto fail;
2155 } else
2156 scratch_bo = queue->scratch_bo;
2157
2158 if (compute_scratch_size > queue->compute_scratch_size) {
2159 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2160 compute_scratch_size,
2161 4096,
2162 RADEON_DOMAIN_VRAM,
2163 ring_bo_flags);
2164 if (!compute_scratch_bo)
2165 goto fail;
2166
2167 } else
2168 compute_scratch_bo = queue->compute_scratch_bo;
2169
2170 if (esgs_ring_size > queue->esgs_ring_size) {
2171 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2172 esgs_ring_size,
2173 4096,
2174 RADEON_DOMAIN_VRAM,
2175 ring_bo_flags);
2176 if (!esgs_ring_bo)
2177 goto fail;
2178 } else {
2179 esgs_ring_bo = queue->esgs_ring_bo;
2180 esgs_ring_size = queue->esgs_ring_size;
2181 }
2182
2183 if (gsvs_ring_size > queue->gsvs_ring_size) {
2184 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2185 gsvs_ring_size,
2186 4096,
2187 RADEON_DOMAIN_VRAM,
2188 ring_bo_flags);
2189 if (!gsvs_ring_bo)
2190 goto fail;
2191 } else {
2192 gsvs_ring_bo = queue->gsvs_ring_bo;
2193 gsvs_ring_size = queue->gsvs_ring_size;
2194 }
2195
2196 if (add_tess_rings) {
2197 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2198 tess_offchip_ring_offset + tess_offchip_ring_size,
2199 256,
2200 RADEON_DOMAIN_VRAM,
2201 ring_bo_flags);
2202 if (!tess_rings_bo)
2203 goto fail;
2204 } else {
2205 tess_rings_bo = queue->tess_rings_bo;
2206 }
2207
2208 if (scratch_bo != queue->scratch_bo ||
2209 esgs_ring_bo != queue->esgs_ring_bo ||
2210 gsvs_ring_bo != queue->gsvs_ring_bo ||
2211 tess_rings_bo != queue->tess_rings_bo ||
2212 add_sample_positions) {
2213 uint32_t size = 0;
2214 if (gsvs_ring_bo || esgs_ring_bo ||
2215 tess_rings_bo || add_sample_positions) {
2216 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2217 if (add_sample_positions)
2218 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2219 }
2220 else if (scratch_bo)
2221 size = 8; /* 2 dword */
2222
2223 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2224 size,
2225 4096,
2226 RADEON_DOMAIN_VRAM,
2227 RADEON_FLAG_CPU_ACCESS |
2228 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2229 RADEON_FLAG_READ_ONLY);
2230 if (!descriptor_bo)
2231 goto fail;
2232 } else
2233 descriptor_bo = queue->descriptor_bo;
2234
2235 for(int i = 0; i < 3; ++i) {
2236 struct radeon_cmdbuf *cs = NULL;
2237 cs = queue->device->ws->cs_create(queue->device->ws,
2238 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2239 if (!cs)
2240 goto fail;
2241
2242 dest_cs[i] = cs;
2243
2244 if (scratch_bo)
2245 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2246
2247 if (descriptor_bo != queue->descriptor_bo) {
2248 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2249
2250 if (scratch_bo) {
2251 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2252 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2253 S_008F04_SWIZZLE_ENABLE(1);
2254 map[0] = scratch_va;
2255 map[1] = rsrc1;
2256 }
2257
2258 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2259 add_sample_positions)
2260 fill_geom_tess_rings(queue, map, add_sample_positions,
2261 esgs_ring_size, esgs_ring_bo,
2262 gsvs_ring_size, gsvs_ring_bo,
2263 tess_factor_ring_size,
2264 tess_offchip_ring_offset,
2265 tess_offchip_ring_size,
2266 tess_rings_bo);
2267
2268 queue->device->ws->buffer_unmap(descriptor_bo);
2269 }
2270
2271 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2272 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2273 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2274 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2275 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2276 }
2277
2278 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2279 gsvs_ring_bo, gsvs_ring_size);
2280 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2281 tess_factor_ring_size, tess_rings_bo);
2282 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2283 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2284
2285 if (i == 0) {
2286 si_cs_emit_cache_flush(cs,
2287 queue->device->physical_device->rad_info.chip_class,
2288 NULL, 0,
2289 queue->queue_family_index == RING_COMPUTE &&
2290 queue->device->physical_device->rad_info.chip_class >= CIK,
2291 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2292 RADV_CMD_FLAG_INV_ICACHE |
2293 RADV_CMD_FLAG_INV_SMEM_L1 |
2294 RADV_CMD_FLAG_INV_VMEM_L1 |
2295 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2296 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2297 } else if (i == 1) {
2298 si_cs_emit_cache_flush(cs,
2299 queue->device->physical_device->rad_info.chip_class,
2300 NULL, 0,
2301 queue->queue_family_index == RING_COMPUTE &&
2302 queue->device->physical_device->rad_info.chip_class >= CIK,
2303 RADV_CMD_FLAG_INV_ICACHE |
2304 RADV_CMD_FLAG_INV_SMEM_L1 |
2305 RADV_CMD_FLAG_INV_VMEM_L1 |
2306 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2307 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2308 }
2309
2310 if (!queue->device->ws->cs_finalize(cs))
2311 goto fail;
2312 }
2313
2314 if (queue->initial_full_flush_preamble_cs)
2315 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2316
2317 if (queue->initial_preamble_cs)
2318 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2319
2320 if (queue->continue_preamble_cs)
2321 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2322
2323 queue->initial_full_flush_preamble_cs = dest_cs[0];
2324 queue->initial_preamble_cs = dest_cs[1];
2325 queue->continue_preamble_cs = dest_cs[2];
2326
2327 if (scratch_bo != queue->scratch_bo) {
2328 if (queue->scratch_bo)
2329 queue->device->ws->buffer_destroy(queue->scratch_bo);
2330 queue->scratch_bo = scratch_bo;
2331 queue->scratch_size = scratch_size;
2332 }
2333
2334 if (compute_scratch_bo != queue->compute_scratch_bo) {
2335 if (queue->compute_scratch_bo)
2336 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2337 queue->compute_scratch_bo = compute_scratch_bo;
2338 queue->compute_scratch_size = compute_scratch_size;
2339 }
2340
2341 if (esgs_ring_bo != queue->esgs_ring_bo) {
2342 if (queue->esgs_ring_bo)
2343 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2344 queue->esgs_ring_bo = esgs_ring_bo;
2345 queue->esgs_ring_size = esgs_ring_size;
2346 }
2347
2348 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2349 if (queue->gsvs_ring_bo)
2350 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2351 queue->gsvs_ring_bo = gsvs_ring_bo;
2352 queue->gsvs_ring_size = gsvs_ring_size;
2353 }
2354
2355 if (tess_rings_bo != queue->tess_rings_bo) {
2356 queue->tess_rings_bo = tess_rings_bo;
2357 queue->has_tess_rings = true;
2358 }
2359
2360 if (descriptor_bo != queue->descriptor_bo) {
2361 if (queue->descriptor_bo)
2362 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2363
2364 queue->descriptor_bo = descriptor_bo;
2365 }
2366
2367 if (add_sample_positions)
2368 queue->has_sample_positions = true;
2369
2370 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2371 *initial_preamble_cs = queue->initial_preamble_cs;
2372 *continue_preamble_cs = queue->continue_preamble_cs;
2373 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2374 *continue_preamble_cs = NULL;
2375 return VK_SUCCESS;
2376 fail:
2377 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2378 if (dest_cs[i])
2379 queue->device->ws->cs_destroy(dest_cs[i]);
2380 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2381 queue->device->ws->buffer_destroy(descriptor_bo);
2382 if (scratch_bo && scratch_bo != queue->scratch_bo)
2383 queue->device->ws->buffer_destroy(scratch_bo);
2384 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2385 queue->device->ws->buffer_destroy(compute_scratch_bo);
2386 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2387 queue->device->ws->buffer_destroy(esgs_ring_bo);
2388 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2389 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2390 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2391 queue->device->ws->buffer_destroy(tess_rings_bo);
2392 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2393 }
2394
2395 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2396 struct radv_winsys_sem_counts *counts,
2397 int num_sems,
2398 const VkSemaphore *sems,
2399 VkFence _fence,
2400 bool reset_temp)
2401 {
2402 int syncobj_idx = 0, sem_idx = 0;
2403
2404 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2405 return VK_SUCCESS;
2406
2407 for (uint32_t i = 0; i < num_sems; i++) {
2408 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2409
2410 if (sem->temp_syncobj || sem->syncobj)
2411 counts->syncobj_count++;
2412 else
2413 counts->sem_count++;
2414 }
2415
2416 if (_fence != VK_NULL_HANDLE) {
2417 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2418 if (fence->temp_syncobj || fence->syncobj)
2419 counts->syncobj_count++;
2420 }
2421
2422 if (counts->syncobj_count) {
2423 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2424 if (!counts->syncobj)
2425 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2426 }
2427
2428 if (counts->sem_count) {
2429 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2430 if (!counts->sem) {
2431 free(counts->syncobj);
2432 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2433 }
2434 }
2435
2436 for (uint32_t i = 0; i < num_sems; i++) {
2437 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2438
2439 if (sem->temp_syncobj) {
2440 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2441 }
2442 else if (sem->syncobj)
2443 counts->syncobj[syncobj_idx++] = sem->syncobj;
2444 else {
2445 assert(sem->sem);
2446 counts->sem[sem_idx++] = sem->sem;
2447 }
2448 }
2449
2450 if (_fence != VK_NULL_HANDLE) {
2451 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2452 if (fence->temp_syncobj)
2453 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2454 else if (fence->syncobj)
2455 counts->syncobj[syncobj_idx++] = fence->syncobj;
2456 }
2457
2458 return VK_SUCCESS;
2459 }
2460
2461 static void
2462 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2463 {
2464 free(sem_info->wait.syncobj);
2465 free(sem_info->wait.sem);
2466 free(sem_info->signal.syncobj);
2467 free(sem_info->signal.sem);
2468 }
2469
2470
2471 static void radv_free_temp_syncobjs(struct radv_device *device,
2472 int num_sems,
2473 const VkSemaphore *sems)
2474 {
2475 for (uint32_t i = 0; i < num_sems; i++) {
2476 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2477
2478 if (sem->temp_syncobj) {
2479 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2480 sem->temp_syncobj = 0;
2481 }
2482 }
2483 }
2484
2485 static VkResult
2486 radv_alloc_sem_info(struct radv_instance *instance,
2487 struct radv_winsys_sem_info *sem_info,
2488 int num_wait_sems,
2489 const VkSemaphore *wait_sems,
2490 int num_signal_sems,
2491 const VkSemaphore *signal_sems,
2492 VkFence fence)
2493 {
2494 VkResult ret;
2495 memset(sem_info, 0, sizeof(*sem_info));
2496
2497 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2498 if (ret)
2499 return ret;
2500 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2501 if (ret)
2502 radv_free_sem_info(sem_info);
2503
2504 /* caller can override these */
2505 sem_info->cs_emit_wait = true;
2506 sem_info->cs_emit_signal = true;
2507 return ret;
2508 }
2509
2510 /* Signals fence as soon as all the work currently put on queue is done. */
2511 static VkResult radv_signal_fence(struct radv_queue *queue,
2512 struct radv_fence *fence)
2513 {
2514 int ret;
2515 VkResult result;
2516 struct radv_winsys_sem_info sem_info;
2517
2518 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2519 radv_fence_to_handle(fence));
2520 if (result != VK_SUCCESS)
2521 return result;
2522
2523 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2524 &queue->device->empty_cs[queue->queue_family_index],
2525 1, NULL, NULL, &sem_info, NULL,
2526 false, fence->fence);
2527 radv_free_sem_info(&sem_info);
2528
2529 if (ret)
2530 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2531
2532 return VK_SUCCESS;
2533 }
2534
2535 VkResult radv_QueueSubmit(
2536 VkQueue _queue,
2537 uint32_t submitCount,
2538 const VkSubmitInfo* pSubmits,
2539 VkFence _fence)
2540 {
2541 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2542 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2543 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2544 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2545 int ret;
2546 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2547 uint32_t scratch_size = 0;
2548 uint32_t compute_scratch_size = 0;
2549 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2550 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2551 VkResult result;
2552 bool fence_emitted = false;
2553 bool tess_rings_needed = false;
2554 bool sample_positions_needed = false;
2555
2556 /* Do this first so failing to allocate scratch buffers can't result in
2557 * partially executed submissions. */
2558 for (uint32_t i = 0; i < submitCount; i++) {
2559 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2560 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2561 pSubmits[i].pCommandBuffers[j]);
2562
2563 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2564 compute_scratch_size = MAX2(compute_scratch_size,
2565 cmd_buffer->compute_scratch_size_needed);
2566 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2567 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2568 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2569 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2570 }
2571 }
2572
2573 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2574 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2575 sample_positions_needed, &initial_flush_preamble_cs,
2576 &initial_preamble_cs, &continue_preamble_cs);
2577 if (result != VK_SUCCESS)
2578 return result;
2579
2580 for (uint32_t i = 0; i < submitCount; i++) {
2581 struct radeon_cmdbuf **cs_array;
2582 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2583 bool can_patch = true;
2584 uint32_t advance;
2585 struct radv_winsys_sem_info sem_info;
2586
2587 result = radv_alloc_sem_info(queue->device->instance,
2588 &sem_info,
2589 pSubmits[i].waitSemaphoreCount,
2590 pSubmits[i].pWaitSemaphores,
2591 pSubmits[i].signalSemaphoreCount,
2592 pSubmits[i].pSignalSemaphores,
2593 _fence);
2594 if (result != VK_SUCCESS)
2595 return result;
2596
2597 if (!pSubmits[i].commandBufferCount) {
2598 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2599 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2600 &queue->device->empty_cs[queue->queue_family_index],
2601 1, NULL, NULL,
2602 &sem_info, NULL,
2603 false, base_fence);
2604 if (ret) {
2605 radv_loge("failed to submit CS %d\n", i);
2606 abort();
2607 }
2608 fence_emitted = true;
2609 }
2610 radv_free_sem_info(&sem_info);
2611 continue;
2612 }
2613
2614 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2615 (pSubmits[i].commandBufferCount));
2616
2617 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2618 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2619 pSubmits[i].pCommandBuffers[j]);
2620 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2621
2622 cs_array[j] = cmd_buffer->cs;
2623 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2624 can_patch = false;
2625
2626 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2627 }
2628
2629 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2630 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2631 const struct radv_winsys_bo_list *bo_list = NULL;
2632
2633 advance = MIN2(max_cs_submission,
2634 pSubmits[i].commandBufferCount - j);
2635
2636 if (queue->device->trace_bo)
2637 *queue->device->trace_id_ptr = 0;
2638
2639 sem_info.cs_emit_wait = j == 0;
2640 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2641
2642 if (unlikely(queue->device->use_global_bo_list)) {
2643 pthread_mutex_lock(&queue->device->bo_list.mutex);
2644 bo_list = &queue->device->bo_list.list;
2645 }
2646
2647 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2648 advance, initial_preamble, continue_preamble_cs,
2649 &sem_info, bo_list,
2650 can_patch, base_fence);
2651
2652 if (unlikely(queue->device->use_global_bo_list))
2653 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2654
2655 if (ret) {
2656 radv_loge("failed to submit CS %d\n", i);
2657 abort();
2658 }
2659 fence_emitted = true;
2660 if (queue->device->trace_bo) {
2661 radv_check_gpu_hangs(queue, cs_array[j]);
2662 }
2663 }
2664
2665 radv_free_temp_syncobjs(queue->device,
2666 pSubmits[i].waitSemaphoreCount,
2667 pSubmits[i].pWaitSemaphores);
2668 radv_free_sem_info(&sem_info);
2669 free(cs_array);
2670 }
2671
2672 if (fence) {
2673 if (!fence_emitted) {
2674 result = radv_signal_fence(queue, fence);
2675 if (result != VK_SUCCESS)
2676 return result;
2677 }
2678 fence->submitted = true;
2679 }
2680
2681 return VK_SUCCESS;
2682 }
2683
2684 VkResult radv_QueueWaitIdle(
2685 VkQueue _queue)
2686 {
2687 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2688
2689 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2690 radv_queue_family_to_ring(queue->queue_family_index),
2691 queue->queue_idx);
2692 return VK_SUCCESS;
2693 }
2694
2695 VkResult radv_DeviceWaitIdle(
2696 VkDevice _device)
2697 {
2698 RADV_FROM_HANDLE(radv_device, device, _device);
2699
2700 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2701 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2702 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2703 }
2704 }
2705 return VK_SUCCESS;
2706 }
2707
2708 VkResult radv_EnumerateInstanceExtensionProperties(
2709 const char* pLayerName,
2710 uint32_t* pPropertyCount,
2711 VkExtensionProperties* pProperties)
2712 {
2713 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2714
2715 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2716 if (radv_supported_instance_extensions.extensions[i]) {
2717 vk_outarray_append(&out, prop) {
2718 *prop = radv_instance_extensions[i];
2719 }
2720 }
2721 }
2722
2723 return vk_outarray_status(&out);
2724 }
2725
2726 VkResult radv_EnumerateDeviceExtensionProperties(
2727 VkPhysicalDevice physicalDevice,
2728 const char* pLayerName,
2729 uint32_t* pPropertyCount,
2730 VkExtensionProperties* pProperties)
2731 {
2732 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2733 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2734
2735 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2736 if (device->supported_extensions.extensions[i]) {
2737 vk_outarray_append(&out, prop) {
2738 *prop = radv_device_extensions[i];
2739 }
2740 }
2741 }
2742
2743 return vk_outarray_status(&out);
2744 }
2745
2746 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2747 VkInstance _instance,
2748 const char* pName)
2749 {
2750 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2751
2752 return radv_lookup_entrypoint_checked(pName,
2753 instance ? instance->apiVersion : 0,
2754 instance ? &instance->enabled_extensions : NULL,
2755 NULL);
2756 }
2757
2758 /* The loader wants us to expose a second GetInstanceProcAddr function
2759 * to work around certain LD_PRELOAD issues seen in apps.
2760 */
2761 PUBLIC
2762 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2763 VkInstance instance,
2764 const char* pName);
2765
2766 PUBLIC
2767 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2768 VkInstance instance,
2769 const char* pName)
2770 {
2771 return radv_GetInstanceProcAddr(instance, pName);
2772 }
2773
2774 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2775 VkDevice _device,
2776 const char* pName)
2777 {
2778 RADV_FROM_HANDLE(radv_device, device, _device);
2779
2780 return radv_lookup_entrypoint_checked(pName,
2781 device->instance->apiVersion,
2782 &device->instance->enabled_extensions,
2783 &device->enabled_extensions);
2784 }
2785
2786 bool radv_get_memory_fd(struct radv_device *device,
2787 struct radv_device_memory *memory,
2788 int *pFD)
2789 {
2790 struct radeon_bo_metadata metadata;
2791
2792 if (memory->image) {
2793 radv_init_metadata(device, memory->image, &metadata);
2794 device->ws->buffer_set_metadata(memory->bo, &metadata);
2795 }
2796
2797 return device->ws->buffer_get_fd(device->ws, memory->bo,
2798 pFD);
2799 }
2800
2801 static VkResult radv_alloc_memory(struct radv_device *device,
2802 const VkMemoryAllocateInfo* pAllocateInfo,
2803 const VkAllocationCallbacks* pAllocator,
2804 VkDeviceMemory* pMem)
2805 {
2806 struct radv_device_memory *mem;
2807 VkResult result;
2808 enum radeon_bo_domain domain;
2809 uint32_t flags = 0;
2810 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2811
2812 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2813
2814 if (pAllocateInfo->allocationSize == 0) {
2815 /* Apparently, this is allowed */
2816 *pMem = VK_NULL_HANDLE;
2817 return VK_SUCCESS;
2818 }
2819
2820 const VkImportMemoryFdInfoKHR *import_info =
2821 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2822 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2823 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2824 const VkExportMemoryAllocateInfoKHR *export_info =
2825 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2826 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2827 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2828
2829 const struct wsi_memory_allocate_info *wsi_info =
2830 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2831
2832 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2833 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2834 if (mem == NULL)
2835 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2836
2837 if (wsi_info && wsi_info->implicit_sync)
2838 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2839
2840 if (dedicate_info) {
2841 mem->image = radv_image_from_handle(dedicate_info->image);
2842 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2843 } else {
2844 mem->image = NULL;
2845 mem->buffer = NULL;
2846 }
2847
2848 mem->user_ptr = NULL;
2849
2850 if (import_info) {
2851 assert(import_info->handleType ==
2852 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2853 import_info->handleType ==
2854 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2855 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2856 NULL, NULL);
2857 if (!mem->bo) {
2858 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2859 goto fail;
2860 } else {
2861 close(import_info->fd);
2862 }
2863 } else if (host_ptr_info) {
2864 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2865 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2866 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2867 pAllocateInfo->allocationSize);
2868 if (!mem->bo) {
2869 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2870 goto fail;
2871 } else {
2872 mem->user_ptr = host_ptr_info->pHostPointer;
2873 }
2874 } else {
2875 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2876 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2877 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2878 domain = RADEON_DOMAIN_GTT;
2879 else
2880 domain = RADEON_DOMAIN_VRAM;
2881
2882 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2883 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2884 else
2885 flags |= RADEON_FLAG_CPU_ACCESS;
2886
2887 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2888 flags |= RADEON_FLAG_GTT_WC;
2889
2890 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2891 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2892
2893 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2894 domain, flags);
2895
2896 if (!mem->bo) {
2897 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2898 goto fail;
2899 }
2900 mem->type_index = mem_type_index;
2901 }
2902
2903 result = radv_bo_list_add(device, mem->bo);
2904 if (result != VK_SUCCESS)
2905 goto fail_bo;
2906
2907 *pMem = radv_device_memory_to_handle(mem);
2908
2909 return VK_SUCCESS;
2910
2911 fail_bo:
2912 device->ws->buffer_destroy(mem->bo);
2913 fail:
2914 vk_free2(&device->alloc, pAllocator, mem);
2915
2916 return result;
2917 }
2918
2919 VkResult radv_AllocateMemory(
2920 VkDevice _device,
2921 const VkMemoryAllocateInfo* pAllocateInfo,
2922 const VkAllocationCallbacks* pAllocator,
2923 VkDeviceMemory* pMem)
2924 {
2925 RADV_FROM_HANDLE(radv_device, device, _device);
2926 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2927 }
2928
2929 void radv_FreeMemory(
2930 VkDevice _device,
2931 VkDeviceMemory _mem,
2932 const VkAllocationCallbacks* pAllocator)
2933 {
2934 RADV_FROM_HANDLE(radv_device, device, _device);
2935 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2936
2937 if (mem == NULL)
2938 return;
2939
2940 radv_bo_list_remove(device, mem->bo);
2941 device->ws->buffer_destroy(mem->bo);
2942 mem->bo = NULL;
2943
2944 vk_free2(&device->alloc, pAllocator, mem);
2945 }
2946
2947 VkResult radv_MapMemory(
2948 VkDevice _device,
2949 VkDeviceMemory _memory,
2950 VkDeviceSize offset,
2951 VkDeviceSize size,
2952 VkMemoryMapFlags flags,
2953 void** ppData)
2954 {
2955 RADV_FROM_HANDLE(radv_device, device, _device);
2956 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2957
2958 if (mem == NULL) {
2959 *ppData = NULL;
2960 return VK_SUCCESS;
2961 }
2962
2963 if (mem->user_ptr)
2964 *ppData = mem->user_ptr;
2965 else
2966 *ppData = device->ws->buffer_map(mem->bo);
2967
2968 if (*ppData) {
2969 *ppData += offset;
2970 return VK_SUCCESS;
2971 }
2972
2973 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2974 }
2975
2976 void radv_UnmapMemory(
2977 VkDevice _device,
2978 VkDeviceMemory _memory)
2979 {
2980 RADV_FROM_HANDLE(radv_device, device, _device);
2981 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2982
2983 if (mem == NULL)
2984 return;
2985
2986 if (mem->user_ptr == NULL)
2987 device->ws->buffer_unmap(mem->bo);
2988 }
2989
2990 VkResult radv_FlushMappedMemoryRanges(
2991 VkDevice _device,
2992 uint32_t memoryRangeCount,
2993 const VkMappedMemoryRange* pMemoryRanges)
2994 {
2995 return VK_SUCCESS;
2996 }
2997
2998 VkResult radv_InvalidateMappedMemoryRanges(
2999 VkDevice _device,
3000 uint32_t memoryRangeCount,
3001 const VkMappedMemoryRange* pMemoryRanges)
3002 {
3003 return VK_SUCCESS;
3004 }
3005
3006 void radv_GetBufferMemoryRequirements(
3007 VkDevice _device,
3008 VkBuffer _buffer,
3009 VkMemoryRequirements* pMemoryRequirements)
3010 {
3011 RADV_FROM_HANDLE(radv_device, device, _device);
3012 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3013
3014 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3015
3016 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3017 pMemoryRequirements->alignment = 4096;
3018 else
3019 pMemoryRequirements->alignment = 16;
3020
3021 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3022 }
3023
3024 void radv_GetBufferMemoryRequirements2(
3025 VkDevice device,
3026 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3027 VkMemoryRequirements2KHR* pMemoryRequirements)
3028 {
3029 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3030 &pMemoryRequirements->memoryRequirements);
3031 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3032 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3033 switch (ext->sType) {
3034 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3035 VkMemoryDedicatedRequirementsKHR *req =
3036 (VkMemoryDedicatedRequirementsKHR *) ext;
3037 req->requiresDedicatedAllocation = buffer->shareable;
3038 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3039 break;
3040 }
3041 default:
3042 break;
3043 }
3044 }
3045 }
3046
3047 void radv_GetImageMemoryRequirements(
3048 VkDevice _device,
3049 VkImage _image,
3050 VkMemoryRequirements* pMemoryRequirements)
3051 {
3052 RADV_FROM_HANDLE(radv_device, device, _device);
3053 RADV_FROM_HANDLE(radv_image, image, _image);
3054
3055 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3056
3057 pMemoryRequirements->size = image->size;
3058 pMemoryRequirements->alignment = image->alignment;
3059 }
3060
3061 void radv_GetImageMemoryRequirements2(
3062 VkDevice device,
3063 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3064 VkMemoryRequirements2KHR* pMemoryRequirements)
3065 {
3066 radv_GetImageMemoryRequirements(device, pInfo->image,
3067 &pMemoryRequirements->memoryRequirements);
3068
3069 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3070
3071 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3072 switch (ext->sType) {
3073 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3074 VkMemoryDedicatedRequirementsKHR *req =
3075 (VkMemoryDedicatedRequirementsKHR *) ext;
3076 req->requiresDedicatedAllocation = image->shareable;
3077 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3078 break;
3079 }
3080 default:
3081 break;
3082 }
3083 }
3084 }
3085
3086 void radv_GetImageSparseMemoryRequirements(
3087 VkDevice device,
3088 VkImage image,
3089 uint32_t* pSparseMemoryRequirementCount,
3090 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3091 {
3092 stub();
3093 }
3094
3095 void radv_GetImageSparseMemoryRequirements2(
3096 VkDevice device,
3097 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3098 uint32_t* pSparseMemoryRequirementCount,
3099 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3100 {
3101 stub();
3102 }
3103
3104 void radv_GetDeviceMemoryCommitment(
3105 VkDevice device,
3106 VkDeviceMemory memory,
3107 VkDeviceSize* pCommittedMemoryInBytes)
3108 {
3109 *pCommittedMemoryInBytes = 0;
3110 }
3111
3112 VkResult radv_BindBufferMemory2(VkDevice device,
3113 uint32_t bindInfoCount,
3114 const VkBindBufferMemoryInfoKHR *pBindInfos)
3115 {
3116 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3117 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3118 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3119
3120 if (mem) {
3121 buffer->bo = mem->bo;
3122 buffer->offset = pBindInfos[i].memoryOffset;
3123 } else {
3124 buffer->bo = NULL;
3125 }
3126 }
3127 return VK_SUCCESS;
3128 }
3129
3130 VkResult radv_BindBufferMemory(
3131 VkDevice device,
3132 VkBuffer buffer,
3133 VkDeviceMemory memory,
3134 VkDeviceSize memoryOffset)
3135 {
3136 const VkBindBufferMemoryInfoKHR info = {
3137 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3138 .buffer = buffer,
3139 .memory = memory,
3140 .memoryOffset = memoryOffset
3141 };
3142
3143 return radv_BindBufferMemory2(device, 1, &info);
3144 }
3145
3146 VkResult radv_BindImageMemory2(VkDevice device,
3147 uint32_t bindInfoCount,
3148 const VkBindImageMemoryInfoKHR *pBindInfos)
3149 {
3150 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3151 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3152 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3153
3154 if (mem) {
3155 image->bo = mem->bo;
3156 image->offset = pBindInfos[i].memoryOffset;
3157 } else {
3158 image->bo = NULL;
3159 image->offset = 0;
3160 }
3161 }
3162 return VK_SUCCESS;
3163 }
3164
3165
3166 VkResult radv_BindImageMemory(
3167 VkDevice device,
3168 VkImage image,
3169 VkDeviceMemory memory,
3170 VkDeviceSize memoryOffset)
3171 {
3172 const VkBindImageMemoryInfoKHR info = {
3173 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3174 .image = image,
3175 .memory = memory,
3176 .memoryOffset = memoryOffset
3177 };
3178
3179 return radv_BindImageMemory2(device, 1, &info);
3180 }
3181
3182
3183 static void
3184 radv_sparse_buffer_bind_memory(struct radv_device *device,
3185 const VkSparseBufferMemoryBindInfo *bind)
3186 {
3187 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3188
3189 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3190 struct radv_device_memory *mem = NULL;
3191
3192 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3193 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3194
3195 device->ws->buffer_virtual_bind(buffer->bo,
3196 bind->pBinds[i].resourceOffset,
3197 bind->pBinds[i].size,
3198 mem ? mem->bo : NULL,
3199 bind->pBinds[i].memoryOffset);
3200 }
3201 }
3202
3203 static void
3204 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3205 const VkSparseImageOpaqueMemoryBindInfo *bind)
3206 {
3207 RADV_FROM_HANDLE(radv_image, image, bind->image);
3208
3209 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3210 struct radv_device_memory *mem = NULL;
3211
3212 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3213 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3214
3215 device->ws->buffer_virtual_bind(image->bo,
3216 bind->pBinds[i].resourceOffset,
3217 bind->pBinds[i].size,
3218 mem ? mem->bo : NULL,
3219 bind->pBinds[i].memoryOffset);
3220 }
3221 }
3222
3223 VkResult radv_QueueBindSparse(
3224 VkQueue _queue,
3225 uint32_t bindInfoCount,
3226 const VkBindSparseInfo* pBindInfo,
3227 VkFence _fence)
3228 {
3229 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3230 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3231 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3232 bool fence_emitted = false;
3233 VkResult result;
3234 int ret;
3235
3236 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3237 struct radv_winsys_sem_info sem_info;
3238 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3239 radv_sparse_buffer_bind_memory(queue->device,
3240 pBindInfo[i].pBufferBinds + j);
3241 }
3242
3243 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3244 radv_sparse_image_opaque_bind_memory(queue->device,
3245 pBindInfo[i].pImageOpaqueBinds + j);
3246 }
3247
3248 VkResult result;
3249 result = radv_alloc_sem_info(queue->device->instance,
3250 &sem_info,
3251 pBindInfo[i].waitSemaphoreCount,
3252 pBindInfo[i].pWaitSemaphores,
3253 pBindInfo[i].signalSemaphoreCount,
3254 pBindInfo[i].pSignalSemaphores,
3255 _fence);
3256 if (result != VK_SUCCESS)
3257 return result;
3258
3259 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3260 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3261 &queue->device->empty_cs[queue->queue_family_index],
3262 1, NULL, NULL,
3263 &sem_info, NULL,
3264 false, base_fence);
3265 if (ret) {
3266 radv_loge("failed to submit CS %d\n", i);
3267 abort();
3268 }
3269
3270 fence_emitted = true;
3271 if (fence)
3272 fence->submitted = true;
3273 }
3274
3275 radv_free_sem_info(&sem_info);
3276
3277 }
3278
3279 if (fence) {
3280 if (!fence_emitted) {
3281 result = radv_signal_fence(queue, fence);
3282 if (result != VK_SUCCESS)
3283 return result;
3284 }
3285 fence->submitted = true;
3286 }
3287
3288 return VK_SUCCESS;
3289 }
3290
3291 VkResult radv_CreateFence(
3292 VkDevice _device,
3293 const VkFenceCreateInfo* pCreateInfo,
3294 const VkAllocationCallbacks* pAllocator,
3295 VkFence* pFence)
3296 {
3297 RADV_FROM_HANDLE(radv_device, device, _device);
3298 const VkExportFenceCreateInfoKHR *export =
3299 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3300 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3301 export ? export->handleTypes : 0;
3302
3303 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3304 sizeof(*fence), 8,
3305 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3306
3307 if (!fence)
3308 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3309
3310 fence->fence_wsi = NULL;
3311 fence->submitted = false;
3312 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3313 fence->temp_syncobj = 0;
3314 if (device->always_use_syncobj || handleTypes) {
3315 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3316 if (ret) {
3317 vk_free2(&device->alloc, pAllocator, fence);
3318 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3319 }
3320 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3321 device->ws->signal_syncobj(device->ws, fence->syncobj);
3322 }
3323 fence->fence = NULL;
3324 } else {
3325 fence->fence = device->ws->create_fence();
3326 if (!fence->fence) {
3327 vk_free2(&device->alloc, pAllocator, fence);
3328 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3329 }
3330 fence->syncobj = 0;
3331 }
3332
3333 *pFence = radv_fence_to_handle(fence);
3334
3335 return VK_SUCCESS;
3336 }
3337
3338 void radv_DestroyFence(
3339 VkDevice _device,
3340 VkFence _fence,
3341 const VkAllocationCallbacks* pAllocator)
3342 {
3343 RADV_FROM_HANDLE(radv_device, device, _device);
3344 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3345
3346 if (!fence)
3347 return;
3348
3349 if (fence->temp_syncobj)
3350 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3351 if (fence->syncobj)
3352 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3353 if (fence->fence)
3354 device->ws->destroy_fence(fence->fence);
3355 if (fence->fence_wsi)
3356 fence->fence_wsi->destroy(fence->fence_wsi);
3357 vk_free2(&device->alloc, pAllocator, fence);
3358 }
3359
3360
3361 static uint64_t radv_get_current_time()
3362 {
3363 struct timespec tv;
3364 clock_gettime(CLOCK_MONOTONIC, &tv);
3365 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3366 }
3367
3368 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3369 {
3370 uint64_t current_time = radv_get_current_time();
3371
3372 timeout = MIN2(UINT64_MAX - current_time, timeout);
3373
3374 return current_time + timeout;
3375 }
3376
3377
3378 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3379 {
3380 for (uint32_t i = 0; i < fenceCount; ++i) {
3381 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3382 if (fence->fence == NULL || fence->syncobj ||
3383 fence->temp_syncobj ||
3384 (!fence->signalled && !fence->submitted))
3385 return false;
3386 }
3387 return true;
3388 }
3389
3390 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3391 {
3392 for (uint32_t i = 0; i < fenceCount; ++i) {
3393 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3394 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3395 return false;
3396 }
3397 return true;
3398 }
3399
3400 VkResult radv_WaitForFences(
3401 VkDevice _device,
3402 uint32_t fenceCount,
3403 const VkFence* pFences,
3404 VkBool32 waitAll,
3405 uint64_t timeout)
3406 {
3407 RADV_FROM_HANDLE(radv_device, device, _device);
3408 timeout = radv_get_absolute_timeout(timeout);
3409
3410 if (device->always_use_syncobj &&
3411 radv_all_fences_syncobj(fenceCount, pFences))
3412 {
3413 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3414 if (!handles)
3415 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3416
3417 for (uint32_t i = 0; i < fenceCount; ++i) {
3418 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3419 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3420 }
3421
3422 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3423
3424 free(handles);
3425 return success ? VK_SUCCESS : VK_TIMEOUT;
3426 }
3427
3428 if (!waitAll && fenceCount > 1) {
3429 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3430 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3431 uint32_t wait_count = 0;
3432 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3433 if (!fences)
3434 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3435
3436 for (uint32_t i = 0; i < fenceCount; ++i) {
3437 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3438
3439 if (fence->signalled) {
3440 free(fences);
3441 return VK_SUCCESS;
3442 }
3443
3444 fences[wait_count++] = fence->fence;
3445 }
3446
3447 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3448 waitAll, timeout - radv_get_current_time());
3449
3450 free(fences);
3451 return success ? VK_SUCCESS : VK_TIMEOUT;
3452 }
3453
3454 while(radv_get_current_time() <= timeout) {
3455 for (uint32_t i = 0; i < fenceCount; ++i) {
3456 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3457 return VK_SUCCESS;
3458 }
3459 }
3460 return VK_TIMEOUT;
3461 }
3462
3463 for (uint32_t i = 0; i < fenceCount; ++i) {
3464 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3465 bool expired = false;
3466
3467 if (fence->temp_syncobj) {
3468 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3469 return VK_TIMEOUT;
3470 continue;
3471 }
3472
3473 if (fence->syncobj) {
3474 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3475 return VK_TIMEOUT;
3476 continue;
3477 }
3478
3479 if (fence->signalled)
3480 continue;
3481
3482 if (fence->fence) {
3483 if (!fence->submitted) {
3484 while(radv_get_current_time() <= timeout &&
3485 !fence->submitted)
3486 /* Do nothing */;
3487
3488 if (!fence->submitted)
3489 return VK_TIMEOUT;
3490
3491 /* Recheck as it may have been set by
3492 * submitting operations. */
3493
3494 if (fence->signalled)
3495 continue;
3496 }
3497
3498 expired = device->ws->fence_wait(device->ws,
3499 fence->fence,
3500 true, timeout);
3501 if (!expired)
3502 return VK_TIMEOUT;
3503 }
3504
3505 if (fence->fence_wsi) {
3506 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3507 if (result != VK_SUCCESS)
3508 return result;
3509 }
3510
3511 fence->signalled = true;
3512 }
3513
3514 return VK_SUCCESS;
3515 }
3516
3517 VkResult radv_ResetFences(VkDevice _device,
3518 uint32_t fenceCount,
3519 const VkFence *pFences)
3520 {
3521 RADV_FROM_HANDLE(radv_device, device, _device);
3522
3523 for (unsigned i = 0; i < fenceCount; ++i) {
3524 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3525 fence->submitted = fence->signalled = false;
3526
3527 /* Per spec, we first restore the permanent payload, and then reset, so
3528 * having a temp syncobj should not skip resetting the permanent syncobj. */
3529 if (fence->temp_syncobj) {
3530 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3531 fence->temp_syncobj = 0;
3532 }
3533
3534 if (fence->syncobj) {
3535 device->ws->reset_syncobj(device->ws, fence->syncobj);
3536 }
3537 }
3538
3539 return VK_SUCCESS;
3540 }
3541
3542 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3543 {
3544 RADV_FROM_HANDLE(radv_device, device, _device);
3545 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3546
3547 if (fence->temp_syncobj) {
3548 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3549 return success ? VK_SUCCESS : VK_NOT_READY;
3550 }
3551
3552 if (fence->syncobj) {
3553 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3554 return success ? VK_SUCCESS : VK_NOT_READY;
3555 }
3556
3557 if (fence->signalled)
3558 return VK_SUCCESS;
3559 if (!fence->submitted)
3560 return VK_NOT_READY;
3561 if (fence->fence) {
3562 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3563 return VK_NOT_READY;
3564 }
3565 if (fence->fence_wsi) {
3566 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3567
3568 if (result != VK_SUCCESS) {
3569 if (result == VK_TIMEOUT)
3570 return VK_NOT_READY;
3571 return result;
3572 }
3573 }
3574 return VK_SUCCESS;
3575 }
3576
3577
3578 // Queue semaphore functions
3579
3580 VkResult radv_CreateSemaphore(
3581 VkDevice _device,
3582 const VkSemaphoreCreateInfo* pCreateInfo,
3583 const VkAllocationCallbacks* pAllocator,
3584 VkSemaphore* pSemaphore)
3585 {
3586 RADV_FROM_HANDLE(radv_device, device, _device);
3587 const VkExportSemaphoreCreateInfoKHR *export =
3588 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3589 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3590 export ? export->handleTypes : 0;
3591
3592 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3593 sizeof(*sem), 8,
3594 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3595 if (!sem)
3596 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3597
3598 sem->temp_syncobj = 0;
3599 /* create a syncobject if we are going to export this semaphore */
3600 if (device->always_use_syncobj || handleTypes) {
3601 assert (device->physical_device->rad_info.has_syncobj);
3602 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3603 if (ret) {
3604 vk_free2(&device->alloc, pAllocator, sem);
3605 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3606 }
3607 sem->sem = NULL;
3608 } else {
3609 sem->sem = device->ws->create_sem(device->ws);
3610 if (!sem->sem) {
3611 vk_free2(&device->alloc, pAllocator, sem);
3612 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3613 }
3614 sem->syncobj = 0;
3615 }
3616
3617 *pSemaphore = radv_semaphore_to_handle(sem);
3618 return VK_SUCCESS;
3619 }
3620
3621 void radv_DestroySemaphore(
3622 VkDevice _device,
3623 VkSemaphore _semaphore,
3624 const VkAllocationCallbacks* pAllocator)
3625 {
3626 RADV_FROM_HANDLE(radv_device, device, _device);
3627 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3628 if (!_semaphore)
3629 return;
3630
3631 if (sem->syncobj)
3632 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3633 else
3634 device->ws->destroy_sem(sem->sem);
3635 vk_free2(&device->alloc, pAllocator, sem);
3636 }
3637
3638 VkResult radv_CreateEvent(
3639 VkDevice _device,
3640 const VkEventCreateInfo* pCreateInfo,
3641 const VkAllocationCallbacks* pAllocator,
3642 VkEvent* pEvent)
3643 {
3644 RADV_FROM_HANDLE(radv_device, device, _device);
3645 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3646 sizeof(*event), 8,
3647 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3648
3649 if (!event)
3650 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3651
3652 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3653 RADEON_DOMAIN_GTT,
3654 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3655 if (!event->bo) {
3656 vk_free2(&device->alloc, pAllocator, event);
3657 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3658 }
3659
3660 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3661
3662 *pEvent = radv_event_to_handle(event);
3663
3664 return VK_SUCCESS;
3665 }
3666
3667 void radv_DestroyEvent(
3668 VkDevice _device,
3669 VkEvent _event,
3670 const VkAllocationCallbacks* pAllocator)
3671 {
3672 RADV_FROM_HANDLE(radv_device, device, _device);
3673 RADV_FROM_HANDLE(radv_event, event, _event);
3674
3675 if (!event)
3676 return;
3677 device->ws->buffer_destroy(event->bo);
3678 vk_free2(&device->alloc, pAllocator, event);
3679 }
3680
3681 VkResult radv_GetEventStatus(
3682 VkDevice _device,
3683 VkEvent _event)
3684 {
3685 RADV_FROM_HANDLE(radv_event, event, _event);
3686
3687 if (*event->map == 1)
3688 return VK_EVENT_SET;
3689 return VK_EVENT_RESET;
3690 }
3691
3692 VkResult radv_SetEvent(
3693 VkDevice _device,
3694 VkEvent _event)
3695 {
3696 RADV_FROM_HANDLE(radv_event, event, _event);
3697 *event->map = 1;
3698
3699 return VK_SUCCESS;
3700 }
3701
3702 VkResult radv_ResetEvent(
3703 VkDevice _device,
3704 VkEvent _event)
3705 {
3706 RADV_FROM_HANDLE(radv_event, event, _event);
3707 *event->map = 0;
3708
3709 return VK_SUCCESS;
3710 }
3711
3712 VkResult radv_CreateBuffer(
3713 VkDevice _device,
3714 const VkBufferCreateInfo* pCreateInfo,
3715 const VkAllocationCallbacks* pAllocator,
3716 VkBuffer* pBuffer)
3717 {
3718 RADV_FROM_HANDLE(radv_device, device, _device);
3719 struct radv_buffer *buffer;
3720
3721 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3722
3723 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3724 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3725 if (buffer == NULL)
3726 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3727
3728 buffer->size = pCreateInfo->size;
3729 buffer->usage = pCreateInfo->usage;
3730 buffer->bo = NULL;
3731 buffer->offset = 0;
3732 buffer->flags = pCreateInfo->flags;
3733
3734 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3735 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3736
3737 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3738 buffer->bo = device->ws->buffer_create(device->ws,
3739 align64(buffer->size, 4096),
3740 4096, 0, RADEON_FLAG_VIRTUAL);
3741 if (!buffer->bo) {
3742 vk_free2(&device->alloc, pAllocator, buffer);
3743 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3744 }
3745 }
3746
3747 *pBuffer = radv_buffer_to_handle(buffer);
3748
3749 return VK_SUCCESS;
3750 }
3751
3752 void radv_DestroyBuffer(
3753 VkDevice _device,
3754 VkBuffer _buffer,
3755 const VkAllocationCallbacks* pAllocator)
3756 {
3757 RADV_FROM_HANDLE(radv_device, device, _device);
3758 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3759
3760 if (!buffer)
3761 return;
3762
3763 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3764 device->ws->buffer_destroy(buffer->bo);
3765
3766 vk_free2(&device->alloc, pAllocator, buffer);
3767 }
3768
3769 static inline unsigned
3770 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3771 {
3772 if (stencil)
3773 return image->surface.u.legacy.stencil_tiling_index[level];
3774 else
3775 return image->surface.u.legacy.tiling_index[level];
3776 }
3777
3778 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3779 {
3780 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3781 }
3782
3783 static uint32_t
3784 radv_init_dcc_control_reg(struct radv_device *device,
3785 struct radv_image_view *iview)
3786 {
3787 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3788 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3789 unsigned max_compressed_block_size;
3790 unsigned independent_64b_blocks;
3791
3792 if (device->physical_device->rad_info.chip_class < VI)
3793 return 0;
3794
3795 if (iview->image->info.samples > 1) {
3796 if (iview->image->surface.bpe == 1)
3797 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3798 else if (iview->image->surface.bpe == 2)
3799 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3800 }
3801
3802 if (!device->physical_device->rad_info.has_dedicated_vram) {
3803 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3804 * dGPU and 64 for APU because all of our APUs to date use
3805 * DIMMs which have a request granularity size of 64B while all
3806 * other chips have a 32B request size.
3807 */
3808 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3809 }
3810
3811 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3812 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3813 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3814 /* If this DCC image is potentially going to be used in texture
3815 * fetches, we need some special settings.
3816 */
3817 independent_64b_blocks = 1;
3818 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3819 } else {
3820 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3821 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3822 * big as possible for better compression state.
3823 */
3824 independent_64b_blocks = 0;
3825 max_compressed_block_size = max_uncompressed_block_size;
3826 }
3827
3828 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3829 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3830 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3831 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3832 }
3833
3834 static void
3835 radv_initialise_color_surface(struct radv_device *device,
3836 struct radv_color_buffer_info *cb,
3837 struct radv_image_view *iview)
3838 {
3839 const struct vk_format_description *desc;
3840 unsigned ntype, format, swap, endian;
3841 unsigned blend_clamp = 0, blend_bypass = 0;
3842 uint64_t va;
3843 const struct radeon_surf *surf = &iview->image->surface;
3844
3845 desc = vk_format_description(iview->vk_format);
3846
3847 memset(cb, 0, sizeof(*cb));
3848
3849 /* Intensity is implemented as Red, so treat it that way. */
3850 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3851
3852 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3853
3854 cb->cb_color_base = va >> 8;
3855
3856 if (device->physical_device->rad_info.chip_class >= GFX9) {
3857 struct gfx9_surf_meta_flags meta;
3858 if (iview->image->dcc_offset)
3859 meta = iview->image->surface.u.gfx9.dcc;
3860 else
3861 meta = iview->image->surface.u.gfx9.cmask;
3862
3863 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3864 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3865 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3866 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3867
3868 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3869 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3870 } else {
3871 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3872 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3873
3874 cb->cb_color_base += level_info->offset >> 8;
3875 if (level_info->mode == RADEON_SURF_MODE_2D)
3876 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3877
3878 pitch_tile_max = level_info->nblk_x / 8 - 1;
3879 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3880 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3881
3882 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3883 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3884 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3885
3886 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3887
3888 if (radv_image_has_fmask(iview->image)) {
3889 if (device->physical_device->rad_info.chip_class >= CIK)
3890 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3891 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3892 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3893 } else {
3894 /* This must be set for fast clear to work without FMASK. */
3895 if (device->physical_device->rad_info.chip_class >= CIK)
3896 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3897 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3898 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3899 }
3900 }
3901
3902 /* CMASK variables */
3903 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3904 va += iview->image->cmask.offset;
3905 cb->cb_color_cmask = va >> 8;
3906
3907 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3908 va += iview->image->dcc_offset;
3909 cb->cb_dcc_base = va >> 8;
3910 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3911
3912 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3913 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3914 S_028C6C_SLICE_MAX(max_slice);
3915
3916 if (iview->image->info.samples > 1) {
3917 unsigned log_samples = util_logbase2(iview->image->info.samples);
3918
3919 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3920 S_028C74_NUM_FRAGMENTS(log_samples);
3921 }
3922
3923 if (radv_image_has_fmask(iview->image)) {
3924 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3925 cb->cb_color_fmask = va >> 8;
3926 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3927 } else {
3928 cb->cb_color_fmask = cb->cb_color_base;
3929 }
3930
3931 ntype = radv_translate_color_numformat(iview->vk_format,
3932 desc,
3933 vk_format_get_first_non_void_channel(iview->vk_format));
3934 format = radv_translate_colorformat(iview->vk_format);
3935 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3936 radv_finishme("Illegal color\n");
3937 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3938 endian = radv_colorformat_endian_swap(format);
3939
3940 /* blend clamp should be set for all NORM/SRGB types */
3941 if (ntype == V_028C70_NUMBER_UNORM ||
3942 ntype == V_028C70_NUMBER_SNORM ||
3943 ntype == V_028C70_NUMBER_SRGB)
3944 blend_clamp = 1;
3945
3946 /* set blend bypass according to docs if SINT/UINT or
3947 8/24 COLOR variants */
3948 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3949 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3950 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3951 blend_clamp = 0;
3952 blend_bypass = 1;
3953 }
3954 #if 0
3955 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3956 (format == V_028C70_COLOR_8 ||
3957 format == V_028C70_COLOR_8_8 ||
3958 format == V_028C70_COLOR_8_8_8_8))
3959 ->color_is_int8 = true;
3960 #endif
3961 cb->cb_color_info = S_028C70_FORMAT(format) |
3962 S_028C70_COMP_SWAP(swap) |
3963 S_028C70_BLEND_CLAMP(blend_clamp) |
3964 S_028C70_BLEND_BYPASS(blend_bypass) |
3965 S_028C70_SIMPLE_FLOAT(1) |
3966 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3967 ntype != V_028C70_NUMBER_SNORM &&
3968 ntype != V_028C70_NUMBER_SRGB &&
3969 format != V_028C70_COLOR_8_24 &&
3970 format != V_028C70_COLOR_24_8) |
3971 S_028C70_NUMBER_TYPE(ntype) |
3972 S_028C70_ENDIAN(endian);
3973 if (radv_image_has_fmask(iview->image)) {
3974 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3975 if (device->physical_device->rad_info.chip_class == SI) {
3976 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3977 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3978 }
3979 }
3980
3981 if (radv_image_has_cmask(iview->image) &&
3982 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3983 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3984
3985 if (radv_dcc_enabled(iview->image, iview->base_mip))
3986 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3987
3988 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3989
3990 /* This must be set for fast clear to work without FMASK. */
3991 if (!radv_image_has_fmask(iview->image) &&
3992 device->physical_device->rad_info.chip_class == SI) {
3993 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3994 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3995 }
3996
3997 if (device->physical_device->rad_info.chip_class >= GFX9) {
3998 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3999 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4000
4001 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4002 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4003 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4004 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4005 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4006 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4007 }
4008 }
4009
4010 static unsigned
4011 radv_calc_decompress_on_z_planes(struct radv_device *device,
4012 struct radv_image_view *iview)
4013 {
4014 unsigned max_zplanes = 0;
4015
4016 assert(radv_image_is_tc_compat_htile(iview->image));
4017
4018 if (device->physical_device->rad_info.chip_class >= GFX9) {
4019 /* Default value for 32-bit depth surfaces. */
4020 max_zplanes = 4;
4021
4022 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4023 iview->image->info.samples > 1)
4024 max_zplanes = 2;
4025
4026 max_zplanes = max_zplanes + 1;
4027 } else {
4028 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4029 /* Do not enable Z plane compression for 16-bit depth
4030 * surfaces because isn't supported on GFX8. Only
4031 * 32-bit depth surfaces are supported by the hardware.
4032 * This allows to maintain shader compatibility and to
4033 * reduce the number of depth decompressions.
4034 */
4035 max_zplanes = 1;
4036 } else {
4037 if (iview->image->info.samples <= 1)
4038 max_zplanes = 5;
4039 else if (iview->image->info.samples <= 4)
4040 max_zplanes = 3;
4041 else
4042 max_zplanes = 2;
4043 }
4044 }
4045
4046 return max_zplanes;
4047 }
4048
4049 static void
4050 radv_initialise_ds_surface(struct radv_device *device,
4051 struct radv_ds_buffer_info *ds,
4052 struct radv_image_view *iview)
4053 {
4054 unsigned level = iview->base_mip;
4055 unsigned format, stencil_format;
4056 uint64_t va, s_offs, z_offs;
4057 bool stencil_only = false;
4058 memset(ds, 0, sizeof(*ds));
4059 switch (iview->image->vk_format) {
4060 case VK_FORMAT_D24_UNORM_S8_UINT:
4061 case VK_FORMAT_X8_D24_UNORM_PACK32:
4062 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4063 ds->offset_scale = 2.0f;
4064 break;
4065 case VK_FORMAT_D16_UNORM:
4066 case VK_FORMAT_D16_UNORM_S8_UINT:
4067 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4068 ds->offset_scale = 4.0f;
4069 break;
4070 case VK_FORMAT_D32_SFLOAT:
4071 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4072 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4073 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4074 ds->offset_scale = 1.0f;
4075 break;
4076 case VK_FORMAT_S8_UINT:
4077 stencil_only = true;
4078 break;
4079 default:
4080 break;
4081 }
4082
4083 format = radv_translate_dbformat(iview->image->vk_format);
4084 stencil_format = iview->image->surface.has_stencil ?
4085 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4086
4087 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4088 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4089 S_028008_SLICE_MAX(max_slice);
4090
4091 ds->db_htile_data_base = 0;
4092 ds->db_htile_surface = 0;
4093
4094 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4095 s_offs = z_offs = va;
4096
4097 if (device->physical_device->rad_info.chip_class >= GFX9) {
4098 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4099 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4100
4101 ds->db_z_info = S_028038_FORMAT(format) |
4102 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4103 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4104 S_028038_MAXMIP(iview->image->info.levels - 1) |
4105 S_028038_ZRANGE_PRECISION(1);
4106 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4107 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4108
4109 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4110 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4111 ds->db_depth_view |= S_028008_MIPID(level);
4112
4113 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4114 S_02801C_Y_MAX(iview->image->info.height - 1);
4115
4116 if (radv_htile_enabled(iview->image, level)) {
4117 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4118
4119 if (radv_image_is_tc_compat_htile(iview->image)) {
4120 unsigned max_zplanes =
4121 radv_calc_decompress_on_z_planes(device, iview);
4122
4123 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4124 S_028038_ITERATE_FLUSH(1);
4125 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4126 }
4127
4128 if (!iview->image->surface.has_stencil)
4129 /* Use all of the htile_buffer for depth if there's no stencil. */
4130 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4131 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4132 iview->image->htile_offset;
4133 ds->db_htile_data_base = va >> 8;
4134 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4135 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4136 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4137 }
4138 } else {
4139 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4140
4141 if (stencil_only)
4142 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4143
4144 z_offs += iview->image->surface.u.legacy.level[level].offset;
4145 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4146
4147 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4148 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4149 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4150
4151 if (iview->image->info.samples > 1)
4152 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4153
4154 if (device->physical_device->rad_info.chip_class >= CIK) {
4155 struct radeon_info *info = &device->physical_device->rad_info;
4156 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4157 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4158 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4159 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4160 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4161 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4162
4163 if (stencil_only)
4164 tile_mode = stencil_tile_mode;
4165
4166 ds->db_depth_info |=
4167 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4168 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4169 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4170 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4171 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4172 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4173 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4174 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4175 } else {
4176 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4177 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4178 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4179 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4180 if (stencil_only)
4181 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4182 }
4183
4184 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4185 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4186 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4187
4188 if (radv_htile_enabled(iview->image, level)) {
4189 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4190
4191 if (!iview->image->surface.has_stencil &&
4192 !radv_image_is_tc_compat_htile(iview->image))
4193 /* Use all of the htile_buffer for depth if there's no stencil. */
4194 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4195
4196 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4197 iview->image->htile_offset;
4198 ds->db_htile_data_base = va >> 8;
4199 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4200
4201 if (radv_image_is_tc_compat_htile(iview->image)) {
4202 unsigned max_zplanes =
4203 radv_calc_decompress_on_z_planes(device, iview);
4204
4205 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4206 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4207 }
4208 }
4209 }
4210
4211 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4212 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4213 }
4214
4215 VkResult radv_CreateFramebuffer(
4216 VkDevice _device,
4217 const VkFramebufferCreateInfo* pCreateInfo,
4218 const VkAllocationCallbacks* pAllocator,
4219 VkFramebuffer* pFramebuffer)
4220 {
4221 RADV_FROM_HANDLE(radv_device, device, _device);
4222 struct radv_framebuffer *framebuffer;
4223
4224 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4225
4226 size_t size = sizeof(*framebuffer) +
4227 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4228 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4229 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4230 if (framebuffer == NULL)
4231 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4232
4233 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4234 framebuffer->width = pCreateInfo->width;
4235 framebuffer->height = pCreateInfo->height;
4236 framebuffer->layers = pCreateInfo->layers;
4237 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4238 VkImageView _iview = pCreateInfo->pAttachments[i];
4239 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4240 framebuffer->attachments[i].attachment = iview;
4241 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4242 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4243 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4244 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4245 }
4246 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4247 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4248 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4249 }
4250
4251 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4252 return VK_SUCCESS;
4253 }
4254
4255 void radv_DestroyFramebuffer(
4256 VkDevice _device,
4257 VkFramebuffer _fb,
4258 const VkAllocationCallbacks* pAllocator)
4259 {
4260 RADV_FROM_HANDLE(radv_device, device, _device);
4261 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4262
4263 if (!fb)
4264 return;
4265 vk_free2(&device->alloc, pAllocator, fb);
4266 }
4267
4268 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4269 {
4270 switch (address_mode) {
4271 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4272 return V_008F30_SQ_TEX_WRAP;
4273 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4274 return V_008F30_SQ_TEX_MIRROR;
4275 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4276 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4277 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4278 return V_008F30_SQ_TEX_CLAMP_BORDER;
4279 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4280 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4281 default:
4282 unreachable("illegal tex wrap mode");
4283 break;
4284 }
4285 }
4286
4287 static unsigned
4288 radv_tex_compare(VkCompareOp op)
4289 {
4290 switch (op) {
4291 case VK_COMPARE_OP_NEVER:
4292 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4293 case VK_COMPARE_OP_LESS:
4294 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4295 case VK_COMPARE_OP_EQUAL:
4296 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4297 case VK_COMPARE_OP_LESS_OR_EQUAL:
4298 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4299 case VK_COMPARE_OP_GREATER:
4300 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4301 case VK_COMPARE_OP_NOT_EQUAL:
4302 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4303 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4304 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4305 case VK_COMPARE_OP_ALWAYS:
4306 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4307 default:
4308 unreachable("illegal compare mode");
4309 break;
4310 }
4311 }
4312
4313 static unsigned
4314 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4315 {
4316 switch (filter) {
4317 case VK_FILTER_NEAREST:
4318 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4319 V_008F38_SQ_TEX_XY_FILTER_POINT);
4320 case VK_FILTER_LINEAR:
4321 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4322 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4323 case VK_FILTER_CUBIC_IMG:
4324 default:
4325 fprintf(stderr, "illegal texture filter");
4326 return 0;
4327 }
4328 }
4329
4330 static unsigned
4331 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4332 {
4333 switch (mode) {
4334 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4335 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4336 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4337 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4338 default:
4339 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4340 }
4341 }
4342
4343 static unsigned
4344 radv_tex_bordercolor(VkBorderColor bcolor)
4345 {
4346 switch (bcolor) {
4347 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4348 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4349 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4350 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4351 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4352 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4353 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4354 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4355 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4356 default:
4357 break;
4358 }
4359 return 0;
4360 }
4361
4362 static unsigned
4363 radv_tex_aniso_filter(unsigned filter)
4364 {
4365 if (filter < 2)
4366 return 0;
4367 if (filter < 4)
4368 return 1;
4369 if (filter < 8)
4370 return 2;
4371 if (filter < 16)
4372 return 3;
4373 return 4;
4374 }
4375
4376 static unsigned
4377 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4378 {
4379 switch (mode) {
4380 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4381 return SQ_IMG_FILTER_MODE_BLEND;
4382 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4383 return SQ_IMG_FILTER_MODE_MIN;
4384 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4385 return SQ_IMG_FILTER_MODE_MAX;
4386 default:
4387 break;
4388 }
4389 return 0;
4390 }
4391
4392 static void
4393 radv_init_sampler(struct radv_device *device,
4394 struct radv_sampler *sampler,
4395 const VkSamplerCreateInfo *pCreateInfo)
4396 {
4397 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4398 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4399 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4400 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4401 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4402
4403 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4404 vk_find_struct_const(pCreateInfo->pNext,
4405 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4406 if (sampler_reduction)
4407 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4408
4409 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4410 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4411 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4412 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4413 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4414 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4415 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4416 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4417 S_008F30_DISABLE_CUBE_WRAP(0) |
4418 S_008F30_COMPAT_MODE(is_vi) |
4419 S_008F30_FILTER_MODE(filter_mode));
4420 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4421 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4422 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4423 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4424 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4425 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4426 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4427 S_008F38_MIP_POINT_PRECLAMP(0) |
4428 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4429 S_008F38_FILTER_PREC_FIX(1) |
4430 S_008F38_ANISO_OVERRIDE(is_vi));
4431 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4432 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4433 }
4434
4435 VkResult radv_CreateSampler(
4436 VkDevice _device,
4437 const VkSamplerCreateInfo* pCreateInfo,
4438 const VkAllocationCallbacks* pAllocator,
4439 VkSampler* pSampler)
4440 {
4441 RADV_FROM_HANDLE(radv_device, device, _device);
4442 struct radv_sampler *sampler;
4443
4444 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4445
4446 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4447 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4448 if (!sampler)
4449 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4450
4451 radv_init_sampler(device, sampler, pCreateInfo);
4452 *pSampler = radv_sampler_to_handle(sampler);
4453
4454 return VK_SUCCESS;
4455 }
4456
4457 void radv_DestroySampler(
4458 VkDevice _device,
4459 VkSampler _sampler,
4460 const VkAllocationCallbacks* pAllocator)
4461 {
4462 RADV_FROM_HANDLE(radv_device, device, _device);
4463 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4464
4465 if (!sampler)
4466 return;
4467 vk_free2(&device->alloc, pAllocator, sampler);
4468 }
4469
4470 /* vk_icd.h does not declare this function, so we declare it here to
4471 * suppress Wmissing-prototypes.
4472 */
4473 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4474 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4475
4476 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4477 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4478 {
4479 /* For the full details on loader interface versioning, see
4480 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4481 * What follows is a condensed summary, to help you navigate the large and
4482 * confusing official doc.
4483 *
4484 * - Loader interface v0 is incompatible with later versions. We don't
4485 * support it.
4486 *
4487 * - In loader interface v1:
4488 * - The first ICD entrypoint called by the loader is
4489 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4490 * entrypoint.
4491 * - The ICD must statically expose no other Vulkan symbol unless it is
4492 * linked with -Bsymbolic.
4493 * - Each dispatchable Vulkan handle created by the ICD must be
4494 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4495 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4496 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4497 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4498 * such loader-managed surfaces.
4499 *
4500 * - Loader interface v2 differs from v1 in:
4501 * - The first ICD entrypoint called by the loader is
4502 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4503 * statically expose this entrypoint.
4504 *
4505 * - Loader interface v3 differs from v2 in:
4506 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4507 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4508 * because the loader no longer does so.
4509 */
4510 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4511 return VK_SUCCESS;
4512 }
4513
4514 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4515 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4516 int *pFD)
4517 {
4518 RADV_FROM_HANDLE(radv_device, device, _device);
4519 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4520
4521 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4522
4523 /* At the moment, we support only the below handle types. */
4524 assert(pGetFdInfo->handleType ==
4525 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4526 pGetFdInfo->handleType ==
4527 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4528
4529 bool ret = radv_get_memory_fd(device, memory, pFD);
4530 if (ret == false)
4531 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4532 return VK_SUCCESS;
4533 }
4534
4535 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4536 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4537 int fd,
4538 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4539 {
4540 RADV_FROM_HANDLE(radv_device, device, _device);
4541
4542 switch (handleType) {
4543 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4544 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4545 return VK_SUCCESS;
4546
4547 default:
4548 /* The valid usage section for this function says:
4549 *
4550 * "handleType must not be one of the handle types defined as
4551 * opaque."
4552 *
4553 * So opaque handle types fall into the default "unsupported" case.
4554 */
4555 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4556 }
4557 }
4558
4559 static VkResult radv_import_opaque_fd(struct radv_device *device,
4560 int fd,
4561 uint32_t *syncobj)
4562 {
4563 uint32_t syncobj_handle = 0;
4564 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4565 if (ret != 0)
4566 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4567
4568 if (*syncobj)
4569 device->ws->destroy_syncobj(device->ws, *syncobj);
4570
4571 *syncobj = syncobj_handle;
4572 close(fd);
4573
4574 return VK_SUCCESS;
4575 }
4576
4577 static VkResult radv_import_sync_fd(struct radv_device *device,
4578 int fd,
4579 uint32_t *syncobj)
4580 {
4581 /* If we create a syncobj we do it locally so that if we have an error, we don't
4582 * leave a syncobj in an undetermined state in the fence. */
4583 uint32_t syncobj_handle = *syncobj;
4584 if (!syncobj_handle) {
4585 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4586 if (ret) {
4587 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4588 }
4589 }
4590
4591 if (fd == -1) {
4592 device->ws->signal_syncobj(device->ws, syncobj_handle);
4593 } else {
4594 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4595 if (ret != 0)
4596 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4597 }
4598
4599 *syncobj = syncobj_handle;
4600 if (fd != -1)
4601 close(fd);
4602
4603 return VK_SUCCESS;
4604 }
4605
4606 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4607 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4608 {
4609 RADV_FROM_HANDLE(radv_device, device, _device);
4610 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4611 uint32_t *syncobj_dst = NULL;
4612
4613 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4614 syncobj_dst = &sem->temp_syncobj;
4615 } else {
4616 syncobj_dst = &sem->syncobj;
4617 }
4618
4619 switch(pImportSemaphoreFdInfo->handleType) {
4620 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4621 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4622 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4623 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4624 default:
4625 unreachable("Unhandled semaphore handle type");
4626 }
4627 }
4628
4629 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4630 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4631 int *pFd)
4632 {
4633 RADV_FROM_HANDLE(radv_device, device, _device);
4634 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4635 int ret;
4636 uint32_t syncobj_handle;
4637
4638 if (sem->temp_syncobj)
4639 syncobj_handle = sem->temp_syncobj;
4640 else
4641 syncobj_handle = sem->syncobj;
4642
4643 switch(pGetFdInfo->handleType) {
4644 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4645 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4646 break;
4647 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4648 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4649 if (!ret) {
4650 if (sem->temp_syncobj) {
4651 close (sem->temp_syncobj);
4652 sem->temp_syncobj = 0;
4653 } else {
4654 device->ws->reset_syncobj(device->ws, syncobj_handle);
4655 }
4656 }
4657 break;
4658 default:
4659 unreachable("Unhandled semaphore handle type");
4660 }
4661
4662 if (ret)
4663 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4664 return VK_SUCCESS;
4665 }
4666
4667 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4668 VkPhysicalDevice physicalDevice,
4669 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4670 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4671 {
4672 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4673
4674 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4675 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4676 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4677 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4678 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4679 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4680 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4681 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4682 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4683 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4684 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4685 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4686 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4687 } else {
4688 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4689 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4690 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4691 }
4692 }
4693
4694 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4695 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4696 {
4697 RADV_FROM_HANDLE(radv_device, device, _device);
4698 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4699 uint32_t *syncobj_dst = NULL;
4700
4701
4702 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4703 syncobj_dst = &fence->temp_syncobj;
4704 } else {
4705 syncobj_dst = &fence->syncobj;
4706 }
4707
4708 switch(pImportFenceFdInfo->handleType) {
4709 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4710 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4711 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4712 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4713 default:
4714 unreachable("Unhandled fence handle type");
4715 }
4716 }
4717
4718 VkResult radv_GetFenceFdKHR(VkDevice _device,
4719 const VkFenceGetFdInfoKHR *pGetFdInfo,
4720 int *pFd)
4721 {
4722 RADV_FROM_HANDLE(radv_device, device, _device);
4723 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4724 int ret;
4725 uint32_t syncobj_handle;
4726
4727 if (fence->temp_syncobj)
4728 syncobj_handle = fence->temp_syncobj;
4729 else
4730 syncobj_handle = fence->syncobj;
4731
4732 switch(pGetFdInfo->handleType) {
4733 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4734 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4735 break;
4736 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4737 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4738 if (!ret) {
4739 if (fence->temp_syncobj) {
4740 close (fence->temp_syncobj);
4741 fence->temp_syncobj = 0;
4742 } else {
4743 device->ws->reset_syncobj(device->ws, syncobj_handle);
4744 }
4745 }
4746 break;
4747 default:
4748 unreachable("Unhandled fence handle type");
4749 }
4750
4751 if (ret)
4752 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4753 return VK_SUCCESS;
4754 }
4755
4756 void radv_GetPhysicalDeviceExternalFenceProperties(
4757 VkPhysicalDevice physicalDevice,
4758 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4759 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4760 {
4761 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4762
4763 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4764 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4765 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4766 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4767 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4768 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4769 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4770 } else {
4771 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4772 pExternalFenceProperties->compatibleHandleTypes = 0;
4773 pExternalFenceProperties->externalFenceFeatures = 0;
4774 }
4775 }
4776
4777 VkResult
4778 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4779 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4780 const VkAllocationCallbacks* pAllocator,
4781 VkDebugReportCallbackEXT* pCallback)
4782 {
4783 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4784 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4785 pCreateInfo, pAllocator, &instance->alloc,
4786 pCallback);
4787 }
4788
4789 void
4790 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4791 VkDebugReportCallbackEXT _callback,
4792 const VkAllocationCallbacks* pAllocator)
4793 {
4794 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4795 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4796 _callback, pAllocator, &instance->alloc);
4797 }
4798
4799 void
4800 radv_DebugReportMessageEXT(VkInstance _instance,
4801 VkDebugReportFlagsEXT flags,
4802 VkDebugReportObjectTypeEXT objectType,
4803 uint64_t object,
4804 size_t location,
4805 int32_t messageCode,
4806 const char* pLayerPrefix,
4807 const char* pMessage)
4808 {
4809 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4810 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4811 object, location, messageCode, pLayerPrefix, pMessage);
4812 }
4813
4814 void
4815 radv_GetDeviceGroupPeerMemoryFeatures(
4816 VkDevice device,
4817 uint32_t heapIndex,
4818 uint32_t localDeviceIndex,
4819 uint32_t remoteDeviceIndex,
4820 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4821 {
4822 assert(localDeviceIndex == remoteDeviceIndex);
4823
4824 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4825 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4826 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4827 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4828 }