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radv: disable DCC for shareable images on GFX9+
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
76 return false;
77
78 if (pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
79 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
80 return false;
81
82 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
83 return false;
84
85 if (pCreateInfo->mipLevels > 1)
86 return false;
87
88 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
89 * tests - disable for now */
90 if (pCreateInfo->samples >= 2 &&
91 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 return true;
104 }
105
106 static bool
107 radv_use_dcc_for_image(struct radv_device *device,
108 const struct radv_image_create_info *create_info,
109 const VkImageCreateInfo *pCreateInfo)
110 {
111 bool dcc_compatible_formats;
112 bool blendable;
113 bool shareable = vk_find_struct_const(pCreateInfo->pNext,
114 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
115
116 /* DCC (Delta Color Compression) is only available for GFX8+. */
117 if (device->physical_device->rad_info.chip_class < VI)
118 return false;
119
120 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
121 return false;
122
123 /* FIXME: DCC is broken for shareable images starting with GFX9 */
124 if (device->physical_device->rad_info.chip_class >= GFX9 &&
125 shareable)
126 return false;
127
128 /* TODO: Enable DCC for storage images. */
129 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
130 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
131 return false;
132
133 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
134 return false;
135
136 /* TODO: Enable DCC for mipmaps and array layers. */
137 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
138 return false;
139
140 if (create_info->scanout)
141 return false;
142
143 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
144 * 2x can be enabled with an option.
145 */
146 if (pCreateInfo->samples > 2 ||
147 (pCreateInfo->samples == 2 &&
148 !device->physical_device->dcc_msaa_allowed))
149 return false;
150
151 /* Determine if the formats are DCC compatible. */
152 dcc_compatible_formats =
153 radv_is_colorbuffer_format_supported(pCreateInfo->format,
154 &blendable);
155
156 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
157 const struct VkImageFormatListCreateInfoKHR *format_list =
158 (const struct VkImageFormatListCreateInfoKHR *)
159 vk_find_struct_const(pCreateInfo->pNext,
160 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
161
162 /* We have to ignore the existence of the list if viewFormatCount = 0 */
163 if (format_list && format_list->viewFormatCount) {
164 /* compatibility is transitive, so we only need to check
165 * one format with everything else. */
166 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
167 if (!radv_dcc_formats_compatible(pCreateInfo->format,
168 format_list->pViewFormats[i]))
169 dcc_compatible_formats = false;
170 }
171 } else {
172 dcc_compatible_formats = false;
173 }
174 }
175
176 if (!dcc_compatible_formats)
177 return false;
178
179 return true;
180 }
181
182 static int
183 radv_init_surface(struct radv_device *device,
184 struct radeon_surf *surface,
185 const struct radv_image_create_info *create_info)
186 {
187 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
188 unsigned array_mode = radv_choose_tiling(device, create_info);
189 const struct vk_format_description *desc =
190 vk_format_description(pCreateInfo->format);
191 bool is_depth, is_stencil;
192
193 is_depth = vk_format_has_depth(desc);
194 is_stencil = vk_format_has_stencil(desc);
195
196 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
197 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
198
199 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
200 /* align byte per element on dword */
201 if (surface->bpe == 3) {
202 surface->bpe = 4;
203 }
204 surface->flags = RADEON_SURF_SET(array_mode, MODE);
205
206 switch (pCreateInfo->imageType){
207 case VK_IMAGE_TYPE_1D:
208 if (pCreateInfo->arrayLayers > 1)
209 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
210 else
211 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
212 break;
213 case VK_IMAGE_TYPE_2D:
214 if (pCreateInfo->arrayLayers > 1)
215 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
216 else
217 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
218 break;
219 case VK_IMAGE_TYPE_3D:
220 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
221 break;
222 default:
223 unreachable("unhandled image type");
224 }
225
226 if (is_depth) {
227 surface->flags |= RADEON_SURF_ZBUFFER;
228 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
229 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
230 }
231
232 if (is_stencil)
233 surface->flags |= RADEON_SURF_SBUFFER;
234
235 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
236
237 if (!radv_use_dcc_for_image(device, create_info, pCreateInfo))
238 surface->flags |= RADEON_SURF_DISABLE_DCC;
239
240 if (create_info->scanout)
241 surface->flags |= RADEON_SURF_SCANOUT;
242 return 0;
243 }
244
245 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
246 {
247 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
248 }
249
250 static inline unsigned
251 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
252 {
253 if (stencil)
254 return image->surface.u.legacy.stencil_tiling_index[level];
255 else
256 return image->surface.u.legacy.tiling_index[level];
257 }
258
259 static unsigned radv_map_swizzle(unsigned swizzle)
260 {
261 switch (swizzle) {
262 case VK_SWIZZLE_Y:
263 return V_008F0C_SQ_SEL_Y;
264 case VK_SWIZZLE_Z:
265 return V_008F0C_SQ_SEL_Z;
266 case VK_SWIZZLE_W:
267 return V_008F0C_SQ_SEL_W;
268 case VK_SWIZZLE_0:
269 return V_008F0C_SQ_SEL_0;
270 case VK_SWIZZLE_1:
271 return V_008F0C_SQ_SEL_1;
272 default: /* VK_SWIZZLE_X */
273 return V_008F0C_SQ_SEL_X;
274 }
275 }
276
277 static void
278 radv_make_buffer_descriptor(struct radv_device *device,
279 struct radv_buffer *buffer,
280 VkFormat vk_format,
281 unsigned offset,
282 unsigned range,
283 uint32_t *state)
284 {
285 const struct vk_format_description *desc;
286 unsigned stride;
287 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
288 uint64_t va = gpu_address + buffer->offset;
289 unsigned num_format, data_format;
290 int first_non_void;
291 desc = vk_format_description(vk_format);
292 first_non_void = vk_format_get_first_non_void_channel(vk_format);
293 stride = desc->block.bits / 8;
294
295 num_format = radv_translate_buffer_numformat(desc, first_non_void);
296 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
297
298 va += offset;
299 state[0] = va;
300 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
301 S_008F04_STRIDE(stride);
302
303 if (device->physical_device->rad_info.chip_class != VI && stride) {
304 range /= stride;
305 }
306
307 state[2] = range;
308 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
309 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
310 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
311 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
312 S_008F0C_NUM_FORMAT(num_format) |
313 S_008F0C_DATA_FORMAT(data_format);
314 }
315
316 static void
317 si_set_mutable_tex_desc_fields(struct radv_device *device,
318 struct radv_image *image,
319 const struct legacy_surf_level *base_level_info,
320 unsigned base_level, unsigned first_level,
321 unsigned block_width, bool is_stencil,
322 bool is_storage_image, uint32_t *state)
323 {
324 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
325 uint64_t va = gpu_address;
326 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
327 uint64_t meta_va = 0;
328 if (chip_class >= GFX9) {
329 if (is_stencil)
330 va += image->surface.u.gfx9.stencil_offset;
331 else
332 va += image->surface.u.gfx9.surf_offset;
333 } else
334 va += base_level_info->offset;
335
336 state[0] = va >> 8;
337 if (chip_class >= GFX9 ||
338 base_level_info->mode == RADEON_SURF_MODE_2D)
339 state[0] |= image->surface.tile_swizzle;
340 state[1] &= C_008F14_BASE_ADDRESS_HI;
341 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
342
343 if (chip_class >= VI) {
344 state[6] &= C_008F28_COMPRESSION_EN;
345 state[7] = 0;
346 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
347 meta_va = gpu_address + image->dcc_offset;
348 if (chip_class <= VI)
349 meta_va += base_level_info->dcc_offset;
350 } else if (!is_storage_image &&
351 radv_image_is_tc_compat_htile(image)) {
352 meta_va = gpu_address + image->htile_offset;
353 }
354
355 if (meta_va) {
356 state[6] |= S_008F28_COMPRESSION_EN(1);
357 state[7] = meta_va >> 8;
358 state[7] |= image->surface.tile_swizzle;
359 }
360 }
361
362 if (chip_class >= GFX9) {
363 state[3] &= C_008F1C_SW_MODE;
364 state[4] &= C_008F20_PITCH_GFX9;
365
366 if (is_stencil) {
367 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
368 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
369 } else {
370 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
371 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
372 }
373
374 state[5] &= C_008F24_META_DATA_ADDRESS &
375 C_008F24_META_PIPE_ALIGNED &
376 C_008F24_META_RB_ALIGNED;
377 if (meta_va) {
378 struct gfx9_surf_meta_flags meta;
379
380 if (image->dcc_offset)
381 meta = image->surface.u.gfx9.dcc;
382 else
383 meta = image->surface.u.gfx9.htile;
384
385 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
386 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
387 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
388 }
389 } else {
390 /* SI-CI-VI */
391 unsigned pitch = base_level_info->nblk_x * block_width;
392 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
393
394 state[3] &= C_008F1C_TILING_INDEX;
395 state[3] |= S_008F1C_TILING_INDEX(index);
396 state[4] &= C_008F20_PITCH_GFX6;
397 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
398 }
399 }
400
401 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
402 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
403 {
404 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
405 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
406
407 /* GFX9 allocates 1D textures as 2D. */
408 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
409 image_type = VK_IMAGE_TYPE_2D;
410 switch (image_type) {
411 case VK_IMAGE_TYPE_1D:
412 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
413 case VK_IMAGE_TYPE_2D:
414 if (nr_samples > 1)
415 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
416 else
417 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
418 case VK_IMAGE_TYPE_3D:
419 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
420 return V_008F1C_SQ_RSRC_IMG_3D;
421 else
422 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
423 default:
424 unreachable("illegal image type");
425 }
426 }
427
428 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
429 {
430 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
431
432 if (swizzle[3] == VK_SWIZZLE_X) {
433 /* For the pre-defined border color values (white, opaque
434 * black, transparent black), the only thing that matters is
435 * that the alpha channel winds up in the correct place
436 * (because the RGB channels are all the same) so either of
437 * these enumerations will work.
438 */
439 if (swizzle[2] == VK_SWIZZLE_Y)
440 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
441 else
442 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
443 } else if (swizzle[0] == VK_SWIZZLE_X) {
444 if (swizzle[1] == VK_SWIZZLE_Y)
445 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
446 else
447 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
448 } else if (swizzle[1] == VK_SWIZZLE_X) {
449 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
450 } else if (swizzle[2] == VK_SWIZZLE_X) {
451 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
452 }
453
454 return bc_swizzle;
455 }
456
457 /**
458 * Build the sampler view descriptor for a texture.
459 */
460 static void
461 si_make_texture_descriptor(struct radv_device *device,
462 struct radv_image *image,
463 bool is_storage_image,
464 VkImageViewType view_type,
465 VkFormat vk_format,
466 const VkComponentMapping *mapping,
467 unsigned first_level, unsigned last_level,
468 unsigned first_layer, unsigned last_layer,
469 unsigned width, unsigned height, unsigned depth,
470 uint32_t *state,
471 uint32_t *fmask_state)
472 {
473 const struct vk_format_description *desc;
474 enum vk_swizzle swizzle[4];
475 int first_non_void;
476 unsigned num_format, data_format, type;
477
478 desc = vk_format_description(vk_format);
479
480 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
481 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
482 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
483 } else {
484 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
485 }
486
487 first_non_void = vk_format_get_first_non_void_channel(vk_format);
488
489 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
490 if (num_format == ~0) {
491 num_format = 0;
492 }
493
494 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
495 if (data_format == ~0) {
496 data_format = 0;
497 }
498
499 /* S8 with either Z16 or Z32 HTILE need a special format. */
500 if (device->physical_device->rad_info.chip_class >= GFX9 &&
501 vk_format == VK_FORMAT_S8_UINT &&
502 radv_image_is_tc_compat_htile(image)) {
503 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
504 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
505 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
506 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
507 }
508 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
509 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
510 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
511 height = 1;
512 depth = image->info.array_size;
513 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
514 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
515 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
516 depth = image->info.array_size;
517 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
518 depth = image->info.array_size / 6;
519
520 state[0] = 0;
521 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
522 S_008F14_NUM_FORMAT_GFX6(num_format));
523 state[2] = (S_008F18_WIDTH(width - 1) |
524 S_008F18_HEIGHT(height - 1) |
525 S_008F18_PERF_MOD(4));
526 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
527 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
528 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
529 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
530 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
531 0 : first_level) |
532 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
533 util_logbase2(image->info.samples) :
534 last_level) |
535 S_008F1C_TYPE(type));
536 state[4] = 0;
537 state[5] = S_008F24_BASE_ARRAY(first_layer);
538 state[6] = 0;
539 state[7] = 0;
540
541 if (device->physical_device->rad_info.chip_class >= GFX9) {
542 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
543
544 /* Depth is the last accessible layer on Gfx9.
545 * The hw doesn't need to know the total number of layers.
546 */
547 if (type == V_008F1C_SQ_RSRC_IMG_3D)
548 state[4] |= S_008F20_DEPTH(depth - 1);
549 else
550 state[4] |= S_008F20_DEPTH(last_layer);
551
552 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
553 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
554 util_logbase2(image->info.samples) :
555 image->info.levels - 1);
556 } else {
557 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
558 state[4] |= S_008F20_DEPTH(depth - 1);
559 state[5] |= S_008F24_LAST_ARRAY(last_layer);
560 }
561 if (image->dcc_offset) {
562 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
563
564 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
565 } else {
566 /* The last dword is unused by hw. The shader uses it to clear
567 * bits in the first dword of sampler state.
568 */
569 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
570 if (first_level == last_level)
571 state[7] = C_008F30_MAX_ANISO_RATIO;
572 else
573 state[7] = 0xffffffff;
574 }
575 }
576
577 /* Initialize the sampler view for FMASK. */
578 if (radv_image_has_fmask(image)) {
579 uint32_t fmask_format, num_format;
580 uint64_t gpu_address = radv_buffer_get_va(image->bo);
581 uint64_t va;
582
583 va = gpu_address + image->offset + image->fmask.offset;
584
585 if (device->physical_device->rad_info.chip_class >= GFX9) {
586 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
587 switch (image->info.samples) {
588 case 2:
589 num_format = V_008F14_IMG_FMASK_8_2_2;
590 break;
591 case 4:
592 num_format = V_008F14_IMG_FMASK_8_4_4;
593 break;
594 case 8:
595 num_format = V_008F14_IMG_FMASK_32_8_8;
596 break;
597 default:
598 unreachable("invalid nr_samples");
599 }
600 } else {
601 switch (image->info.samples) {
602 case 2:
603 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
604 break;
605 case 4:
606 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
607 break;
608 case 8:
609 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
610 break;
611 default:
612 assert(0);
613 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
614 }
615 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
616 }
617
618 fmask_state[0] = va >> 8;
619 fmask_state[0] |= image->fmask.tile_swizzle;
620 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
621 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
622 S_008F14_NUM_FORMAT_GFX6(num_format);
623 fmask_state[2] = S_008F18_WIDTH(width - 1) |
624 S_008F18_HEIGHT(height - 1);
625 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
626 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
627 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
628 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
629 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
630 fmask_state[4] = 0;
631 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
632 fmask_state[6] = 0;
633 fmask_state[7] = 0;
634
635 if (device->physical_device->rad_info.chip_class >= GFX9) {
636 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
637 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
638 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
639 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
640 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
641 } else {
642 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
643 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
644 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
645 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
646 }
647 } else if (fmask_state)
648 memset(fmask_state, 0, 8 * 4);
649 }
650
651 static void
652 radv_query_opaque_metadata(struct radv_device *device,
653 struct radv_image *image,
654 struct radeon_bo_metadata *md)
655 {
656 static const VkComponentMapping fixedmapping;
657 uint32_t desc[8], i;
658
659 /* Metadata image format format version 1:
660 * [0] = 1 (metadata format identifier)
661 * [1] = (VENDOR_ID << 16) | PCI_ID
662 * [2:9] = image descriptor for the whole resource
663 * [2] is always 0, because the base address is cleared
664 * [9] is the DCC offset bits [39:8] from the beginning of
665 * the buffer
666 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
667 */
668 md->metadata[0] = 1; /* metadata image format version 1 */
669
670 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
671 md->metadata[1] = si_get_bo_metadata_word1(device);
672
673
674 si_make_texture_descriptor(device, image, false,
675 (VkImageViewType)image->type, image->vk_format,
676 &fixedmapping, 0, image->info.levels - 1, 0,
677 image->info.array_size,
678 image->info.width, image->info.height,
679 image->info.depth,
680 desc, NULL);
681
682 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
683 image->surface.blk_w, false, false, desc);
684
685 /* Clear the base address and set the relative DCC offset. */
686 desc[0] = 0;
687 desc[1] &= C_008F14_BASE_ADDRESS_HI;
688 desc[7] = image->dcc_offset >> 8;
689
690 /* Dwords [2:9] contain the image descriptor. */
691 memcpy(&md->metadata[2], desc, sizeof(desc));
692
693 /* Dwords [10:..] contain the mipmap level offsets. */
694 if (device->physical_device->rad_info.chip_class <= VI) {
695 for (i = 0; i <= image->info.levels - 1; i++)
696 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
697 md->size_metadata = (11 + image->info.levels - 1) * 4;
698 }
699 }
700
701 void
702 radv_init_metadata(struct radv_device *device,
703 struct radv_image *image,
704 struct radeon_bo_metadata *metadata)
705 {
706 struct radeon_surf *surface = &image->surface;
707
708 memset(metadata, 0, sizeof(*metadata));
709
710 if (device->physical_device->rad_info.chip_class >= GFX9) {
711 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
712 } else {
713 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
714 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
715 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
716 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
717 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
718 metadata->u.legacy.bankw = surface->u.legacy.bankw;
719 metadata->u.legacy.bankh = surface->u.legacy.bankh;
720 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
721 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
722 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
723 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
724 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
725 }
726 radv_query_opaque_metadata(device, image, metadata);
727 }
728
729 /* The number of samples can be specified independently of the texture. */
730 static void
731 radv_image_get_fmask_info(struct radv_device *device,
732 struct radv_image *image,
733 unsigned nr_samples,
734 struct radv_fmask_info *out)
735 {
736 /* FMASK is allocated like an ordinary texture. */
737 struct radeon_surf fmask = {};
738 struct ac_surf_info info = image->info;
739 memset(out, 0, sizeof(*out));
740
741 if (device->physical_device->rad_info.chip_class >= GFX9) {
742 out->alignment = image->surface.u.gfx9.fmask_alignment;
743 out->size = image->surface.u.gfx9.fmask_size;
744 return;
745 }
746
747 fmask.blk_w = image->surface.blk_w;
748 fmask.blk_h = image->surface.blk_h;
749 info.samples = 1;
750 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
751
752 if (!image->shareable) {
753 info.fmask_surf_index = &device->fmask_mrt_offset_counter;
754 info.surf_index = &device->fmask_mrt_offset_counter;
755 }
756
757 /* Force 2D tiling if it wasn't set. This may occur when creating
758 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
759 * destination buffer must have an FMASK too. */
760 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
761 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
762
763 switch (nr_samples) {
764 case 2:
765 case 4:
766 fmask.bpe = 1;
767 break;
768 case 8:
769 fmask.bpe = 4;
770 break;
771 default:
772 return;
773 }
774
775 device->ws->surface_init(device->ws, &info, &fmask);
776 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
777
778 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
779 if (out->slice_tile_max)
780 out->slice_tile_max -= 1;
781
782 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
783 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
784 out->bank_height = fmask.u.legacy.bankh;
785 out->tile_swizzle = fmask.tile_swizzle;
786 out->alignment = MAX2(256, fmask.surf_alignment);
787 out->size = fmask.surf_size;
788
789 assert(!out->tile_swizzle || !image->shareable);
790 }
791
792 static void
793 radv_image_alloc_fmask(struct radv_device *device,
794 struct radv_image *image)
795 {
796 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
797
798 image->fmask.offset = align64(image->size, image->fmask.alignment);
799 image->size = image->fmask.offset + image->fmask.size;
800 image->alignment = MAX2(image->alignment, image->fmask.alignment);
801 }
802
803 static void
804 radv_image_get_cmask_info(struct radv_device *device,
805 struct radv_image *image,
806 struct radv_cmask_info *out)
807 {
808 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
809 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
810 unsigned cl_width, cl_height;
811
812 if (device->physical_device->rad_info.chip_class >= GFX9) {
813 out->alignment = image->surface.u.gfx9.cmask_alignment;
814 out->size = image->surface.u.gfx9.cmask_size;
815 return;
816 }
817
818 switch (num_pipes) {
819 case 2:
820 cl_width = 32;
821 cl_height = 16;
822 break;
823 case 4:
824 cl_width = 32;
825 cl_height = 32;
826 break;
827 case 8:
828 cl_width = 64;
829 cl_height = 32;
830 break;
831 case 16: /* Hawaii */
832 cl_width = 64;
833 cl_height = 64;
834 break;
835 default:
836 assert(0);
837 return;
838 }
839
840 unsigned base_align = num_pipes * pipe_interleave_bytes;
841
842 unsigned width = align(image->info.width, cl_width*8);
843 unsigned height = align(image->info.height, cl_height*8);
844 unsigned slice_elements = (width * height) / (8*8);
845
846 /* Each element of CMASK is a nibble. */
847 unsigned slice_bytes = slice_elements / 2;
848
849 out->slice_tile_max = (width * height) / (128*128);
850 if (out->slice_tile_max)
851 out->slice_tile_max -= 1;
852
853 out->alignment = MAX2(256, base_align);
854 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
855 align(slice_bytes, base_align);
856 }
857
858 static void
859 radv_image_alloc_cmask(struct radv_device *device,
860 struct radv_image *image)
861 {
862 uint32_t clear_value_size = 0;
863 radv_image_get_cmask_info(device, image, &image->cmask);
864
865 image->cmask.offset = align64(image->size, image->cmask.alignment);
866 /* + 8 for storing the clear values */
867 if (!image->clear_value_offset) {
868 image->clear_value_offset = image->cmask.offset + image->cmask.size;
869 clear_value_size = 8;
870 }
871 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
872 image->alignment = MAX2(image->alignment, image->cmask.alignment);
873 }
874
875 static void
876 radv_image_alloc_dcc(struct radv_image *image)
877 {
878 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
879 /* + 16 for storing the clear values + dcc pred */
880 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
881 image->dcc_pred_offset = image->clear_value_offset + 8;
882 image->size = image->dcc_offset + image->surface.dcc_size + 16;
883 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
884 }
885
886 static void
887 radv_image_alloc_htile(struct radv_image *image)
888 {
889 image->htile_offset = align64(image->size, image->surface.htile_alignment);
890
891 /* + 8 for storing the clear values */
892 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
893 image->size = image->clear_value_offset + 8;
894 image->alignment = align64(image->alignment, image->surface.htile_alignment);
895 }
896
897 static inline bool
898 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
899 {
900 if (image->info.samples <= 1 &&
901 image->info.width * image->info.height <= 512 * 512) {
902 /* Do not enable CMASK or DCC for small surfaces where the cost
903 * of the eliminate pass can be higher than the benefit of fast
904 * clear. RadeonSI does this, but the image threshold is
905 * different.
906 */
907 return false;
908 }
909
910 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
911 (image->exclusive || image->queue_family_mask == 1);
912 }
913
914 static inline bool
915 radv_image_can_enable_dcc(struct radv_image *image)
916 {
917 return radv_image_can_enable_dcc_or_cmask(image) &&
918 radv_image_has_dcc(image);
919 }
920
921 static inline bool
922 radv_image_can_enable_cmask(struct radv_image *image)
923 {
924 if (image->surface.bpe > 8 && image->info.samples == 1) {
925 /* Do not enable CMASK for non-MSAA images (fast color clear)
926 * because 128 bit formats are not supported, but FMASK might
927 * still be used.
928 */
929 return false;
930 }
931
932 return radv_image_can_enable_dcc_or_cmask(image) &&
933 image->info.levels == 1 &&
934 image->info.depth == 1 &&
935 !image->surface.is_linear;
936 }
937
938 static inline bool
939 radv_image_can_enable_fmask(struct radv_image *image)
940 {
941 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
942 }
943
944 static inline bool
945 radv_image_can_enable_htile(struct radv_image *image)
946 {
947 return image->info.levels == 1 && vk_format_is_depth(image->vk_format);
948 }
949
950 VkResult
951 radv_image_create(VkDevice _device,
952 const struct radv_image_create_info *create_info,
953 const VkAllocationCallbacks* alloc,
954 VkImage *pImage)
955 {
956 RADV_FROM_HANDLE(radv_device, device, _device);
957 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
958 struct radv_image *image = NULL;
959 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
960
961 radv_assert(pCreateInfo->mipLevels > 0);
962 radv_assert(pCreateInfo->arrayLayers > 0);
963 radv_assert(pCreateInfo->samples > 0);
964 radv_assert(pCreateInfo->extent.width > 0);
965 radv_assert(pCreateInfo->extent.height > 0);
966 radv_assert(pCreateInfo->extent.depth > 0);
967
968 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
969 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
970 if (!image)
971 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
972
973 image->type = pCreateInfo->imageType;
974 image->info.width = pCreateInfo->extent.width;
975 image->info.height = pCreateInfo->extent.height;
976 image->info.depth = pCreateInfo->extent.depth;
977 image->info.samples = pCreateInfo->samples;
978 image->info.array_size = pCreateInfo->arrayLayers;
979 image->info.levels = pCreateInfo->mipLevels;
980 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
981
982 image->vk_format = pCreateInfo->format;
983 image->tiling = pCreateInfo->tiling;
984 image->usage = pCreateInfo->usage;
985 image->flags = pCreateInfo->flags;
986
987 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
988 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
989 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
990 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
991 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
992 else
993 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
994 }
995
996 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
997 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
998 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
999 image->info.surf_index = &device->image_mrt_offset_counter;
1000 }
1001
1002 radv_init_surface(device, &image->surface, create_info);
1003
1004 device->ws->surface_init(device->ws, &image->info, &image->surface);
1005
1006 image->size = image->surface.surf_size;
1007 image->alignment = image->surface.surf_alignment;
1008
1009 if (!create_info->no_metadata_planes) {
1010 /* Try to enable DCC first. */
1011 if (radv_image_can_enable_dcc(image)) {
1012 radv_image_alloc_dcc(image);
1013 if (image->info.samples > 1) {
1014 /* CMASK should be enabled because DCC fast
1015 * clear with MSAA needs it.
1016 */
1017 assert(radv_image_can_enable_cmask(image));
1018 radv_image_alloc_cmask(device, image);
1019 }
1020 } else {
1021 /* When DCC cannot be enabled, try CMASK. */
1022 image->surface.dcc_size = 0;
1023 if (radv_image_can_enable_cmask(image)) {
1024 radv_image_alloc_cmask(device, image);
1025 }
1026 }
1027
1028 /* Try to enable FMASK for multisampled images. */
1029 if (radv_image_can_enable_fmask(image)) {
1030 radv_image_alloc_fmask(device, image);
1031 } else {
1032 /* Otherwise, try to enable HTILE for depth surfaces. */
1033 if (radv_image_can_enable_htile(image) &&
1034 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1035 radv_image_alloc_htile(image);
1036 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1037 } else {
1038 image->surface.htile_size = 0;
1039 }
1040 }
1041 } else {
1042 image->surface.dcc_size = 0;
1043 image->surface.htile_size = 0;
1044 }
1045
1046 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1047 image->alignment = MAX2(image->alignment, 4096);
1048 image->size = align64(image->size, image->alignment);
1049 image->offset = 0;
1050
1051 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1052 0, RADEON_FLAG_VIRTUAL);
1053 if (!image->bo) {
1054 vk_free2(&device->alloc, alloc, image);
1055 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1056 }
1057 }
1058
1059 *pImage = radv_image_to_handle(image);
1060
1061 return VK_SUCCESS;
1062 }
1063
1064 static void
1065 radv_image_view_make_descriptor(struct radv_image_view *iview,
1066 struct radv_device *device,
1067 const VkComponentMapping *components,
1068 bool is_storage_image)
1069 {
1070 struct radv_image *image = iview->image;
1071 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1072 uint32_t blk_w;
1073 uint32_t *descriptor;
1074 uint32_t hw_level = 0;
1075
1076 if (is_storage_image) {
1077 descriptor = iview->storage_descriptor;
1078 } else {
1079 descriptor = iview->descriptor;
1080 }
1081
1082 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1083 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1084
1085 if (device->physical_device->rad_info.chip_class >= GFX9)
1086 hw_level = iview->base_mip;
1087 si_make_texture_descriptor(device, image, is_storage_image,
1088 iview->type,
1089 iview->vk_format,
1090 components,
1091 hw_level, hw_level + iview->level_count - 1,
1092 iview->base_layer,
1093 iview->base_layer + iview->layer_count - 1,
1094 iview->extent.width,
1095 iview->extent.height,
1096 iview->extent.depth,
1097 descriptor,
1098 descriptor + 8);
1099
1100 const struct legacy_surf_level *base_level_info = NULL;
1101 if (device->physical_device->rad_info.chip_class <= GFX9) {
1102 if (is_stencil)
1103 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1104 else
1105 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1106 }
1107 si_set_mutable_tex_desc_fields(device, image,
1108 base_level_info,
1109 iview->base_mip,
1110 iview->base_mip,
1111 blk_w, is_stencil, is_storage_image, descriptor);
1112 }
1113
1114 void
1115 radv_image_view_init(struct radv_image_view *iview,
1116 struct radv_device *device,
1117 const VkImageViewCreateInfo* pCreateInfo)
1118 {
1119 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1120 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1121
1122 switch (image->type) {
1123 case VK_IMAGE_TYPE_1D:
1124 case VK_IMAGE_TYPE_2D:
1125 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1126 break;
1127 case VK_IMAGE_TYPE_3D:
1128 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1129 <= radv_minify(image->info.depth, range->baseMipLevel));
1130 break;
1131 default:
1132 unreachable("bad VkImageType");
1133 }
1134 iview->image = image;
1135 iview->bo = image->bo;
1136 iview->type = pCreateInfo->viewType;
1137 iview->vk_format = pCreateInfo->format;
1138 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1139
1140 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1141 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1142 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1143 iview->vk_format = vk_format_depth_only(iview->vk_format);
1144 }
1145
1146 if (device->physical_device->rad_info.chip_class >= GFX9) {
1147 iview->extent = (VkExtent3D) {
1148 .width = image->info.width,
1149 .height = image->info.height,
1150 .depth = image->info.depth,
1151 };
1152 } else {
1153 iview->extent = (VkExtent3D) {
1154 .width = radv_minify(image->info.width , range->baseMipLevel),
1155 .height = radv_minify(image->info.height, range->baseMipLevel),
1156 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1157 };
1158 }
1159
1160 if (iview->vk_format != image->vk_format) {
1161 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1162 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1163 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1164 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1165
1166 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1167 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1168
1169 /* Comment ported from amdvlk -
1170 * If we have the following image:
1171 * Uncompressed pixels Compressed block sizes (4x4)
1172 * mip0: 22 x 22 6 x 6
1173 * mip1: 11 x 11 3 x 3
1174 * mip2: 5 x 5 2 x 2
1175 * mip3: 2 x 2 1 x 1
1176 * mip4: 1 x 1 1 x 1
1177 *
1178 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1179 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1180 * divide-by-two integer math):
1181 * mip0: 6x6
1182 * mip1: 3x3
1183 * mip2: 1x1
1184 * mip3: 1x1
1185 *
1186 * This means that mip2 will be missing texels.
1187 *
1188 * Fix this by calculating the base mip's width and height, then convert that, and round it
1189 * back up to get the level 0 size.
1190 * Clamp the converted size between the original values, and next power of two, which
1191 * means we don't oversize the image.
1192 */
1193 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1194 vk_format_is_compressed(image->vk_format) &&
1195 !vk_format_is_compressed(iview->vk_format)) {
1196 unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
1197 unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
1198 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1199 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1200
1201 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1202 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1203
1204 lvl_width <<= range->baseMipLevel;
1205 lvl_height <<= range->baseMipLevel;
1206
1207 iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
1208 iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
1209 }
1210 }
1211
1212 iview->base_layer = range->baseArrayLayer;
1213 iview->layer_count = radv_get_layerCount(image, range);
1214 iview->base_mip = range->baseMipLevel;
1215 iview->level_count = radv_get_levelCount(image, range);
1216
1217 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1218 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1219 }
1220
1221 bool radv_layout_has_htile(const struct radv_image *image,
1222 VkImageLayout layout,
1223 unsigned queue_mask)
1224 {
1225 if (radv_image_is_tc_compat_htile(image))
1226 return layout != VK_IMAGE_LAYOUT_GENERAL;
1227
1228 return radv_image_has_htile(image) &&
1229 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1230 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1231 queue_mask == (1u << RADV_QUEUE_GENERAL);
1232 }
1233
1234 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1235 VkImageLayout layout,
1236 unsigned queue_mask)
1237 {
1238 if (radv_image_is_tc_compat_htile(image))
1239 return layout != VK_IMAGE_LAYOUT_GENERAL;
1240
1241 return radv_image_has_htile(image) &&
1242 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1243 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1244 queue_mask == (1u << RADV_QUEUE_GENERAL);
1245 }
1246
1247 bool radv_layout_can_fast_clear(const struct radv_image *image,
1248 VkImageLayout layout,
1249 unsigned queue_mask)
1250 {
1251 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1252 queue_mask == (1u << RADV_QUEUE_GENERAL);
1253 }
1254
1255 bool radv_layout_dcc_compressed(const struct radv_image *image,
1256 VkImageLayout layout,
1257 unsigned queue_mask)
1258 {
1259 /* Don't compress compute transfer dst, as image stores are not supported. */
1260 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1261 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1262 return false;
1263
1264 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1265 }
1266
1267
1268 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1269 {
1270 if (!image->exclusive)
1271 return image->queue_family_mask;
1272 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1273 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1274 if (family == VK_QUEUE_FAMILY_IGNORED)
1275 return 1u << queue_family;
1276 return 1u << family;
1277 }
1278
1279 VkResult
1280 radv_CreateImage(VkDevice device,
1281 const VkImageCreateInfo *pCreateInfo,
1282 const VkAllocationCallbacks *pAllocator,
1283 VkImage *pImage)
1284 {
1285 #ifdef ANDROID
1286 const VkNativeBufferANDROID *gralloc_info =
1287 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1288
1289 if (gralloc_info)
1290 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1291 pAllocator, pImage);
1292 #endif
1293
1294 const struct wsi_image_create_info *wsi_info =
1295 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1296 bool scanout = wsi_info && wsi_info->scanout;
1297
1298 return radv_image_create(device,
1299 &(struct radv_image_create_info) {
1300 .vk_info = pCreateInfo,
1301 .scanout = scanout,
1302 },
1303 pAllocator,
1304 pImage);
1305 }
1306
1307 void
1308 radv_DestroyImage(VkDevice _device, VkImage _image,
1309 const VkAllocationCallbacks *pAllocator)
1310 {
1311 RADV_FROM_HANDLE(radv_device, device, _device);
1312 RADV_FROM_HANDLE(radv_image, image, _image);
1313
1314 if (!image)
1315 return;
1316
1317 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1318 device->ws->buffer_destroy(image->bo);
1319
1320 if (image->owned_memory != VK_NULL_HANDLE)
1321 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1322
1323 vk_free2(&device->alloc, pAllocator, image);
1324 }
1325
1326 void radv_GetImageSubresourceLayout(
1327 VkDevice _device,
1328 VkImage _image,
1329 const VkImageSubresource* pSubresource,
1330 VkSubresourceLayout* pLayout)
1331 {
1332 RADV_FROM_HANDLE(radv_image, image, _image);
1333 RADV_FROM_HANDLE(radv_device, device, _device);
1334 int level = pSubresource->mipLevel;
1335 int layer = pSubresource->arrayLayer;
1336 struct radeon_surf *surface = &image->surface;
1337
1338 if (device->physical_device->rad_info.chip_class >= GFX9) {
1339 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1340 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1341 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1342 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1343 pLayout->size = surface->u.gfx9.surf_slice_size;
1344 if (image->type == VK_IMAGE_TYPE_3D)
1345 pLayout->size *= u_minify(image->info.depth, level);
1346 } else {
1347 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1348 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1349 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1350 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1351 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1352 if (image->type == VK_IMAGE_TYPE_3D)
1353 pLayout->size *= u_minify(image->info.depth, level);
1354 }
1355 }
1356
1357
1358 VkResult
1359 radv_CreateImageView(VkDevice _device,
1360 const VkImageViewCreateInfo *pCreateInfo,
1361 const VkAllocationCallbacks *pAllocator,
1362 VkImageView *pView)
1363 {
1364 RADV_FROM_HANDLE(radv_device, device, _device);
1365 struct radv_image_view *view;
1366
1367 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1368 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1369 if (view == NULL)
1370 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1371
1372 radv_image_view_init(view, device, pCreateInfo);
1373
1374 *pView = radv_image_view_to_handle(view);
1375
1376 return VK_SUCCESS;
1377 }
1378
1379 void
1380 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1381 const VkAllocationCallbacks *pAllocator)
1382 {
1383 RADV_FROM_HANDLE(radv_device, device, _device);
1384 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1385
1386 if (!iview)
1387 return;
1388 vk_free2(&device->alloc, pAllocator, iview);
1389 }
1390
1391 void radv_buffer_view_init(struct radv_buffer_view *view,
1392 struct radv_device *device,
1393 const VkBufferViewCreateInfo* pCreateInfo)
1394 {
1395 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1396
1397 view->bo = buffer->bo;
1398 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1399 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1400 view->vk_format = pCreateInfo->format;
1401
1402 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1403 pCreateInfo->offset, view->range, view->state);
1404 }
1405
1406 VkResult
1407 radv_CreateBufferView(VkDevice _device,
1408 const VkBufferViewCreateInfo *pCreateInfo,
1409 const VkAllocationCallbacks *pAllocator,
1410 VkBufferView *pView)
1411 {
1412 RADV_FROM_HANDLE(radv_device, device, _device);
1413 struct radv_buffer_view *view;
1414
1415 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1416 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1417 if (!view)
1418 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1419
1420 radv_buffer_view_init(view, device, pCreateInfo);
1421
1422 *pView = radv_buffer_view_to_handle(view);
1423
1424 return VK_SUCCESS;
1425 }
1426
1427 void
1428 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1429 const VkAllocationCallbacks *pAllocator)
1430 {
1431 RADV_FROM_HANDLE(radv_device, device, _device);
1432 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1433
1434 if (!view)
1435 return;
1436
1437 vk_free2(&device->alloc, pAllocator, view);
1438 }