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15410f140e74bec333a0e7909135464484559a0e
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66 static int
67 radv_init_surface(struct radv_device *device,
68 struct radeon_surf *surface,
69 const struct radv_image_create_info *create_info)
70 {
71 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
72 unsigned array_mode = radv_choose_tiling(device, create_info);
73 const struct vk_format_description *desc =
74 vk_format_description(pCreateInfo->format);
75 bool is_depth, is_stencil, blendable;
76
77 is_depth = vk_format_has_depth(desc);
78 is_stencil = vk_format_has_stencil(desc);
79
80 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
81 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
82
83 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
84 /* align byte per element on dword */
85 if (surface->bpe == 3) {
86 surface->bpe = 4;
87 }
88 surface->flags = RADEON_SURF_SET(array_mode, MODE);
89
90 switch (pCreateInfo->imageType){
91 case VK_IMAGE_TYPE_1D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_2D:
98 if (pCreateInfo->arrayLayers > 1)
99 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
100 else
101 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
102 break;
103 case VK_IMAGE_TYPE_3D:
104 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
105 break;
106 default:
107 unreachable("unhandled image type");
108 }
109
110 if (is_depth) {
111 surface->flags |= RADEON_SURF_ZBUFFER;
112 if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
113 !(pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
114 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR)) &&
115 pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
116 pCreateInfo->mipLevels <= 1 &&
117 device->physical_device->rad_info.chip_class >= VI &&
118 ((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
119 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
120 (device->physical_device->rad_info.chip_class >= GFX9 &&
121 pCreateInfo->format == VK_FORMAT_D16_UNORM)))
122 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
123 }
124
125 if (is_stencil)
126 surface->flags |= RADEON_SURF_SBUFFER;
127
128 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
129
130 bool dcc_compatible_formats = !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
131 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
132 const struct VkImageFormatListCreateInfoKHR *format_list =
133 (const struct VkImageFormatListCreateInfoKHR *)
134 vk_find_struct_const(pCreateInfo->pNext,
135 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
136
137 /* We have to ignore the existence of the list if viewFormatCount = 0 */
138 if (format_list && format_list->viewFormatCount) {
139 /* compatibility is transitive, so we only need to check
140 * one format with everything else. */
141 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
142 if (!radv_dcc_formats_compatible(pCreateInfo->format,
143 format_list->pViewFormats[i]))
144 dcc_compatible_formats = false;
145 }
146 } else {
147 dcc_compatible_formats = false;
148 }
149 }
150
151 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
152 VK_IMAGE_USAGE_STORAGE_BIT)) ||
153 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
154 !dcc_compatible_formats ||
155 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
156 pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
157 device->physical_device->rad_info.chip_class < VI ||
158 create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) ||
159 pCreateInfo->samples >= 2)
160 surface->flags |= RADEON_SURF_DISABLE_DCC;
161 if (create_info->scanout)
162 surface->flags |= RADEON_SURF_SCANOUT;
163 return 0;
164 }
165
166 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
167 {
168 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
169 }
170
171 static inline unsigned
172 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
173 {
174 if (stencil)
175 return image->surface.u.legacy.stencil_tiling_index[level];
176 else
177 return image->surface.u.legacy.tiling_index[level];
178 }
179
180 static unsigned radv_map_swizzle(unsigned swizzle)
181 {
182 switch (swizzle) {
183 case VK_SWIZZLE_Y:
184 return V_008F0C_SQ_SEL_Y;
185 case VK_SWIZZLE_Z:
186 return V_008F0C_SQ_SEL_Z;
187 case VK_SWIZZLE_W:
188 return V_008F0C_SQ_SEL_W;
189 case VK_SWIZZLE_0:
190 return V_008F0C_SQ_SEL_0;
191 case VK_SWIZZLE_1:
192 return V_008F0C_SQ_SEL_1;
193 default: /* VK_SWIZZLE_X */
194 return V_008F0C_SQ_SEL_X;
195 }
196 }
197
198 static void
199 radv_make_buffer_descriptor(struct radv_device *device,
200 struct radv_buffer *buffer,
201 VkFormat vk_format,
202 unsigned offset,
203 unsigned range,
204 uint32_t *state)
205 {
206 const struct vk_format_description *desc;
207 unsigned stride;
208 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
209 uint64_t va = gpu_address + buffer->offset;
210 unsigned num_format, data_format;
211 int first_non_void;
212 desc = vk_format_description(vk_format);
213 first_non_void = vk_format_get_first_non_void_channel(vk_format);
214 stride = desc->block.bits / 8;
215
216 num_format = radv_translate_buffer_numformat(desc, first_non_void);
217 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
218
219 va += offset;
220 state[0] = va;
221 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
222 S_008F04_STRIDE(stride);
223
224 if (device->physical_device->rad_info.chip_class != VI && stride) {
225 range /= stride;
226 }
227
228 state[2] = range;
229 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
230 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
231 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
232 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
233 S_008F0C_NUM_FORMAT(num_format) |
234 S_008F0C_DATA_FORMAT(data_format);
235 }
236
237 static void
238 si_set_mutable_tex_desc_fields(struct radv_device *device,
239 struct radv_image *image,
240 const struct legacy_surf_level *base_level_info,
241 unsigned base_level, unsigned first_level,
242 unsigned block_width, bool is_stencil,
243 uint32_t *state)
244 {
245 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
246 uint64_t va = gpu_address;
247 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
248 uint64_t meta_va = 0;
249 if (chip_class >= GFX9) {
250 if (is_stencil)
251 va += image->surface.u.gfx9.stencil_offset;
252 else
253 va += image->surface.u.gfx9.surf_offset;
254 } else
255 va += base_level_info->offset;
256
257 state[0] = va >> 8;
258 if (chip_class >= GFX9 ||
259 base_level_info->mode == RADEON_SURF_MODE_2D)
260 state[0] |= image->surface.tile_swizzle;
261 state[1] &= C_008F14_BASE_ADDRESS_HI;
262 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
263
264 if (chip_class >= VI) {
265 state[6] &= C_008F28_COMPRESSION_EN;
266 state[7] = 0;
267 if (radv_vi_dcc_enabled(image, first_level)) {
268 meta_va = gpu_address + image->dcc_offset;
269 if (chip_class <= VI)
270 meta_va += base_level_info->dcc_offset;
271 } else if(image->tc_compatible_htile && image->surface.htile_size) {
272 meta_va = gpu_address + image->htile_offset;
273 }
274
275 if (meta_va) {
276 state[6] |= S_008F28_COMPRESSION_EN(1);
277 state[7] = meta_va >> 8;
278 state[7] |= image->surface.tile_swizzle;
279 }
280 }
281
282 if (chip_class >= GFX9) {
283 state[3] &= C_008F1C_SW_MODE;
284 state[4] &= C_008F20_PITCH_GFX9;
285
286 if (is_stencil) {
287 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
288 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
289 } else {
290 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
291 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
292 }
293
294 state[5] &= C_008F24_META_DATA_ADDRESS &
295 C_008F24_META_PIPE_ALIGNED &
296 C_008F24_META_RB_ALIGNED;
297 if (meta_va) {
298 struct gfx9_surf_meta_flags meta;
299
300 if (image->dcc_offset)
301 meta = image->surface.u.gfx9.dcc;
302 else
303 meta = image->surface.u.gfx9.htile;
304
305 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
306 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
307 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
308 }
309 } else {
310 /* SI-CI-VI */
311 unsigned pitch = base_level_info->nblk_x * block_width;
312 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
313
314 state[3] &= C_008F1C_TILING_INDEX;
315 state[3] |= S_008F1C_TILING_INDEX(index);
316 state[4] &= C_008F20_PITCH_GFX6;
317 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
318 }
319 }
320
321 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
322 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
323 {
324 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
325 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
326
327 /* GFX9 allocates 1D textures as 2D. */
328 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
329 image_type = VK_IMAGE_TYPE_2D;
330 switch (image_type) {
331 case VK_IMAGE_TYPE_1D:
332 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
333 case VK_IMAGE_TYPE_2D:
334 if (nr_samples > 1)
335 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
336 else
337 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
338 case VK_IMAGE_TYPE_3D:
339 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
340 return V_008F1C_SQ_RSRC_IMG_3D;
341 else
342 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
343 default:
344 unreachable("illegale image type");
345 }
346 }
347
348 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
349 {
350 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
351
352 if (swizzle[3] == VK_SWIZZLE_X) {
353 /* For the pre-defined border color values (white, opaque
354 * black, transparent black), the only thing that matters is
355 * that the alpha channel winds up in the correct place
356 * (because the RGB channels are all the same) so either of
357 * these enumerations will work.
358 */
359 if (swizzle[2] == VK_SWIZZLE_Y)
360 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
361 else
362 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
363 } else if (swizzle[0] == VK_SWIZZLE_X) {
364 if (swizzle[1] == VK_SWIZZLE_Y)
365 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
366 else
367 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
368 } else if (swizzle[1] == VK_SWIZZLE_X) {
369 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
370 } else if (swizzle[2] == VK_SWIZZLE_X) {
371 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
372 }
373
374 return bc_swizzle;
375 }
376
377 /**
378 * Build the sampler view descriptor for a texture.
379 */
380 static void
381 si_make_texture_descriptor(struct radv_device *device,
382 struct radv_image *image,
383 bool is_storage_image,
384 VkImageViewType view_type,
385 VkFormat vk_format,
386 const VkComponentMapping *mapping,
387 unsigned first_level, unsigned last_level,
388 unsigned first_layer, unsigned last_layer,
389 unsigned width, unsigned height, unsigned depth,
390 uint32_t *state,
391 uint32_t *fmask_state)
392 {
393 const struct vk_format_description *desc;
394 enum vk_swizzle swizzle[4];
395 int first_non_void;
396 unsigned num_format, data_format, type;
397
398 desc = vk_format_description(vk_format);
399
400 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
401 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
402 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
403 } else {
404 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
405 }
406
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408
409 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
410 if (num_format == ~0) {
411 num_format = 0;
412 }
413
414 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
415 if (data_format == ~0) {
416 data_format = 0;
417 }
418
419 /* S8 with Z32 HTILE needs a special format. */
420 if (device->physical_device->rad_info.chip_class >= GFX9 &&
421 vk_format == VK_FORMAT_S8_UINT &&
422 image->tc_compatible_htile)
423 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
424
425 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
426 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
427 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
428 height = 1;
429 depth = image->info.array_size;
430 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
431 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
432 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
433 depth = image->info.array_size;
434 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
435 depth = image->info.array_size / 6;
436
437 state[0] = 0;
438 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
439 S_008F14_NUM_FORMAT_GFX6(num_format));
440 state[2] = (S_008F18_WIDTH(width - 1) |
441 S_008F18_HEIGHT(height - 1) |
442 S_008F18_PERF_MOD(4));
443 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
444 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
445 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
446 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
447 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
448 0 : first_level) |
449 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
450 util_logbase2(image->info.samples) :
451 last_level) |
452 S_008F1C_TYPE(type));
453 state[4] = 0;
454 state[5] = S_008F24_BASE_ARRAY(first_layer);
455 state[6] = 0;
456 state[7] = 0;
457
458 if (device->physical_device->rad_info.chip_class >= GFX9) {
459 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
460
461 /* Depth is the the last accessible layer on Gfx9.
462 * The hw doesn't need to know the total number of layers.
463 */
464 if (type == V_008F1C_SQ_RSRC_IMG_3D)
465 state[4] |= S_008F20_DEPTH(depth - 1);
466 else
467 state[4] |= S_008F20_DEPTH(last_layer);
468
469 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
470 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
471 util_logbase2(image->info.samples) :
472 image->info.levels - 1);
473 } else {
474 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
475 state[4] |= S_008F20_DEPTH(depth - 1);
476 state[5] |= S_008F24_LAST_ARRAY(last_layer);
477 }
478 if (image->dcc_offset) {
479 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
480
481 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
482 } else {
483 /* The last dword is unused by hw. The shader uses it to clear
484 * bits in the first dword of sampler state.
485 */
486 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
487 if (first_level == last_level)
488 state[7] = C_008F30_MAX_ANISO_RATIO;
489 else
490 state[7] = 0xffffffff;
491 }
492 }
493
494 /* Initialize the sampler view for FMASK. */
495 if (image->fmask.size) {
496 uint32_t fmask_format, num_format;
497 uint64_t gpu_address = radv_buffer_get_va(image->bo);
498 uint64_t va;
499
500 va = gpu_address + image->offset + image->fmask.offset;
501
502 if (device->physical_device->rad_info.chip_class >= GFX9) {
503 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
504 switch (image->info.samples) {
505 case 2:
506 num_format = V_008F14_IMG_FMASK_8_2_2;
507 break;
508 case 4:
509 num_format = V_008F14_IMG_FMASK_8_4_4;
510 break;
511 case 8:
512 num_format = V_008F14_IMG_FMASK_32_8_8;
513 break;
514 default:
515 unreachable("invalid nr_samples");
516 }
517 } else {
518 switch (image->info.samples) {
519 case 2:
520 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
521 break;
522 case 4:
523 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
524 break;
525 case 8:
526 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
527 break;
528 default:
529 assert(0);
530 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
531 }
532 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
533 }
534
535 fmask_state[0] = va >> 8;
536 fmask_state[0] |= image->fmask.tile_swizzle;
537 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
538 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
539 S_008F14_NUM_FORMAT_GFX6(num_format);
540 fmask_state[2] = S_008F18_WIDTH(width - 1) |
541 S_008F18_HEIGHT(height - 1);
542 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
543 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
544 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
545 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
546 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
547 fmask_state[4] = 0;
548 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
549 fmask_state[6] = 0;
550 fmask_state[7] = 0;
551
552 if (device->physical_device->rad_info.chip_class >= GFX9) {
553 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
554 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
555 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
556 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
557 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
558 } else {
559 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
560 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
561 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
562 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
563 }
564 } else if (fmask_state)
565 memset(fmask_state, 0, 8 * 4);
566 }
567
568 static void
569 radv_query_opaque_metadata(struct radv_device *device,
570 struct radv_image *image,
571 struct radeon_bo_metadata *md)
572 {
573 static const VkComponentMapping fixedmapping;
574 uint32_t desc[8], i;
575
576 /* Metadata image format format version 1:
577 * [0] = 1 (metadata format identifier)
578 * [1] = (VENDOR_ID << 16) | PCI_ID
579 * [2:9] = image descriptor for the whole resource
580 * [2] is always 0, because the base address is cleared
581 * [9] is the DCC offset bits [39:8] from the beginning of
582 * the buffer
583 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
584 */
585 md->metadata[0] = 1; /* metadata image format version 1 */
586
587 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
588 md->metadata[1] = si_get_bo_metadata_word1(device);
589
590
591 si_make_texture_descriptor(device, image, false,
592 (VkImageViewType)image->type, image->vk_format,
593 &fixedmapping, 0, image->info.levels - 1, 0,
594 image->info.array_size,
595 image->info.width, image->info.height,
596 image->info.depth,
597 desc, NULL);
598
599 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
600 image->surface.blk_w, false, desc);
601
602 /* Clear the base address and set the relative DCC offset. */
603 desc[0] = 0;
604 desc[1] &= C_008F14_BASE_ADDRESS_HI;
605 desc[7] = image->dcc_offset >> 8;
606
607 /* Dwords [2:9] contain the image descriptor. */
608 memcpy(&md->metadata[2], desc, sizeof(desc));
609
610 /* Dwords [10:..] contain the mipmap level offsets. */
611 if (device->physical_device->rad_info.chip_class <= VI) {
612 for (i = 0; i <= image->info.levels - 1; i++)
613 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
614 md->size_metadata = (11 + image->info.levels - 1) * 4;
615 }
616 }
617
618 void
619 radv_init_metadata(struct radv_device *device,
620 struct radv_image *image,
621 struct radeon_bo_metadata *metadata)
622 {
623 struct radeon_surf *surface = &image->surface;
624
625 memset(metadata, 0, sizeof(*metadata));
626
627 if (device->physical_device->rad_info.chip_class >= GFX9) {
628 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
629 } else {
630 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
631 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
632 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
633 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
634 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
635 metadata->u.legacy.bankw = surface->u.legacy.bankw;
636 metadata->u.legacy.bankh = surface->u.legacy.bankh;
637 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
638 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
639 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
640 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
641 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
642 }
643 radv_query_opaque_metadata(device, image, metadata);
644 }
645
646 /* The number of samples can be specified independently of the texture. */
647 static void
648 radv_image_get_fmask_info(struct radv_device *device,
649 struct radv_image *image,
650 unsigned nr_samples,
651 struct radv_fmask_info *out)
652 {
653 /* FMASK is allocated like an ordinary texture. */
654 struct radeon_surf fmask = {};
655 struct ac_surf_info info = image->info;
656 memset(out, 0, sizeof(*out));
657
658 if (device->physical_device->rad_info.chip_class >= GFX9) {
659 out->alignment = image->surface.u.gfx9.fmask_alignment;
660 out->size = image->surface.u.gfx9.fmask_size;
661 return;
662 }
663
664 fmask.blk_w = image->surface.blk_w;
665 fmask.blk_h = image->surface.blk_h;
666 info.samples = 1;
667 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
668
669 if (!image->shareable)
670 info.surf_index = &device->fmask_mrt_offset_counter;
671
672 /* Force 2D tiling if it wasn't set. This may occur when creating
673 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
674 * destination buffer must have an FMASK too. */
675 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
676 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
677
678 switch (nr_samples) {
679 case 2:
680 case 4:
681 fmask.bpe = 1;
682 break;
683 case 8:
684 fmask.bpe = 4;
685 break;
686 default:
687 return;
688 }
689
690 device->ws->surface_init(device->ws, &info, &fmask);
691 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
692
693 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
694 if (out->slice_tile_max)
695 out->slice_tile_max -= 1;
696
697 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
698 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
699 out->bank_height = fmask.u.legacy.bankh;
700 out->tile_swizzle = fmask.tile_swizzle;
701 out->alignment = MAX2(256, fmask.surf_alignment);
702 out->size = fmask.surf_size;
703
704 assert(!out->tile_swizzle || !image->shareable);
705 }
706
707 static void
708 radv_image_alloc_fmask(struct radv_device *device,
709 struct radv_image *image)
710 {
711 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
712
713 image->fmask.offset = align64(image->size, image->fmask.alignment);
714 image->size = image->fmask.offset + image->fmask.size;
715 image->alignment = MAX2(image->alignment, image->fmask.alignment);
716 }
717
718 static void
719 radv_image_get_cmask_info(struct radv_device *device,
720 struct radv_image *image,
721 struct radv_cmask_info *out)
722 {
723 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
724 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
725 unsigned cl_width, cl_height;
726
727 if (device->physical_device->rad_info.chip_class >= GFX9) {
728 out->alignment = image->surface.u.gfx9.cmask_alignment;
729 out->size = image->surface.u.gfx9.cmask_size;
730 return;
731 }
732
733 switch (num_pipes) {
734 case 2:
735 cl_width = 32;
736 cl_height = 16;
737 break;
738 case 4:
739 cl_width = 32;
740 cl_height = 32;
741 break;
742 case 8:
743 cl_width = 64;
744 cl_height = 32;
745 break;
746 case 16: /* Hawaii */
747 cl_width = 64;
748 cl_height = 64;
749 break;
750 default:
751 assert(0);
752 return;
753 }
754
755 unsigned base_align = num_pipes * pipe_interleave_bytes;
756
757 unsigned width = align(image->info.width, cl_width*8);
758 unsigned height = align(image->info.height, cl_height*8);
759 unsigned slice_elements = (width * height) / (8*8);
760
761 /* Each element of CMASK is a nibble. */
762 unsigned slice_bytes = slice_elements / 2;
763
764 out->slice_tile_max = (width * height) / (128*128);
765 if (out->slice_tile_max)
766 out->slice_tile_max -= 1;
767
768 out->alignment = MAX2(256, base_align);
769 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
770 align(slice_bytes, base_align);
771 }
772
773 static void
774 radv_image_alloc_cmask(struct radv_device *device,
775 struct radv_image *image)
776 {
777 uint32_t clear_value_size = 0;
778 radv_image_get_cmask_info(device, image, &image->cmask);
779
780 image->cmask.offset = align64(image->size, image->cmask.alignment);
781 /* + 8 for storing the clear values */
782 if (!image->clear_value_offset) {
783 image->clear_value_offset = image->cmask.offset + image->cmask.size;
784 clear_value_size = 8;
785 }
786 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
787 image->alignment = MAX2(image->alignment, image->cmask.alignment);
788 }
789
790 static void
791 radv_image_alloc_dcc(struct radv_image *image)
792 {
793 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
794 /* + 16 for storing the clear values + dcc pred */
795 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
796 image->dcc_pred_offset = image->clear_value_offset + 8;
797 image->size = image->dcc_offset + image->surface.dcc_size + 16;
798 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
799 }
800
801 static void
802 radv_image_alloc_htile(struct radv_image *image)
803 {
804 image->htile_offset = align64(image->size, image->surface.htile_alignment);
805
806 /* + 8 for storing the clear values */
807 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
808 image->size = image->clear_value_offset + 8;
809 image->alignment = align64(image->alignment, image->surface.htile_alignment);
810 }
811
812 static inline bool
813 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
814 {
815 if (image->info.samples <= 1 &&
816 image->info.width * image->info.height <= 512 * 512) {
817 /* Do not enable CMASK or DCC for small surfaces where the cost
818 * of the eliminate pass can be higher than the benefit of fast
819 * clear. RadeonSI does this, but the image threshold is
820 * different.
821 */
822 return false;
823 }
824
825 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
826 (image->exclusive || image->queue_family_mask == 1);
827 }
828
829 static inline bool
830 radv_image_can_enable_dcc(struct radv_image *image)
831 {
832 return radv_image_can_enable_dcc_or_cmask(image) &&
833 image->surface.dcc_size;
834 }
835
836 static inline bool
837 radv_image_can_enable_cmask(struct radv_image *image)
838 {
839 if (image->surface.bpe > 8 && image->info.samples == 1) {
840 /* Do not enable CMASK for non-MSAA images (fast color clear)
841 * because 128 bit formats are not supported, but FMASK might
842 * still be used.
843 */
844 return false;
845 }
846
847 return radv_image_can_enable_dcc_or_cmask(image) &&
848 image->info.levels == 1 &&
849 image->info.depth == 1 &&
850 !image->surface.is_linear;
851 }
852
853 static inline bool
854 radv_image_can_enable_fmask(struct radv_image *image)
855 {
856 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
857 }
858
859 static inline bool
860 radv_image_can_enable_htile(struct radv_image *image)
861 {
862 return image->info.levels == 1 && vk_format_is_depth(image->vk_format);
863 }
864
865 VkResult
866 radv_image_create(VkDevice _device,
867 const struct radv_image_create_info *create_info,
868 const VkAllocationCallbacks* alloc,
869 VkImage *pImage)
870 {
871 RADV_FROM_HANDLE(radv_device, device, _device);
872 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
873 struct radv_image *image = NULL;
874 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
875
876 radv_assert(pCreateInfo->mipLevels > 0);
877 radv_assert(pCreateInfo->arrayLayers > 0);
878 radv_assert(pCreateInfo->samples > 0);
879 radv_assert(pCreateInfo->extent.width > 0);
880 radv_assert(pCreateInfo->extent.height > 0);
881 radv_assert(pCreateInfo->extent.depth > 0);
882
883 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
884 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
885 if (!image)
886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
887
888 image->type = pCreateInfo->imageType;
889 image->info.width = pCreateInfo->extent.width;
890 image->info.height = pCreateInfo->extent.height;
891 image->info.depth = pCreateInfo->extent.depth;
892 image->info.samples = pCreateInfo->samples;
893 image->info.array_size = pCreateInfo->arrayLayers;
894 image->info.levels = pCreateInfo->mipLevels;
895
896 image->vk_format = pCreateInfo->format;
897 image->tiling = pCreateInfo->tiling;
898 image->usage = pCreateInfo->usage;
899 image->flags = pCreateInfo->flags;
900
901 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
902 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
903 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
904 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
905 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
906 else
907 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
908 }
909
910 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
911 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
912 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
913 image->info.surf_index = &device->image_mrt_offset_counter;
914 }
915
916 radv_init_surface(device, &image->surface, create_info);
917
918 device->ws->surface_init(device->ws, &image->info, &image->surface);
919
920 image->size = image->surface.surf_size;
921 image->alignment = image->surface.surf_alignment;
922
923 /* Try to enable DCC first. */
924 if (radv_image_can_enable_dcc(image)) {
925 radv_image_alloc_dcc(image);
926 } else {
927 /* When DCC cannot be enabled, try CMASK. */
928 image->surface.dcc_size = 0;
929 if (radv_image_can_enable_cmask(image)) {
930 radv_image_alloc_cmask(device, image);
931 }
932 }
933
934 /* Try to enable FMASK for multisampled images. */
935 if (radv_image_can_enable_fmask(image)) {
936 radv_image_alloc_fmask(device, image);
937 } else {
938 /* Otherwise, try to enable HTILE for depth surfaces. */
939 if (radv_image_can_enable_htile(image) &&
940 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
941 radv_image_alloc_htile(image);
942 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
943 } else {
944 image->surface.htile_size = 0;
945 }
946 }
947
948 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
949 image->alignment = MAX2(image->alignment, 4096);
950 image->size = align64(image->size, image->alignment);
951 image->offset = 0;
952
953 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
954 0, RADEON_FLAG_VIRTUAL);
955 if (!image->bo) {
956 vk_free2(&device->alloc, alloc, image);
957 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
958 }
959 }
960
961 *pImage = radv_image_to_handle(image);
962
963 return VK_SUCCESS;
964 }
965
966 static void
967 radv_image_view_make_descriptor(struct radv_image_view *iview,
968 struct radv_device *device,
969 const VkComponentMapping *components,
970 bool is_storage_image)
971 {
972 struct radv_image *image = iview->image;
973 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
974 uint32_t blk_w;
975 uint32_t *descriptor;
976 uint32_t hw_level = 0;
977
978 if (is_storage_image) {
979 descriptor = iview->storage_descriptor;
980 } else {
981 descriptor = iview->descriptor;
982 }
983
984 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
985 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
986
987 if (device->physical_device->rad_info.chip_class >= GFX9)
988 hw_level = iview->base_mip;
989 si_make_texture_descriptor(device, image, is_storage_image,
990 iview->type,
991 iview->vk_format,
992 components,
993 hw_level, hw_level + iview->level_count - 1,
994 iview->base_layer,
995 iview->base_layer + iview->layer_count - 1,
996 iview->extent.width,
997 iview->extent.height,
998 iview->extent.depth,
999 descriptor,
1000 descriptor + 8);
1001
1002 const struct legacy_surf_level *base_level_info = NULL;
1003 if (device->physical_device->rad_info.chip_class <= GFX9) {
1004 if (is_stencil)
1005 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1006 else
1007 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1008 }
1009 si_set_mutable_tex_desc_fields(device, image,
1010 base_level_info,
1011 iview->base_mip,
1012 iview->base_mip,
1013 blk_w, is_stencil, descriptor);
1014 }
1015
1016 void
1017 radv_image_view_init(struct radv_image_view *iview,
1018 struct radv_device *device,
1019 const VkImageViewCreateInfo* pCreateInfo)
1020 {
1021 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1022 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1023
1024 switch (image->type) {
1025 case VK_IMAGE_TYPE_1D:
1026 case VK_IMAGE_TYPE_2D:
1027 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1028 break;
1029 case VK_IMAGE_TYPE_3D:
1030 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1031 <= radv_minify(image->info.depth, range->baseMipLevel));
1032 break;
1033 default:
1034 unreachable("bad VkImageType");
1035 }
1036 iview->image = image;
1037 iview->bo = image->bo;
1038 iview->type = pCreateInfo->viewType;
1039 iview->vk_format = pCreateInfo->format;
1040 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1041
1042 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1043 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1044 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1045 iview->vk_format = vk_format_depth_only(iview->vk_format);
1046 }
1047
1048 if (device->physical_device->rad_info.chip_class >= GFX9) {
1049 iview->extent = (VkExtent3D) {
1050 .width = image->info.width,
1051 .height = image->info.height,
1052 .depth = image->info.depth,
1053 };
1054 } else {
1055 iview->extent = (VkExtent3D) {
1056 .width = radv_minify(image->info.width , range->baseMipLevel),
1057 .height = radv_minify(image->info.height, range->baseMipLevel),
1058 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1059 };
1060 }
1061
1062 if (iview->vk_format != image->vk_format) {
1063 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
1064 vk_format_get_blockwidth(image->vk_format));
1065 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
1066 vk_format_get_blockheight(image->vk_format));
1067 }
1068
1069 iview->base_layer = range->baseArrayLayer;
1070 iview->layer_count = radv_get_layerCount(image, range);
1071 iview->base_mip = range->baseMipLevel;
1072 iview->level_count = radv_get_levelCount(image, range);
1073
1074 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1075 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1076 }
1077
1078 bool radv_layout_has_htile(const struct radv_image *image,
1079 VkImageLayout layout,
1080 unsigned queue_mask)
1081 {
1082 if (image->surface.htile_size && image->tc_compatible_htile)
1083 return layout != VK_IMAGE_LAYOUT_GENERAL;
1084
1085 return image->surface.htile_size &&
1086 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1087 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1088 queue_mask == (1u << RADV_QUEUE_GENERAL);
1089 }
1090
1091 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1092 VkImageLayout layout,
1093 unsigned queue_mask)
1094 {
1095 if (image->surface.htile_size && image->tc_compatible_htile)
1096 return layout != VK_IMAGE_LAYOUT_GENERAL;
1097
1098 return image->surface.htile_size &&
1099 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1100 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1101 queue_mask == (1u << RADV_QUEUE_GENERAL);
1102 }
1103
1104 bool radv_layout_can_fast_clear(const struct radv_image *image,
1105 VkImageLayout layout,
1106 unsigned queue_mask)
1107 {
1108 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1109 queue_mask == (1u << RADV_QUEUE_GENERAL);
1110 }
1111
1112
1113 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1114 {
1115 if (!image->exclusive)
1116 return image->queue_family_mask;
1117 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1118 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1119 if (family == VK_QUEUE_FAMILY_IGNORED)
1120 return 1u << queue_family;
1121 return 1u << family;
1122 }
1123
1124 VkResult
1125 radv_CreateImage(VkDevice device,
1126 const VkImageCreateInfo *pCreateInfo,
1127 const VkAllocationCallbacks *pAllocator,
1128 VkImage *pImage)
1129 {
1130 const struct wsi_image_create_info *wsi_info =
1131 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1132 bool scanout = wsi_info && wsi_info->scanout;
1133
1134 return radv_image_create(device,
1135 &(struct radv_image_create_info) {
1136 .vk_info = pCreateInfo,
1137 .scanout = scanout,
1138 },
1139 pAllocator,
1140 pImage);
1141 }
1142
1143 void
1144 radv_DestroyImage(VkDevice _device, VkImage _image,
1145 const VkAllocationCallbacks *pAllocator)
1146 {
1147 RADV_FROM_HANDLE(radv_device, device, _device);
1148 RADV_FROM_HANDLE(radv_image, image, _image);
1149
1150 if (!image)
1151 return;
1152
1153 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1154 device->ws->buffer_destroy(image->bo);
1155
1156 vk_free2(&device->alloc, pAllocator, image);
1157 }
1158
1159 void radv_GetImageSubresourceLayout(
1160 VkDevice _device,
1161 VkImage _image,
1162 const VkImageSubresource* pSubresource,
1163 VkSubresourceLayout* pLayout)
1164 {
1165 RADV_FROM_HANDLE(radv_image, image, _image);
1166 RADV_FROM_HANDLE(radv_device, device, _device);
1167 int level = pSubresource->mipLevel;
1168 int layer = pSubresource->arrayLayer;
1169 struct radeon_surf *surface = &image->surface;
1170
1171 if (device->physical_device->rad_info.chip_class >= GFX9) {
1172 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1173 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1174 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1175 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1176 pLayout->size = surface->u.gfx9.surf_slice_size;
1177 if (image->type == VK_IMAGE_TYPE_3D)
1178 pLayout->size *= u_minify(image->info.depth, level);
1179 } else {
1180 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1181 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1182 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1183 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1184 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1185 if (image->type == VK_IMAGE_TYPE_3D)
1186 pLayout->size *= u_minify(image->info.depth, level);
1187 }
1188 }
1189
1190
1191 VkResult
1192 radv_CreateImageView(VkDevice _device,
1193 const VkImageViewCreateInfo *pCreateInfo,
1194 const VkAllocationCallbacks *pAllocator,
1195 VkImageView *pView)
1196 {
1197 RADV_FROM_HANDLE(radv_device, device, _device);
1198 struct radv_image_view *view;
1199
1200 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1201 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1202 if (view == NULL)
1203 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1204
1205 radv_image_view_init(view, device, pCreateInfo);
1206
1207 *pView = radv_image_view_to_handle(view);
1208
1209 return VK_SUCCESS;
1210 }
1211
1212 void
1213 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1214 const VkAllocationCallbacks *pAllocator)
1215 {
1216 RADV_FROM_HANDLE(radv_device, device, _device);
1217 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1218
1219 if (!iview)
1220 return;
1221 vk_free2(&device->alloc, pAllocator, iview);
1222 }
1223
1224 void radv_buffer_view_init(struct radv_buffer_view *view,
1225 struct radv_device *device,
1226 const VkBufferViewCreateInfo* pCreateInfo)
1227 {
1228 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1229
1230 view->bo = buffer->bo;
1231 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1232 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1233 view->vk_format = pCreateInfo->format;
1234
1235 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1236 pCreateInfo->offset, view->range, view->state);
1237 }
1238
1239 VkResult
1240 radv_CreateBufferView(VkDevice _device,
1241 const VkBufferViewCreateInfo *pCreateInfo,
1242 const VkAllocationCallbacks *pAllocator,
1243 VkBufferView *pView)
1244 {
1245 RADV_FROM_HANDLE(radv_device, device, _device);
1246 struct radv_buffer_view *view;
1247
1248 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1249 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1250 if (!view)
1251 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1252
1253 radv_buffer_view_init(view, device, pCreateInfo);
1254
1255 *pView = radv_buffer_view_to_handle(view);
1256
1257 return VK_SUCCESS;
1258 }
1259
1260 void
1261 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1262 const VkAllocationCallbacks *pAllocator)
1263 {
1264 RADV_FROM_HANDLE(radv_device, device, _device);
1265 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1266
1267 if (!view)
1268 return;
1269
1270 vk_free2(&device->alloc, pAllocator, view);
1271 }