2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
32 #include "util/debug.h"
34 radv_choose_tiling(struct radv_device
*Device
,
35 const struct radv_image_create_info
*create_info
)
37 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
39 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
40 assert(pCreateInfo
->samples
<= 1);
41 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
44 /* Textures with a very small height are recommended to be linear. */
45 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
46 /* Only very thin and long 2D textures should benefit from
48 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
49 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
51 /* MSAA resources must be 2D tiled. */
52 if (pCreateInfo
->samples
> 1)
53 return RADEON_SURF_MODE_2D
;
55 return RADEON_SURF_MODE_2D
;
58 radv_init_surface(struct radv_device
*device
,
59 struct radeon_surf
*surface
,
60 const struct radv_image_create_info
*create_info
)
62 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
63 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
64 const struct vk_format_description
*desc
=
65 vk_format_description(pCreateInfo
->format
);
66 bool is_depth
, is_stencil
, blendable
;
68 is_depth
= vk_format_has_depth(desc
);
69 is_stencil
= vk_format_has_stencil(desc
);
70 surface
->npix_x
= pCreateInfo
->extent
.width
;
71 surface
->npix_y
= pCreateInfo
->extent
.height
;
72 surface
->npix_z
= pCreateInfo
->extent
.depth
;
74 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
75 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
77 surface
->array_size
= pCreateInfo
->arrayLayers
;
78 surface
->last_level
= pCreateInfo
->mipLevels
- 1;
80 surface
->bpe
= vk_format_get_blocksize(pCreateInfo
->format
);
81 /* align byte per element on dword */
82 if (surface
->bpe
== 3) {
85 surface
->nsamples
= pCreateInfo
->samples
? pCreateInfo
->samples
: 1;
86 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
88 switch (pCreateInfo
->imageType
){
89 case VK_IMAGE_TYPE_1D
:
90 if (pCreateInfo
->arrayLayers
> 1)
91 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
93 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
95 case VK_IMAGE_TYPE_2D
:
96 if (pCreateInfo
->arrayLayers
> 1)
97 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
99 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
101 case VK_IMAGE_TYPE_3D
:
102 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
105 unreachable("unhandled image type");
109 surface
->flags
|= RADEON_SURF_ZBUFFER
;
113 surface
->flags
|= RADEON_SURF_SBUFFER
|
114 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
116 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
118 if ((pCreateInfo
->usage
& (VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
119 VK_IMAGE_USAGE_STORAGE_BIT
)) ||
120 (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) ||
121 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
122 device
->physical_device
->rad_info
.chip_class
< VI
||
123 create_info
->scanout
|| (device
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
124 !radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
))
125 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
126 if (create_info
->scanout
)
127 surface
->flags
|= RADEON_SURF_SCANOUT
;
130 #define ATI_VENDOR_ID 0x1002
131 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
133 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
136 static inline unsigned
137 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
140 return image
->surface
.stencil_tiling_index
[level
];
142 return image
->surface
.tiling_index
[level
];
145 static unsigned radv_map_swizzle(unsigned swizzle
)
149 return V_008F0C_SQ_SEL_Y
;
151 return V_008F0C_SQ_SEL_Z
;
153 return V_008F0C_SQ_SEL_W
;
155 return V_008F0C_SQ_SEL_0
;
157 return V_008F0C_SQ_SEL_1
;
158 default: /* VK_SWIZZLE_X */
159 return V_008F0C_SQ_SEL_X
;
164 radv_make_buffer_descriptor(struct radv_device
*device
,
165 struct radv_buffer
*buffer
,
171 const struct vk_format_description
*desc
;
173 uint64_t gpu_address
= device
->ws
->buffer_get_va(buffer
->bo
);
174 uint64_t va
= gpu_address
+ buffer
->offset
;
175 unsigned num_format
, data_format
;
177 desc
= vk_format_description(vk_format
);
178 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
179 stride
= desc
->block
.bits
/ 8;
181 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
182 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
186 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
187 S_008F04_STRIDE(stride
);
189 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
190 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
191 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
192 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
193 S_008F0C_NUM_FORMAT(num_format
) |
194 S_008F0C_DATA_FORMAT(data_format
);
198 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
199 struct radv_image
*image
,
200 const struct radeon_surf_level
*base_level_info
,
201 unsigned base_level
, unsigned first_level
,
202 unsigned block_width
, bool is_stencil
,
205 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
) + image
->offset
;
206 uint64_t va
= gpu_address
+ base_level_info
->offset
;
207 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
209 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
210 state
[3] &= C_008F1C_TILING_INDEX
;
211 state
[4] &= C_008F20_PITCH_GFX6
;
212 state
[6] &= C_008F28_COMPRESSION_EN
;
217 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
218 state
[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image
, base_level
,
220 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
222 if (image
->surface
.dcc_size
&& image
->surface
.level
[first_level
].dcc_enabled
) {
223 state
[6] |= S_008F28_COMPRESSION_EN(1);
224 state
[7] = (gpu_address
+
226 base_level_info
->dcc_offset
) >> 8;
230 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
231 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
)
233 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
234 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
235 switch (image_type
) {
236 case VK_IMAGE_TYPE_1D
:
237 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
238 case VK_IMAGE_TYPE_2D
:
240 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
242 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
243 case VK_IMAGE_TYPE_3D
:
244 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
245 return V_008F1C_SQ_RSRC_IMG_3D
;
247 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
249 unreachable("illegale image type");
253 * Build the sampler view descriptor for a texture.
256 si_make_texture_descriptor(struct radv_device
*device
,
257 struct radv_image
*image
,
259 VkImageViewType view_type
,
261 const VkComponentMapping
*mapping
,
262 unsigned first_level
, unsigned last_level
,
263 unsigned first_layer
, unsigned last_layer
,
264 unsigned width
, unsigned height
, unsigned depth
,
266 uint32_t *fmask_state
)
268 const struct vk_format_description
*desc
;
269 enum vk_swizzle swizzle
[4];
271 unsigned num_format
, data_format
, type
;
273 desc
= vk_format_description(vk_format
);
275 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
276 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
277 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
279 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
282 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
284 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
285 if (num_format
== ~0) {
289 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
290 if (data_format
== ~0) {
294 type
= radv_tex_dim(image
->type
, view_type
, image
->array_size
, image
->samples
,
295 (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
296 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
298 depth
= image
->array_size
;
299 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
300 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
301 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
302 depth
= image
->array_size
;
303 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
304 depth
= image
->array_size
/ 6;
307 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
308 S_008F14_NUM_FORMAT_GFX6(num_format
));
309 state
[2] = (S_008F18_WIDTH(width
- 1) |
310 S_008F18_HEIGHT(height
- 1));
311 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
312 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
313 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
314 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
315 S_008F1C_BASE_LEVEL(image
->samples
> 1 ?
317 S_008F1C_LAST_LEVEL(image
->samples
> 1 ?
318 util_logbase2(image
->samples
) :
320 S_008F1C_POW2_PAD(image
->levels
> 1) |
321 S_008F1C_TYPE(type
));
322 state
[4] = S_008F20_DEPTH(depth
- 1);
323 state
[5] = (S_008F24_BASE_ARRAY(first_layer
) |
324 S_008F24_LAST_ARRAY(last_layer
));
328 if (image
->dcc_offset
) {
329 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
331 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
333 /* The last dword is unused by hw. The shader uses it to clear
334 * bits in the first dword of sampler state.
336 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->samples
<= 1) {
337 if (first_level
== last_level
)
338 state
[7] = C_008F30_MAX_ANISO_RATIO
;
340 state
[7] = 0xffffffff;
344 /* Initialize the sampler view for FMASK. */
345 if (image
->fmask
.size
) {
346 uint32_t fmask_format
;
347 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
);
350 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
352 switch (image
->samples
) {
354 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
357 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
360 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
364 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
367 fmask_state
[0] = va
>> 8;
368 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
369 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
370 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_UINT
);
371 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
372 S_008F18_HEIGHT(height
- 1);
373 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
374 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
375 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
376 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
377 S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
) |
378 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false));
379 fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
380 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
381 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
) |
382 S_008F24_LAST_ARRAY(last_layer
);
389 radv_query_opaque_metadata(struct radv_device
*device
,
390 struct radv_image
*image
,
391 struct radeon_bo_metadata
*md
)
393 static const VkComponentMapping fixedmapping
;
396 /* Metadata image format format version 1:
397 * [0] = 1 (metadata format identifier)
398 * [1] = (VENDOR_ID << 16) | PCI_ID
399 * [2:9] = image descriptor for the whole resource
400 * [2] is always 0, because the base address is cleared
401 * [9] is the DCC offset bits [39:8] from the beginning of
403 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
405 md
->metadata
[0] = 1; /* metadata image format version 1 */
407 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
408 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
411 si_make_texture_descriptor(device
, image
, true,
412 (VkImageViewType
)image
->type
, image
->vk_format
,
413 &fixedmapping
, 0, image
->levels
- 1, 0,
415 image
->extent
.width
, image
->extent
.height
,
419 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.level
[0], 0, 0,
420 image
->surface
.blk_w
, false, desc
);
422 /* Clear the base address and set the relative DCC offset. */
424 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
425 desc
[7] = image
->dcc_offset
>> 8;
427 /* Dwords [2:9] contain the image descriptor. */
428 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
430 /* Dwords [10:..] contain the mipmap level offsets. */
431 for (i
= 0; i
<= image
->levels
- 1; i
++)
432 md
->metadata
[10+i
] = image
->surface
.level
[i
].offset
>> 8;
434 md
->size_metadata
= (11 + image
->levels
- 1) * 4;
438 radv_init_metadata(struct radv_device
*device
,
439 struct radv_image
*image
,
440 struct radeon_bo_metadata
*metadata
)
442 struct radeon_surf
*surface
= &image
->surface
;
444 memset(metadata
, 0, sizeof(*metadata
));
445 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
446 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
447 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
448 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
449 metadata
->pipe_config
= surface
->pipe_config
;
450 metadata
->bankw
= surface
->bankw
;
451 metadata
->bankh
= surface
->bankh
;
452 metadata
->tile_split
= surface
->tile_split
;
453 metadata
->mtilea
= surface
->mtilea
;
454 metadata
->num_banks
= surface
->num_banks
;
455 metadata
->stride
= surface
->level
[0].pitch_bytes
;
456 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
458 radv_query_opaque_metadata(device
, image
, metadata
);
461 /* The number of samples can be specified independently of the texture. */
463 radv_image_get_fmask_info(struct radv_device
*device
,
464 struct radv_image
*image
,
466 struct radv_fmask_info
*out
)
468 /* FMASK is allocated like an ordinary texture. */
469 struct radeon_surf fmask
= image
->surface
;
471 memset(out
, 0, sizeof(*out
));
473 fmask
.bo_alignment
= 0;
476 fmask
.flags
|= RADEON_SURF_FMASK
;
478 /* Force 2D tiling if it wasn't set. This may occur when creating
479 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
480 * destination buffer must have an FMASK too. */
481 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
482 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
484 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
486 switch (nr_samples
) {
498 device
->ws
->surface_init(device
->ws
, &fmask
);
499 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
501 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
502 if (out
->slice_tile_max
)
503 out
->slice_tile_max
-= 1;
505 out
->tile_mode_index
= fmask
.tiling_index
[0];
506 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
507 out
->bank_height
= fmask
.bankh
;
508 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
509 out
->size
= fmask
.bo_size
;
513 radv_image_alloc_fmask(struct radv_device
*device
,
514 struct radv_image
*image
)
516 radv_image_get_fmask_info(device
, image
, image
->samples
, &image
->fmask
);
518 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
519 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
520 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
524 radv_image_get_cmask_info(struct radv_device
*device
,
525 struct radv_image
*image
,
526 struct radv_cmask_info
*out
)
528 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
529 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
530 unsigned cl_width
, cl_height
;
545 case 16: /* Hawaii */
554 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
556 unsigned width
= align(image
->surface
.npix_x
, cl_width
*8);
557 unsigned height
= align(image
->surface
.npix_y
, cl_height
*8);
558 unsigned slice_elements
= (width
* height
) / (8*8);
560 /* Each element of CMASK is a nibble. */
561 unsigned slice_bytes
= slice_elements
/ 2;
563 out
->slice_tile_max
= (width
* height
) / (128*128);
564 if (out
->slice_tile_max
)
565 out
->slice_tile_max
-= 1;
567 out
->alignment
= MAX2(256, base_align
);
568 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->extent
.depth
: image
->array_size
) *
569 align(slice_bytes
, base_align
);
573 radv_image_alloc_cmask(struct radv_device
*device
,
574 struct radv_image
*image
)
576 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
578 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
579 /* + 8 for storing the clear values */
580 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
581 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ 8;
582 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
586 radv_image_alloc_dcc(struct radv_device
*device
,
587 struct radv_image
*image
)
589 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
590 /* + 8 for storing the clear values */
591 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
592 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 8;
593 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
597 radv_image_alloc_htile(struct radv_device
*device
,
598 struct radv_image
*image
)
600 if ((device
->debug_flags
& RADV_DEBUG_NO_HIZ
) || image
->levels
> 1) {
601 image
->surface
.htile_size
= 0;
605 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
607 /* + 8 for storing the clear values */
608 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
609 image
->size
= image
->clear_value_offset
+ 8;
610 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
614 radv_image_create(VkDevice _device
,
615 const struct radv_image_create_info
*create_info
,
616 const VkAllocationCallbacks
* alloc
,
619 RADV_FROM_HANDLE(radv_device
, device
, _device
);
620 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
621 struct radv_image
*image
= NULL
;
622 bool can_cmask_dcc
= false;
623 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
625 radv_assert(pCreateInfo
->mipLevels
> 0);
626 radv_assert(pCreateInfo
->arrayLayers
> 0);
627 radv_assert(pCreateInfo
->samples
> 0);
628 radv_assert(pCreateInfo
->extent
.width
> 0);
629 radv_assert(pCreateInfo
->extent
.height
> 0);
630 radv_assert(pCreateInfo
->extent
.depth
> 0);
632 image
= vk_alloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
633 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
635 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
637 memset(image
, 0, sizeof(*image
));
638 image
->type
= pCreateInfo
->imageType
;
639 image
->extent
= pCreateInfo
->extent
;
640 image
->vk_format
= pCreateInfo
->format
;
641 image
->levels
= pCreateInfo
->mipLevels
;
642 image
->array_size
= pCreateInfo
->arrayLayers
;
643 image
->samples
= pCreateInfo
->samples
;
644 image
->tiling
= pCreateInfo
->tiling
;
645 image
->usage
= pCreateInfo
->usage
;
646 image
->flags
= pCreateInfo
->flags
;
648 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
649 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
650 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
651 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
654 radv_init_surface(device
, &image
->surface
, create_info
);
656 device
->ws
->surface_init(device
->ws
, &image
->surface
);
658 image
->size
= image
->surface
.bo_size
;
659 image
->alignment
= image
->surface
.bo_alignment
;
661 if (image
->exclusive
|| image
->queue_family_mask
== 1)
662 can_cmask_dcc
= true;
664 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
665 image
->surface
.dcc_size
&& can_cmask_dcc
)
666 radv_image_alloc_dcc(device
, image
);
668 image
->surface
.dcc_size
= 0;
670 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
671 pCreateInfo
->mipLevels
== 1 &&
672 !image
->surface
.dcc_size
&& image
->extent
.depth
== 1 && can_cmask_dcc
)
673 radv_image_alloc_cmask(device
, image
);
674 if (image
->samples
> 1 && vk_format_is_color(pCreateInfo
->format
)) {
675 radv_image_alloc_fmask(device
, image
);
676 } else if (vk_format_is_depth(pCreateInfo
->format
)) {
678 radv_image_alloc_htile(device
, image
);
682 if (create_info
->stride
&& create_info
->stride
!= image
->surface
.level
[0].pitch_bytes
) {
683 image
->surface
.level
[0].nblk_x
= create_info
->stride
/ image
->surface
.bpe
;
684 image
->surface
.level
[0].pitch_bytes
= create_info
->stride
;
685 image
->surface
.level
[0].slice_size
= create_info
->stride
* image
->surface
.level
[0].nblk_y
;
688 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
689 image
->alignment
= MAX2(image
->alignment
, 4096);
690 image
->size
= align64(image
->size
, image
->alignment
);
693 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
694 0, RADEON_FLAG_VIRTUAL
);
696 vk_free2(&device
->alloc
, alloc
, image
);
697 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
701 *pImage
= radv_image_to_handle(image
);
707 radv_image_view_init(struct radv_image_view
*iview
,
708 struct radv_device
*device
,
709 const VkImageViewCreateInfo
* pCreateInfo
,
710 struct radv_cmd_buffer
*cmd_buffer
,
711 VkImageUsageFlags usage_mask
)
713 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
714 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
716 bool is_stencil
= false;
717 switch (image
->type
) {
718 case VK_IMAGE_TYPE_1D
:
719 case VK_IMAGE_TYPE_2D
:
720 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
722 case VK_IMAGE_TYPE_3D
:
723 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
724 <= radv_minify(image
->extent
.depth
, range
->baseMipLevel
));
727 unreachable("bad VkImageType");
729 iview
->image
= image
;
730 iview
->bo
= image
->bo
;
731 iview
->type
= pCreateInfo
->viewType
;
732 iview
->vk_format
= pCreateInfo
->format
;
733 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
735 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
737 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
738 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
739 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
742 iview
->extent
= (VkExtent3D
) {
743 .width
= radv_minify(image
->extent
.width
, range
->baseMipLevel
),
744 .height
= radv_minify(image
->extent
.height
, range
->baseMipLevel
),
745 .depth
= radv_minify(image
->extent
.depth
, range
->baseMipLevel
),
748 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
749 vk_format_get_blockwidth(image
->vk_format
));
750 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
751 vk_format_get_blockheight(image
->vk_format
));
753 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
754 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
755 iview
->base_layer
= range
->baseArrayLayer
;
756 iview
->layer_count
= radv_get_layerCount(image
, range
);
757 iview
->base_mip
= range
->baseMipLevel
;
759 si_make_texture_descriptor(device
, image
, false,
762 &pCreateInfo
->components
,
763 0, radv_get_levelCount(image
, range
) - 1,
764 range
->baseArrayLayer
,
765 range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1,
767 iview
->extent
.height
,
770 iview
->fmask_descriptor
);
771 si_set_mutable_tex_desc_fields(device
, image
,
772 is_stencil
? &image
->surface
.stencil_level
[range
->baseMipLevel
] : &image
->surface
.level
[range
->baseMipLevel
], range
->baseMipLevel
,
774 blk_w
, is_stencil
, iview
->descriptor
);
777 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
778 struct radv_image
*image
, uint32_t micro_tile_mode
)
780 /* These magic numbers were copied from addrlib. It doesn't use any
781 * definitions for them either. They are all 2D_TILED_THIN1 modes with
782 * different bpp and micro tile mode.
784 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
785 switch (micro_tile_mode
) {
786 case 0: /* displayable */
787 image
->surface
.tiling_index
[0] = 10;
790 image
->surface
.tiling_index
[0] = 14;
792 case 3: /* rotated */
793 image
->surface
.tiling_index
[0] = 28;
795 default: /* depth, thick */
796 assert(!"unexpected micro mode");
800 switch (micro_tile_mode
) {
801 case 0: /* displayable */
802 switch (image
->surface
.bpe
) {
804 image
->surface
.tiling_index
[0] = 10;
807 image
->surface
.tiling_index
[0] = 11;
810 image
->surface
.tiling_index
[0] = 12;
815 switch (image
->surface
.bpe
) {
817 image
->surface
.tiling_index
[0] = 14;
820 image
->surface
.tiling_index
[0] = 15;
823 image
->surface
.tiling_index
[0] = 16;
826 image
->surface
.tiling_index
[0] = 17;
830 default: /* depth, thick */
831 assert(!"unexpected micro mode");
836 image
->surface
.micro_tile_mode
= micro_tile_mode
;
839 bool radv_layout_has_htile(const struct radv_image
*image
,
840 VkImageLayout layout
)
842 return (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
843 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
846 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
847 VkImageLayout layout
)
849 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
;
852 bool radv_layout_can_expclear(const struct radv_image
*image
,
853 VkImageLayout layout
)
855 return (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
856 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
859 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
860 VkImageLayout layout
,
863 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
864 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
868 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
870 if (!image
->exclusive
)
871 return image
->queue_family_mask
;
872 if (family
== VK_QUEUE_FAMILY_IGNORED
)
873 return 1u << queue_family
;
878 radv_CreateImage(VkDevice device
,
879 const VkImageCreateInfo
*pCreateInfo
,
880 const VkAllocationCallbacks
*pAllocator
,
883 return radv_image_create(device
,
884 &(struct radv_image_create_info
) {
885 .vk_info
= pCreateInfo
,
893 radv_DestroyImage(VkDevice _device
, VkImage _image
,
894 const VkAllocationCallbacks
*pAllocator
)
896 RADV_FROM_HANDLE(radv_device
, device
, _device
);
897 RADV_FROM_HANDLE(radv_image
, image
, _image
);
902 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
903 device
->ws
->buffer_destroy(image
->bo
);
905 vk_free2(&device
->alloc
, pAllocator
, image
);
908 void radv_GetImageSubresourceLayout(
911 const VkImageSubresource
* pSubresource
,
912 VkSubresourceLayout
* pLayout
)
914 RADV_FROM_HANDLE(radv_image
, image
, _image
);
915 int level
= pSubresource
->mipLevel
;
916 int layer
= pSubresource
->arrayLayer
;
918 pLayout
->offset
= image
->surface
.level
[level
].offset
+ image
->surface
.level
[level
].slice_size
* layer
;
919 pLayout
->rowPitch
= image
->surface
.level
[level
].pitch_bytes
;
920 pLayout
->arrayPitch
= image
->surface
.level
[level
].slice_size
;
921 pLayout
->depthPitch
= image
->surface
.level
[level
].slice_size
;
922 pLayout
->size
= image
->surface
.level
[level
].slice_size
;
923 if (image
->type
== VK_IMAGE_TYPE_3D
)
924 pLayout
->size
*= image
->surface
.level
[level
].nblk_z
;
929 radv_CreateImageView(VkDevice _device
,
930 const VkImageViewCreateInfo
*pCreateInfo
,
931 const VkAllocationCallbacks
*pAllocator
,
934 RADV_FROM_HANDLE(radv_device
, device
, _device
);
935 struct radv_image_view
*view
;
937 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
938 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
940 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
942 radv_image_view_init(view
, device
, pCreateInfo
, NULL
, ~0);
944 *pView
= radv_image_view_to_handle(view
);
950 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
951 const VkAllocationCallbacks
*pAllocator
)
953 RADV_FROM_HANDLE(radv_device
, device
, _device
);
954 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
958 vk_free2(&device
->alloc
, pAllocator
, iview
);
961 void radv_buffer_view_init(struct radv_buffer_view
*view
,
962 struct radv_device
*device
,
963 const VkBufferViewCreateInfo
* pCreateInfo
,
964 struct radv_cmd_buffer
*cmd_buffer
)
966 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
968 view
->bo
= buffer
->bo
;
969 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
970 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
971 view
->vk_format
= pCreateInfo
->format
;
973 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
974 pCreateInfo
->offset
, view
->range
, view
->state
);
978 radv_CreateBufferView(VkDevice _device
,
979 const VkBufferViewCreateInfo
*pCreateInfo
,
980 const VkAllocationCallbacks
*pAllocator
,
983 RADV_FROM_HANDLE(radv_device
, device
, _device
);
984 struct radv_buffer_view
*view
;
986 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
987 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
989 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
991 radv_buffer_view_init(view
, device
, pCreateInfo
, NULL
);
993 *pView
= radv_buffer_view_to_handle(view
);
999 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1000 const VkAllocationCallbacks
*pAllocator
)
1002 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1003 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1008 vk_free2(&device
->alloc
, pAllocator
, view
);