2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
32 #include "util/debug.h"
34 radv_choose_tiling(struct radv_device
*Device
,
35 const struct radv_image_create_info
*create_info
)
37 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
39 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
40 assert(pCreateInfo
->samples
<= 1);
41 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
44 /* MSAA resources must be 2D tiled. */
45 if (pCreateInfo
->samples
> 1)
46 return RADEON_SURF_MODE_2D
;
48 return RADEON_SURF_MODE_2D
;
51 radv_init_surface(struct radv_device
*device
,
52 struct radeon_surf
*surface
,
53 const struct radv_image_create_info
*create_info
)
55 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
56 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
57 const struct vk_format_description
*desc
=
58 vk_format_description(pCreateInfo
->format
);
59 bool is_depth
, is_stencil
, blendable
;
61 is_depth
= vk_format_has_depth(desc
);
62 is_stencil
= vk_format_has_stencil(desc
);
63 surface
->npix_x
= pCreateInfo
->extent
.width
;
64 surface
->npix_y
= pCreateInfo
->extent
.height
;
65 surface
->npix_z
= pCreateInfo
->extent
.depth
;
67 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
68 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
70 surface
->array_size
= pCreateInfo
->arrayLayers
;
71 surface
->last_level
= pCreateInfo
->mipLevels
- 1;
73 surface
->bpe
= vk_format_get_blocksize(pCreateInfo
->format
);
74 /* align byte per element on dword */
75 if (surface
->bpe
== 3) {
78 surface
->nsamples
= pCreateInfo
->samples
? pCreateInfo
->samples
: 1;
79 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
81 switch (pCreateInfo
->imageType
){
82 case VK_IMAGE_TYPE_1D
:
83 if (pCreateInfo
->arrayLayers
> 1)
84 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
86 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
88 case VK_IMAGE_TYPE_2D
:
89 if (pCreateInfo
->arrayLayers
> 1)
90 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
92 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
94 case VK_IMAGE_TYPE_3D
:
95 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
98 unreachable("unhandled image type");
102 surface
->flags
|= RADEON_SURF_ZBUFFER
;
106 surface
->flags
|= RADEON_SURF_SBUFFER
|
107 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
109 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
111 if ((pCreateInfo
->usage
& (VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
112 VK_IMAGE_USAGE_STORAGE_BIT
)) ||
113 (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) ||
114 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
115 device
->physical_device
->rad_info
.chip_class
< VI
||
116 create_info
->scanout
|| (device
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
117 !radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
))
118 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
119 if (create_info
->scanout
)
120 surface
->flags
|= RADEON_SURF_SCANOUT
;
123 #define ATI_VENDOR_ID 0x1002
124 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
126 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
129 static inline unsigned
130 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
133 return image
->surface
.stencil_tiling_index
[level
];
135 return image
->surface
.tiling_index
[level
];
138 static unsigned radv_map_swizzle(unsigned swizzle
)
142 return V_008F0C_SQ_SEL_Y
;
144 return V_008F0C_SQ_SEL_Z
;
146 return V_008F0C_SQ_SEL_W
;
148 return V_008F0C_SQ_SEL_0
;
150 return V_008F0C_SQ_SEL_1
;
151 default: /* VK_SWIZZLE_X */
152 return V_008F0C_SQ_SEL_X
;
157 radv_make_buffer_descriptor(struct radv_device
*device
,
158 struct radv_buffer
*buffer
,
164 const struct vk_format_description
*desc
;
166 uint64_t gpu_address
= device
->ws
->buffer_get_va(buffer
->bo
);
167 uint64_t va
= gpu_address
+ buffer
->offset
;
168 unsigned num_format
, data_format
;
170 desc
= vk_format_description(vk_format
);
171 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
172 stride
= desc
->block
.bits
/ 8;
174 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
175 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
179 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
180 S_008F04_STRIDE(stride
);
182 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
183 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
184 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
185 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
186 S_008F0C_NUM_FORMAT(num_format
) |
187 S_008F0C_DATA_FORMAT(data_format
);
191 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
192 struct radv_image
*image
,
193 const struct radeon_surf_level
*base_level_info
,
194 unsigned base_level
, unsigned first_level
,
195 unsigned block_width
, bool is_stencil
,
198 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
) + image
->offset
;
199 uint64_t va
= gpu_address
+ base_level_info
->offset
;
200 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
202 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
203 state
[3] &= C_008F1C_TILING_INDEX
;
204 state
[4] &= C_008F20_PITCH
;
205 state
[6] &= C_008F28_COMPRESSION_EN
;
210 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
211 state
[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image
, base_level
,
213 state
[4] |= S_008F20_PITCH(pitch
- 1);
215 if (image
->surface
.dcc_size
&& image
->surface
.level
[first_level
].dcc_enabled
) {
216 state
[6] |= S_008F28_COMPRESSION_EN(1);
217 state
[7] = (gpu_address
+
219 base_level_info
->dcc_offset
) >> 8;
223 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
224 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
)
226 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
227 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
228 switch (image_type
) {
229 case VK_IMAGE_TYPE_1D
:
230 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
231 case VK_IMAGE_TYPE_2D
:
233 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
235 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
236 case VK_IMAGE_TYPE_3D
:
237 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
238 return V_008F1C_SQ_RSRC_IMG_3D
;
240 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
242 unreachable("illegale image type");
246 * Build the sampler view descriptor for a texture.
249 si_make_texture_descriptor(struct radv_device
*device
,
250 struct radv_image
*image
,
252 VkImageViewType view_type
,
254 const VkComponentMapping
*mapping
,
255 unsigned first_level
, unsigned last_level
,
256 unsigned first_layer
, unsigned last_layer
,
257 unsigned width
, unsigned height
, unsigned depth
,
259 uint32_t *fmask_state
)
261 const struct vk_format_description
*desc
;
262 enum vk_swizzle swizzle
[4];
264 unsigned num_format
, data_format
, type
;
266 desc
= vk_format_description(vk_format
);
268 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
269 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
270 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
272 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
275 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
277 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
278 if (num_format
== ~0) {
282 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
283 if (data_format
== ~0) {
287 type
= radv_tex_dim(image
->type
, view_type
, image
->array_size
, image
->samples
,
288 (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
289 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
291 depth
= image
->array_size
;
292 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
293 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
294 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
295 depth
= image
->array_size
;
296 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
297 depth
= image
->array_size
/ 6;
300 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
301 S_008F14_NUM_FORMAT(num_format
));
302 state
[2] = (S_008F18_WIDTH(width
- 1) |
303 S_008F18_HEIGHT(height
- 1));
304 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
305 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
306 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
307 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
308 S_008F1C_BASE_LEVEL(image
->samples
> 1 ?
310 S_008F1C_LAST_LEVEL(image
->samples
> 1 ?
311 util_logbase2(image
->samples
) :
313 S_008F1C_POW2_PAD(image
->levels
> 1) |
314 S_008F1C_TYPE(type
));
315 state
[4] = S_008F20_DEPTH(depth
- 1);
316 state
[5] = (S_008F24_BASE_ARRAY(first_layer
) |
317 S_008F24_LAST_ARRAY(last_layer
));
321 if (image
->dcc_offset
) {
322 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
324 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
326 /* The last dword is unused by hw. The shader uses it to clear
327 * bits in the first dword of sampler state.
329 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->samples
<= 1) {
330 if (first_level
== last_level
)
331 state
[7] = C_008F30_MAX_ANISO_RATIO
;
333 state
[7] = 0xffffffff;
337 /* Initialize the sampler view for FMASK. */
338 if (image
->fmask
.size
) {
339 uint32_t fmask_format
;
340 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
);
343 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
345 switch (image
->samples
) {
347 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
350 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
353 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
357 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
360 fmask_state
[0] = va
>> 8;
361 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
362 S_008F14_DATA_FORMAT(fmask_format
) |
363 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
364 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
365 S_008F18_HEIGHT(height
- 1);
366 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
367 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
368 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
369 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
370 S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
) |
371 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false));
372 fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
373 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
374 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
) |
375 S_008F24_LAST_ARRAY(last_layer
);
382 radv_query_opaque_metadata(struct radv_device
*device
,
383 struct radv_image
*image
,
384 struct radeon_bo_metadata
*md
)
386 static const VkComponentMapping fixedmapping
;
389 /* Metadata image format format version 1:
390 * [0] = 1 (metadata format identifier)
391 * [1] = (VENDOR_ID << 16) | PCI_ID
392 * [2:9] = image descriptor for the whole resource
393 * [2] is always 0, because the base address is cleared
394 * [9] is the DCC offset bits [39:8] from the beginning of
396 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
398 md
->metadata
[0] = 1; /* metadata image format version 1 */
400 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
401 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
404 si_make_texture_descriptor(device
, image
, true,
405 (VkImageViewType
)image
->type
, image
->vk_format
,
406 &fixedmapping
, 0, image
->levels
- 1, 0,
408 image
->extent
.width
, image
->extent
.height
,
412 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.level
[0], 0, 0,
413 image
->surface
.blk_w
, false, desc
);
415 /* Clear the base address and set the relative DCC offset. */
417 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
418 desc
[7] = image
->dcc_offset
>> 8;
420 /* Dwords [2:9] contain the image descriptor. */
421 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
423 /* Dwords [10:..] contain the mipmap level offsets. */
424 for (i
= 0; i
<= image
->levels
- 1; i
++)
425 md
->metadata
[10+i
] = image
->surface
.level
[i
].offset
>> 8;
427 md
->size_metadata
= (11 + image
->levels
- 1) * 4;
431 radv_init_metadata(struct radv_device
*device
,
432 struct radv_image
*image
,
433 struct radeon_bo_metadata
*metadata
)
435 struct radeon_surf
*surface
= &image
->surface
;
437 memset(metadata
, 0, sizeof(*metadata
));
438 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
439 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
440 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
441 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
442 metadata
->pipe_config
= surface
->pipe_config
;
443 metadata
->bankw
= surface
->bankw
;
444 metadata
->bankh
= surface
->bankh
;
445 metadata
->tile_split
= surface
->tile_split
;
446 metadata
->mtilea
= surface
->mtilea
;
447 metadata
->num_banks
= surface
->num_banks
;
448 metadata
->stride
= surface
->level
[0].pitch_bytes
;
449 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
451 radv_query_opaque_metadata(device
, image
, metadata
);
454 /* The number of samples can be specified independently of the texture. */
456 radv_image_get_fmask_info(struct radv_device
*device
,
457 struct radv_image
*image
,
459 struct radv_fmask_info
*out
)
461 /* FMASK is allocated like an ordinary texture. */
462 struct radeon_surf fmask
= image
->surface
;
464 memset(out
, 0, sizeof(*out
));
466 fmask
.bo_alignment
= 0;
469 fmask
.flags
|= RADEON_SURF_FMASK
;
471 /* Force 2D tiling if it wasn't set. This may occur when creating
472 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
473 * destination buffer must have an FMASK too. */
474 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
475 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
477 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
479 switch (nr_samples
) {
491 device
->ws
->surface_init(device
->ws
, &fmask
);
492 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
494 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
495 if (out
->slice_tile_max
)
496 out
->slice_tile_max
-= 1;
498 out
->tile_mode_index
= fmask
.tiling_index
[0];
499 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
500 out
->bank_height
= fmask
.bankh
;
501 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
502 out
->size
= fmask
.bo_size
;
506 radv_image_alloc_fmask(struct radv_device
*device
,
507 struct radv_image
*image
)
509 radv_image_get_fmask_info(device
, image
, image
->samples
, &image
->fmask
);
511 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
512 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
513 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
517 radv_image_get_cmask_info(struct radv_device
*device
,
518 struct radv_image
*image
,
519 struct radv_cmask_info
*out
)
521 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
522 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
523 unsigned cl_width
, cl_height
;
538 case 16: /* Hawaii */
547 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
549 unsigned width
= align(image
->surface
.npix_x
, cl_width
*8);
550 unsigned height
= align(image
->surface
.npix_y
, cl_height
*8);
551 unsigned slice_elements
= (width
* height
) / (8*8);
553 /* Each element of CMASK is a nibble. */
554 unsigned slice_bytes
= slice_elements
/ 2;
556 out
->slice_tile_max
= (width
* height
) / (128*128);
557 if (out
->slice_tile_max
)
558 out
->slice_tile_max
-= 1;
560 out
->alignment
= MAX2(256, base_align
);
561 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->extent
.depth
: image
->array_size
) *
562 align(slice_bytes
, base_align
);
566 radv_image_alloc_cmask(struct radv_device
*device
,
567 struct radv_image
*image
)
569 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
571 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
572 /* + 8 for storing the clear values */
573 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
574 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ 8;
575 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
579 radv_image_alloc_dcc(struct radv_device
*device
,
580 struct radv_image
*image
)
582 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
583 /* + 8 for storing the clear values */
584 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
585 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 8;
586 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
590 radv_image_get_htile_size(struct radv_device
*device
,
591 struct radv_image
*image
)
593 unsigned cl_width
, cl_height
, width
, height
;
594 unsigned slice_elements
, slice_bytes
, base_align
;
595 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
596 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
598 /* Overalign HTILE on P2 configs to work around GPU hangs in
599 * piglit/depthstencil-render-miplevels 585.
601 * This has been confirmed to help Kabini & Stoney, where the hangs
602 * are always reproducible. I think I have seen the test hang
603 * on Carrizo too, though it was very rare there.
605 if (device
->physical_device
->rad_info
.chip_class
>= CIK
&& num_pipes
< 4)
634 width
= align(image
->surface
.npix_x
, cl_width
* 8);
635 height
= align(image
->surface
.npix_y
, cl_height
* 8);
637 slice_elements
= (width
* height
) / (8 * 8);
638 slice_bytes
= slice_elements
* 4;
640 base_align
= num_pipes
* pipe_interleave_bytes
;
642 image
->htile
.pitch
= width
;
643 image
->htile
.height
= height
;
644 image
->htile
.xalign
= cl_width
* 8;
645 image
->htile
.yalign
= cl_height
* 8;
647 return image
->array_size
*
648 align(slice_bytes
, base_align
);
652 radv_image_alloc_htile(struct radv_device
*device
,
653 struct radv_image
*image
)
655 if (device
->debug_flags
& RADV_DEBUG_NO_HIZ
)
658 image
->htile
.size
= radv_image_get_htile_size(device
, image
);
660 if (!image
->htile
.size
)
663 image
->htile
.offset
= align64(image
->size
, 32768);
665 /* + 8 for storing the clear values */
666 image
->clear_value_offset
= image
->htile
.offset
+ image
->htile
.size
;
667 image
->size
= image
->htile
.offset
+ image
->htile
.size
+ 8;
668 image
->alignment
= align64(image
->alignment
, 32768);
672 radv_image_create(VkDevice _device
,
673 const struct radv_image_create_info
*create_info
,
674 const VkAllocationCallbacks
* alloc
,
677 RADV_FROM_HANDLE(radv_device
, device
, _device
);
678 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
679 struct radv_image
*image
= NULL
;
680 bool can_cmask_dcc
= false;
681 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
683 radv_assert(pCreateInfo
->mipLevels
> 0);
684 radv_assert(pCreateInfo
->arrayLayers
> 0);
685 radv_assert(pCreateInfo
->samples
> 0);
686 radv_assert(pCreateInfo
->extent
.width
> 0);
687 radv_assert(pCreateInfo
->extent
.height
> 0);
688 radv_assert(pCreateInfo
->extent
.depth
> 0);
690 image
= vk_alloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
691 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
693 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
695 memset(image
, 0, sizeof(*image
));
696 image
->type
= pCreateInfo
->imageType
;
697 image
->extent
= pCreateInfo
->extent
;
698 image
->vk_format
= pCreateInfo
->format
;
699 image
->levels
= pCreateInfo
->mipLevels
;
700 image
->array_size
= pCreateInfo
->arrayLayers
;
701 image
->samples
= pCreateInfo
->samples
;
702 image
->tiling
= pCreateInfo
->tiling
;
703 image
->usage
= pCreateInfo
->usage
;
705 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
706 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
707 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
708 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
711 radv_init_surface(device
, &image
->surface
, create_info
);
713 device
->ws
->surface_init(device
->ws
, &image
->surface
);
715 image
->size
= image
->surface
.bo_size
;
716 image
->alignment
= image
->surface
.bo_alignment
;
718 if (image
->exclusive
|| image
->queue_family_mask
== 1)
719 can_cmask_dcc
= true;
721 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
722 image
->surface
.dcc_size
&& can_cmask_dcc
)
723 radv_image_alloc_dcc(device
, image
);
725 image
->surface
.dcc_size
= 0;
727 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
728 pCreateInfo
->mipLevels
== 1 &&
729 !image
->surface
.dcc_size
&& image
->extent
.depth
== 1 && can_cmask_dcc
)
730 radv_image_alloc_cmask(device
, image
);
731 if (image
->samples
> 1 && vk_format_is_color(pCreateInfo
->format
)) {
732 radv_image_alloc_fmask(device
, image
);
733 } else if (vk_format_is_depth(pCreateInfo
->format
)) {
735 radv_image_alloc_htile(device
, image
);
739 if (create_info
->stride
&& create_info
->stride
!= image
->surface
.level
[0].pitch_bytes
) {
740 image
->surface
.level
[0].nblk_x
= create_info
->stride
/ image
->surface
.bpe
;
741 image
->surface
.level
[0].pitch_bytes
= create_info
->stride
;
742 image
->surface
.level
[0].slice_size
= create_info
->stride
* image
->surface
.level
[0].nblk_y
;
744 *pImage
= radv_image_to_handle(image
);
750 radv_image_view_init(struct radv_image_view
*iview
,
751 struct radv_device
*device
,
752 const VkImageViewCreateInfo
* pCreateInfo
,
753 struct radv_cmd_buffer
*cmd_buffer
,
754 VkImageUsageFlags usage_mask
)
756 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
757 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
759 bool is_stencil
= false;
760 switch (image
->type
) {
761 case VK_IMAGE_TYPE_1D
:
762 case VK_IMAGE_TYPE_2D
:
763 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
765 case VK_IMAGE_TYPE_3D
:
766 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
767 <= radv_minify(image
->extent
.depth
, range
->baseMipLevel
));
770 unreachable("bad VkImageType");
772 iview
->image
= image
;
773 iview
->bo
= image
->bo
;
774 iview
->type
= pCreateInfo
->viewType
;
775 iview
->vk_format
= pCreateInfo
->format
;
776 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
778 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
780 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
781 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
782 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
785 iview
->extent
= (VkExtent3D
) {
786 .width
= radv_minify(image
->extent
.width
, range
->baseMipLevel
),
787 .height
= radv_minify(image
->extent
.height
, range
->baseMipLevel
),
788 .depth
= radv_minify(image
->extent
.depth
, range
->baseMipLevel
),
791 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
792 vk_format_get_blockwidth(image
->vk_format
));
793 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
794 vk_format_get_blockheight(image
->vk_format
));
796 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
797 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
798 iview
->base_layer
= range
->baseArrayLayer
;
799 iview
->layer_count
= radv_get_layerCount(image
, range
);
800 iview
->base_mip
= range
->baseMipLevel
;
802 si_make_texture_descriptor(device
, image
, false,
805 &pCreateInfo
->components
,
806 0, radv_get_levelCount(image
, range
) - 1,
807 range
->baseArrayLayer
,
808 range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1,
810 iview
->extent
.height
,
813 iview
->fmask_descriptor
);
814 si_set_mutable_tex_desc_fields(device
, image
,
815 is_stencil
? &image
->surface
.stencil_level
[range
->baseMipLevel
] : &image
->surface
.level
[range
->baseMipLevel
], range
->baseMipLevel
,
817 blk_w
, is_stencil
, iview
->descriptor
);
820 void radv_image_set_optimal_micro_tile_mode(struct radv_device
*device
,
821 struct radv_image
*image
, uint32_t micro_tile_mode
)
823 /* These magic numbers were copied from addrlib. It doesn't use any
824 * definitions for them either. They are all 2D_TILED_THIN1 modes with
825 * different bpp and micro tile mode.
827 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
828 switch (micro_tile_mode
) {
829 case 0: /* displayable */
830 image
->surface
.tiling_index
[0] = 10;
833 image
->surface
.tiling_index
[0] = 14;
835 case 3: /* rotated */
836 image
->surface
.tiling_index
[0] = 28;
838 default: /* depth, thick */
839 assert(!"unexpected micro mode");
843 switch (micro_tile_mode
) {
844 case 0: /* displayable */
845 switch (image
->surface
.bpe
) {
847 image
->surface
.tiling_index
[0] = 10;
850 image
->surface
.tiling_index
[0] = 11;
853 image
->surface
.tiling_index
[0] = 12;
858 switch (image
->surface
.bpe
) {
860 image
->surface
.tiling_index
[0] = 14;
863 image
->surface
.tiling_index
[0] = 15;
866 image
->surface
.tiling_index
[0] = 16;
869 image
->surface
.tiling_index
[0] = 17;
873 default: /* depth, thick */
874 assert(!"unexpected micro mode");
879 image
->surface
.micro_tile_mode
= micro_tile_mode
;
882 bool radv_layout_has_htile(const struct radv_image
*image
,
883 VkImageLayout layout
)
885 return (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
886 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
889 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
890 VkImageLayout layout
)
892 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
;
895 bool radv_layout_can_expclear(const struct radv_image
*image
,
896 VkImageLayout layout
)
898 return (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
899 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
902 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
903 VkImageLayout layout
,
906 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
907 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
911 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
913 if (!image
->exclusive
)
914 return image
->queue_family_mask
;
915 if (family
== VK_QUEUE_FAMILY_IGNORED
)
916 return 1u << queue_family
;
921 radv_CreateImage(VkDevice device
,
922 const VkImageCreateInfo
*pCreateInfo
,
923 const VkAllocationCallbacks
*pAllocator
,
926 return radv_image_create(device
,
927 &(struct radv_image_create_info
) {
928 .vk_info
= pCreateInfo
,
936 radv_DestroyImage(VkDevice _device
, VkImage _image
,
937 const VkAllocationCallbacks
*pAllocator
)
939 RADV_FROM_HANDLE(radv_device
, device
, _device
);
944 vk_free2(&device
->alloc
, pAllocator
, radv_image_from_handle(_image
));
947 void radv_GetImageSubresourceLayout(
950 const VkImageSubresource
* pSubresource
,
951 VkSubresourceLayout
* pLayout
)
953 RADV_FROM_HANDLE(radv_image
, image
, _image
);
954 int level
= pSubresource
->mipLevel
;
955 int layer
= pSubresource
->arrayLayer
;
957 pLayout
->offset
= image
->surface
.level
[level
].offset
+ image
->surface
.level
[level
].slice_size
* layer
;
958 pLayout
->rowPitch
= image
->surface
.level
[level
].pitch_bytes
;
959 pLayout
->arrayPitch
= image
->surface
.level
[level
].slice_size
;
960 pLayout
->depthPitch
= image
->surface
.level
[level
].slice_size
;
961 pLayout
->size
= image
->surface
.level
[level
].slice_size
;
962 if (image
->type
== VK_IMAGE_TYPE_3D
)
963 pLayout
->size
*= image
->surface
.level
[level
].nblk_z
;
968 radv_CreateImageView(VkDevice _device
,
969 const VkImageViewCreateInfo
*pCreateInfo
,
970 const VkAllocationCallbacks
*pAllocator
,
973 RADV_FROM_HANDLE(radv_device
, device
, _device
);
974 struct radv_image_view
*view
;
976 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
977 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
979 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
981 radv_image_view_init(view
, device
, pCreateInfo
, NULL
, ~0);
983 *pView
= radv_image_view_to_handle(view
);
989 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
990 const VkAllocationCallbacks
*pAllocator
)
992 RADV_FROM_HANDLE(radv_device
, device
, _device
);
993 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
997 vk_free2(&device
->alloc
, pAllocator
, iview
);
1000 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1001 struct radv_device
*device
,
1002 const VkBufferViewCreateInfo
* pCreateInfo
,
1003 struct radv_cmd_buffer
*cmd_buffer
)
1005 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1007 view
->bo
= buffer
->bo
;
1008 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1009 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1010 view
->vk_format
= pCreateInfo
->format
;
1012 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1013 pCreateInfo
->offset
, view
->range
, view
->state
);
1017 radv_CreateBufferView(VkDevice _device
,
1018 const VkBufferViewCreateInfo
*pCreateInfo
,
1019 const VkAllocationCallbacks
*pAllocator
,
1020 VkBufferView
*pView
)
1022 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1023 struct radv_buffer_view
*view
;
1025 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1026 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1028 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1030 radv_buffer_view_init(view
, device
, pCreateInfo
, NULL
);
1032 *pView
= radv_buffer_view_to_handle(view
);
1038 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1039 const VkAllocationCallbacks
*pAllocator
)
1041 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1042 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1047 vk_free2(&device
->alloc
, pAllocator
, view
);