2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= VI
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
67 radv_init_surface(struct radv_device
*device
,
68 struct radeon_surf
*surface
,
69 const struct radv_image_create_info
*create_info
)
71 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
72 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
73 const struct vk_format_description
*desc
=
74 vk_format_description(pCreateInfo
->format
);
75 bool is_depth
, is_stencil
, blendable
;
77 is_depth
= vk_format_has_depth(desc
);
78 is_stencil
= vk_format_has_stencil(desc
);
80 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
81 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
83 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
84 /* align byte per element on dword */
85 if (surface
->bpe
== 3) {
88 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
90 switch (pCreateInfo
->imageType
){
91 case VK_IMAGE_TYPE_1D
:
92 if (pCreateInfo
->arrayLayers
> 1)
93 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
95 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
97 case VK_IMAGE_TYPE_2D
:
98 if (pCreateInfo
->arrayLayers
> 1)
99 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
101 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
103 case VK_IMAGE_TYPE_3D
:
104 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
107 unreachable("unhandled image type");
111 surface
->flags
|= RADEON_SURF_ZBUFFER
;
112 if (!(pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
113 !(pCreateInfo
->flags
& (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
|
114 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
)) &&
115 pCreateInfo
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
116 pCreateInfo
->mipLevels
<= 1 &&
117 device
->physical_device
->rad_info
.chip_class
>= VI
&&
118 ((pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT
||
119 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
) ||
120 (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
121 pCreateInfo
->format
== VK_FORMAT_D16_UNORM
)))
122 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
126 surface
->flags
|= RADEON_SURF_SBUFFER
;
128 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
130 bool dcc_compatible_formats
= !radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
);
131 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
132 const struct VkImageFormatListCreateInfoKHR
*format_list
=
133 (const struct VkImageFormatListCreateInfoKHR
*)
134 vk_find_struct_const(pCreateInfo
->pNext
,
135 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
137 /* We have to ignore the existence of the list if viewFormatCount = 0 */
138 if (format_list
&& format_list
->viewFormatCount
) {
139 /* compatibility is transitive, so we only need to check
140 * one format with everything else. */
141 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
142 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
143 format_list
->pViewFormats
[i
]))
144 dcc_compatible_formats
= false;
147 dcc_compatible_formats
= false;
151 if ((pCreateInfo
->usage
& (VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
152 VK_IMAGE_USAGE_STORAGE_BIT
)) ||
153 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
) ||
154 !dcc_compatible_formats
||
155 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
156 pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1 ||
157 device
->physical_device
->rad_info
.chip_class
< VI
||
158 create_info
->scanout
|| (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
159 pCreateInfo
->samples
>= 2)
160 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
161 if (create_info
->scanout
)
162 surface
->flags
|= RADEON_SURF_SCANOUT
;
166 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
168 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
171 static inline unsigned
172 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
175 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
177 return image
->surface
.u
.legacy
.tiling_index
[level
];
180 static unsigned radv_map_swizzle(unsigned swizzle
)
184 return V_008F0C_SQ_SEL_Y
;
186 return V_008F0C_SQ_SEL_Z
;
188 return V_008F0C_SQ_SEL_W
;
190 return V_008F0C_SQ_SEL_0
;
192 return V_008F0C_SQ_SEL_1
;
193 default: /* VK_SWIZZLE_X */
194 return V_008F0C_SQ_SEL_X
;
199 radv_make_buffer_descriptor(struct radv_device
*device
,
200 struct radv_buffer
*buffer
,
206 const struct vk_format_description
*desc
;
208 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
209 uint64_t va
= gpu_address
+ buffer
->offset
;
210 unsigned num_format
, data_format
;
212 desc
= vk_format_description(vk_format
);
213 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
214 stride
= desc
->block
.bits
/ 8;
216 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
217 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
221 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
222 S_008F04_STRIDE(stride
);
224 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
229 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
230 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
231 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
232 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
233 S_008F0C_NUM_FORMAT(num_format
) |
234 S_008F0C_DATA_FORMAT(data_format
);
238 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
239 struct radv_image
*image
,
240 const struct legacy_surf_level
*base_level_info
,
241 unsigned base_level
, unsigned first_level
,
242 unsigned block_width
, bool is_stencil
,
245 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
246 uint64_t va
= gpu_address
;
247 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
248 uint64_t meta_va
= 0;
249 if (chip_class
>= GFX9
) {
251 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
253 va
+= image
->surface
.u
.gfx9
.surf_offset
;
255 va
+= base_level_info
->offset
;
258 if (chip_class
>= GFX9
||
259 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
260 state
[0] |= image
->surface
.tile_swizzle
;
261 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
262 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
264 if (chip_class
>= VI
) {
265 state
[6] &= C_008F28_COMPRESSION_EN
;
267 if (radv_vi_dcc_enabled(image
, first_level
)) {
268 meta_va
= gpu_address
+ image
->dcc_offset
;
269 if (chip_class
<= VI
)
270 meta_va
+= base_level_info
->dcc_offset
;
271 } else if(image
->tc_compatible_htile
&& image
->surface
.htile_size
) {
272 meta_va
= gpu_address
+ image
->htile_offset
;
276 state
[6] |= S_008F28_COMPRESSION_EN(1);
277 state
[7] = meta_va
>> 8;
278 state
[7] |= image
->surface
.tile_swizzle
;
282 if (chip_class
>= GFX9
) {
283 state
[3] &= C_008F1C_SW_MODE
;
284 state
[4] &= C_008F20_PITCH_GFX9
;
287 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
288 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
290 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
291 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
294 state
[5] &= C_008F24_META_DATA_ADDRESS
&
295 C_008F24_META_PIPE_ALIGNED
&
296 C_008F24_META_RB_ALIGNED
;
298 struct gfx9_surf_meta_flags meta
;
300 if (image
->dcc_offset
)
301 meta
= image
->surface
.u
.gfx9
.dcc
;
303 meta
= image
->surface
.u
.gfx9
.htile
;
305 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
306 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
307 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
311 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
312 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
314 state
[3] &= C_008F1C_TILING_INDEX
;
315 state
[3] |= S_008F1C_TILING_INDEX(index
);
316 state
[4] &= C_008F20_PITCH_GFX6
;
317 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
321 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
322 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
324 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
325 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
327 /* GFX9 allocates 1D textures as 2D. */
328 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
329 image_type
= VK_IMAGE_TYPE_2D
;
330 switch (image_type
) {
331 case VK_IMAGE_TYPE_1D
:
332 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
333 case VK_IMAGE_TYPE_2D
:
335 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
337 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
338 case VK_IMAGE_TYPE_3D
:
339 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
340 return V_008F1C_SQ_RSRC_IMG_3D
;
342 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
344 unreachable("illegale image type");
348 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
350 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
352 if (swizzle
[3] == VK_SWIZZLE_X
) {
353 /* For the pre-defined border color values (white, opaque
354 * black, transparent black), the only thing that matters is
355 * that the alpha channel winds up in the correct place
356 * (because the RGB channels are all the same) so either of
357 * these enumerations will work.
359 if (swizzle
[2] == VK_SWIZZLE_Y
)
360 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
362 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
363 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
364 if (swizzle
[1] == VK_SWIZZLE_Y
)
365 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
367 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
368 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
369 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
370 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
371 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
378 * Build the sampler view descriptor for a texture.
381 si_make_texture_descriptor(struct radv_device
*device
,
382 struct radv_image
*image
,
383 bool is_storage_image
,
384 VkImageViewType view_type
,
386 const VkComponentMapping
*mapping
,
387 unsigned first_level
, unsigned last_level
,
388 unsigned first_layer
, unsigned last_layer
,
389 unsigned width
, unsigned height
, unsigned depth
,
391 uint32_t *fmask_state
)
393 const struct vk_format_description
*desc
;
394 enum vk_swizzle swizzle
[4];
396 unsigned num_format
, data_format
, type
;
398 desc
= vk_format_description(vk_format
);
400 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
401 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
402 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
404 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
407 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
409 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
410 if (num_format
== ~0) {
414 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
415 if (data_format
== ~0) {
419 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
420 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
421 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
423 depth
= image
->info
.array_size
;
424 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
425 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
426 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
427 depth
= image
->info
.array_size
;
428 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
429 depth
= image
->info
.array_size
/ 6;
432 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
433 S_008F14_NUM_FORMAT_GFX6(num_format
));
434 state
[2] = (S_008F18_WIDTH(width
- 1) |
435 S_008F18_HEIGHT(height
- 1) |
436 S_008F18_PERF_MOD(4));
437 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
438 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
439 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
440 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
441 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
443 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
444 util_logbase2(image
->info
.samples
) :
446 S_008F1C_TYPE(type
));
448 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
452 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
453 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
455 /* Depth is the the last accessible layer on Gfx9.
456 * The hw doesn't need to know the total number of layers.
458 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
459 state
[4] |= S_008F20_DEPTH(depth
- 1);
461 state
[4] |= S_008F20_DEPTH(last_layer
);
463 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
464 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
465 util_logbase2(image
->info
.samples
) :
466 image
->info
.levels
- 1);
468 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
469 state
[4] |= S_008F20_DEPTH(depth
- 1);
470 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
472 if (image
->dcc_offset
) {
473 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
475 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
477 /* The last dword is unused by hw. The shader uses it to clear
478 * bits in the first dword of sampler state.
480 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
481 if (first_level
== last_level
)
482 state
[7] = C_008F30_MAX_ANISO_RATIO
;
484 state
[7] = 0xffffffff;
488 /* Initialize the sampler view for FMASK. */
489 if (image
->fmask
.size
) {
490 uint32_t fmask_format
, num_format
;
491 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
494 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
496 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
497 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
498 switch (image
->info
.samples
) {
500 num_format
= V_008F14_IMG_FMASK_8_2_2
;
503 num_format
= V_008F14_IMG_FMASK_8_4_4
;
506 num_format
= V_008F14_IMG_FMASK_32_8_8
;
509 unreachable("invalid nr_samples");
512 switch (image
->info
.samples
) {
514 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
517 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
520 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
524 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
526 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
529 fmask_state
[0] = va
>> 8;
530 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
531 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
532 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
533 S_008F14_NUM_FORMAT_GFX6(num_format
);
534 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
535 S_008F18_HEIGHT(height
- 1);
536 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
537 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
538 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
539 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
540 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false, false));
542 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
546 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
547 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
548 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
549 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
550 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
551 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
553 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
554 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
555 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
556 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
558 } else if (fmask_state
)
559 memset(fmask_state
, 0, 8 * 4);
563 radv_query_opaque_metadata(struct radv_device
*device
,
564 struct radv_image
*image
,
565 struct radeon_bo_metadata
*md
)
567 static const VkComponentMapping fixedmapping
;
570 /* Metadata image format format version 1:
571 * [0] = 1 (metadata format identifier)
572 * [1] = (VENDOR_ID << 16) | PCI_ID
573 * [2:9] = image descriptor for the whole resource
574 * [2] is always 0, because the base address is cleared
575 * [9] is the DCC offset bits [39:8] from the beginning of
577 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
579 md
->metadata
[0] = 1; /* metadata image format version 1 */
581 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
582 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
585 si_make_texture_descriptor(device
, image
, false,
586 (VkImageViewType
)image
->type
, image
->vk_format
,
587 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
588 image
->info
.array_size
,
589 image
->info
.width
, image
->info
.height
,
593 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
594 image
->surface
.blk_w
, false, desc
);
596 /* Clear the base address and set the relative DCC offset. */
598 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
599 desc
[7] = image
->dcc_offset
>> 8;
601 /* Dwords [2:9] contain the image descriptor. */
602 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
604 /* Dwords [10:..] contain the mipmap level offsets. */
605 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
606 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
607 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
608 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
613 radv_init_metadata(struct radv_device
*device
,
614 struct radv_image
*image
,
615 struct radeon_bo_metadata
*metadata
)
617 struct radeon_surf
*surface
= &image
->surface
;
619 memset(metadata
, 0, sizeof(*metadata
));
621 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
622 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
624 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
625 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
626 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
627 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
628 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
629 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
630 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
631 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
632 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
633 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
634 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
635 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
637 radv_query_opaque_metadata(device
, image
, metadata
);
640 /* The number of samples can be specified independently of the texture. */
642 radv_image_get_fmask_info(struct radv_device
*device
,
643 struct radv_image
*image
,
645 struct radv_fmask_info
*out
)
647 /* FMASK is allocated like an ordinary texture. */
648 struct radeon_surf fmask
= {};
649 struct ac_surf_info info
= image
->info
;
650 memset(out
, 0, sizeof(*out
));
652 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
653 out
->alignment
= image
->surface
.u
.gfx9
.fmask_alignment
;
654 out
->size
= image
->surface
.u
.gfx9
.fmask_size
;
658 fmask
.blk_w
= image
->surface
.blk_w
;
659 fmask
.blk_h
= image
->surface
.blk_h
;
661 fmask
.flags
= image
->surface
.flags
| RADEON_SURF_FMASK
;
663 if (!image
->shareable
)
664 info
.surf_index
= &device
->fmask_mrt_offset_counter
;
666 /* Force 2D tiling if it wasn't set. This may occur when creating
667 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
668 * destination buffer must have an FMASK too. */
669 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
670 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
672 switch (nr_samples
) {
684 device
->ws
->surface_init(device
->ws
, &info
, &fmask
);
685 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
687 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
688 if (out
->slice_tile_max
)
689 out
->slice_tile_max
-= 1;
691 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
692 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
693 out
->bank_height
= fmask
.u
.legacy
.bankh
;
694 out
->tile_swizzle
= fmask
.tile_swizzle
;
695 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
696 out
->size
= fmask
.surf_size
;
698 assert(!out
->tile_swizzle
|| !image
->shareable
);
702 radv_image_alloc_fmask(struct radv_device
*device
,
703 struct radv_image
*image
)
705 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
707 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
708 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
709 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
713 radv_image_get_cmask_info(struct radv_device
*device
,
714 struct radv_image
*image
,
715 struct radv_cmask_info
*out
)
717 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
718 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
719 unsigned cl_width
, cl_height
;
721 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
722 out
->alignment
= image
->surface
.u
.gfx9
.cmask_alignment
;
723 out
->size
= image
->surface
.u
.gfx9
.cmask_size
;
740 case 16: /* Hawaii */
749 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
751 unsigned width
= align(image
->info
.width
, cl_width
*8);
752 unsigned height
= align(image
->info
.height
, cl_height
*8);
753 unsigned slice_elements
= (width
* height
) / (8*8);
755 /* Each element of CMASK is a nibble. */
756 unsigned slice_bytes
= slice_elements
/ 2;
758 out
->slice_tile_max
= (width
* height
) / (128*128);
759 if (out
->slice_tile_max
)
760 out
->slice_tile_max
-= 1;
762 out
->alignment
= MAX2(256, base_align
);
763 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
764 align(slice_bytes
, base_align
);
768 radv_image_alloc_cmask(struct radv_device
*device
,
769 struct radv_image
*image
)
771 uint32_t clear_value_size
= 0;
772 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
774 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
775 /* + 8 for storing the clear values */
776 if (!image
->clear_value_offset
) {
777 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
778 clear_value_size
= 8;
780 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
781 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
785 radv_image_alloc_dcc(struct radv_image
*image
)
787 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
788 /* + 16 for storing the clear values + dcc pred */
789 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
790 image
->dcc_pred_offset
= image
->clear_value_offset
+ 8;
791 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
792 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
796 radv_image_alloc_htile(struct radv_image
*image
)
798 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
800 /* + 8 for storing the clear values */
801 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
802 image
->size
= image
->clear_value_offset
+ 8;
803 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
807 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
809 if (image
->info
.samples
<= 1 &&
810 image
->info
.width
<= 512 && image
->info
.height
<= 512) {
811 /* Do not enable CMASK or DCC for small surfaces where the cost
812 * of the eliminate pass can be higher than the benefit of fast
813 * clear. RadeonSI does this, but the image threshold is
819 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
820 (image
->exclusive
|| image
->queue_family_mask
== 1);
824 radv_image_can_enable_dcc(struct radv_image
*image
)
826 return radv_image_can_enable_dcc_or_cmask(image
) &&
827 image
->surface
.dcc_size
;
831 radv_image_can_enable_cmask(struct radv_image
*image
)
833 if (image
->surface
.bpe
> 8 && image
->info
.samples
== 1) {
834 /* Do not enable CMASK for non-MSAA images (fast color clear)
835 * because 128 bit formats are not supported, but FMASK might
841 return radv_image_can_enable_dcc_or_cmask(image
) &&
842 image
->info
.levels
== 1 &&
843 image
->info
.depth
== 1 &&
844 !image
->surface
.is_linear
;
848 radv_image_can_enable_fmask(struct radv_image
*image
)
850 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
854 radv_image_can_enable_htile(struct radv_image
*image
)
856 return image
->info
.levels
== 1 && vk_format_is_depth(image
->vk_format
);
860 radv_image_create(VkDevice _device
,
861 const struct radv_image_create_info
*create_info
,
862 const VkAllocationCallbacks
* alloc
,
865 RADV_FROM_HANDLE(radv_device
, device
, _device
);
866 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
867 struct radv_image
*image
= NULL
;
868 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
870 radv_assert(pCreateInfo
->mipLevels
> 0);
871 radv_assert(pCreateInfo
->arrayLayers
> 0);
872 radv_assert(pCreateInfo
->samples
> 0);
873 radv_assert(pCreateInfo
->extent
.width
> 0);
874 radv_assert(pCreateInfo
->extent
.height
> 0);
875 radv_assert(pCreateInfo
->extent
.depth
> 0);
877 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
878 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
880 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
882 image
->type
= pCreateInfo
->imageType
;
883 image
->info
.width
= pCreateInfo
->extent
.width
;
884 image
->info
.height
= pCreateInfo
->extent
.height
;
885 image
->info
.depth
= pCreateInfo
->extent
.depth
;
886 image
->info
.samples
= pCreateInfo
->samples
;
887 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
888 image
->info
.levels
= pCreateInfo
->mipLevels
;
890 image
->vk_format
= pCreateInfo
->format
;
891 image
->tiling
= pCreateInfo
->tiling
;
892 image
->usage
= pCreateInfo
->usage
;
893 image
->flags
= pCreateInfo
->flags
;
895 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
896 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
897 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
898 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
899 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
901 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
904 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
905 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
906 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
907 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
910 radv_init_surface(device
, &image
->surface
, create_info
);
912 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
914 image
->size
= image
->surface
.surf_size
;
915 image
->alignment
= image
->surface
.surf_alignment
;
917 /* Try to enable DCC first. */
918 if (radv_image_can_enable_dcc(image
)) {
919 radv_image_alloc_dcc(image
);
921 /* When DCC cannot be enabled, try CMASK. */
922 image
->surface
.dcc_size
= 0;
923 if (radv_image_can_enable_cmask(image
)) {
924 radv_image_alloc_cmask(device
, image
);
928 /* Try to enable FMASK for multisampled images. */
929 if (radv_image_can_enable_fmask(image
)) {
930 radv_image_alloc_fmask(device
, image
);
932 /* Otherwise, try to enable HTILE for depth surfaces. */
933 if (radv_image_can_enable_htile(image
) &&
934 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
935 radv_image_alloc_htile(image
);
936 image
->tc_compatible_htile
= image
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
938 image
->surface
.htile_size
= 0;
942 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
943 image
->alignment
= MAX2(image
->alignment
, 4096);
944 image
->size
= align64(image
->size
, image
->alignment
);
947 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
948 0, RADEON_FLAG_VIRTUAL
);
950 vk_free2(&device
->alloc
, alloc
, image
);
951 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
955 *pImage
= radv_image_to_handle(image
);
961 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
962 struct radv_device
*device
,
963 const VkComponentMapping
*components
,
964 bool is_storage_image
)
966 struct radv_image
*image
= iview
->image
;
967 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
969 uint32_t *descriptor
;
970 uint32_t hw_level
= 0;
972 if (is_storage_image
) {
973 descriptor
= iview
->storage_descriptor
;
975 descriptor
= iview
->descriptor
;
978 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
979 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
981 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
982 hw_level
= iview
->base_mip
;
983 si_make_texture_descriptor(device
, image
, is_storage_image
,
987 hw_level
, hw_level
+ iview
->level_count
- 1,
989 iview
->base_layer
+ iview
->layer_count
- 1,
991 iview
->extent
.height
,
996 const struct legacy_surf_level
*base_level_info
= NULL
;
997 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
999 base_level_info
= &image
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1001 base_level_info
= &image
->surface
.u
.legacy
.level
[iview
->base_mip
];
1003 si_set_mutable_tex_desc_fields(device
, image
,
1007 blk_w
, is_stencil
, descriptor
);
1011 radv_image_view_init(struct radv_image_view
*iview
,
1012 struct radv_device
*device
,
1013 const VkImageViewCreateInfo
* pCreateInfo
)
1015 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1016 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1018 switch (image
->type
) {
1019 case VK_IMAGE_TYPE_1D
:
1020 case VK_IMAGE_TYPE_2D
:
1021 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1023 case VK_IMAGE_TYPE_3D
:
1024 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1025 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1028 unreachable("bad VkImageType");
1030 iview
->image
= image
;
1031 iview
->bo
= image
->bo
;
1032 iview
->type
= pCreateInfo
->viewType
;
1033 iview
->vk_format
= pCreateInfo
->format
;
1034 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1036 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1037 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1038 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1039 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1042 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1043 iview
->extent
= (VkExtent3D
) {
1044 .width
= image
->info
.width
,
1045 .height
= image
->info
.height
,
1046 .depth
= image
->info
.depth
,
1049 iview
->extent
= (VkExtent3D
) {
1050 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1051 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1052 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1056 if (iview
->vk_format
!= image
->vk_format
) {
1057 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
1058 vk_format_get_blockwidth(image
->vk_format
));
1059 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
1060 vk_format_get_blockheight(image
->vk_format
));
1063 iview
->base_layer
= range
->baseArrayLayer
;
1064 iview
->layer_count
= radv_get_layerCount(image
, range
);
1065 iview
->base_mip
= range
->baseMipLevel
;
1066 iview
->level_count
= radv_get_levelCount(image
, range
);
1068 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, false);
1069 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, true);
1072 bool radv_layout_has_htile(const struct radv_image
*image
,
1073 VkImageLayout layout
,
1074 unsigned queue_mask
)
1076 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1077 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1079 return image
->surface
.htile_size
&&
1080 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1081 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1082 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1085 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1086 VkImageLayout layout
,
1087 unsigned queue_mask
)
1089 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1090 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1092 return image
->surface
.htile_size
&&
1093 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1094 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1095 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1098 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1099 VkImageLayout layout
,
1100 unsigned queue_mask
)
1102 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
1103 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1107 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1109 if (!image
->exclusive
)
1110 return image
->queue_family_mask
;
1111 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
1112 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1113 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1114 return 1u << queue_family
;
1115 return 1u << family
;
1119 radv_CreateImage(VkDevice device
,
1120 const VkImageCreateInfo
*pCreateInfo
,
1121 const VkAllocationCallbacks
*pAllocator
,
1124 const struct wsi_image_create_info
*wsi_info
=
1125 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1126 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1128 return radv_image_create(device
,
1129 &(struct radv_image_create_info
) {
1130 .vk_info
= pCreateInfo
,
1138 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1139 const VkAllocationCallbacks
*pAllocator
)
1141 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1142 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1147 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1148 device
->ws
->buffer_destroy(image
->bo
);
1150 vk_free2(&device
->alloc
, pAllocator
, image
);
1153 void radv_GetImageSubresourceLayout(
1156 const VkImageSubresource
* pSubresource
,
1157 VkSubresourceLayout
* pLayout
)
1159 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1160 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1161 int level
= pSubresource
->mipLevel
;
1162 int layer
= pSubresource
->arrayLayer
;
1163 struct radeon_surf
*surface
= &image
->surface
;
1165 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1166 pLayout
->offset
= surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1167 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1168 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1169 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1170 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1171 if (image
->type
== VK_IMAGE_TYPE_3D
)
1172 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1174 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1175 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1176 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1177 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1178 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1179 if (image
->type
== VK_IMAGE_TYPE_3D
)
1180 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1186 radv_CreateImageView(VkDevice _device
,
1187 const VkImageViewCreateInfo
*pCreateInfo
,
1188 const VkAllocationCallbacks
*pAllocator
,
1191 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1192 struct radv_image_view
*view
;
1194 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1195 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1197 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1199 radv_image_view_init(view
, device
, pCreateInfo
);
1201 *pView
= radv_image_view_to_handle(view
);
1207 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1208 const VkAllocationCallbacks
*pAllocator
)
1210 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1211 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1215 vk_free2(&device
->alloc
, pAllocator
, iview
);
1218 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1219 struct radv_device
*device
,
1220 const VkBufferViewCreateInfo
* pCreateInfo
)
1222 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1224 view
->bo
= buffer
->bo
;
1225 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1226 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1227 view
->vk_format
= pCreateInfo
->format
;
1229 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1230 pCreateInfo
->offset
, view
->range
, view
->state
);
1234 radv_CreateBufferView(VkDevice _device
,
1235 const VkBufferViewCreateInfo
*pCreateInfo
,
1236 const VkAllocationCallbacks
*pAllocator
,
1237 VkBufferView
*pView
)
1239 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1240 struct radv_buffer_view
*view
;
1242 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1245 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1247 radv_buffer_view_init(view
, device
, pCreateInfo
);
1249 *pView
= radv_buffer_view_to_handle(view
);
1255 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1256 const VkAllocationCallbacks
*pAllocator
)
1258 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1259 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1264 vk_free2(&device
->alloc
, pAllocator
, view
);