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7a4b2d57a513d15324e4f2340694a0234ae79ed7
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "vk_util.h"
31 #include "radv_radeon_winsys.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36 static unsigned
37 radv_choose_tiling(struct radv_device *Device,
38 const struct radv_image_create_info *create_info)
39 {
40 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
41
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
49 /* Only very thin and long 2D textures should benefit from
50 * linear_aligned. */
51 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED;
53
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo->samples > 1)
56 return RADEON_SURF_MODE_2D;
57
58 return RADEON_SURF_MODE_2D;
59 }
60 static int
61 radv_init_surface(struct radv_device *device,
62 struct radeon_surf *surface,
63 const struct radv_image_create_info *create_info)
64 {
65 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
66 unsigned array_mode = radv_choose_tiling(device, create_info);
67 const struct vk_format_description *desc =
68 vk_format_description(pCreateInfo->format);
69 bool is_depth, is_stencil, blendable;
70
71 is_depth = vk_format_has_depth(desc);
72 is_stencil = vk_format_has_stencil(desc);
73
74 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
75 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
76
77 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
78 /* align byte per element on dword */
79 if (surface->bpe == 3) {
80 surface->bpe = 4;
81 }
82 surface->flags = RADEON_SURF_SET(array_mode, MODE);
83
84 switch (pCreateInfo->imageType){
85 case VK_IMAGE_TYPE_1D:
86 if (pCreateInfo->arrayLayers > 1)
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
88 else
89 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
90 break;
91 case VK_IMAGE_TYPE_2D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_3D:
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
99 break;
100 default:
101 unreachable("unhandled image type");
102 }
103
104 if (is_depth) {
105 surface->flags |= RADEON_SURF_ZBUFFER;
106 }
107
108 if (is_stencil)
109 surface->flags |= RADEON_SURF_SBUFFER;
110
111 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
112
113 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
114 VK_IMAGE_USAGE_STORAGE_BIT)) ||
115 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
116 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
117 device->physical_device->rad_info.chip_class < VI ||
118 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
119 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
120 surface->flags |= RADEON_SURF_DISABLE_DCC;
121 if (create_info->scanout)
122 surface->flags |= RADEON_SURF_SCANOUT;
123 return 0;
124 }
125 #define ATI_VENDOR_ID 0x1002
126 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
127 {
128 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
129 }
130
131 static inline unsigned
132 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
133 {
134 if (stencil)
135 return image->surface.u.legacy.stencil_tiling_index[level];
136 else
137 return image->surface.u.legacy.tiling_index[level];
138 }
139
140 static unsigned radv_map_swizzle(unsigned swizzle)
141 {
142 switch (swizzle) {
143 case VK_SWIZZLE_Y:
144 return V_008F0C_SQ_SEL_Y;
145 case VK_SWIZZLE_Z:
146 return V_008F0C_SQ_SEL_Z;
147 case VK_SWIZZLE_W:
148 return V_008F0C_SQ_SEL_W;
149 case VK_SWIZZLE_0:
150 return V_008F0C_SQ_SEL_0;
151 case VK_SWIZZLE_1:
152 return V_008F0C_SQ_SEL_1;
153 default: /* VK_SWIZZLE_X */
154 return V_008F0C_SQ_SEL_X;
155 }
156 }
157
158 static void
159 radv_make_buffer_descriptor(struct radv_device *device,
160 struct radv_buffer *buffer,
161 VkFormat vk_format,
162 unsigned offset,
163 unsigned range,
164 uint32_t *state)
165 {
166 const struct vk_format_description *desc;
167 unsigned stride;
168 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
169 uint64_t va = gpu_address + buffer->offset;
170 unsigned num_format, data_format;
171 int first_non_void;
172 desc = vk_format_description(vk_format);
173 first_non_void = vk_format_get_first_non_void_channel(vk_format);
174 stride = desc->block.bits / 8;
175
176 num_format = radv_translate_buffer_numformat(desc, first_non_void);
177 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
178
179 va += offset;
180 state[0] = va;
181 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
182 S_008F04_STRIDE(stride);
183
184 if (device->physical_device->rad_info.chip_class < VI && stride) {
185 range /= stride;
186 }
187
188 state[2] = range;
189 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
190 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
191 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
192 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
193 S_008F0C_NUM_FORMAT(num_format) |
194 S_008F0C_DATA_FORMAT(data_format);
195 }
196
197 static void
198 si_set_mutable_tex_desc_fields(struct radv_device *device,
199 struct radv_image *image,
200 const struct legacy_surf_level *base_level_info,
201 unsigned base_level, unsigned first_level,
202 unsigned block_width, bool is_stencil,
203 uint32_t *state)
204 {
205 uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
206 uint64_t va = gpu_address;
207 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
208 uint64_t meta_va = 0;
209 if (chip_class >= GFX9) {
210 if (is_stencil)
211 va += image->surface.u.gfx9.stencil_offset;
212 else
213 va += image->surface.u.gfx9.surf_offset;
214 } else
215 va += base_level_info->offset;
216
217 state[0] = va >> 8;
218 if (chip_class < GFX9)
219 if (base_level_info->mode == RADEON_SURF_MODE_2D)
220 state[0] |= image->surface.tile_swizzle;
221 state[1] &= C_008F14_BASE_ADDRESS_HI;
222 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
223
224 if (chip_class >= VI) {
225 state[6] &= C_008F28_COMPRESSION_EN;
226 state[7] = 0;
227 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
228 meta_va = gpu_address + image->dcc_offset;
229 if (chip_class <= VI)
230 meta_va += base_level_info->dcc_offset;
231 state[6] |= S_008F28_COMPRESSION_EN(1);
232 state[7] = meta_va >> 8;
233 if (chip_class < GFX9)
234 state[7] |= image->surface.tile_swizzle;
235 }
236 }
237
238 if (chip_class >= GFX9) {
239 state[3] &= C_008F1C_SW_MODE;
240 state[4] &= C_008F20_PITCH_GFX9;
241
242 if (is_stencil) {
243 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
244 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
245 } else {
246 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
247 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
248 }
249
250 state[5] &= C_008F24_META_DATA_ADDRESS &
251 C_008F24_META_PIPE_ALIGNED &
252 C_008F24_META_RB_ALIGNED;
253 if (meta_va) {
254 struct gfx9_surf_meta_flags meta;
255
256 if (image->dcc_offset)
257 meta = image->surface.u.gfx9.dcc;
258 else
259 meta = image->surface.u.gfx9.htile;
260
261 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
262 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
263 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
264 }
265 } else {
266 /* SI-CI-VI */
267 unsigned pitch = base_level_info->nblk_x * block_width;
268 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
269
270 state[3] &= C_008F1C_TILING_INDEX;
271 state[3] |= S_008F1C_TILING_INDEX(index);
272 state[4] &= C_008F20_PITCH_GFX6;
273 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
274 }
275 }
276
277 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
278 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
279 {
280 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
281 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
282 switch (image_type) {
283 case VK_IMAGE_TYPE_1D:
284 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
285 case VK_IMAGE_TYPE_2D:
286 if (nr_samples > 1)
287 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
288 else
289 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
290 case VK_IMAGE_TYPE_3D:
291 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
292 return V_008F1C_SQ_RSRC_IMG_3D;
293 else
294 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
295 default:
296 unreachable("illegale image type");
297 }
298 }
299
300 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
301 {
302 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
303
304 if (swizzle[3] == VK_SWIZZLE_X) {
305 /* For the pre-defined border color values (white, opaque
306 * black, transparent black), the only thing that matters is
307 * that the alpha channel winds up in the correct place
308 * (because the RGB channels are all the same) so either of
309 * these enumerations will work.
310 */
311 if (swizzle[2] == VK_SWIZZLE_Y)
312 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
313 else
314 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
315 } else if (swizzle[0] == VK_SWIZZLE_X) {
316 if (swizzle[1] == VK_SWIZZLE_Y)
317 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
318 else
319 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
320 } else if (swizzle[1] == VK_SWIZZLE_X) {
321 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
322 } else if (swizzle[2] == VK_SWIZZLE_X) {
323 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
324 }
325
326 return bc_swizzle;
327 }
328
329 /**
330 * Build the sampler view descriptor for a texture.
331 */
332 static void
333 si_make_texture_descriptor(struct radv_device *device,
334 struct radv_image *image,
335 bool is_storage_image,
336 VkImageViewType view_type,
337 VkFormat vk_format,
338 const VkComponentMapping *mapping,
339 unsigned first_level, unsigned last_level,
340 unsigned first_layer, unsigned last_layer,
341 unsigned width, unsigned height, unsigned depth,
342 uint32_t *state,
343 uint32_t *fmask_state)
344 {
345 const struct vk_format_description *desc;
346 enum vk_swizzle swizzle[4];
347 int first_non_void;
348 unsigned num_format, data_format, type;
349
350 desc = vk_format_description(vk_format);
351
352 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
353 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
354 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
355 } else {
356 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
357 }
358
359 first_non_void = vk_format_get_first_non_void_channel(vk_format);
360
361 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
362 if (num_format == ~0) {
363 num_format = 0;
364 }
365
366 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
367 if (data_format == ~0) {
368 data_format = 0;
369 }
370
371 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
372 is_storage_image);
373 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
374 height = 1;
375 depth = image->info.array_size;
376 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
377 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
378 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
379 depth = image->info.array_size;
380 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
381 depth = image->info.array_size / 6;
382
383 state[0] = 0;
384 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
385 S_008F14_NUM_FORMAT_GFX6(num_format));
386 state[2] = (S_008F18_WIDTH(width - 1) |
387 S_008F18_HEIGHT(height - 1) |
388 S_008F18_PERF_MOD(4));
389 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
390 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
391 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
392 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
393 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
394 0 : first_level) |
395 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
396 util_logbase2(image->info.samples) :
397 last_level) |
398 S_008F1C_TYPE(type));
399 state[4] = 0;
400 state[5] = S_008F24_BASE_ARRAY(first_layer);
401 state[6] = 0;
402 state[7] = 0;
403
404 if (device->physical_device->rad_info.chip_class >= GFX9) {
405 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
406
407 /* Depth is the the last accessible layer on Gfx9.
408 * The hw doesn't need to know the total number of layers.
409 */
410 if (type == V_008F1C_SQ_RSRC_IMG_3D)
411 state[4] |= S_008F20_DEPTH(depth - 1);
412 else
413 state[4] |= S_008F20_DEPTH(last_layer);
414
415 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
416 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
417 util_logbase2(image->info.samples) :
418 last_level);
419 } else {
420 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
421 state[4] |= S_008F20_DEPTH(depth - 1);
422 state[5] |= S_008F24_LAST_ARRAY(last_layer);
423 }
424 if (image->dcc_offset) {
425 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
426
427 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
428 } else {
429 /* The last dword is unused by hw. The shader uses it to clear
430 * bits in the first dword of sampler state.
431 */
432 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
433 if (first_level == last_level)
434 state[7] = C_008F30_MAX_ANISO_RATIO;
435 else
436 state[7] = 0xffffffff;
437 }
438 }
439
440 /* Initialize the sampler view for FMASK. */
441 if (image->fmask.size) {
442 uint32_t fmask_format, num_format;
443 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
444 uint64_t va;
445
446 va = gpu_address + image->offset + image->fmask.offset;
447
448 if (device->physical_device->rad_info.chip_class >= GFX9) {
449 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
450 switch (image->info.samples) {
451 case 2:
452 num_format = V_008F14_IMG_FMASK_8_2_2;
453 break;
454 case 4:
455 num_format = V_008F14_IMG_FMASK_8_4_4;
456 break;
457 case 8:
458 num_format = V_008F14_IMG_FMASK_32_8_8;
459 break;
460 default:
461 unreachable("invalid nr_samples");
462 }
463 } else {
464 switch (image->info.samples) {
465 case 2:
466 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
467 break;
468 case 4:
469 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
470 break;
471 case 8:
472 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
473 break;
474 default:
475 assert(0);
476 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
477 }
478 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
479 }
480
481 fmask_state[0] = va >> 8;
482 if (device->physical_device->rad_info.chip_class < GFX9)
483 fmask_state[0] |= image->fmask.tile_swizzle;
484 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
485 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
486 S_008F14_NUM_FORMAT_GFX6(num_format);
487 fmask_state[2] = S_008F18_WIDTH(width - 1) |
488 S_008F18_HEIGHT(height - 1);
489 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
490 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
491 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
492 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
493 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
494 fmask_state[4] = 0;
495 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
496 fmask_state[6] = 0;
497 fmask_state[7] = 0;
498
499 if (device->physical_device->rad_info.chip_class >= GFX9) {
500 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
501 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
502 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
503 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
504 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
505 } else {
506 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
507 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
508 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
509 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
510 }
511 } else if (fmask_state)
512 memset(fmask_state, 0, 8 * 4);
513 }
514
515 static void
516 radv_query_opaque_metadata(struct radv_device *device,
517 struct radv_image *image,
518 struct radeon_bo_metadata *md)
519 {
520 static const VkComponentMapping fixedmapping;
521 uint32_t desc[8], i;
522
523 /* Metadata image format format version 1:
524 * [0] = 1 (metadata format identifier)
525 * [1] = (VENDOR_ID << 16) | PCI_ID
526 * [2:9] = image descriptor for the whole resource
527 * [2] is always 0, because the base address is cleared
528 * [9] is the DCC offset bits [39:8] from the beginning of
529 * the buffer
530 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
531 */
532 md->metadata[0] = 1; /* metadata image format version 1 */
533
534 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
535 md->metadata[1] = si_get_bo_metadata_word1(device);
536
537
538 si_make_texture_descriptor(device, image, false,
539 (VkImageViewType)image->type, image->vk_format,
540 &fixedmapping, 0, image->info.levels - 1, 0,
541 image->info.array_size,
542 image->info.width, image->info.height,
543 image->info.depth,
544 desc, NULL);
545
546 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
547 image->surface.blk_w, false, desc);
548
549 /* Clear the base address and set the relative DCC offset. */
550 desc[0] = 0;
551 desc[1] &= C_008F14_BASE_ADDRESS_HI;
552 desc[7] = image->dcc_offset >> 8;
553
554 /* Dwords [2:9] contain the image descriptor. */
555 memcpy(&md->metadata[2], desc, sizeof(desc));
556
557 /* Dwords [10:..] contain the mipmap level offsets. */
558 if (device->physical_device->rad_info.chip_class <= VI) {
559 for (i = 0; i <= image->info.levels - 1; i++)
560 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
561 md->size_metadata = (11 + image->info.levels - 1) * 4;
562 }
563 }
564
565 void
566 radv_init_metadata(struct radv_device *device,
567 struct radv_image *image,
568 struct radeon_bo_metadata *metadata)
569 {
570 struct radeon_surf *surface = &image->surface;
571
572 memset(metadata, 0, sizeof(*metadata));
573
574 if (device->physical_device->rad_info.chip_class >= GFX9) {
575 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
576 } else {
577 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
578 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
579 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
580 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
581 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
582 metadata->u.legacy.bankw = surface->u.legacy.bankw;
583 metadata->u.legacy.bankh = surface->u.legacy.bankh;
584 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
585 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
586 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
587 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
588 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
589 }
590 radv_query_opaque_metadata(device, image, metadata);
591 }
592
593 /* The number of samples can be specified independently of the texture. */
594 static void
595 radv_image_get_fmask_info(struct radv_device *device,
596 struct radv_image *image,
597 unsigned nr_samples,
598 struct radv_fmask_info *out)
599 {
600 /* FMASK is allocated like an ordinary texture. */
601 struct radeon_surf fmask = {};
602 struct ac_surf_info info = image->info;
603 memset(out, 0, sizeof(*out));
604
605 if (device->physical_device->rad_info.chip_class >= GFX9) {
606 out->alignment = image->surface.u.gfx9.fmask_alignment;
607 out->size = image->surface.u.gfx9.fmask_size;
608 return;
609 }
610
611 fmask.blk_w = image->surface.blk_w;
612 fmask.blk_h = image->surface.blk_h;
613 info.samples = 1;
614 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
615
616 if (!image->shareable)
617 info.surf_index = &device->fmask_mrt_offset_counter;
618
619 /* Force 2D tiling if it wasn't set. This may occur when creating
620 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
621 * destination buffer must have an FMASK too. */
622 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
623 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
624
625 switch (nr_samples) {
626 case 2:
627 case 4:
628 fmask.bpe = 1;
629 break;
630 case 8:
631 fmask.bpe = 4;
632 break;
633 default:
634 return;
635 }
636
637 device->ws->surface_init(device->ws, &info, &fmask);
638 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
639
640 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
641 if (out->slice_tile_max)
642 out->slice_tile_max -= 1;
643
644 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
645 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
646 out->bank_height = fmask.u.legacy.bankh;
647 out->tile_swizzle = fmask.tile_swizzle;
648 out->alignment = MAX2(256, fmask.surf_alignment);
649 out->size = fmask.surf_size;
650
651 assert(!out->tile_swizzle || !image->shareable);
652 }
653
654 static void
655 radv_image_alloc_fmask(struct radv_device *device,
656 struct radv_image *image)
657 {
658 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
659
660 image->fmask.offset = align64(image->size, image->fmask.alignment);
661 image->size = image->fmask.offset + image->fmask.size;
662 image->alignment = MAX2(image->alignment, image->fmask.alignment);
663 }
664
665 static void
666 radv_image_get_cmask_info(struct radv_device *device,
667 struct radv_image *image,
668 struct radv_cmask_info *out)
669 {
670 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
671 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
672 unsigned cl_width, cl_height;
673
674 if (device->physical_device->rad_info.chip_class >= GFX9) {
675 out->alignment = image->surface.u.gfx9.cmask_alignment;
676 out->size = image->surface.u.gfx9.cmask_size;
677 return;
678 }
679
680 switch (num_pipes) {
681 case 2:
682 cl_width = 32;
683 cl_height = 16;
684 break;
685 case 4:
686 cl_width = 32;
687 cl_height = 32;
688 break;
689 case 8:
690 cl_width = 64;
691 cl_height = 32;
692 break;
693 case 16: /* Hawaii */
694 cl_width = 64;
695 cl_height = 64;
696 break;
697 default:
698 assert(0);
699 return;
700 }
701
702 unsigned base_align = num_pipes * pipe_interleave_bytes;
703
704 unsigned width = align(image->info.width, cl_width*8);
705 unsigned height = align(image->info.height, cl_height*8);
706 unsigned slice_elements = (width * height) / (8*8);
707
708 /* Each element of CMASK is a nibble. */
709 unsigned slice_bytes = slice_elements / 2;
710
711 out->slice_tile_max = (width * height) / (128*128);
712 if (out->slice_tile_max)
713 out->slice_tile_max -= 1;
714
715 out->alignment = MAX2(256, base_align);
716 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
717 align(slice_bytes, base_align);
718 }
719
720 static void
721 radv_image_alloc_cmask(struct radv_device *device,
722 struct radv_image *image)
723 {
724 uint32_t clear_value_size = 0;
725 radv_image_get_cmask_info(device, image, &image->cmask);
726
727 image->cmask.offset = align64(image->size, image->cmask.alignment);
728 /* + 8 for storing the clear values */
729 if (!image->clear_value_offset) {
730 image->clear_value_offset = image->cmask.offset + image->cmask.size;
731 clear_value_size = 8;
732 }
733 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
734 image->alignment = MAX2(image->alignment, image->cmask.alignment);
735 }
736
737 static void
738 radv_image_alloc_dcc(struct radv_device *device,
739 struct radv_image *image)
740 {
741 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
742 /* + 16 for storing the clear values + dcc pred */
743 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
744 image->dcc_pred_offset = image->clear_value_offset + 8;
745 image->size = image->dcc_offset + image->surface.dcc_size + 16;
746 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
747 }
748
749 static void
750 radv_image_alloc_htile(struct radv_device *device,
751 struct radv_image *image)
752 {
753 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
754 image->surface.htile_size = 0;
755 return;
756 }
757
758 image->htile_offset = align64(image->size, image->surface.htile_alignment);
759
760 /* + 8 for storing the clear values */
761 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
762 image->size = image->clear_value_offset + 8;
763 image->alignment = align64(image->alignment, image->surface.htile_alignment);
764 }
765
766 VkResult
767 radv_image_create(VkDevice _device,
768 const struct radv_image_create_info *create_info,
769 const VkAllocationCallbacks* alloc,
770 VkImage *pImage)
771 {
772 RADV_FROM_HANDLE(radv_device, device, _device);
773 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
774 struct radv_image *image = NULL;
775 bool can_cmask_dcc = false;
776 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
777
778 radv_assert(pCreateInfo->mipLevels > 0);
779 radv_assert(pCreateInfo->arrayLayers > 0);
780 radv_assert(pCreateInfo->samples > 0);
781 radv_assert(pCreateInfo->extent.width > 0);
782 radv_assert(pCreateInfo->extent.height > 0);
783 radv_assert(pCreateInfo->extent.depth > 0);
784
785 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
786 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
787 if (!image)
788 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
789
790 memset(image, 0, sizeof(*image));
791 image->type = pCreateInfo->imageType;
792 image->info.width = pCreateInfo->extent.width;
793 image->info.height = pCreateInfo->extent.height;
794 image->info.depth = pCreateInfo->extent.depth;
795 image->info.samples = pCreateInfo->samples;
796 image->info.array_size = pCreateInfo->arrayLayers;
797 image->info.levels = pCreateInfo->mipLevels;
798
799 image->vk_format = pCreateInfo->format;
800 image->tiling = pCreateInfo->tiling;
801 image->usage = pCreateInfo->usage;
802 image->flags = pCreateInfo->flags;
803
804 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
805 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
806 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
807 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
808 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
809 else
810 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
811 }
812
813 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
814 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
815 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
816 image->info.surf_index = &device->image_mrt_offset_counter;
817 }
818
819 radv_init_surface(device, &image->surface, create_info);
820
821 device->ws->surface_init(device->ws, &image->info, &image->surface);
822
823 image->size = image->surface.surf_size;
824 image->alignment = image->surface.surf_alignment;
825
826 if (image->exclusive || image->queue_family_mask == 1)
827 can_cmask_dcc = true;
828
829 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
830 image->surface.dcc_size && can_cmask_dcc)
831 radv_image_alloc_dcc(device, image);
832 else
833 image->surface.dcc_size = 0;
834
835 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
836 pCreateInfo->mipLevels == 1 &&
837 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
838 radv_image_alloc_cmask(device, image);
839 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
840 radv_image_alloc_fmask(device, image);
841 } else if (vk_format_is_depth(pCreateInfo->format)) {
842
843 radv_image_alloc_htile(device, image);
844 }
845
846 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
847 image->alignment = MAX2(image->alignment, 4096);
848 image->size = align64(image->size, image->alignment);
849 image->offset = 0;
850
851 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
852 0, RADEON_FLAG_VIRTUAL);
853 if (!image->bo) {
854 vk_free2(&device->alloc, alloc, image);
855 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
856 }
857 }
858
859 *pImage = radv_image_to_handle(image);
860
861 return VK_SUCCESS;
862 }
863
864 static void
865 radv_image_view_make_descriptor(struct radv_image_view *iview,
866 struct radv_device *device,
867 const VkImageViewCreateInfo* pCreateInfo,
868 bool is_storage_image)
869 {
870 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
871 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
872 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
873 uint32_t blk_w;
874 uint32_t *descriptor;
875 uint32_t *fmask_descriptor;
876
877 if (is_storage_image) {
878 descriptor = iview->storage_descriptor;
879 fmask_descriptor = iview->storage_fmask_descriptor;
880 } else {
881 descriptor = iview->descriptor;
882 fmask_descriptor = iview->fmask_descriptor;
883 }
884
885 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
886 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
887
888 si_make_texture_descriptor(device, image, is_storage_image,
889 iview->type,
890 iview->vk_format,
891 &pCreateInfo->components,
892 0, radv_get_levelCount(image, range) - 1,
893 range->baseArrayLayer,
894 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
895 iview->extent.width,
896 iview->extent.height,
897 iview->extent.depth,
898 descriptor,
899 fmask_descriptor);
900 si_set_mutable_tex_desc_fields(device, image,
901 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
902 : &image->surface.u.legacy.level[range->baseMipLevel],
903 range->baseMipLevel,
904 range->baseMipLevel,
905 blk_w, is_stencil, descriptor);
906 }
907
908 void
909 radv_image_view_init(struct radv_image_view *iview,
910 struct radv_device *device,
911 const VkImageViewCreateInfo* pCreateInfo)
912 {
913 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
914 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
915
916 switch (image->type) {
917 case VK_IMAGE_TYPE_1D:
918 case VK_IMAGE_TYPE_2D:
919 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
920 break;
921 case VK_IMAGE_TYPE_3D:
922 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
923 <= radv_minify(image->info.depth, range->baseMipLevel));
924 break;
925 default:
926 unreachable("bad VkImageType");
927 }
928 iview->image = image;
929 iview->bo = image->bo;
930 iview->type = pCreateInfo->viewType;
931 iview->vk_format = pCreateInfo->format;
932 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
933
934 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
935 iview->vk_format = vk_format_stencil_only(iview->vk_format);
936 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
937 iview->vk_format = vk_format_depth_only(iview->vk_format);
938 }
939
940 iview->extent = (VkExtent3D) {
941 .width = radv_minify(image->info.width , range->baseMipLevel),
942 .height = radv_minify(image->info.height, range->baseMipLevel),
943 .depth = radv_minify(image->info.depth , range->baseMipLevel),
944 };
945
946 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
947 vk_format_get_blockwidth(image->vk_format));
948 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
949 vk_format_get_blockheight(image->vk_format));
950
951 iview->base_layer = range->baseArrayLayer;
952 iview->layer_count = radv_get_layerCount(image, range);
953 iview->base_mip = range->baseMipLevel;
954
955 radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
956 radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
957 }
958
959 bool radv_layout_has_htile(const struct radv_image *image,
960 VkImageLayout layout,
961 unsigned queue_mask)
962 {
963 return image->surface.htile_size &&
964 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
965 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
966 queue_mask == (1u << RADV_QUEUE_GENERAL);
967 }
968
969 bool radv_layout_is_htile_compressed(const struct radv_image *image,
970 VkImageLayout layout,
971 unsigned queue_mask)
972 {
973 return image->surface.htile_size &&
974 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
975 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
976 queue_mask == (1u << RADV_QUEUE_GENERAL);
977 }
978
979 bool radv_layout_can_fast_clear(const struct radv_image *image,
980 VkImageLayout layout,
981 unsigned queue_mask)
982 {
983 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
984 queue_mask == (1u << RADV_QUEUE_GENERAL);
985 }
986
987
988 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
989 {
990 if (!image->exclusive)
991 return image->queue_family_mask;
992 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
993 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
994 if (family == VK_QUEUE_FAMILY_IGNORED)
995 return 1u << queue_family;
996 return 1u << family;
997 }
998
999 VkResult
1000 radv_CreateImage(VkDevice device,
1001 const VkImageCreateInfo *pCreateInfo,
1002 const VkAllocationCallbacks *pAllocator,
1003 VkImage *pImage)
1004 {
1005 return radv_image_create(device,
1006 &(struct radv_image_create_info) {
1007 .vk_info = pCreateInfo,
1008 .scanout = false,
1009 },
1010 pAllocator,
1011 pImage);
1012 }
1013
1014 void
1015 radv_DestroyImage(VkDevice _device, VkImage _image,
1016 const VkAllocationCallbacks *pAllocator)
1017 {
1018 RADV_FROM_HANDLE(radv_device, device, _device);
1019 RADV_FROM_HANDLE(radv_image, image, _image);
1020
1021 if (!image)
1022 return;
1023
1024 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1025 device->ws->buffer_destroy(image->bo);
1026
1027 vk_free2(&device->alloc, pAllocator, image);
1028 }
1029
1030 void radv_GetImageSubresourceLayout(
1031 VkDevice device,
1032 VkImage _image,
1033 const VkImageSubresource* pSubresource,
1034 VkSubresourceLayout* pLayout)
1035 {
1036 RADV_FROM_HANDLE(radv_image, image, _image);
1037 int level = pSubresource->mipLevel;
1038 int layer = pSubresource->arrayLayer;
1039 struct radeon_surf *surface = &image->surface;
1040
1041 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1042 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1043 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1044 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1045 pLayout->size = surface->u.legacy.level[level].slice_size;
1046 if (image->type == VK_IMAGE_TYPE_3D)
1047 pLayout->size *= u_minify(image->info.depth, level);
1048 }
1049
1050
1051 VkResult
1052 radv_CreateImageView(VkDevice _device,
1053 const VkImageViewCreateInfo *pCreateInfo,
1054 const VkAllocationCallbacks *pAllocator,
1055 VkImageView *pView)
1056 {
1057 RADV_FROM_HANDLE(radv_device, device, _device);
1058 struct radv_image_view *view;
1059
1060 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1062 if (view == NULL)
1063 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1064
1065 radv_image_view_init(view, device, pCreateInfo);
1066
1067 *pView = radv_image_view_to_handle(view);
1068
1069 return VK_SUCCESS;
1070 }
1071
1072 void
1073 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1074 const VkAllocationCallbacks *pAllocator)
1075 {
1076 RADV_FROM_HANDLE(radv_device, device, _device);
1077 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1078
1079 if (!iview)
1080 return;
1081 vk_free2(&device->alloc, pAllocator, iview);
1082 }
1083
1084 void radv_buffer_view_init(struct radv_buffer_view *view,
1085 struct radv_device *device,
1086 const VkBufferViewCreateInfo* pCreateInfo,
1087 struct radv_cmd_buffer *cmd_buffer)
1088 {
1089 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1090
1091 view->bo = buffer->bo;
1092 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1093 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1094 view->vk_format = pCreateInfo->format;
1095
1096 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1097 pCreateInfo->offset, view->range, view->state);
1098 }
1099
1100 VkResult
1101 radv_CreateBufferView(VkDevice _device,
1102 const VkBufferViewCreateInfo *pCreateInfo,
1103 const VkAllocationCallbacks *pAllocator,
1104 VkBufferView *pView)
1105 {
1106 RADV_FROM_HANDLE(radv_device, device, _device);
1107 struct radv_buffer_view *view;
1108
1109 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1110 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1111 if (!view)
1112 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1113
1114 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1115
1116 *pView = radv_buffer_view_to_handle(view);
1117
1118 return VK_SUCCESS;
1119 }
1120
1121 void
1122 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1123 const VkAllocationCallbacks *pAllocator)
1124 {
1125 RADV_FROM_HANDLE(radv_device, device, _device);
1126 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1127
1128 if (!view)
1129 return;
1130
1131 vk_free2(&device->alloc, pAllocator, view);
1132 }