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radv: set correct INDEX_TYPE for indexed indirect draws on GFX9
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66 static int
67 radv_init_surface(struct radv_device *device,
68 struct radeon_surf *surface,
69 const struct radv_image_create_info *create_info)
70 {
71 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
72 unsigned array_mode = radv_choose_tiling(device, create_info);
73 const struct vk_format_description *desc =
74 vk_format_description(pCreateInfo->format);
75 bool is_depth, is_stencil, blendable;
76
77 is_depth = vk_format_has_depth(desc);
78 is_stencil = vk_format_has_stencil(desc);
79
80 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
81 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
82
83 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
84 /* align byte per element on dword */
85 if (surface->bpe == 3) {
86 surface->bpe = 4;
87 }
88 surface->flags = RADEON_SURF_SET(array_mode, MODE);
89
90 switch (pCreateInfo->imageType){
91 case VK_IMAGE_TYPE_1D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_2D:
98 if (pCreateInfo->arrayLayers > 1)
99 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
100 else
101 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
102 break;
103 case VK_IMAGE_TYPE_3D:
104 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
105 break;
106 default:
107 unreachable("unhandled image type");
108 }
109
110 if (is_depth) {
111 surface->flags |= RADEON_SURF_ZBUFFER;
112 if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
113 !(pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
114 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR)) &&
115 pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
116 pCreateInfo->mipLevels <= 1 &&
117 device->physical_device->rad_info.chip_class >= VI &&
118 ((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
119 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
120 (device->physical_device->rad_info.chip_class >= GFX9 &&
121 pCreateInfo->format == VK_FORMAT_D16_UNORM)))
122 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
123 }
124
125 if (is_stencil)
126 surface->flags |= RADEON_SURF_SBUFFER;
127
128 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
129
130 bool dcc_compatible_formats = !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
131 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
132 const struct VkImageFormatListCreateInfoKHR *format_list =
133 (const struct VkImageFormatListCreateInfoKHR *)
134 vk_find_struct_const(pCreateInfo->pNext,
135 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
136
137 /* We have to ignore the existence of the list if viewFormatCount = 0 */
138 if (format_list && format_list->viewFormatCount) {
139 /* compatibility is transitive, so we only need to check
140 * one format with everything else. */
141 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
142 if (!radv_dcc_formats_compatible(pCreateInfo->format,
143 format_list->pViewFormats[i]))
144 dcc_compatible_formats = false;
145 }
146 } else {
147 dcc_compatible_formats = false;
148 }
149 }
150
151 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
152 VK_IMAGE_USAGE_STORAGE_BIT)) ||
153 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
154 !dcc_compatible_formats ||
155 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
156 pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
157 device->physical_device->rad_info.chip_class < VI ||
158 create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC))
159 surface->flags |= RADEON_SURF_DISABLE_DCC;
160 if (create_info->scanout)
161 surface->flags |= RADEON_SURF_SCANOUT;
162 return 0;
163 }
164
165 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
166 {
167 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
168 }
169
170 static inline unsigned
171 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
172 {
173 if (stencil)
174 return image->surface.u.legacy.stencil_tiling_index[level];
175 else
176 return image->surface.u.legacy.tiling_index[level];
177 }
178
179 static unsigned radv_map_swizzle(unsigned swizzle)
180 {
181 switch (swizzle) {
182 case VK_SWIZZLE_Y:
183 return V_008F0C_SQ_SEL_Y;
184 case VK_SWIZZLE_Z:
185 return V_008F0C_SQ_SEL_Z;
186 case VK_SWIZZLE_W:
187 return V_008F0C_SQ_SEL_W;
188 case VK_SWIZZLE_0:
189 return V_008F0C_SQ_SEL_0;
190 case VK_SWIZZLE_1:
191 return V_008F0C_SQ_SEL_1;
192 default: /* VK_SWIZZLE_X */
193 return V_008F0C_SQ_SEL_X;
194 }
195 }
196
197 static void
198 radv_make_buffer_descriptor(struct radv_device *device,
199 struct radv_buffer *buffer,
200 VkFormat vk_format,
201 unsigned offset,
202 unsigned range,
203 uint32_t *state)
204 {
205 const struct vk_format_description *desc;
206 unsigned stride;
207 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
208 uint64_t va = gpu_address + buffer->offset;
209 unsigned num_format, data_format;
210 int first_non_void;
211 desc = vk_format_description(vk_format);
212 first_non_void = vk_format_get_first_non_void_channel(vk_format);
213 stride = desc->block.bits / 8;
214
215 num_format = radv_translate_buffer_numformat(desc, first_non_void);
216 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
217
218 va += offset;
219 state[0] = va;
220 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
221 S_008F04_STRIDE(stride);
222
223 if (device->physical_device->rad_info.chip_class != VI && stride) {
224 range /= stride;
225 }
226
227 state[2] = range;
228 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
229 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
230 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
231 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
232 S_008F0C_NUM_FORMAT(num_format) |
233 S_008F0C_DATA_FORMAT(data_format);
234 }
235
236 static void
237 si_set_mutable_tex_desc_fields(struct radv_device *device,
238 struct radv_image *image,
239 const struct legacy_surf_level *base_level_info,
240 unsigned base_level, unsigned first_level,
241 unsigned block_width, bool is_stencil,
242 uint32_t *state)
243 {
244 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
245 uint64_t va = gpu_address;
246 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
247 uint64_t meta_va = 0;
248 if (chip_class >= GFX9) {
249 if (is_stencil)
250 va += image->surface.u.gfx9.stencil_offset;
251 else
252 va += image->surface.u.gfx9.surf_offset;
253 } else
254 va += base_level_info->offset;
255
256 state[0] = va >> 8;
257 if (chip_class >= GFX9 ||
258 base_level_info->mode == RADEON_SURF_MODE_2D)
259 state[0] |= image->surface.tile_swizzle;
260 state[1] &= C_008F14_BASE_ADDRESS_HI;
261 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
262
263 if (chip_class >= VI) {
264 state[6] &= C_008F28_COMPRESSION_EN;
265 state[7] = 0;
266 if (radv_vi_dcc_enabled(image, first_level)) {
267 meta_va = gpu_address + image->dcc_offset;
268 if (chip_class <= VI)
269 meta_va += base_level_info->dcc_offset;
270 } else if(image->tc_compatible_htile && image->surface.htile_size) {
271 meta_va = gpu_address + image->htile_offset;
272 }
273
274 if (meta_va) {
275 state[6] |= S_008F28_COMPRESSION_EN(1);
276 state[7] = meta_va >> 8;
277 state[7] |= image->surface.tile_swizzle;
278 }
279 }
280
281 if (chip_class >= GFX9) {
282 state[3] &= C_008F1C_SW_MODE;
283 state[4] &= C_008F20_PITCH_GFX9;
284
285 if (is_stencil) {
286 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
287 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
288 } else {
289 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
290 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
291 }
292
293 state[5] &= C_008F24_META_DATA_ADDRESS &
294 C_008F24_META_PIPE_ALIGNED &
295 C_008F24_META_RB_ALIGNED;
296 if (meta_va) {
297 struct gfx9_surf_meta_flags meta;
298
299 if (image->dcc_offset)
300 meta = image->surface.u.gfx9.dcc;
301 else
302 meta = image->surface.u.gfx9.htile;
303
304 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
305 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
306 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
307 }
308 } else {
309 /* SI-CI-VI */
310 unsigned pitch = base_level_info->nblk_x * block_width;
311 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
312
313 state[3] &= C_008F1C_TILING_INDEX;
314 state[3] |= S_008F1C_TILING_INDEX(index);
315 state[4] &= C_008F20_PITCH_GFX6;
316 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
317 }
318 }
319
320 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
321 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
322 {
323 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
324 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
325
326 /* GFX9 allocates 1D textures as 2D. */
327 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
328 image_type = VK_IMAGE_TYPE_2D;
329 switch (image_type) {
330 case VK_IMAGE_TYPE_1D:
331 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
332 case VK_IMAGE_TYPE_2D:
333 if (nr_samples > 1)
334 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
335 else
336 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
337 case VK_IMAGE_TYPE_3D:
338 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
339 return V_008F1C_SQ_RSRC_IMG_3D;
340 else
341 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
342 default:
343 unreachable("illegale image type");
344 }
345 }
346
347 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
348 {
349 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
350
351 if (swizzle[3] == VK_SWIZZLE_X) {
352 /* For the pre-defined border color values (white, opaque
353 * black, transparent black), the only thing that matters is
354 * that the alpha channel winds up in the correct place
355 * (because the RGB channels are all the same) so either of
356 * these enumerations will work.
357 */
358 if (swizzle[2] == VK_SWIZZLE_Y)
359 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
360 else
361 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
362 } else if (swizzle[0] == VK_SWIZZLE_X) {
363 if (swizzle[1] == VK_SWIZZLE_Y)
364 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
365 else
366 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
367 } else if (swizzle[1] == VK_SWIZZLE_X) {
368 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
369 } else if (swizzle[2] == VK_SWIZZLE_X) {
370 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
371 }
372
373 return bc_swizzle;
374 }
375
376 /**
377 * Build the sampler view descriptor for a texture.
378 */
379 static void
380 si_make_texture_descriptor(struct radv_device *device,
381 struct radv_image *image,
382 bool is_storage_image,
383 VkImageViewType view_type,
384 VkFormat vk_format,
385 const VkComponentMapping *mapping,
386 unsigned first_level, unsigned last_level,
387 unsigned first_layer, unsigned last_layer,
388 unsigned width, unsigned height, unsigned depth,
389 uint32_t *state,
390 uint32_t *fmask_state)
391 {
392 const struct vk_format_description *desc;
393 enum vk_swizzle swizzle[4];
394 int first_non_void;
395 unsigned num_format, data_format, type;
396
397 desc = vk_format_description(vk_format);
398
399 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
400 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
401 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
402 } else {
403 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
404 }
405
406 first_non_void = vk_format_get_first_non_void_channel(vk_format);
407
408 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
409 if (num_format == ~0) {
410 num_format = 0;
411 }
412
413 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
414 if (data_format == ~0) {
415 data_format = 0;
416 }
417
418 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
419 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
420 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
421 height = 1;
422 depth = image->info.array_size;
423 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
424 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
425 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
426 depth = image->info.array_size;
427 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
428 depth = image->info.array_size / 6;
429
430 state[0] = 0;
431 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
432 S_008F14_NUM_FORMAT_GFX6(num_format));
433 state[2] = (S_008F18_WIDTH(width - 1) |
434 S_008F18_HEIGHT(height - 1) |
435 S_008F18_PERF_MOD(4));
436 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
437 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
438 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
439 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
440 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
441 0 : first_level) |
442 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
443 util_logbase2(image->info.samples) :
444 last_level) |
445 S_008F1C_TYPE(type));
446 state[4] = 0;
447 state[5] = S_008F24_BASE_ARRAY(first_layer);
448 state[6] = 0;
449 state[7] = 0;
450
451 if (device->physical_device->rad_info.chip_class >= GFX9) {
452 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
453
454 /* Depth is the the last accessible layer on Gfx9.
455 * The hw doesn't need to know the total number of layers.
456 */
457 if (type == V_008F1C_SQ_RSRC_IMG_3D)
458 state[4] |= S_008F20_DEPTH(depth - 1);
459 else
460 state[4] |= S_008F20_DEPTH(last_layer);
461
462 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
463 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
464 util_logbase2(image->info.samples) :
465 image->info.levels - 1);
466 } else {
467 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
468 state[4] |= S_008F20_DEPTH(depth - 1);
469 state[5] |= S_008F24_LAST_ARRAY(last_layer);
470 }
471 if (image->dcc_offset) {
472 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
473
474 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
475 } else {
476 /* The last dword is unused by hw. The shader uses it to clear
477 * bits in the first dword of sampler state.
478 */
479 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
480 if (first_level == last_level)
481 state[7] = C_008F30_MAX_ANISO_RATIO;
482 else
483 state[7] = 0xffffffff;
484 }
485 }
486
487 /* Initialize the sampler view for FMASK. */
488 if (image->fmask.size) {
489 uint32_t fmask_format, num_format;
490 uint64_t gpu_address = radv_buffer_get_va(image->bo);
491 uint64_t va;
492
493 va = gpu_address + image->offset + image->fmask.offset;
494
495 if (device->physical_device->rad_info.chip_class >= GFX9) {
496 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
497 switch (image->info.samples) {
498 case 2:
499 num_format = V_008F14_IMG_FMASK_8_2_2;
500 break;
501 case 4:
502 num_format = V_008F14_IMG_FMASK_8_4_4;
503 break;
504 case 8:
505 num_format = V_008F14_IMG_FMASK_32_8_8;
506 break;
507 default:
508 unreachable("invalid nr_samples");
509 }
510 } else {
511 switch (image->info.samples) {
512 case 2:
513 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
514 break;
515 case 4:
516 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
517 break;
518 case 8:
519 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
520 break;
521 default:
522 assert(0);
523 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
524 }
525 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
526 }
527
528 fmask_state[0] = va >> 8;
529 fmask_state[0] |= image->fmask.tile_swizzle;
530 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
531 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
532 S_008F14_NUM_FORMAT_GFX6(num_format);
533 fmask_state[2] = S_008F18_WIDTH(width - 1) |
534 S_008F18_HEIGHT(height - 1);
535 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
536 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
537 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
538 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
539 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
540 fmask_state[4] = 0;
541 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
542 fmask_state[6] = 0;
543 fmask_state[7] = 0;
544
545 if (device->physical_device->rad_info.chip_class >= GFX9) {
546 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
547 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
548 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
549 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
550 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
551 } else {
552 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
553 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
554 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
555 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
556 }
557 } else if (fmask_state)
558 memset(fmask_state, 0, 8 * 4);
559 }
560
561 static void
562 radv_query_opaque_metadata(struct radv_device *device,
563 struct radv_image *image,
564 struct radeon_bo_metadata *md)
565 {
566 static const VkComponentMapping fixedmapping;
567 uint32_t desc[8], i;
568
569 /* Metadata image format format version 1:
570 * [0] = 1 (metadata format identifier)
571 * [1] = (VENDOR_ID << 16) | PCI_ID
572 * [2:9] = image descriptor for the whole resource
573 * [2] is always 0, because the base address is cleared
574 * [9] is the DCC offset bits [39:8] from the beginning of
575 * the buffer
576 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
577 */
578 md->metadata[0] = 1; /* metadata image format version 1 */
579
580 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
581 md->metadata[1] = si_get_bo_metadata_word1(device);
582
583
584 si_make_texture_descriptor(device, image, false,
585 (VkImageViewType)image->type, image->vk_format,
586 &fixedmapping, 0, image->info.levels - 1, 0,
587 image->info.array_size,
588 image->info.width, image->info.height,
589 image->info.depth,
590 desc, NULL);
591
592 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
593 image->surface.blk_w, false, desc);
594
595 /* Clear the base address and set the relative DCC offset. */
596 desc[0] = 0;
597 desc[1] &= C_008F14_BASE_ADDRESS_HI;
598 desc[7] = image->dcc_offset >> 8;
599
600 /* Dwords [2:9] contain the image descriptor. */
601 memcpy(&md->metadata[2], desc, sizeof(desc));
602
603 /* Dwords [10:..] contain the mipmap level offsets. */
604 if (device->physical_device->rad_info.chip_class <= VI) {
605 for (i = 0; i <= image->info.levels - 1; i++)
606 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
607 md->size_metadata = (11 + image->info.levels - 1) * 4;
608 }
609 }
610
611 void
612 radv_init_metadata(struct radv_device *device,
613 struct radv_image *image,
614 struct radeon_bo_metadata *metadata)
615 {
616 struct radeon_surf *surface = &image->surface;
617
618 memset(metadata, 0, sizeof(*metadata));
619
620 if (device->physical_device->rad_info.chip_class >= GFX9) {
621 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
622 } else {
623 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
624 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
625 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
626 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
627 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
628 metadata->u.legacy.bankw = surface->u.legacy.bankw;
629 metadata->u.legacy.bankh = surface->u.legacy.bankh;
630 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
631 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
632 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
633 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
634 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
635 }
636 radv_query_opaque_metadata(device, image, metadata);
637 }
638
639 /* The number of samples can be specified independently of the texture. */
640 static void
641 radv_image_get_fmask_info(struct radv_device *device,
642 struct radv_image *image,
643 unsigned nr_samples,
644 struct radv_fmask_info *out)
645 {
646 /* FMASK is allocated like an ordinary texture. */
647 struct radeon_surf fmask = {};
648 struct ac_surf_info info = image->info;
649 memset(out, 0, sizeof(*out));
650
651 if (device->physical_device->rad_info.chip_class >= GFX9) {
652 out->alignment = image->surface.u.gfx9.fmask_alignment;
653 out->size = image->surface.u.gfx9.fmask_size;
654 return;
655 }
656
657 fmask.blk_w = image->surface.blk_w;
658 fmask.blk_h = image->surface.blk_h;
659 info.samples = 1;
660 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
661
662 if (!image->shareable)
663 info.surf_index = &device->fmask_mrt_offset_counter;
664
665 /* Force 2D tiling if it wasn't set. This may occur when creating
666 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
667 * destination buffer must have an FMASK too. */
668 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
669 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
670
671 switch (nr_samples) {
672 case 2:
673 case 4:
674 fmask.bpe = 1;
675 break;
676 case 8:
677 fmask.bpe = 4;
678 break;
679 default:
680 return;
681 }
682
683 device->ws->surface_init(device->ws, &info, &fmask);
684 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
685
686 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
687 if (out->slice_tile_max)
688 out->slice_tile_max -= 1;
689
690 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
691 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
692 out->bank_height = fmask.u.legacy.bankh;
693 out->tile_swizzle = fmask.tile_swizzle;
694 out->alignment = MAX2(256, fmask.surf_alignment);
695 out->size = fmask.surf_size;
696
697 assert(!out->tile_swizzle || !image->shareable);
698 }
699
700 static void
701 radv_image_alloc_fmask(struct radv_device *device,
702 struct radv_image *image)
703 {
704 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
705
706 image->fmask.offset = align64(image->size, image->fmask.alignment);
707 image->size = image->fmask.offset + image->fmask.size;
708 image->alignment = MAX2(image->alignment, image->fmask.alignment);
709 }
710
711 static void
712 radv_image_get_cmask_info(struct radv_device *device,
713 struct radv_image *image,
714 struct radv_cmask_info *out)
715 {
716 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
717 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
718 unsigned cl_width, cl_height;
719
720 if (device->physical_device->rad_info.chip_class >= GFX9) {
721 out->alignment = image->surface.u.gfx9.cmask_alignment;
722 out->size = image->surface.u.gfx9.cmask_size;
723 return;
724 }
725
726 switch (num_pipes) {
727 case 2:
728 cl_width = 32;
729 cl_height = 16;
730 break;
731 case 4:
732 cl_width = 32;
733 cl_height = 32;
734 break;
735 case 8:
736 cl_width = 64;
737 cl_height = 32;
738 break;
739 case 16: /* Hawaii */
740 cl_width = 64;
741 cl_height = 64;
742 break;
743 default:
744 assert(0);
745 return;
746 }
747
748 unsigned base_align = num_pipes * pipe_interleave_bytes;
749
750 unsigned width = align(image->info.width, cl_width*8);
751 unsigned height = align(image->info.height, cl_height*8);
752 unsigned slice_elements = (width * height) / (8*8);
753
754 /* Each element of CMASK is a nibble. */
755 unsigned slice_bytes = slice_elements / 2;
756
757 out->slice_tile_max = (width * height) / (128*128);
758 if (out->slice_tile_max)
759 out->slice_tile_max -= 1;
760
761 out->alignment = MAX2(256, base_align);
762 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
763 align(slice_bytes, base_align);
764 }
765
766 static void
767 radv_image_alloc_cmask(struct radv_device *device,
768 struct radv_image *image)
769 {
770 uint32_t clear_value_size = 0;
771 radv_image_get_cmask_info(device, image, &image->cmask);
772
773 image->cmask.offset = align64(image->size, image->cmask.alignment);
774 /* + 8 for storing the clear values */
775 if (!image->clear_value_offset) {
776 image->clear_value_offset = image->cmask.offset + image->cmask.size;
777 clear_value_size = 8;
778 }
779 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
780 image->alignment = MAX2(image->alignment, image->cmask.alignment);
781 }
782
783 static void
784 radv_image_alloc_dcc(struct radv_image *image)
785 {
786 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
787 /* + 16 for storing the clear values + dcc pred */
788 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
789 image->dcc_pred_offset = image->clear_value_offset + 8;
790 image->size = image->dcc_offset + image->surface.dcc_size + 16;
791 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
792 }
793
794 static void
795 radv_image_alloc_htile(struct radv_image *image)
796 {
797 image->htile_offset = align64(image->size, image->surface.htile_alignment);
798
799 /* + 8 for storing the clear values */
800 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
801 image->size = image->clear_value_offset + 8;
802 image->alignment = align64(image->alignment, image->surface.htile_alignment);
803 }
804
805 static inline bool
806 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
807 {
808 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
809 (image->exclusive || image->queue_family_mask == 1);
810 }
811
812 static inline bool
813 radv_image_can_enable_dcc(struct radv_image *image)
814 {
815 return radv_image_can_enable_dcc_or_cmask(image) &&
816 image->surface.dcc_size;
817 }
818
819 static inline bool
820 radv_image_can_enable_cmask(struct radv_image *image)
821 {
822 return radv_image_can_enable_dcc_or_cmask(image) &&
823 image->info.levels == 1 &&
824 image->info.depth == 1 &&
825 !image->surface.is_linear;
826 }
827
828 static inline bool
829 radv_image_can_enable_fmask(struct radv_image *image)
830 {
831 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
832 }
833
834 static inline bool
835 radv_image_can_enable_htile(struct radv_image *image)
836 {
837 return image->info.levels == 1 && vk_format_is_depth(image->vk_format);
838 }
839
840 VkResult
841 radv_image_create(VkDevice _device,
842 const struct radv_image_create_info *create_info,
843 const VkAllocationCallbacks* alloc,
844 VkImage *pImage)
845 {
846 RADV_FROM_HANDLE(radv_device, device, _device);
847 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
848 struct radv_image *image = NULL;
849 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
850
851 radv_assert(pCreateInfo->mipLevels > 0);
852 radv_assert(pCreateInfo->arrayLayers > 0);
853 radv_assert(pCreateInfo->samples > 0);
854 radv_assert(pCreateInfo->extent.width > 0);
855 radv_assert(pCreateInfo->extent.height > 0);
856 radv_assert(pCreateInfo->extent.depth > 0);
857
858 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
859 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
860 if (!image)
861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
862
863 memset(image, 0, sizeof(*image));
864 image->type = pCreateInfo->imageType;
865 image->info.width = pCreateInfo->extent.width;
866 image->info.height = pCreateInfo->extent.height;
867 image->info.depth = pCreateInfo->extent.depth;
868 image->info.samples = pCreateInfo->samples;
869 image->info.array_size = pCreateInfo->arrayLayers;
870 image->info.levels = pCreateInfo->mipLevels;
871
872 image->vk_format = pCreateInfo->format;
873 image->tiling = pCreateInfo->tiling;
874 image->usage = pCreateInfo->usage;
875 image->flags = pCreateInfo->flags;
876
877 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
878 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
879 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
880 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
881 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
882 else
883 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
884 }
885
886 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
887 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
888 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
889 image->info.surf_index = &device->image_mrt_offset_counter;
890 }
891
892 radv_init_surface(device, &image->surface, create_info);
893
894 device->ws->surface_init(device->ws, &image->info, &image->surface);
895
896 image->size = image->surface.surf_size;
897 image->alignment = image->surface.surf_alignment;
898
899 /* Try to enable DCC first. */
900 if (radv_image_can_enable_dcc(image)) {
901 radv_image_alloc_dcc(image);
902 } else {
903 /* When DCC cannot be enabled, try CMASK. */
904 image->surface.dcc_size = 0;
905 if (radv_image_can_enable_cmask(image)) {
906 radv_image_alloc_cmask(device, image);
907 }
908 }
909
910 /* Try to enable FMASK for multisampled images. */
911 if (radv_image_can_enable_fmask(image)) {
912 radv_image_alloc_fmask(device, image);
913 } else {
914 /* Otherwise, try to enable HTILE for depth surfaces. */
915 if (radv_image_can_enable_htile(image) &&
916 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
917 radv_image_alloc_htile(image);
918 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
919 } else {
920 image->surface.htile_size = 0;
921 }
922 }
923
924 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
925 image->alignment = MAX2(image->alignment, 4096);
926 image->size = align64(image->size, image->alignment);
927 image->offset = 0;
928
929 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
930 0, RADEON_FLAG_VIRTUAL);
931 if (!image->bo) {
932 vk_free2(&device->alloc, alloc, image);
933 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
934 }
935 }
936
937 *pImage = radv_image_to_handle(image);
938
939 return VK_SUCCESS;
940 }
941
942 static void
943 radv_image_view_make_descriptor(struct radv_image_view *iview,
944 struct radv_device *device,
945 const VkComponentMapping *components,
946 bool is_storage_image)
947 {
948 struct radv_image *image = iview->image;
949 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
950 uint32_t blk_w;
951 uint32_t *descriptor;
952 uint32_t *fmask_descriptor;
953 uint32_t hw_level = 0;
954
955 if (is_storage_image) {
956 descriptor = iview->storage_descriptor;
957 fmask_descriptor = iview->storage_fmask_descriptor;
958 } else {
959 descriptor = iview->descriptor;
960 fmask_descriptor = iview->fmask_descriptor;
961 }
962
963 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
964 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
965
966 if (device->physical_device->rad_info.chip_class >= GFX9)
967 hw_level = iview->base_mip;
968 si_make_texture_descriptor(device, image, is_storage_image,
969 iview->type,
970 iview->vk_format,
971 components,
972 hw_level, hw_level + iview->level_count - 1,
973 iview->base_layer,
974 iview->base_layer + iview->layer_count - 1,
975 iview->extent.width,
976 iview->extent.height,
977 iview->extent.depth,
978 descriptor,
979 fmask_descriptor);
980
981 const struct legacy_surf_level *base_level_info = NULL;
982 if (device->physical_device->rad_info.chip_class <= GFX9) {
983 if (is_stencil)
984 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
985 else
986 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
987 }
988 si_set_mutable_tex_desc_fields(device, image,
989 base_level_info,
990 iview->base_mip,
991 iview->base_mip,
992 blk_w, is_stencil, descriptor);
993 }
994
995 void
996 radv_image_view_init(struct radv_image_view *iview,
997 struct radv_device *device,
998 const VkImageViewCreateInfo* pCreateInfo)
999 {
1000 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1001 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1002
1003 switch (image->type) {
1004 case VK_IMAGE_TYPE_1D:
1005 case VK_IMAGE_TYPE_2D:
1006 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1007 break;
1008 case VK_IMAGE_TYPE_3D:
1009 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1010 <= radv_minify(image->info.depth, range->baseMipLevel));
1011 break;
1012 default:
1013 unreachable("bad VkImageType");
1014 }
1015 iview->image = image;
1016 iview->bo = image->bo;
1017 iview->type = pCreateInfo->viewType;
1018 iview->vk_format = pCreateInfo->format;
1019 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1020
1021 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1022 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1023 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1024 iview->vk_format = vk_format_depth_only(iview->vk_format);
1025 }
1026
1027 if (device->physical_device->rad_info.chip_class >= GFX9) {
1028 iview->extent = (VkExtent3D) {
1029 .width = image->info.width,
1030 .height = image->info.height,
1031 .depth = image->info.depth,
1032 };
1033 } else {
1034 iview->extent = (VkExtent3D) {
1035 .width = radv_minify(image->info.width , range->baseMipLevel),
1036 .height = radv_minify(image->info.height, range->baseMipLevel),
1037 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1038 };
1039 }
1040
1041 if (iview->vk_format != image->vk_format) {
1042 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
1043 vk_format_get_blockwidth(image->vk_format));
1044 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
1045 vk_format_get_blockheight(image->vk_format));
1046 }
1047
1048 iview->base_layer = range->baseArrayLayer;
1049 iview->layer_count = radv_get_layerCount(image, range);
1050 iview->base_mip = range->baseMipLevel;
1051 iview->level_count = radv_get_levelCount(image, range);
1052
1053 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1054 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1055 }
1056
1057 bool radv_layout_has_htile(const struct radv_image *image,
1058 VkImageLayout layout,
1059 unsigned queue_mask)
1060 {
1061 if (image->surface.htile_size && image->tc_compatible_htile)
1062 return layout != VK_IMAGE_LAYOUT_GENERAL;
1063
1064 return image->surface.htile_size &&
1065 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1066 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1067 queue_mask == (1u << RADV_QUEUE_GENERAL);
1068 }
1069
1070 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1071 VkImageLayout layout,
1072 unsigned queue_mask)
1073 {
1074 if (image->surface.htile_size && image->tc_compatible_htile)
1075 return layout != VK_IMAGE_LAYOUT_GENERAL;
1076
1077 return image->surface.htile_size &&
1078 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1079 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1080 queue_mask == (1u << RADV_QUEUE_GENERAL);
1081 }
1082
1083 bool radv_layout_can_fast_clear(const struct radv_image *image,
1084 VkImageLayout layout,
1085 unsigned queue_mask)
1086 {
1087 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1088 queue_mask == (1u << RADV_QUEUE_GENERAL);
1089 }
1090
1091
1092 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1093 {
1094 if (!image->exclusive)
1095 return image->queue_family_mask;
1096 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1097 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1098 if (family == VK_QUEUE_FAMILY_IGNORED)
1099 return 1u << queue_family;
1100 return 1u << family;
1101 }
1102
1103 VkResult
1104 radv_CreateImage(VkDevice device,
1105 const VkImageCreateInfo *pCreateInfo,
1106 const VkAllocationCallbacks *pAllocator,
1107 VkImage *pImage)
1108 {
1109 return radv_image_create(device,
1110 &(struct radv_image_create_info) {
1111 .vk_info = pCreateInfo,
1112 .scanout = false,
1113 },
1114 pAllocator,
1115 pImage);
1116 }
1117
1118 void
1119 radv_DestroyImage(VkDevice _device, VkImage _image,
1120 const VkAllocationCallbacks *pAllocator)
1121 {
1122 RADV_FROM_HANDLE(radv_device, device, _device);
1123 RADV_FROM_HANDLE(radv_image, image, _image);
1124
1125 if (!image)
1126 return;
1127
1128 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1129 device->ws->buffer_destroy(image->bo);
1130
1131 vk_free2(&device->alloc, pAllocator, image);
1132 }
1133
1134 void radv_GetImageSubresourceLayout(
1135 VkDevice _device,
1136 VkImage _image,
1137 const VkImageSubresource* pSubresource,
1138 VkSubresourceLayout* pLayout)
1139 {
1140 RADV_FROM_HANDLE(radv_image, image, _image);
1141 RADV_FROM_HANDLE(radv_device, device, _device);
1142 int level = pSubresource->mipLevel;
1143 int layer = pSubresource->arrayLayer;
1144 struct radeon_surf *surface = &image->surface;
1145
1146 if (device->physical_device->rad_info.chip_class >= GFX9) {
1147 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1148 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1149 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1150 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1151 pLayout->size = surface->u.gfx9.surf_slice_size;
1152 if (image->type == VK_IMAGE_TYPE_3D)
1153 pLayout->size *= u_minify(image->info.depth, level);
1154 } else {
1155 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1156 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1157 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1158 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1159 pLayout->size = surface->u.legacy.level[level].slice_size;
1160 if (image->type == VK_IMAGE_TYPE_3D)
1161 pLayout->size *= u_minify(image->info.depth, level);
1162 }
1163 }
1164
1165
1166 VkResult
1167 radv_CreateImageView(VkDevice _device,
1168 const VkImageViewCreateInfo *pCreateInfo,
1169 const VkAllocationCallbacks *pAllocator,
1170 VkImageView *pView)
1171 {
1172 RADV_FROM_HANDLE(radv_device, device, _device);
1173 struct radv_image_view *view;
1174
1175 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1176 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1177 if (view == NULL)
1178 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1179
1180 radv_image_view_init(view, device, pCreateInfo);
1181
1182 *pView = radv_image_view_to_handle(view);
1183
1184 return VK_SUCCESS;
1185 }
1186
1187 void
1188 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1189 const VkAllocationCallbacks *pAllocator)
1190 {
1191 RADV_FROM_HANDLE(radv_device, device, _device);
1192 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1193
1194 if (!iview)
1195 return;
1196 vk_free2(&device->alloc, pAllocator, iview);
1197 }
1198
1199 void radv_buffer_view_init(struct radv_buffer_view *view,
1200 struct radv_device *device,
1201 const VkBufferViewCreateInfo* pCreateInfo)
1202 {
1203 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1204
1205 view->bo = buffer->bo;
1206 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1207 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1208 view->vk_format = pCreateInfo->format;
1209
1210 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1211 pCreateInfo->offset, view->range, view->state);
1212 }
1213
1214 VkResult
1215 radv_CreateBufferView(VkDevice _device,
1216 const VkBufferViewCreateInfo *pCreateInfo,
1217 const VkAllocationCallbacks *pAllocator,
1218 VkBufferView *pView)
1219 {
1220 RADV_FROM_HANDLE(radv_device, device, _device);
1221 struct radv_buffer_view *view;
1222
1223 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1224 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1225 if (!view)
1226 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1227
1228 radv_buffer_view_init(view, device, pCreateInfo);
1229
1230 *pView = radv_buffer_view_to_handle(view);
1231
1232 return VK_SUCCESS;
1233 }
1234
1235 void
1236 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1237 const VkAllocationCallbacks *pAllocator)
1238 {
1239 RADV_FROM_HANDLE(radv_device, device, _device);
1240 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1241
1242 if (!view)
1243 return;
1244
1245 vk_free2(&device->alloc, pAllocator, view);
1246 }