2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "vk_format.h"
31 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
37 radv_choose_tiling(struct radv_device
*Device
,
38 const struct radv_image_create_info
*create_info
)
40 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
42 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
43 assert(pCreateInfo
->samples
<= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
49 /* Only very thin and long 2D textures should benefit from
51 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo
->samples
> 1)
56 return RADEON_SURF_MODE_2D
;
58 return RADEON_SURF_MODE_2D
;
61 radv_init_surface(struct radv_device
*device
,
62 struct radeon_surf
*surface
,
63 const struct radv_image_create_info
*create_info
)
65 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
66 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
67 const struct vk_format_description
*desc
=
68 vk_format_description(pCreateInfo
->format
);
69 bool is_depth
, is_stencil
, blendable
;
71 is_depth
= vk_format_has_depth(desc
);
72 is_stencil
= vk_format_has_stencil(desc
);
74 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
75 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
77 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
78 /* align byte per element on dword */
79 if (surface
->bpe
== 3) {
82 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
84 switch (pCreateInfo
->imageType
){
85 case VK_IMAGE_TYPE_1D
:
86 if (pCreateInfo
->arrayLayers
> 1)
87 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
89 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
91 case VK_IMAGE_TYPE_2D
:
92 if (pCreateInfo
->arrayLayers
> 1)
93 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
95 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
97 case VK_IMAGE_TYPE_3D
:
98 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
101 unreachable("unhandled image type");
105 surface
->flags
|= RADEON_SURF_ZBUFFER
;
109 surface
->flags
|= RADEON_SURF_SBUFFER
;
111 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
113 if ((pCreateInfo
->usage
& (VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
114 VK_IMAGE_USAGE_STORAGE_BIT
)) ||
115 (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) ||
116 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
117 device
->physical_device
->rad_info
.chip_class
< VI
||
118 create_info
->scanout
|| (device
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
119 !radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
))
120 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
121 if (create_info
->scanout
)
122 surface
->flags
|= RADEON_SURF_SCANOUT
;
125 #define ATI_VENDOR_ID 0x1002
126 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
128 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
131 static inline unsigned
132 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
135 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
137 return image
->surface
.u
.legacy
.tiling_index
[level
];
140 static unsigned radv_map_swizzle(unsigned swizzle
)
144 return V_008F0C_SQ_SEL_Y
;
146 return V_008F0C_SQ_SEL_Z
;
148 return V_008F0C_SQ_SEL_W
;
150 return V_008F0C_SQ_SEL_0
;
152 return V_008F0C_SQ_SEL_1
;
153 default: /* VK_SWIZZLE_X */
154 return V_008F0C_SQ_SEL_X
;
159 radv_make_buffer_descriptor(struct radv_device
*device
,
160 struct radv_buffer
*buffer
,
166 const struct vk_format_description
*desc
;
168 uint64_t gpu_address
= device
->ws
->buffer_get_va(buffer
->bo
);
169 uint64_t va
= gpu_address
+ buffer
->offset
;
170 unsigned num_format
, data_format
;
172 desc
= vk_format_description(vk_format
);
173 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
174 stride
= desc
->block
.bits
/ 8;
176 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
177 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
181 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
182 S_008F04_STRIDE(stride
);
184 if (device
->physical_device
->rad_info
.chip_class
< VI
&& stride
) {
189 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
190 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
191 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
192 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
193 S_008F0C_NUM_FORMAT(num_format
) |
194 S_008F0C_DATA_FORMAT(data_format
);
198 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
199 struct radv_image
*image
,
200 const struct legacy_surf_level
*base_level_info
,
201 unsigned base_level
, unsigned first_level
,
202 unsigned block_width
, bool is_stencil
,
205 uint64_t gpu_address
= image
->bo
? device
->ws
->buffer_get_va(image
->bo
) + image
->offset
: 0;
206 uint64_t va
= gpu_address
;
207 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
208 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
209 uint64_t meta_va
= 0;
210 if (chip_class
>= GFX9
) {
212 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
214 va
+= image
->surface
.u
.gfx9
.surf_offset
;
216 va
+= base_level_info
->offset
;
219 if (chip_class
< GFX9
)
220 if (base_level_info
->mode
== RADEON_SURF_MODE_2D
)
221 state
[0] |= image
->surface
.tile_swizzle
;
222 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
223 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
224 state
[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image
, base_level
,
226 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
228 if (chip_class
>= VI
) {
229 state
[6] &= C_008F28_COMPRESSION_EN
;
231 if (image
->surface
.dcc_size
&& first_level
< image
->surface
.num_dcc_levels
) {
232 meta_va
= gpu_address
+ image
->dcc_offset
;
233 if (chip_class
<= VI
)
234 meta_va
+= base_level_info
->dcc_offset
;
235 state
[6] |= S_008F28_COMPRESSION_EN(1);
236 state
[7] = meta_va
>> 8;
237 if (chip_class
< GFX9
)
238 state
[7] |= image
->surface
.tile_swizzle
;
242 if (chip_class
>= GFX9
) {
243 state
[3] &= C_008F1C_SW_MODE
;
244 state
[4] &= C_008F20_PITCH_GFX9
;
247 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
248 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
250 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
251 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
254 state
[5] &= C_008F24_META_DATA_ADDRESS
&
255 C_008F24_META_PIPE_ALIGNED
&
256 C_008F24_META_RB_ALIGNED
;
258 struct gfx9_surf_meta_flags meta
;
260 if (image
->dcc_offset
)
261 meta
= image
->surface
.u
.gfx9
.dcc
;
263 meta
= image
->surface
.u
.gfx9
.htile
;
265 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
266 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
267 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
271 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
272 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
274 state
[3] &= C_008F1C_TILING_INDEX
;
275 state
[3] |= S_008F1C_TILING_INDEX(index
);
276 state
[4] &= C_008F20_PITCH_GFX6
;
277 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
281 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
282 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
)
284 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
285 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
286 switch (image_type
) {
287 case VK_IMAGE_TYPE_1D
:
288 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
289 case VK_IMAGE_TYPE_2D
:
291 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
293 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
294 case VK_IMAGE_TYPE_3D
:
295 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
296 return V_008F1C_SQ_RSRC_IMG_3D
;
298 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
300 unreachable("illegale image type");
304 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
306 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
308 if (swizzle
[3] == VK_SWIZZLE_X
) {
309 /* For the pre-defined border color values (white, opaque
310 * black, transparent black), the only thing that matters is
311 * that the alpha channel winds up in the correct place
312 * (because the RGB channels are all the same) so either of
313 * these enumerations will work.
315 if (swizzle
[2] == VK_SWIZZLE_Y
)
316 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
318 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
319 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
320 if (swizzle
[1] == VK_SWIZZLE_Y
)
321 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
323 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
324 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
325 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
326 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
327 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
334 * Build the sampler view descriptor for a texture.
337 si_make_texture_descriptor(struct radv_device
*device
,
338 struct radv_image
*image
,
339 bool is_storage_image
,
340 VkImageViewType view_type
,
342 const VkComponentMapping
*mapping
,
343 unsigned first_level
, unsigned last_level
,
344 unsigned first_layer
, unsigned last_layer
,
345 unsigned width
, unsigned height
, unsigned depth
,
347 uint32_t *fmask_state
)
349 const struct vk_format_description
*desc
;
350 enum vk_swizzle swizzle
[4];
352 unsigned num_format
, data_format
, type
;
354 desc
= vk_format_description(vk_format
);
356 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
357 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
358 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
360 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
363 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
365 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
366 if (num_format
== ~0) {
370 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
371 if (data_format
== ~0) {
375 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
377 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
379 depth
= image
->info
.array_size
;
380 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
381 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
382 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
383 depth
= image
->info
.array_size
;
384 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
385 depth
= image
->info
.array_size
/ 6;
388 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
389 S_008F14_NUM_FORMAT_GFX6(num_format
));
390 state
[2] = (S_008F18_WIDTH(width
- 1) |
391 S_008F18_HEIGHT(height
- 1) |
392 S_008F18_PERF_MOD(4));
393 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
394 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
395 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
396 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
397 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
399 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
400 util_logbase2(image
->info
.samples
) :
402 S_008F1C_TYPE(type
));
404 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
408 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
409 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
411 /* Depth is the the last accessible layer on Gfx9.
412 * The hw doesn't need to know the total number of layers.
414 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
415 state
[4] |= S_008F20_DEPTH(depth
- 1);
417 state
[4] |= S_008F20_DEPTH(last_layer
);
419 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
420 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
421 util_logbase2(image
->info
.samples
) :
424 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
425 state
[4] |= S_008F20_DEPTH(depth
- 1);
426 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
428 if (image
->dcc_offset
) {
429 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
431 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
433 /* The last dword is unused by hw. The shader uses it to clear
434 * bits in the first dword of sampler state.
436 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
437 if (first_level
== last_level
)
438 state
[7] = C_008F30_MAX_ANISO_RATIO
;
440 state
[7] = 0xffffffff;
444 /* Initialize the sampler view for FMASK. */
445 if (image
->fmask
.size
) {
446 uint32_t fmask_format
, num_format
;
447 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
);
450 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
452 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
453 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
454 switch (image
->info
.samples
) {
456 num_format
= V_008F14_IMG_FMASK_8_2_2
;
459 num_format
= V_008F14_IMG_FMASK_8_4_4
;
462 num_format
= V_008F14_IMG_FMASK_32_8_8
;
465 unreachable("invalid nr_samples");
468 switch (image
->info
.samples
) {
470 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
473 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
476 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
480 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
482 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
485 fmask_state
[0] = va
>> 8;
486 if (device
->physical_device
->rad_info
.chip_class
< GFX9
)
487 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
488 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
489 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
490 S_008F14_NUM_FORMAT_GFX6(num_format
);
491 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
492 S_008F18_HEIGHT(height
- 1);
493 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
494 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
495 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
496 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
497 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false));
499 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
503 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
504 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
505 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
506 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
507 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
508 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
510 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
511 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
512 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
513 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
515 } else if (fmask_state
)
516 memset(fmask_state
, 0, 8 * 4);
520 radv_query_opaque_metadata(struct radv_device
*device
,
521 struct radv_image
*image
,
522 struct radeon_bo_metadata
*md
)
524 static const VkComponentMapping fixedmapping
;
527 /* Metadata image format format version 1:
528 * [0] = 1 (metadata format identifier)
529 * [1] = (VENDOR_ID << 16) | PCI_ID
530 * [2:9] = image descriptor for the whole resource
531 * [2] is always 0, because the base address is cleared
532 * [9] is the DCC offset bits [39:8] from the beginning of
534 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
536 md
->metadata
[0] = 1; /* metadata image format version 1 */
538 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
539 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
542 si_make_texture_descriptor(device
, image
, false,
543 (VkImageViewType
)image
->type
, image
->vk_format
,
544 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
545 image
->info
.array_size
,
546 image
->info
.width
, image
->info
.height
,
550 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
551 image
->surface
.blk_w
, false, desc
);
553 /* Clear the base address and set the relative DCC offset. */
555 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
556 desc
[7] = image
->dcc_offset
>> 8;
558 /* Dwords [2:9] contain the image descriptor. */
559 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
561 /* Dwords [10:..] contain the mipmap level offsets. */
562 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
563 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
565 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
569 radv_init_metadata(struct radv_device
*device
,
570 struct radv_image
*image
,
571 struct radeon_bo_metadata
*metadata
)
573 struct radeon_surf
*surface
= &image
->surface
;
575 memset(metadata
, 0, sizeof(*metadata
));
577 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
578 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
580 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
581 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
582 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
583 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
584 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
585 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
586 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
587 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
588 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
589 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
590 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
591 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
593 radv_query_opaque_metadata(device
, image
, metadata
);
596 /* The number of samples can be specified independently of the texture. */
598 radv_image_get_fmask_info(struct radv_device
*device
,
599 struct radv_image
*image
,
601 struct radv_fmask_info
*out
)
603 /* FMASK is allocated like an ordinary texture. */
604 struct radeon_surf fmask
= {};
605 struct ac_surf_info info
= image
->info
;
606 memset(out
, 0, sizeof(*out
));
608 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
609 out
->alignment
= image
->surface
.u
.gfx9
.fmask_alignment
;
610 out
->size
= image
->surface
.u
.gfx9
.fmask_size
;
614 fmask
.blk_w
= image
->surface
.blk_w
;
615 fmask
.blk_h
= image
->surface
.blk_h
;
617 fmask
.flags
= image
->surface
.flags
| RADEON_SURF_FMASK
;
619 if (!image
->shareable
);
620 info
.surf_index
= &device
->fmask_mrt_offset_counter
;
622 /* Force 2D tiling if it wasn't set. This may occur when creating
623 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
624 * destination buffer must have an FMASK too. */
625 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
626 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
628 switch (nr_samples
) {
640 device
->ws
->surface_init(device
->ws
, &info
, &fmask
);
641 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
643 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
644 if (out
->slice_tile_max
)
645 out
->slice_tile_max
-= 1;
647 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
648 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
649 out
->bank_height
= fmask
.u
.legacy
.bankh
;
650 out
->tile_swizzle
= fmask
.tile_swizzle
;
651 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
652 out
->size
= fmask
.surf_size
;
654 assert(!out
->tile_swizzle
|| !image
->shareable
);
658 radv_image_alloc_fmask(struct radv_device
*device
,
659 struct radv_image
*image
)
661 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
663 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
664 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
665 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
669 radv_image_get_cmask_info(struct radv_device
*device
,
670 struct radv_image
*image
,
671 struct radv_cmask_info
*out
)
673 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
674 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
675 unsigned cl_width
, cl_height
;
677 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
678 out
->alignment
= image
->surface
.u
.gfx9
.cmask_alignment
;
679 out
->size
= image
->surface
.u
.gfx9
.cmask_size
;
696 case 16: /* Hawaii */
705 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
707 unsigned width
= align(image
->info
.width
, cl_width
*8);
708 unsigned height
= align(image
->info
.height
, cl_height
*8);
709 unsigned slice_elements
= (width
* height
) / (8*8);
711 /* Each element of CMASK is a nibble. */
712 unsigned slice_bytes
= slice_elements
/ 2;
714 out
->slice_tile_max
= (width
* height
) / (128*128);
715 if (out
->slice_tile_max
)
716 out
->slice_tile_max
-= 1;
718 out
->alignment
= MAX2(256, base_align
);
719 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
720 align(slice_bytes
, base_align
);
724 radv_image_alloc_cmask(struct radv_device
*device
,
725 struct radv_image
*image
)
727 uint32_t clear_value_size
= 0;
728 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
730 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
731 /* + 8 for storing the clear values */
732 if (!image
->clear_value_offset
) {
733 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
734 clear_value_size
= 8;
736 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
737 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
741 radv_image_alloc_dcc(struct radv_device
*device
,
742 struct radv_image
*image
)
744 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
745 /* + 16 for storing the clear values + dcc pred */
746 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
747 image
->dcc_pred_offset
= image
->clear_value_offset
+ 8;
748 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
749 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
753 radv_image_alloc_htile(struct radv_device
*device
,
754 struct radv_image
*image
)
756 if ((device
->debug_flags
& RADV_DEBUG_NO_HIZ
) || image
->info
.levels
> 1) {
757 image
->surface
.htile_size
= 0;
761 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
763 /* + 8 for storing the clear values */
764 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
765 image
->size
= image
->clear_value_offset
+ 8;
766 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
770 radv_image_create(VkDevice _device
,
771 const struct radv_image_create_info
*create_info
,
772 const VkAllocationCallbacks
* alloc
,
775 RADV_FROM_HANDLE(radv_device
, device
, _device
);
776 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
777 struct radv_image
*image
= NULL
;
778 bool can_cmask_dcc
= false;
779 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
781 radv_assert(pCreateInfo
->mipLevels
> 0);
782 radv_assert(pCreateInfo
->arrayLayers
> 0);
783 radv_assert(pCreateInfo
->samples
> 0);
784 radv_assert(pCreateInfo
->extent
.width
> 0);
785 radv_assert(pCreateInfo
->extent
.height
> 0);
786 radv_assert(pCreateInfo
->extent
.depth
> 0);
788 image
= vk_alloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
789 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
791 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
793 memset(image
, 0, sizeof(*image
));
794 image
->type
= pCreateInfo
->imageType
;
795 image
->info
.width
= pCreateInfo
->extent
.width
;
796 image
->info
.height
= pCreateInfo
->extent
.height
;
797 image
->info
.depth
= pCreateInfo
->extent
.depth
;
798 image
->info
.samples
= pCreateInfo
->samples
;
799 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
800 image
->info
.levels
= pCreateInfo
->mipLevels
;
802 image
->vk_format
= pCreateInfo
->format
;
803 image
->tiling
= pCreateInfo
->tiling
;
804 image
->usage
= pCreateInfo
->usage
;
805 image
->flags
= pCreateInfo
->flags
;
807 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
808 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
809 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
810 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
811 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
813 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
816 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
817 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
818 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
819 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
822 radv_init_surface(device
, &image
->surface
, create_info
);
824 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
826 image
->size
= image
->surface
.surf_size
;
827 image
->alignment
= image
->surface
.surf_alignment
;
829 if (image
->exclusive
|| image
->queue_family_mask
== 1)
830 can_cmask_dcc
= true;
832 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
833 image
->surface
.dcc_size
&& can_cmask_dcc
)
834 radv_image_alloc_dcc(device
, image
);
836 image
->surface
.dcc_size
= 0;
838 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
839 pCreateInfo
->mipLevels
== 1 &&
840 !image
->surface
.dcc_size
&& image
->info
.depth
== 1 && can_cmask_dcc
)
841 radv_image_alloc_cmask(device
, image
);
842 if (image
->info
.samples
> 1 && vk_format_is_color(pCreateInfo
->format
)) {
843 radv_image_alloc_fmask(device
, image
);
844 } else if (vk_format_is_depth(pCreateInfo
->format
)) {
846 radv_image_alloc_htile(device
, image
);
849 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
850 image
->alignment
= MAX2(image
->alignment
, 4096);
851 image
->size
= align64(image
->size
, image
->alignment
);
854 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
855 0, RADEON_FLAG_VIRTUAL
);
857 vk_free2(&device
->alloc
, alloc
, image
);
858 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
862 *pImage
= radv_image_to_handle(image
);
868 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
869 struct radv_device
*device
,
870 const VkImageViewCreateInfo
* pCreateInfo
,
871 bool is_storage_image
)
873 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
874 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
875 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
877 uint32_t *descriptor
;
878 uint32_t *fmask_descriptor
;
880 if (is_storage_image
) {
881 descriptor
= iview
->storage_descriptor
;
882 fmask_descriptor
= iview
->storage_fmask_descriptor
;
884 descriptor
= iview
->descriptor
;
885 fmask_descriptor
= iview
->fmask_descriptor
;
888 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
889 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
891 si_make_texture_descriptor(device
, image
, is_storage_image
,
894 &pCreateInfo
->components
,
895 0, radv_get_levelCount(image
, range
) - 1,
896 range
->baseArrayLayer
,
897 range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1,
899 iview
->extent
.height
,
903 si_set_mutable_tex_desc_fields(device
, image
,
904 is_stencil
? &image
->surface
.u
.legacy
.stencil_level
[range
->baseMipLevel
]
905 : &image
->surface
.u
.legacy
.level
[range
->baseMipLevel
],
908 blk_w
, is_stencil
, descriptor
);
912 radv_image_view_init(struct radv_image_view
*iview
,
913 struct radv_device
*device
,
914 const VkImageViewCreateInfo
* pCreateInfo
)
916 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
917 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
919 switch (image
->type
) {
920 case VK_IMAGE_TYPE_1D
:
921 case VK_IMAGE_TYPE_2D
:
922 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
924 case VK_IMAGE_TYPE_3D
:
925 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
926 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
929 unreachable("bad VkImageType");
931 iview
->image
= image
;
932 iview
->bo
= image
->bo
;
933 iview
->type
= pCreateInfo
->viewType
;
934 iview
->vk_format
= pCreateInfo
->format
;
935 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
937 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
938 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
939 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
940 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
943 iview
->extent
= (VkExtent3D
) {
944 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
945 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
946 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
949 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
950 vk_format_get_blockwidth(image
->vk_format
));
951 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
952 vk_format_get_blockheight(image
->vk_format
));
954 iview
->base_layer
= range
->baseArrayLayer
;
955 iview
->layer_count
= radv_get_layerCount(image
, range
);
956 iview
->base_mip
= range
->baseMipLevel
;
958 radv_image_view_make_descriptor(iview
, device
, pCreateInfo
, false);
959 radv_image_view_make_descriptor(iview
, device
, pCreateInfo
, true);
962 bool radv_layout_has_htile(const struct radv_image
*image
,
963 VkImageLayout layout
,
966 return image
->surface
.htile_size
&&
967 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
968 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
969 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
972 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
973 VkImageLayout layout
,
976 return image
->surface
.htile_size
&&
977 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
978 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
979 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
982 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
983 VkImageLayout layout
,
986 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
987 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
991 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
993 if (!image
->exclusive
)
994 return image
->queue_family_mask
;
995 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
996 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
997 if (family
== VK_QUEUE_FAMILY_IGNORED
)
998 return 1u << queue_family
;
1003 radv_CreateImage(VkDevice device
,
1004 const VkImageCreateInfo
*pCreateInfo
,
1005 const VkAllocationCallbacks
*pAllocator
,
1008 return radv_image_create(device
,
1009 &(struct radv_image_create_info
) {
1010 .vk_info
= pCreateInfo
,
1018 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1019 const VkAllocationCallbacks
*pAllocator
)
1021 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1022 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1027 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1028 device
->ws
->buffer_destroy(image
->bo
);
1030 vk_free2(&device
->alloc
, pAllocator
, image
);
1033 void radv_GetImageSubresourceLayout(
1036 const VkImageSubresource
* pSubresource
,
1037 VkSubresourceLayout
* pLayout
)
1039 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1040 int level
= pSubresource
->mipLevel
;
1041 int layer
= pSubresource
->arrayLayer
;
1042 struct radeon_surf
*surface
= &image
->surface
;
1044 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ surface
->u
.legacy
.level
[level
].slice_size
* layer
;
1045 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1046 pLayout
->arrayPitch
= surface
->u
.legacy
.level
[level
].slice_size
;
1047 pLayout
->depthPitch
= surface
->u
.legacy
.level
[level
].slice_size
;
1048 pLayout
->size
= surface
->u
.legacy
.level
[level
].slice_size
;
1049 if (image
->type
== VK_IMAGE_TYPE_3D
)
1050 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1055 radv_CreateImageView(VkDevice _device
,
1056 const VkImageViewCreateInfo
*pCreateInfo
,
1057 const VkAllocationCallbacks
*pAllocator
,
1060 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1061 struct radv_image_view
*view
;
1063 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1064 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1066 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1068 radv_image_view_init(view
, device
, pCreateInfo
);
1070 *pView
= radv_image_view_to_handle(view
);
1076 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1077 const VkAllocationCallbacks
*pAllocator
)
1079 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1080 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1084 vk_free2(&device
->alloc
, pAllocator
, iview
);
1087 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1088 struct radv_device
*device
,
1089 const VkBufferViewCreateInfo
* pCreateInfo
,
1090 struct radv_cmd_buffer
*cmd_buffer
)
1092 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1094 view
->bo
= buffer
->bo
;
1095 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1096 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1097 view
->vk_format
= pCreateInfo
->format
;
1099 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1100 pCreateInfo
->offset
, view
->range
, view
->state
);
1104 radv_CreateBufferView(VkDevice _device
,
1105 const VkBufferViewCreateInfo
*pCreateInfo
,
1106 const VkAllocationCallbacks
*pAllocator
,
1107 VkBufferView
*pView
)
1109 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1110 struct radv_buffer_view
*view
;
1112 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1113 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1115 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1117 radv_buffer_view_init(view
, device
, pCreateInfo
, NULL
);
1119 *pView
= radv_buffer_view_to_handle(view
);
1125 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1126 const VkAllocationCallbacks
*pAllocator
)
1128 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1129 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1134 vk_free2(&device
->alloc
, pAllocator
, view
);