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9c04d7ecca54c6133034e5914a3d14439f91853d
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66 static int
67 radv_init_surface(struct radv_device *device,
68 struct radeon_surf *surface,
69 const struct radv_image_create_info *create_info)
70 {
71 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
72 unsigned array_mode = radv_choose_tiling(device, create_info);
73 const struct vk_format_description *desc =
74 vk_format_description(pCreateInfo->format);
75 bool is_depth, is_stencil, blendable;
76
77 is_depth = vk_format_has_depth(desc);
78 is_stencil = vk_format_has_stencil(desc);
79
80 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
81 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
82
83 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
84 /* align byte per element on dword */
85 if (surface->bpe == 3) {
86 surface->bpe = 4;
87 }
88 surface->flags = RADEON_SURF_SET(array_mode, MODE);
89
90 switch (pCreateInfo->imageType){
91 case VK_IMAGE_TYPE_1D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_2D:
98 if (pCreateInfo->arrayLayers > 1)
99 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
100 else
101 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
102 break;
103 case VK_IMAGE_TYPE_3D:
104 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
105 break;
106 default:
107 unreachable("unhandled image type");
108 }
109
110 if (is_depth) {
111 surface->flags |= RADEON_SURF_ZBUFFER;
112 }
113
114 if (is_stencil)
115 surface->flags |= RADEON_SURF_SBUFFER;
116
117 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
118
119 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
120 VK_IMAGE_USAGE_STORAGE_BIT)) ||
121 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
122 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
123 pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
124 device->physical_device->rad_info.chip_class < VI ||
125 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
126 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
127 surface->flags |= RADEON_SURF_DISABLE_DCC;
128 if (create_info->scanout)
129 surface->flags |= RADEON_SURF_SCANOUT;
130 return 0;
131 }
132 #define ATI_VENDOR_ID 0x1002
133 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
134 {
135 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
136 }
137
138 static inline unsigned
139 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
140 {
141 if (stencil)
142 return image->surface.u.legacy.stencil_tiling_index[level];
143 else
144 return image->surface.u.legacy.tiling_index[level];
145 }
146
147 static unsigned radv_map_swizzle(unsigned swizzle)
148 {
149 switch (swizzle) {
150 case VK_SWIZZLE_Y:
151 return V_008F0C_SQ_SEL_Y;
152 case VK_SWIZZLE_Z:
153 return V_008F0C_SQ_SEL_Z;
154 case VK_SWIZZLE_W:
155 return V_008F0C_SQ_SEL_W;
156 case VK_SWIZZLE_0:
157 return V_008F0C_SQ_SEL_0;
158 case VK_SWIZZLE_1:
159 return V_008F0C_SQ_SEL_1;
160 default: /* VK_SWIZZLE_X */
161 return V_008F0C_SQ_SEL_X;
162 }
163 }
164
165 static void
166 radv_make_buffer_descriptor(struct radv_device *device,
167 struct radv_buffer *buffer,
168 VkFormat vk_format,
169 unsigned offset,
170 unsigned range,
171 uint32_t *state)
172 {
173 const struct vk_format_description *desc;
174 unsigned stride;
175 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
176 uint64_t va = gpu_address + buffer->offset;
177 unsigned num_format, data_format;
178 int first_non_void;
179 desc = vk_format_description(vk_format);
180 first_non_void = vk_format_get_first_non_void_channel(vk_format);
181 stride = desc->block.bits / 8;
182
183 num_format = radv_translate_buffer_numformat(desc, first_non_void);
184 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
185
186 va += offset;
187 state[0] = va;
188 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
189 S_008F04_STRIDE(stride);
190
191 if (device->physical_device->rad_info.chip_class != VI && stride) {
192 range /= stride;
193 }
194
195 state[2] = range;
196 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
197 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
198 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
199 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
200 S_008F0C_NUM_FORMAT(num_format) |
201 S_008F0C_DATA_FORMAT(data_format);
202 }
203
204 static void
205 si_set_mutable_tex_desc_fields(struct radv_device *device,
206 struct radv_image *image,
207 const struct legacy_surf_level *base_level_info,
208 unsigned base_level, unsigned first_level,
209 unsigned block_width, bool is_stencil,
210 uint32_t *state)
211 {
212 uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
213 uint64_t va = gpu_address;
214 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
215 uint64_t meta_va = 0;
216 if (chip_class >= GFX9) {
217 if (is_stencil)
218 va += image->surface.u.gfx9.stencil_offset;
219 else
220 va += image->surface.u.gfx9.surf_offset;
221 } else
222 va += base_level_info->offset;
223
224 state[0] = va >> 8;
225 if (chip_class >= GFX9 ||
226 base_level_info->mode == RADEON_SURF_MODE_2D)
227 state[0] |= image->surface.tile_swizzle;
228 state[1] &= C_008F14_BASE_ADDRESS_HI;
229 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
230
231 if (chip_class >= VI) {
232 state[6] &= C_008F28_COMPRESSION_EN;
233 state[7] = 0;
234 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
235 meta_va = gpu_address + image->dcc_offset;
236 if (chip_class <= VI)
237 meta_va += base_level_info->dcc_offset;
238 state[6] |= S_008F28_COMPRESSION_EN(1);
239 state[7] = meta_va >> 8;
240 state[7] |= image->surface.tile_swizzle;
241 }
242 }
243
244 if (chip_class >= GFX9) {
245 state[3] &= C_008F1C_SW_MODE;
246 state[4] &= C_008F20_PITCH_GFX9;
247
248 if (is_stencil) {
249 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
250 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
251 } else {
252 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
253 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
254 }
255
256 state[5] &= C_008F24_META_DATA_ADDRESS &
257 C_008F24_META_PIPE_ALIGNED &
258 C_008F24_META_RB_ALIGNED;
259 if (meta_va) {
260 struct gfx9_surf_meta_flags meta;
261
262 if (image->dcc_offset)
263 meta = image->surface.u.gfx9.dcc;
264 else
265 meta = image->surface.u.gfx9.htile;
266
267 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
268 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
269 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
270 }
271 } else {
272 /* SI-CI-VI */
273 unsigned pitch = base_level_info->nblk_x * block_width;
274 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
275
276 state[3] &= C_008F1C_TILING_INDEX;
277 state[3] |= S_008F1C_TILING_INDEX(index);
278 state[4] &= C_008F20_PITCH_GFX6;
279 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
280 }
281 }
282
283 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
284 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
285 {
286 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
287 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
288
289 /* GFX9 allocates 1D textures as 2D. */
290 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
291 image_type = VK_IMAGE_TYPE_2D;
292 switch (image_type) {
293 case VK_IMAGE_TYPE_1D:
294 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
295 case VK_IMAGE_TYPE_2D:
296 if (nr_samples > 1)
297 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
298 else
299 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
300 case VK_IMAGE_TYPE_3D:
301 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
302 return V_008F1C_SQ_RSRC_IMG_3D;
303 else
304 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
305 default:
306 unreachable("illegale image type");
307 }
308 }
309
310 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
311 {
312 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
313
314 if (swizzle[3] == VK_SWIZZLE_X) {
315 /* For the pre-defined border color values (white, opaque
316 * black, transparent black), the only thing that matters is
317 * that the alpha channel winds up in the correct place
318 * (because the RGB channels are all the same) so either of
319 * these enumerations will work.
320 */
321 if (swizzle[2] == VK_SWIZZLE_Y)
322 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
323 else
324 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
325 } else if (swizzle[0] == VK_SWIZZLE_X) {
326 if (swizzle[1] == VK_SWIZZLE_Y)
327 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
328 else
329 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
330 } else if (swizzle[1] == VK_SWIZZLE_X) {
331 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
332 } else if (swizzle[2] == VK_SWIZZLE_X) {
333 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
334 }
335
336 return bc_swizzle;
337 }
338
339 /**
340 * Build the sampler view descriptor for a texture.
341 */
342 static void
343 si_make_texture_descriptor(struct radv_device *device,
344 struct radv_image *image,
345 bool is_storage_image,
346 VkImageViewType view_type,
347 VkFormat vk_format,
348 const VkComponentMapping *mapping,
349 unsigned first_level, unsigned last_level,
350 unsigned first_layer, unsigned last_layer,
351 unsigned width, unsigned height, unsigned depth,
352 uint32_t *state,
353 uint32_t *fmask_state)
354 {
355 const struct vk_format_description *desc;
356 enum vk_swizzle swizzle[4];
357 int first_non_void;
358 unsigned num_format, data_format, type;
359
360 desc = vk_format_description(vk_format);
361
362 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
363 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
364 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
365 } else {
366 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
367 }
368
369 first_non_void = vk_format_get_first_non_void_channel(vk_format);
370
371 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
372 if (num_format == ~0) {
373 num_format = 0;
374 }
375
376 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
377 if (data_format == ~0) {
378 data_format = 0;
379 }
380
381 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
382 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
383 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
384 height = 1;
385 depth = image->info.array_size;
386 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
387 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
388 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
389 depth = image->info.array_size;
390 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
391 depth = image->info.array_size / 6;
392
393 state[0] = 0;
394 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
395 S_008F14_NUM_FORMAT_GFX6(num_format));
396 state[2] = (S_008F18_WIDTH(width - 1) |
397 S_008F18_HEIGHT(height - 1) |
398 S_008F18_PERF_MOD(4));
399 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
400 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
401 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
402 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
403 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
404 0 : first_level) |
405 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
406 util_logbase2(image->info.samples) :
407 last_level) |
408 S_008F1C_TYPE(type));
409 state[4] = 0;
410 state[5] = S_008F24_BASE_ARRAY(first_layer);
411 state[6] = 0;
412 state[7] = 0;
413
414 if (device->physical_device->rad_info.chip_class >= GFX9) {
415 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
416
417 /* Depth is the the last accessible layer on Gfx9.
418 * The hw doesn't need to know the total number of layers.
419 */
420 if (type == V_008F1C_SQ_RSRC_IMG_3D)
421 state[4] |= S_008F20_DEPTH(depth - 1);
422 else
423 state[4] |= S_008F20_DEPTH(last_layer);
424
425 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
426 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
427 util_logbase2(image->info.samples) :
428 image->info.levels - 1);
429 } else {
430 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
431 state[4] |= S_008F20_DEPTH(depth - 1);
432 state[5] |= S_008F24_LAST_ARRAY(last_layer);
433 }
434 if (image->dcc_offset) {
435 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
436
437 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
438 } else {
439 /* The last dword is unused by hw. The shader uses it to clear
440 * bits in the first dword of sampler state.
441 */
442 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
443 if (first_level == last_level)
444 state[7] = C_008F30_MAX_ANISO_RATIO;
445 else
446 state[7] = 0xffffffff;
447 }
448 }
449
450 /* Initialize the sampler view for FMASK. */
451 if (image->fmask.size) {
452 uint32_t fmask_format, num_format;
453 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
454 uint64_t va;
455
456 va = gpu_address + image->offset + image->fmask.offset;
457
458 if (device->physical_device->rad_info.chip_class >= GFX9) {
459 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
460 switch (image->info.samples) {
461 case 2:
462 num_format = V_008F14_IMG_FMASK_8_2_2;
463 break;
464 case 4:
465 num_format = V_008F14_IMG_FMASK_8_4_4;
466 break;
467 case 8:
468 num_format = V_008F14_IMG_FMASK_32_8_8;
469 break;
470 default:
471 unreachable("invalid nr_samples");
472 }
473 } else {
474 switch (image->info.samples) {
475 case 2:
476 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
477 break;
478 case 4:
479 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
480 break;
481 case 8:
482 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
483 break;
484 default:
485 assert(0);
486 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
487 }
488 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
489 }
490
491 fmask_state[0] = va >> 8;
492 fmask_state[0] |= image->fmask.tile_swizzle;
493 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
494 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
495 S_008F14_NUM_FORMAT_GFX6(num_format);
496 fmask_state[2] = S_008F18_WIDTH(width - 1) |
497 S_008F18_HEIGHT(height - 1);
498 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
499 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
500 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
501 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
502 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
503 fmask_state[4] = 0;
504 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
505 fmask_state[6] = 0;
506 fmask_state[7] = 0;
507
508 if (device->physical_device->rad_info.chip_class >= GFX9) {
509 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
510 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
511 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
512 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
513 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
514 } else {
515 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
516 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
517 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
518 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
519 }
520 } else if (fmask_state)
521 memset(fmask_state, 0, 8 * 4);
522 }
523
524 static void
525 radv_query_opaque_metadata(struct radv_device *device,
526 struct radv_image *image,
527 struct radeon_bo_metadata *md)
528 {
529 static const VkComponentMapping fixedmapping;
530 uint32_t desc[8], i;
531
532 /* Metadata image format format version 1:
533 * [0] = 1 (metadata format identifier)
534 * [1] = (VENDOR_ID << 16) | PCI_ID
535 * [2:9] = image descriptor for the whole resource
536 * [2] is always 0, because the base address is cleared
537 * [9] is the DCC offset bits [39:8] from the beginning of
538 * the buffer
539 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
540 */
541 md->metadata[0] = 1; /* metadata image format version 1 */
542
543 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
544 md->metadata[1] = si_get_bo_metadata_word1(device);
545
546
547 si_make_texture_descriptor(device, image, false,
548 (VkImageViewType)image->type, image->vk_format,
549 &fixedmapping, 0, image->info.levels - 1, 0,
550 image->info.array_size,
551 image->info.width, image->info.height,
552 image->info.depth,
553 desc, NULL);
554
555 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
556 image->surface.blk_w, false, desc);
557
558 /* Clear the base address and set the relative DCC offset. */
559 desc[0] = 0;
560 desc[1] &= C_008F14_BASE_ADDRESS_HI;
561 desc[7] = image->dcc_offset >> 8;
562
563 /* Dwords [2:9] contain the image descriptor. */
564 memcpy(&md->metadata[2], desc, sizeof(desc));
565
566 /* Dwords [10:..] contain the mipmap level offsets. */
567 if (device->physical_device->rad_info.chip_class <= VI) {
568 for (i = 0; i <= image->info.levels - 1; i++)
569 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
570 md->size_metadata = (11 + image->info.levels - 1) * 4;
571 }
572 }
573
574 void
575 radv_init_metadata(struct radv_device *device,
576 struct radv_image *image,
577 struct radeon_bo_metadata *metadata)
578 {
579 struct radeon_surf *surface = &image->surface;
580
581 memset(metadata, 0, sizeof(*metadata));
582
583 if (device->physical_device->rad_info.chip_class >= GFX9) {
584 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
585 } else {
586 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
587 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
588 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
589 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
590 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
591 metadata->u.legacy.bankw = surface->u.legacy.bankw;
592 metadata->u.legacy.bankh = surface->u.legacy.bankh;
593 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
594 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
595 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
596 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
597 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
598 }
599 radv_query_opaque_metadata(device, image, metadata);
600 }
601
602 /* The number of samples can be specified independently of the texture. */
603 static void
604 radv_image_get_fmask_info(struct radv_device *device,
605 struct radv_image *image,
606 unsigned nr_samples,
607 struct radv_fmask_info *out)
608 {
609 /* FMASK is allocated like an ordinary texture. */
610 struct radeon_surf fmask = {};
611 struct ac_surf_info info = image->info;
612 memset(out, 0, sizeof(*out));
613
614 if (device->physical_device->rad_info.chip_class >= GFX9) {
615 out->alignment = image->surface.u.gfx9.fmask_alignment;
616 out->size = image->surface.u.gfx9.fmask_size;
617 return;
618 }
619
620 fmask.blk_w = image->surface.blk_w;
621 fmask.blk_h = image->surface.blk_h;
622 info.samples = 1;
623 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
624
625 if (!image->shareable)
626 info.surf_index = &device->fmask_mrt_offset_counter;
627
628 /* Force 2D tiling if it wasn't set. This may occur when creating
629 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
630 * destination buffer must have an FMASK too. */
631 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
632 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
633
634 switch (nr_samples) {
635 case 2:
636 case 4:
637 fmask.bpe = 1;
638 break;
639 case 8:
640 fmask.bpe = 4;
641 break;
642 default:
643 return;
644 }
645
646 device->ws->surface_init(device->ws, &info, &fmask);
647 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
648
649 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
650 if (out->slice_tile_max)
651 out->slice_tile_max -= 1;
652
653 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
654 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
655 out->bank_height = fmask.u.legacy.bankh;
656 out->tile_swizzle = fmask.tile_swizzle;
657 out->alignment = MAX2(256, fmask.surf_alignment);
658 out->size = fmask.surf_size;
659
660 assert(!out->tile_swizzle || !image->shareable);
661 }
662
663 static void
664 radv_image_alloc_fmask(struct radv_device *device,
665 struct radv_image *image)
666 {
667 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
668
669 image->fmask.offset = align64(image->size, image->fmask.alignment);
670 image->size = image->fmask.offset + image->fmask.size;
671 image->alignment = MAX2(image->alignment, image->fmask.alignment);
672 }
673
674 static void
675 radv_image_get_cmask_info(struct radv_device *device,
676 struct radv_image *image,
677 struct radv_cmask_info *out)
678 {
679 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
680 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
681 unsigned cl_width, cl_height;
682
683 if (device->physical_device->rad_info.chip_class >= GFX9) {
684 out->alignment = image->surface.u.gfx9.cmask_alignment;
685 out->size = image->surface.u.gfx9.cmask_size;
686 return;
687 }
688
689 switch (num_pipes) {
690 case 2:
691 cl_width = 32;
692 cl_height = 16;
693 break;
694 case 4:
695 cl_width = 32;
696 cl_height = 32;
697 break;
698 case 8:
699 cl_width = 64;
700 cl_height = 32;
701 break;
702 case 16: /* Hawaii */
703 cl_width = 64;
704 cl_height = 64;
705 break;
706 default:
707 assert(0);
708 return;
709 }
710
711 unsigned base_align = num_pipes * pipe_interleave_bytes;
712
713 unsigned width = align(image->info.width, cl_width*8);
714 unsigned height = align(image->info.height, cl_height*8);
715 unsigned slice_elements = (width * height) / (8*8);
716
717 /* Each element of CMASK is a nibble. */
718 unsigned slice_bytes = slice_elements / 2;
719
720 out->slice_tile_max = (width * height) / (128*128);
721 if (out->slice_tile_max)
722 out->slice_tile_max -= 1;
723
724 out->alignment = MAX2(256, base_align);
725 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
726 align(slice_bytes, base_align);
727 }
728
729 static void
730 radv_image_alloc_cmask(struct radv_device *device,
731 struct radv_image *image)
732 {
733 uint32_t clear_value_size = 0;
734 radv_image_get_cmask_info(device, image, &image->cmask);
735
736 image->cmask.offset = align64(image->size, image->cmask.alignment);
737 /* + 8 for storing the clear values */
738 if (!image->clear_value_offset) {
739 image->clear_value_offset = image->cmask.offset + image->cmask.size;
740 clear_value_size = 8;
741 }
742 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
743 image->alignment = MAX2(image->alignment, image->cmask.alignment);
744 }
745
746 static void
747 radv_image_alloc_dcc(struct radv_device *device,
748 struct radv_image *image)
749 {
750 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
751 /* + 16 for storing the clear values + dcc pred */
752 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
753 image->dcc_pred_offset = image->clear_value_offset + 8;
754 image->size = image->dcc_offset + image->surface.dcc_size + 16;
755 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
756 }
757
758 static void
759 radv_image_alloc_htile(struct radv_device *device,
760 struct radv_image *image)
761 {
762 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
763 image->surface.htile_size = 0;
764 return;
765 }
766
767 image->htile_offset = align64(image->size, image->surface.htile_alignment);
768
769 /* + 8 for storing the clear values */
770 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
771 image->size = image->clear_value_offset + 8;
772 image->alignment = align64(image->alignment, image->surface.htile_alignment);
773 }
774
775 VkResult
776 radv_image_create(VkDevice _device,
777 const struct radv_image_create_info *create_info,
778 const VkAllocationCallbacks* alloc,
779 VkImage *pImage)
780 {
781 RADV_FROM_HANDLE(radv_device, device, _device);
782 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
783 struct radv_image *image = NULL;
784 bool can_cmask_dcc = false;
785 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
786
787 radv_assert(pCreateInfo->mipLevels > 0);
788 radv_assert(pCreateInfo->arrayLayers > 0);
789 radv_assert(pCreateInfo->samples > 0);
790 radv_assert(pCreateInfo->extent.width > 0);
791 radv_assert(pCreateInfo->extent.height > 0);
792 radv_assert(pCreateInfo->extent.depth > 0);
793
794 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
795 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
796 if (!image)
797 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
798
799 memset(image, 0, sizeof(*image));
800 image->type = pCreateInfo->imageType;
801 image->info.width = pCreateInfo->extent.width;
802 image->info.height = pCreateInfo->extent.height;
803 image->info.depth = pCreateInfo->extent.depth;
804 image->info.samples = pCreateInfo->samples;
805 image->info.array_size = pCreateInfo->arrayLayers;
806 image->info.levels = pCreateInfo->mipLevels;
807
808 image->vk_format = pCreateInfo->format;
809 image->tiling = pCreateInfo->tiling;
810 image->usage = pCreateInfo->usage;
811 image->flags = pCreateInfo->flags;
812
813 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
814 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
815 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
816 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
817 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
818 else
819 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
820 }
821
822 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
823 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
824 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
825 image->info.surf_index = &device->image_mrt_offset_counter;
826 }
827
828 radv_init_surface(device, &image->surface, create_info);
829
830 device->ws->surface_init(device->ws, &image->info, &image->surface);
831
832 image->size = image->surface.surf_size;
833 image->alignment = image->surface.surf_alignment;
834
835 if (image->exclusive || image->queue_family_mask == 1)
836 can_cmask_dcc = true;
837
838 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
839 image->surface.dcc_size && can_cmask_dcc)
840 radv_image_alloc_dcc(device, image);
841 else
842 image->surface.dcc_size = 0;
843
844 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
845 pCreateInfo->mipLevels == 1 &&
846 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc &&
847 !image->surface.is_linear)
848 radv_image_alloc_cmask(device, image);
849
850 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
851 radv_image_alloc_fmask(device, image);
852 } else if (vk_format_is_depth(pCreateInfo->format)) {
853
854 radv_image_alloc_htile(device, image);
855 }
856
857 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
858 image->alignment = MAX2(image->alignment, 4096);
859 image->size = align64(image->size, image->alignment);
860 image->offset = 0;
861
862 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
863 0, RADEON_FLAG_VIRTUAL);
864 if (!image->bo) {
865 vk_free2(&device->alloc, alloc, image);
866 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
867 }
868 }
869
870 *pImage = radv_image_to_handle(image);
871
872 return VK_SUCCESS;
873 }
874
875 static void
876 radv_image_view_make_descriptor(struct radv_image_view *iview,
877 struct radv_device *device,
878 const VkComponentMapping *components,
879 bool is_storage_image)
880 {
881 struct radv_image *image = iview->image;
882 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
883 uint32_t blk_w;
884 uint32_t *descriptor;
885 uint32_t *fmask_descriptor;
886 uint32_t hw_level = 0;
887
888 if (is_storage_image) {
889 descriptor = iview->storage_descriptor;
890 fmask_descriptor = iview->storage_fmask_descriptor;
891 } else {
892 descriptor = iview->descriptor;
893 fmask_descriptor = iview->fmask_descriptor;
894 }
895
896 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
897 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
898
899 if (device->physical_device->rad_info.chip_class >= GFX9)
900 hw_level = iview->base_mip;
901 si_make_texture_descriptor(device, image, is_storage_image,
902 iview->type,
903 iview->vk_format,
904 components,
905 hw_level, hw_level + iview->level_count - 1,
906 iview->base_layer,
907 iview->base_layer + iview->layer_count - 1,
908 iview->extent.width,
909 iview->extent.height,
910 iview->extent.depth,
911 descriptor,
912 fmask_descriptor);
913
914 const struct legacy_surf_level *base_level_info = NULL;
915 if (device->physical_device->rad_info.chip_class <= GFX9) {
916 if (is_stencil)
917 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
918 else
919 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
920 }
921 si_set_mutable_tex_desc_fields(device, image,
922 base_level_info,
923 iview->base_mip,
924 iview->base_mip,
925 blk_w, is_stencil, descriptor);
926 }
927
928 void
929 radv_image_view_init(struct radv_image_view *iview,
930 struct radv_device *device,
931 const VkImageViewCreateInfo* pCreateInfo)
932 {
933 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
934 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
935
936 switch (image->type) {
937 case VK_IMAGE_TYPE_1D:
938 case VK_IMAGE_TYPE_2D:
939 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
940 break;
941 case VK_IMAGE_TYPE_3D:
942 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
943 <= radv_minify(image->info.depth, range->baseMipLevel));
944 break;
945 default:
946 unreachable("bad VkImageType");
947 }
948 iview->image = image;
949 iview->bo = image->bo;
950 iview->type = pCreateInfo->viewType;
951 iview->vk_format = pCreateInfo->format;
952 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
953
954 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
955 iview->vk_format = vk_format_stencil_only(iview->vk_format);
956 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
957 iview->vk_format = vk_format_depth_only(iview->vk_format);
958 }
959
960 if (device->physical_device->rad_info.chip_class >= GFX9) {
961 iview->extent = (VkExtent3D) {
962 .width = image->info.width,
963 .height = image->info.height,
964 .depth = image->info.depth,
965 };
966 } else {
967 iview->extent = (VkExtent3D) {
968 .width = radv_minify(image->info.width , range->baseMipLevel),
969 .height = radv_minify(image->info.height, range->baseMipLevel),
970 .depth = radv_minify(image->info.depth , range->baseMipLevel),
971 };
972 }
973
974 if (iview->vk_format != image->vk_format) {
975 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
976 vk_format_get_blockwidth(image->vk_format));
977 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
978 vk_format_get_blockheight(image->vk_format));
979 }
980
981 iview->base_layer = range->baseArrayLayer;
982 iview->layer_count = radv_get_layerCount(image, range);
983 iview->base_mip = range->baseMipLevel;
984 iview->level_count = radv_get_levelCount(image, range);
985
986 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
987 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
988 }
989
990 bool radv_layout_has_htile(const struct radv_image *image,
991 VkImageLayout layout,
992 unsigned queue_mask)
993 {
994 return image->surface.htile_size &&
995 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
996 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
997 queue_mask == (1u << RADV_QUEUE_GENERAL);
998 }
999
1000 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1001 VkImageLayout layout,
1002 unsigned queue_mask)
1003 {
1004 return image->surface.htile_size &&
1005 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1006 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1007 queue_mask == (1u << RADV_QUEUE_GENERAL);
1008 }
1009
1010 bool radv_layout_can_fast_clear(const struct radv_image *image,
1011 VkImageLayout layout,
1012 unsigned queue_mask)
1013 {
1014 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1015 queue_mask == (1u << RADV_QUEUE_GENERAL);
1016 }
1017
1018
1019 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1020 {
1021 if (!image->exclusive)
1022 return image->queue_family_mask;
1023 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1024 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1025 if (family == VK_QUEUE_FAMILY_IGNORED)
1026 return 1u << queue_family;
1027 return 1u << family;
1028 }
1029
1030 VkResult
1031 radv_CreateImage(VkDevice device,
1032 const VkImageCreateInfo *pCreateInfo,
1033 const VkAllocationCallbacks *pAllocator,
1034 VkImage *pImage)
1035 {
1036 return radv_image_create(device,
1037 &(struct radv_image_create_info) {
1038 .vk_info = pCreateInfo,
1039 .scanout = false,
1040 },
1041 pAllocator,
1042 pImage);
1043 }
1044
1045 void
1046 radv_DestroyImage(VkDevice _device, VkImage _image,
1047 const VkAllocationCallbacks *pAllocator)
1048 {
1049 RADV_FROM_HANDLE(radv_device, device, _device);
1050 RADV_FROM_HANDLE(radv_image, image, _image);
1051
1052 if (!image)
1053 return;
1054
1055 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1056 device->ws->buffer_destroy(image->bo);
1057
1058 vk_free2(&device->alloc, pAllocator, image);
1059 }
1060
1061 void radv_GetImageSubresourceLayout(
1062 VkDevice _device,
1063 VkImage _image,
1064 const VkImageSubresource* pSubresource,
1065 VkSubresourceLayout* pLayout)
1066 {
1067 RADV_FROM_HANDLE(radv_image, image, _image);
1068 RADV_FROM_HANDLE(radv_device, device, _device);
1069 int level = pSubresource->mipLevel;
1070 int layer = pSubresource->arrayLayer;
1071 struct radeon_surf *surface = &image->surface;
1072
1073 if (device->physical_device->rad_info.chip_class >= GFX9) {
1074 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1075 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1076 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1077 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1078 pLayout->size = surface->u.gfx9.surf_slice_size;
1079 if (image->type == VK_IMAGE_TYPE_3D)
1080 pLayout->size *= u_minify(image->info.depth, level);
1081 } else {
1082 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1083 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1084 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1085 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1086 pLayout->size = surface->u.legacy.level[level].slice_size;
1087 if (image->type == VK_IMAGE_TYPE_3D)
1088 pLayout->size *= u_minify(image->info.depth, level);
1089 }
1090 }
1091
1092
1093 VkResult
1094 radv_CreateImageView(VkDevice _device,
1095 const VkImageViewCreateInfo *pCreateInfo,
1096 const VkAllocationCallbacks *pAllocator,
1097 VkImageView *pView)
1098 {
1099 RADV_FROM_HANDLE(radv_device, device, _device);
1100 struct radv_image_view *view;
1101
1102 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1103 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1104 if (view == NULL)
1105 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1106
1107 radv_image_view_init(view, device, pCreateInfo);
1108
1109 *pView = radv_image_view_to_handle(view);
1110
1111 return VK_SUCCESS;
1112 }
1113
1114 void
1115 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1116 const VkAllocationCallbacks *pAllocator)
1117 {
1118 RADV_FROM_HANDLE(radv_device, device, _device);
1119 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1120
1121 if (!iview)
1122 return;
1123 vk_free2(&device->alloc, pAllocator, iview);
1124 }
1125
1126 void radv_buffer_view_init(struct radv_buffer_view *view,
1127 struct radv_device *device,
1128 const VkBufferViewCreateInfo* pCreateInfo)
1129 {
1130 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1131
1132 view->bo = buffer->bo;
1133 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1134 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1135 view->vk_format = pCreateInfo->format;
1136
1137 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1138 pCreateInfo->offset, view->range, view->state);
1139 }
1140
1141 VkResult
1142 radv_CreateBufferView(VkDevice _device,
1143 const VkBufferViewCreateInfo *pCreateInfo,
1144 const VkAllocationCallbacks *pAllocator,
1145 VkBufferView *pView)
1146 {
1147 RADV_FROM_HANDLE(radv_device, device, _device);
1148 struct radv_buffer_view *view;
1149
1150 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1151 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1152 if (!view)
1153 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1154
1155 radv_buffer_view_init(view, device, pCreateInfo);
1156
1157 *pView = radv_buffer_view_to_handle(view);
1158
1159 return VK_SUCCESS;
1160 }
1161
1162 void
1163 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1164 const VkAllocationCallbacks *pAllocator)
1165 {
1166 RADV_FROM_HANDLE(radv_device, device, _device);
1167 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1168
1169 if (!view)
1170 return;
1171
1172 vk_free2(&device->alloc, pAllocator, view);
1173 }