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radv: move RADV_TRACE_FILE functions to radv_debug.c
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *Device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)) {
50 /* Textures with a very small height are recommended to be linear. */
51 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
52 /* Only very thin and long 2D textures should benefit from
53 * linear_aligned. */
54 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
55 return RADEON_SURF_MODE_LINEAR_ALIGNED;
56
57 }
58
59 /* MSAA resources must be 2D tiled. */
60 if (pCreateInfo->samples > 1)
61 return RADEON_SURF_MODE_2D;
62
63 return RADEON_SURF_MODE_2D;
64 }
65 static int
66 radv_init_surface(struct radv_device *device,
67 struct radeon_surf *surface,
68 const struct radv_image_create_info *create_info)
69 {
70 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
71 unsigned array_mode = radv_choose_tiling(device, create_info);
72 const struct vk_format_description *desc =
73 vk_format_description(pCreateInfo->format);
74 bool is_depth, is_stencil, blendable;
75
76 is_depth = vk_format_has_depth(desc);
77 is_stencil = vk_format_has_stencil(desc);
78
79 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
80 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
81
82 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
83 /* align byte per element on dword */
84 if (surface->bpe == 3) {
85 surface->bpe = 4;
86 }
87 surface->flags = RADEON_SURF_SET(array_mode, MODE);
88
89 switch (pCreateInfo->imageType){
90 case VK_IMAGE_TYPE_1D:
91 if (pCreateInfo->arrayLayers > 1)
92 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
93 else
94 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
95 break;
96 case VK_IMAGE_TYPE_2D:
97 if (pCreateInfo->arrayLayers > 1)
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
99 else
100 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
101 break;
102 case VK_IMAGE_TYPE_3D:
103 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
104 break;
105 default:
106 unreachable("unhandled image type");
107 }
108
109 if (is_depth) {
110 surface->flags |= RADEON_SURF_ZBUFFER;
111 }
112
113 if (is_stencil)
114 surface->flags |= RADEON_SURF_SBUFFER;
115
116 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
117
118 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
119 VK_IMAGE_USAGE_STORAGE_BIT)) ||
120 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
121 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
122 device->physical_device->rad_info.chip_class < VI ||
123 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
124 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
125 surface->flags |= RADEON_SURF_DISABLE_DCC;
126 if (create_info->scanout)
127 surface->flags |= RADEON_SURF_SCANOUT;
128 return 0;
129 }
130 #define ATI_VENDOR_ID 0x1002
131 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
132 {
133 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
134 }
135
136 static inline unsigned
137 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
138 {
139 if (stencil)
140 return image->surface.u.legacy.stencil_tiling_index[level];
141 else
142 return image->surface.u.legacy.tiling_index[level];
143 }
144
145 static unsigned radv_map_swizzle(unsigned swizzle)
146 {
147 switch (swizzle) {
148 case VK_SWIZZLE_Y:
149 return V_008F0C_SQ_SEL_Y;
150 case VK_SWIZZLE_Z:
151 return V_008F0C_SQ_SEL_Z;
152 case VK_SWIZZLE_W:
153 return V_008F0C_SQ_SEL_W;
154 case VK_SWIZZLE_0:
155 return V_008F0C_SQ_SEL_0;
156 case VK_SWIZZLE_1:
157 return V_008F0C_SQ_SEL_1;
158 default: /* VK_SWIZZLE_X */
159 return V_008F0C_SQ_SEL_X;
160 }
161 }
162
163 static void
164 radv_make_buffer_descriptor(struct radv_device *device,
165 struct radv_buffer *buffer,
166 VkFormat vk_format,
167 unsigned offset,
168 unsigned range,
169 uint32_t *state)
170 {
171 const struct vk_format_description *desc;
172 unsigned stride;
173 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
174 uint64_t va = gpu_address + buffer->offset;
175 unsigned num_format, data_format;
176 int first_non_void;
177 desc = vk_format_description(vk_format);
178 first_non_void = vk_format_get_first_non_void_channel(vk_format);
179 stride = desc->block.bits / 8;
180
181 num_format = radv_translate_buffer_numformat(desc, first_non_void);
182 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
183
184 va += offset;
185 state[0] = va;
186 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
187 S_008F04_STRIDE(stride);
188
189 if (device->physical_device->rad_info.chip_class != VI && stride) {
190 range /= stride;
191 }
192
193 state[2] = range;
194 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
195 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
196 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
197 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
198 S_008F0C_NUM_FORMAT(num_format) |
199 S_008F0C_DATA_FORMAT(data_format);
200 }
201
202 static void
203 si_set_mutable_tex_desc_fields(struct radv_device *device,
204 struct radv_image *image,
205 const struct legacy_surf_level *base_level_info,
206 unsigned base_level, unsigned first_level,
207 unsigned block_width, bool is_stencil,
208 uint32_t *state)
209 {
210 uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
211 uint64_t va = gpu_address;
212 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
213 uint64_t meta_va = 0;
214 if (chip_class >= GFX9) {
215 if (is_stencil)
216 va += image->surface.u.gfx9.stencil_offset;
217 else
218 va += image->surface.u.gfx9.surf_offset;
219 } else
220 va += base_level_info->offset;
221
222 state[0] = va >> 8;
223 if (chip_class >= GFX9 ||
224 base_level_info->mode == RADEON_SURF_MODE_2D)
225 state[0] |= image->surface.tile_swizzle;
226 state[1] &= C_008F14_BASE_ADDRESS_HI;
227 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
228
229 if (chip_class >= VI) {
230 state[6] &= C_008F28_COMPRESSION_EN;
231 state[7] = 0;
232 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
233 meta_va = gpu_address + image->dcc_offset;
234 if (chip_class <= VI)
235 meta_va += base_level_info->dcc_offset;
236 state[6] |= S_008F28_COMPRESSION_EN(1);
237 state[7] = meta_va >> 8;
238 state[7] |= image->surface.tile_swizzle;
239 }
240 }
241
242 if (chip_class >= GFX9) {
243 state[3] &= C_008F1C_SW_MODE;
244 state[4] &= C_008F20_PITCH_GFX9;
245
246 if (is_stencil) {
247 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
248 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
249 } else {
250 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
251 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
252 }
253
254 state[5] &= C_008F24_META_DATA_ADDRESS &
255 C_008F24_META_PIPE_ALIGNED &
256 C_008F24_META_RB_ALIGNED;
257 if (meta_va) {
258 struct gfx9_surf_meta_flags meta;
259
260 if (image->dcc_offset)
261 meta = image->surface.u.gfx9.dcc;
262 else
263 meta = image->surface.u.gfx9.htile;
264
265 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
266 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
267 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
268 }
269 } else {
270 /* SI-CI-VI */
271 unsigned pitch = base_level_info->nblk_x * block_width;
272 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
273
274 state[3] &= C_008F1C_TILING_INDEX;
275 state[3] |= S_008F1C_TILING_INDEX(index);
276 state[4] &= C_008F20_PITCH_GFX6;
277 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
278 }
279 }
280
281 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
282 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
283 {
284 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
285 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
286 switch (image_type) {
287 case VK_IMAGE_TYPE_1D:
288 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
289 case VK_IMAGE_TYPE_2D:
290 if (nr_samples > 1)
291 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
292 else
293 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
294 case VK_IMAGE_TYPE_3D:
295 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
296 return V_008F1C_SQ_RSRC_IMG_3D;
297 else
298 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
299 default:
300 unreachable("illegale image type");
301 }
302 }
303
304 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
305 {
306 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
307
308 if (swizzle[3] == VK_SWIZZLE_X) {
309 /* For the pre-defined border color values (white, opaque
310 * black, transparent black), the only thing that matters is
311 * that the alpha channel winds up in the correct place
312 * (because the RGB channels are all the same) so either of
313 * these enumerations will work.
314 */
315 if (swizzle[2] == VK_SWIZZLE_Y)
316 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
317 else
318 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
319 } else if (swizzle[0] == VK_SWIZZLE_X) {
320 if (swizzle[1] == VK_SWIZZLE_Y)
321 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
322 else
323 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
324 } else if (swizzle[1] == VK_SWIZZLE_X) {
325 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
326 } else if (swizzle[2] == VK_SWIZZLE_X) {
327 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
328 }
329
330 return bc_swizzle;
331 }
332
333 /**
334 * Build the sampler view descriptor for a texture.
335 */
336 static void
337 si_make_texture_descriptor(struct radv_device *device,
338 struct radv_image *image,
339 bool is_storage_image,
340 VkImageViewType view_type,
341 VkFormat vk_format,
342 const VkComponentMapping *mapping,
343 unsigned first_level, unsigned last_level,
344 unsigned first_layer, unsigned last_layer,
345 unsigned width, unsigned height, unsigned depth,
346 uint32_t *state,
347 uint32_t *fmask_state)
348 {
349 const struct vk_format_description *desc;
350 enum vk_swizzle swizzle[4];
351 int first_non_void;
352 unsigned num_format, data_format, type;
353
354 desc = vk_format_description(vk_format);
355
356 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
357 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
358 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
359 } else {
360 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
361 }
362
363 first_non_void = vk_format_get_first_non_void_channel(vk_format);
364
365 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
366 if (num_format == ~0) {
367 num_format = 0;
368 }
369
370 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
371 if (data_format == ~0) {
372 data_format = 0;
373 }
374
375 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
376 is_storage_image);
377 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
378 height = 1;
379 depth = image->info.array_size;
380 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
381 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
382 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
383 depth = image->info.array_size;
384 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
385 depth = image->info.array_size / 6;
386
387 state[0] = 0;
388 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
389 S_008F14_NUM_FORMAT_GFX6(num_format));
390 state[2] = (S_008F18_WIDTH(width - 1) |
391 S_008F18_HEIGHT(height - 1) |
392 S_008F18_PERF_MOD(4));
393 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
394 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
395 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
396 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
397 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
398 0 : first_level) |
399 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
400 util_logbase2(image->info.samples) :
401 last_level) |
402 S_008F1C_TYPE(type));
403 state[4] = 0;
404 state[5] = S_008F24_BASE_ARRAY(first_layer);
405 state[6] = 0;
406 state[7] = 0;
407
408 if (device->physical_device->rad_info.chip_class >= GFX9) {
409 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
410
411 /* Depth is the the last accessible layer on Gfx9.
412 * The hw doesn't need to know the total number of layers.
413 */
414 if (type == V_008F1C_SQ_RSRC_IMG_3D)
415 state[4] |= S_008F20_DEPTH(depth - 1);
416 else
417 state[4] |= S_008F20_DEPTH(last_layer);
418
419 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
420 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
421 util_logbase2(image->info.samples) :
422 image->info.levels - 1);
423 } else {
424 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
425 state[4] |= S_008F20_DEPTH(depth - 1);
426 state[5] |= S_008F24_LAST_ARRAY(last_layer);
427 }
428 if (image->dcc_offset) {
429 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
430
431 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
432 } else {
433 /* The last dword is unused by hw. The shader uses it to clear
434 * bits in the first dword of sampler state.
435 */
436 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
437 if (first_level == last_level)
438 state[7] = C_008F30_MAX_ANISO_RATIO;
439 else
440 state[7] = 0xffffffff;
441 }
442 }
443
444 /* Initialize the sampler view for FMASK. */
445 if (image->fmask.size) {
446 uint32_t fmask_format, num_format;
447 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
448 uint64_t va;
449
450 va = gpu_address + image->offset + image->fmask.offset;
451
452 if (device->physical_device->rad_info.chip_class >= GFX9) {
453 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
454 switch (image->info.samples) {
455 case 2:
456 num_format = V_008F14_IMG_FMASK_8_2_2;
457 break;
458 case 4:
459 num_format = V_008F14_IMG_FMASK_8_4_4;
460 break;
461 case 8:
462 num_format = V_008F14_IMG_FMASK_32_8_8;
463 break;
464 default:
465 unreachable("invalid nr_samples");
466 }
467 } else {
468 switch (image->info.samples) {
469 case 2:
470 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
471 break;
472 case 4:
473 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
474 break;
475 case 8:
476 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
477 break;
478 default:
479 assert(0);
480 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
481 }
482 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
483 }
484
485 fmask_state[0] = va >> 8;
486 fmask_state[0] |= image->fmask.tile_swizzle;
487 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
488 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
489 S_008F14_NUM_FORMAT_GFX6(num_format);
490 fmask_state[2] = S_008F18_WIDTH(width - 1) |
491 S_008F18_HEIGHT(height - 1);
492 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
493 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
494 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
495 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
496 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
497 fmask_state[4] = 0;
498 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
499 fmask_state[6] = 0;
500 fmask_state[7] = 0;
501
502 if (device->physical_device->rad_info.chip_class >= GFX9) {
503 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
504 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
505 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
506 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
507 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
508 } else {
509 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
510 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
511 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
512 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
513 }
514 } else if (fmask_state)
515 memset(fmask_state, 0, 8 * 4);
516 }
517
518 static void
519 radv_query_opaque_metadata(struct radv_device *device,
520 struct radv_image *image,
521 struct radeon_bo_metadata *md)
522 {
523 static const VkComponentMapping fixedmapping;
524 uint32_t desc[8], i;
525
526 /* Metadata image format format version 1:
527 * [0] = 1 (metadata format identifier)
528 * [1] = (VENDOR_ID << 16) | PCI_ID
529 * [2:9] = image descriptor for the whole resource
530 * [2] is always 0, because the base address is cleared
531 * [9] is the DCC offset bits [39:8] from the beginning of
532 * the buffer
533 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
534 */
535 md->metadata[0] = 1; /* metadata image format version 1 */
536
537 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
538 md->metadata[1] = si_get_bo_metadata_word1(device);
539
540
541 si_make_texture_descriptor(device, image, false,
542 (VkImageViewType)image->type, image->vk_format,
543 &fixedmapping, 0, image->info.levels - 1, 0,
544 image->info.array_size,
545 image->info.width, image->info.height,
546 image->info.depth,
547 desc, NULL);
548
549 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
550 image->surface.blk_w, false, desc);
551
552 /* Clear the base address and set the relative DCC offset. */
553 desc[0] = 0;
554 desc[1] &= C_008F14_BASE_ADDRESS_HI;
555 desc[7] = image->dcc_offset >> 8;
556
557 /* Dwords [2:9] contain the image descriptor. */
558 memcpy(&md->metadata[2], desc, sizeof(desc));
559
560 /* Dwords [10:..] contain the mipmap level offsets. */
561 if (device->physical_device->rad_info.chip_class <= VI) {
562 for (i = 0; i <= image->info.levels - 1; i++)
563 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
564 md->size_metadata = (11 + image->info.levels - 1) * 4;
565 }
566 }
567
568 void
569 radv_init_metadata(struct radv_device *device,
570 struct radv_image *image,
571 struct radeon_bo_metadata *metadata)
572 {
573 struct radeon_surf *surface = &image->surface;
574
575 memset(metadata, 0, sizeof(*metadata));
576
577 if (device->physical_device->rad_info.chip_class >= GFX9) {
578 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
579 } else {
580 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
581 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
582 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
583 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
584 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
585 metadata->u.legacy.bankw = surface->u.legacy.bankw;
586 metadata->u.legacy.bankh = surface->u.legacy.bankh;
587 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
588 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
589 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
590 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
591 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
592 }
593 radv_query_opaque_metadata(device, image, metadata);
594 }
595
596 /* The number of samples can be specified independently of the texture. */
597 static void
598 radv_image_get_fmask_info(struct radv_device *device,
599 struct radv_image *image,
600 unsigned nr_samples,
601 struct radv_fmask_info *out)
602 {
603 /* FMASK is allocated like an ordinary texture. */
604 struct radeon_surf fmask = {};
605 struct ac_surf_info info = image->info;
606 memset(out, 0, sizeof(*out));
607
608 if (device->physical_device->rad_info.chip_class >= GFX9) {
609 out->alignment = image->surface.u.gfx9.fmask_alignment;
610 out->size = image->surface.u.gfx9.fmask_size;
611 return;
612 }
613
614 fmask.blk_w = image->surface.blk_w;
615 fmask.blk_h = image->surface.blk_h;
616 info.samples = 1;
617 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
618
619 if (!image->shareable)
620 info.surf_index = &device->fmask_mrt_offset_counter;
621
622 /* Force 2D tiling if it wasn't set. This may occur when creating
623 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
624 * destination buffer must have an FMASK too. */
625 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
626 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
627
628 switch (nr_samples) {
629 case 2:
630 case 4:
631 fmask.bpe = 1;
632 break;
633 case 8:
634 fmask.bpe = 4;
635 break;
636 default:
637 return;
638 }
639
640 device->ws->surface_init(device->ws, &info, &fmask);
641 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
642
643 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
644 if (out->slice_tile_max)
645 out->slice_tile_max -= 1;
646
647 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
648 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
649 out->bank_height = fmask.u.legacy.bankh;
650 out->tile_swizzle = fmask.tile_swizzle;
651 out->alignment = MAX2(256, fmask.surf_alignment);
652 out->size = fmask.surf_size;
653
654 assert(!out->tile_swizzle || !image->shareable);
655 }
656
657 static void
658 radv_image_alloc_fmask(struct radv_device *device,
659 struct radv_image *image)
660 {
661 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
662
663 image->fmask.offset = align64(image->size, image->fmask.alignment);
664 image->size = image->fmask.offset + image->fmask.size;
665 image->alignment = MAX2(image->alignment, image->fmask.alignment);
666 }
667
668 static void
669 radv_image_get_cmask_info(struct radv_device *device,
670 struct radv_image *image,
671 struct radv_cmask_info *out)
672 {
673 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
674 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
675 unsigned cl_width, cl_height;
676
677 if (device->physical_device->rad_info.chip_class >= GFX9) {
678 out->alignment = image->surface.u.gfx9.cmask_alignment;
679 out->size = image->surface.u.gfx9.cmask_size;
680 return;
681 }
682
683 switch (num_pipes) {
684 case 2:
685 cl_width = 32;
686 cl_height = 16;
687 break;
688 case 4:
689 cl_width = 32;
690 cl_height = 32;
691 break;
692 case 8:
693 cl_width = 64;
694 cl_height = 32;
695 break;
696 case 16: /* Hawaii */
697 cl_width = 64;
698 cl_height = 64;
699 break;
700 default:
701 assert(0);
702 return;
703 }
704
705 unsigned base_align = num_pipes * pipe_interleave_bytes;
706
707 unsigned width = align(image->info.width, cl_width*8);
708 unsigned height = align(image->info.height, cl_height*8);
709 unsigned slice_elements = (width * height) / (8*8);
710
711 /* Each element of CMASK is a nibble. */
712 unsigned slice_bytes = slice_elements / 2;
713
714 out->slice_tile_max = (width * height) / (128*128);
715 if (out->slice_tile_max)
716 out->slice_tile_max -= 1;
717
718 out->alignment = MAX2(256, base_align);
719 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
720 align(slice_bytes, base_align);
721 }
722
723 static void
724 radv_image_alloc_cmask(struct radv_device *device,
725 struct radv_image *image)
726 {
727 uint32_t clear_value_size = 0;
728 radv_image_get_cmask_info(device, image, &image->cmask);
729
730 image->cmask.offset = align64(image->size, image->cmask.alignment);
731 /* + 8 for storing the clear values */
732 if (!image->clear_value_offset) {
733 image->clear_value_offset = image->cmask.offset + image->cmask.size;
734 clear_value_size = 8;
735 }
736 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
737 image->alignment = MAX2(image->alignment, image->cmask.alignment);
738 }
739
740 static void
741 radv_image_alloc_dcc(struct radv_device *device,
742 struct radv_image *image)
743 {
744 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
745 /* + 16 for storing the clear values + dcc pred */
746 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
747 image->dcc_pred_offset = image->clear_value_offset + 8;
748 image->size = image->dcc_offset + image->surface.dcc_size + 16;
749 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
750 }
751
752 static void
753 radv_image_alloc_htile(struct radv_device *device,
754 struct radv_image *image)
755 {
756 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
757 image->surface.htile_size = 0;
758 return;
759 }
760
761 image->htile_offset = align64(image->size, image->surface.htile_alignment);
762
763 /* + 8 for storing the clear values */
764 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
765 image->size = image->clear_value_offset + 8;
766 image->alignment = align64(image->alignment, image->surface.htile_alignment);
767 }
768
769 VkResult
770 radv_image_create(VkDevice _device,
771 const struct radv_image_create_info *create_info,
772 const VkAllocationCallbacks* alloc,
773 VkImage *pImage)
774 {
775 RADV_FROM_HANDLE(radv_device, device, _device);
776 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
777 struct radv_image *image = NULL;
778 bool can_cmask_dcc = false;
779 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
780
781 radv_assert(pCreateInfo->mipLevels > 0);
782 radv_assert(pCreateInfo->arrayLayers > 0);
783 radv_assert(pCreateInfo->samples > 0);
784 radv_assert(pCreateInfo->extent.width > 0);
785 radv_assert(pCreateInfo->extent.height > 0);
786 radv_assert(pCreateInfo->extent.depth > 0);
787
788 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
789 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
790 if (!image)
791 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
792
793 memset(image, 0, sizeof(*image));
794 image->type = pCreateInfo->imageType;
795 image->info.width = pCreateInfo->extent.width;
796 image->info.height = pCreateInfo->extent.height;
797 image->info.depth = pCreateInfo->extent.depth;
798 image->info.samples = pCreateInfo->samples;
799 image->info.array_size = pCreateInfo->arrayLayers;
800 image->info.levels = pCreateInfo->mipLevels;
801
802 image->vk_format = pCreateInfo->format;
803 image->tiling = pCreateInfo->tiling;
804 image->usage = pCreateInfo->usage;
805 image->flags = pCreateInfo->flags;
806
807 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
808 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
809 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
810 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
811 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
812 else
813 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
814 }
815
816 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
817 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
818 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
819 image->info.surf_index = &device->image_mrt_offset_counter;
820 }
821
822 radv_init_surface(device, &image->surface, create_info);
823
824 device->ws->surface_init(device->ws, &image->info, &image->surface);
825
826 image->size = image->surface.surf_size;
827 image->alignment = image->surface.surf_alignment;
828
829 if (image->exclusive || image->queue_family_mask == 1)
830 can_cmask_dcc = true;
831
832 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
833 image->surface.dcc_size && can_cmask_dcc)
834 radv_image_alloc_dcc(device, image);
835 else
836 image->surface.dcc_size = 0;
837
838 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
839 pCreateInfo->mipLevels == 1 &&
840 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
841 radv_image_alloc_cmask(device, image);
842 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
843 radv_image_alloc_fmask(device, image);
844 } else if (vk_format_is_depth(pCreateInfo->format)) {
845
846 radv_image_alloc_htile(device, image);
847 }
848
849 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
850 image->alignment = MAX2(image->alignment, 4096);
851 image->size = align64(image->size, image->alignment);
852 image->offset = 0;
853
854 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
855 0, RADEON_FLAG_VIRTUAL);
856 if (!image->bo) {
857 vk_free2(&device->alloc, alloc, image);
858 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
859 }
860 }
861
862 *pImage = radv_image_to_handle(image);
863
864 return VK_SUCCESS;
865 }
866
867 static void
868 radv_image_view_make_descriptor(struct radv_image_view *iview,
869 struct radv_device *device,
870 const VkComponentMapping *components,
871 bool is_storage_image)
872 {
873 struct radv_image *image = iview->image;
874 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
875 uint32_t blk_w;
876 uint32_t *descriptor;
877 uint32_t *fmask_descriptor;
878
879 if (is_storage_image) {
880 descriptor = iview->storage_descriptor;
881 fmask_descriptor = iview->storage_fmask_descriptor;
882 } else {
883 descriptor = iview->descriptor;
884 fmask_descriptor = iview->fmask_descriptor;
885 }
886
887 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
888 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
889
890 si_make_texture_descriptor(device, image, is_storage_image,
891 iview->type,
892 iview->vk_format,
893 components,
894 0, iview->level_count - 1,
895 iview->base_layer,
896 iview->base_layer + iview->layer_count - 1,
897 iview->extent.width,
898 iview->extent.height,
899 iview->extent.depth,
900 descriptor,
901 fmask_descriptor);
902
903 const struct legacy_surf_level *base_level_info = NULL;
904 if (device->physical_device->rad_info.chip_class <= GFX9) {
905 if (is_stencil)
906 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
907 else
908 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
909 }
910 si_set_mutable_tex_desc_fields(device, image,
911 base_level_info,
912 iview->base_mip,
913 iview->base_mip,
914 blk_w, is_stencil, descriptor);
915 }
916
917 void
918 radv_image_view_init(struct radv_image_view *iview,
919 struct radv_device *device,
920 const VkImageViewCreateInfo* pCreateInfo)
921 {
922 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
923 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
924
925 switch (image->type) {
926 case VK_IMAGE_TYPE_1D:
927 case VK_IMAGE_TYPE_2D:
928 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
929 break;
930 case VK_IMAGE_TYPE_3D:
931 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
932 <= radv_minify(image->info.depth, range->baseMipLevel));
933 break;
934 default:
935 unreachable("bad VkImageType");
936 }
937 iview->image = image;
938 iview->bo = image->bo;
939 iview->type = pCreateInfo->viewType;
940 iview->vk_format = pCreateInfo->format;
941 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
942
943 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
944 iview->vk_format = vk_format_stencil_only(iview->vk_format);
945 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
946 iview->vk_format = vk_format_depth_only(iview->vk_format);
947 }
948
949 if (device->physical_device->rad_info.chip_class >= GFX9) {
950 iview->extent = (VkExtent3D) {
951 .width = image->info.width,
952 .height = image->info.height,
953 .depth = image->info.depth,
954 };
955 } else {
956 iview->extent = (VkExtent3D) {
957 .width = radv_minify(image->info.width , range->baseMipLevel),
958 .height = radv_minify(image->info.height, range->baseMipLevel),
959 .depth = radv_minify(image->info.depth , range->baseMipLevel),
960 };
961 }
962
963 if (iview->vk_format != image->vk_format) {
964 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
965 vk_format_get_blockwidth(image->vk_format));
966 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
967 vk_format_get_blockheight(image->vk_format));
968 }
969
970 iview->base_layer = range->baseArrayLayer;
971 iview->layer_count = radv_get_layerCount(image, range);
972 iview->base_mip = range->baseMipLevel;
973 iview->level_count = radv_get_levelCount(image, range);
974
975 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
976 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
977 }
978
979 bool radv_layout_has_htile(const struct radv_image *image,
980 VkImageLayout layout,
981 unsigned queue_mask)
982 {
983 return image->surface.htile_size &&
984 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
985 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
986 queue_mask == (1u << RADV_QUEUE_GENERAL);
987 }
988
989 bool radv_layout_is_htile_compressed(const struct radv_image *image,
990 VkImageLayout layout,
991 unsigned queue_mask)
992 {
993 return image->surface.htile_size &&
994 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
995 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
996 queue_mask == (1u << RADV_QUEUE_GENERAL);
997 }
998
999 bool radv_layout_can_fast_clear(const struct radv_image *image,
1000 VkImageLayout layout,
1001 unsigned queue_mask)
1002 {
1003 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1004 queue_mask == (1u << RADV_QUEUE_GENERAL);
1005 }
1006
1007
1008 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1009 {
1010 if (!image->exclusive)
1011 return image->queue_family_mask;
1012 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1013 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1014 if (family == VK_QUEUE_FAMILY_IGNORED)
1015 return 1u << queue_family;
1016 return 1u << family;
1017 }
1018
1019 VkResult
1020 radv_CreateImage(VkDevice device,
1021 const VkImageCreateInfo *pCreateInfo,
1022 const VkAllocationCallbacks *pAllocator,
1023 VkImage *pImage)
1024 {
1025 return radv_image_create(device,
1026 &(struct radv_image_create_info) {
1027 .vk_info = pCreateInfo,
1028 .scanout = false,
1029 },
1030 pAllocator,
1031 pImage);
1032 }
1033
1034 void
1035 radv_DestroyImage(VkDevice _device, VkImage _image,
1036 const VkAllocationCallbacks *pAllocator)
1037 {
1038 RADV_FROM_HANDLE(radv_device, device, _device);
1039 RADV_FROM_HANDLE(radv_image, image, _image);
1040
1041 if (!image)
1042 return;
1043
1044 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1045 device->ws->buffer_destroy(image->bo);
1046
1047 vk_free2(&device->alloc, pAllocator, image);
1048 }
1049
1050 void radv_GetImageSubresourceLayout(
1051 VkDevice device,
1052 VkImage _image,
1053 const VkImageSubresource* pSubresource,
1054 VkSubresourceLayout* pLayout)
1055 {
1056 RADV_FROM_HANDLE(radv_image, image, _image);
1057 int level = pSubresource->mipLevel;
1058 int layer = pSubresource->arrayLayer;
1059 struct radeon_surf *surface = &image->surface;
1060
1061 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1062 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1063 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1064 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1065 pLayout->size = surface->u.legacy.level[level].slice_size;
1066 if (image->type == VK_IMAGE_TYPE_3D)
1067 pLayout->size *= u_minify(image->info.depth, level);
1068 }
1069
1070
1071 VkResult
1072 radv_CreateImageView(VkDevice _device,
1073 const VkImageViewCreateInfo *pCreateInfo,
1074 const VkAllocationCallbacks *pAllocator,
1075 VkImageView *pView)
1076 {
1077 RADV_FROM_HANDLE(radv_device, device, _device);
1078 struct radv_image_view *view;
1079
1080 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1081 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1082 if (view == NULL)
1083 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1084
1085 radv_image_view_init(view, device, pCreateInfo);
1086
1087 *pView = radv_image_view_to_handle(view);
1088
1089 return VK_SUCCESS;
1090 }
1091
1092 void
1093 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1094 const VkAllocationCallbacks *pAllocator)
1095 {
1096 RADV_FROM_HANDLE(radv_device, device, _device);
1097 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1098
1099 if (!iview)
1100 return;
1101 vk_free2(&device->alloc, pAllocator, iview);
1102 }
1103
1104 void radv_buffer_view_init(struct radv_buffer_view *view,
1105 struct radv_device *device,
1106 const VkBufferViewCreateInfo* pCreateInfo,
1107 struct radv_cmd_buffer *cmd_buffer)
1108 {
1109 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1110
1111 view->bo = buffer->bo;
1112 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1113 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1114 view->vk_format = pCreateInfo->format;
1115
1116 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1117 pCreateInfo->offset, view->range, view->state);
1118 }
1119
1120 VkResult
1121 radv_CreateBufferView(VkDevice _device,
1122 const VkBufferViewCreateInfo *pCreateInfo,
1123 const VkAllocationCallbacks *pAllocator,
1124 VkBufferView *pView)
1125 {
1126 RADV_FROM_HANDLE(radv_device, device, _device);
1127 struct radv_buffer_view *view;
1128
1129 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1130 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1131 if (!view)
1132 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1133
1134 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1135
1136 *pView = radv_buffer_view_to_handle(view);
1137
1138 return VK_SUCCESS;
1139 }
1140
1141 void
1142 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1143 const VkAllocationCallbacks *pAllocator)
1144 {
1145 RADV_FROM_HANDLE(radv_device, device, _device);
1146 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1147
1148 if (!view)
1149 return;
1150
1151 vk_free2(&device->alloc, pAllocator, view);
1152 }