2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= VI
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
67 radv_init_surface(struct radv_device
*device
,
68 struct radeon_surf
*surface
,
69 const struct radv_image_create_info
*create_info
)
71 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
72 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
73 const struct vk_format_description
*desc
=
74 vk_format_description(pCreateInfo
->format
);
75 bool is_depth
, is_stencil
, blendable
;
77 is_depth
= vk_format_has_depth(desc
);
78 is_stencil
= vk_format_has_stencil(desc
);
80 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
81 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
83 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
84 /* align byte per element on dword */
85 if (surface
->bpe
== 3) {
88 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
90 switch (pCreateInfo
->imageType
){
91 case VK_IMAGE_TYPE_1D
:
92 if (pCreateInfo
->arrayLayers
> 1)
93 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
95 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
97 case VK_IMAGE_TYPE_2D
:
98 if (pCreateInfo
->arrayLayers
> 1)
99 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
101 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
103 case VK_IMAGE_TYPE_3D
:
104 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
107 unreachable("unhandled image type");
111 surface
->flags
|= RADEON_SURF_ZBUFFER
;
112 if (!(pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
113 !(pCreateInfo
->flags
& (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
|
114 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
)) &&
115 pCreateInfo
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
116 pCreateInfo
->mipLevels
<= 1 &&
117 device
->physical_device
->rad_info
.chip_class
>= VI
&&
118 ((pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT
||
119 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
) ||
120 (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
121 pCreateInfo
->format
== VK_FORMAT_D16_UNORM
)))
122 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
126 surface
->flags
|= RADEON_SURF_SBUFFER
;
128 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
130 bool dcc_compatible_formats
= radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
);
131 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
132 const struct VkImageFormatListCreateInfoKHR
*format_list
=
133 (const struct VkImageFormatListCreateInfoKHR
*)
134 vk_find_struct_const(pCreateInfo
->pNext
,
135 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
137 /* We have to ignore the existence of the list if viewFormatCount = 0 */
138 if (format_list
&& format_list
->viewFormatCount
) {
139 /* compatibility is transitive, so we only need to check
140 * one format with everything else. */
141 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
142 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
143 format_list
->pViewFormats
[i
]))
144 dcc_compatible_formats
= false;
147 dcc_compatible_formats
= false;
151 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
152 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
) ||
153 !dcc_compatible_formats
||
154 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
155 pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1 ||
156 device
->physical_device
->rad_info
.chip_class
< VI
||
157 create_info
->scanout
|| (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
158 pCreateInfo
->samples
>= 2)
159 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
160 if (create_info
->scanout
)
161 surface
->flags
|= RADEON_SURF_SCANOUT
;
165 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
167 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
170 static inline unsigned
171 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
174 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
176 return image
->surface
.u
.legacy
.tiling_index
[level
];
179 static unsigned radv_map_swizzle(unsigned swizzle
)
183 return V_008F0C_SQ_SEL_Y
;
185 return V_008F0C_SQ_SEL_Z
;
187 return V_008F0C_SQ_SEL_W
;
189 return V_008F0C_SQ_SEL_0
;
191 return V_008F0C_SQ_SEL_1
;
192 default: /* VK_SWIZZLE_X */
193 return V_008F0C_SQ_SEL_X
;
198 radv_make_buffer_descriptor(struct radv_device
*device
,
199 struct radv_buffer
*buffer
,
205 const struct vk_format_description
*desc
;
207 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
208 uint64_t va
= gpu_address
+ buffer
->offset
;
209 unsigned num_format
, data_format
;
211 desc
= vk_format_description(vk_format
);
212 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
213 stride
= desc
->block
.bits
/ 8;
215 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
216 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
220 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
221 S_008F04_STRIDE(stride
);
223 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
228 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
229 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
230 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
231 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
232 S_008F0C_NUM_FORMAT(num_format
) |
233 S_008F0C_DATA_FORMAT(data_format
);
237 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
238 struct radv_image
*image
,
239 const struct legacy_surf_level
*base_level_info
,
240 unsigned base_level
, unsigned first_level
,
241 unsigned block_width
, bool is_stencil
,
242 bool is_storage_image
, uint32_t *state
)
244 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
245 uint64_t va
= gpu_address
;
246 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
247 uint64_t meta_va
= 0;
248 if (chip_class
>= GFX9
) {
250 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
252 va
+= image
->surface
.u
.gfx9
.surf_offset
;
254 va
+= base_level_info
->offset
;
257 if (chip_class
>= GFX9
||
258 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
259 state
[0] |= image
->surface
.tile_swizzle
;
260 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
261 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
263 if (chip_class
>= VI
) {
264 state
[6] &= C_008F28_COMPRESSION_EN
;
266 if (!is_storage_image
&& radv_vi_dcc_enabled(image
, first_level
)) {
267 meta_va
= gpu_address
+ image
->dcc_offset
;
268 if (chip_class
<= VI
)
269 meta_va
+= base_level_info
->dcc_offset
;
270 } else if(!is_storage_image
&& image
->tc_compatible_htile
&&
271 image
->surface
.htile_size
) {
272 meta_va
= gpu_address
+ image
->htile_offset
;
276 state
[6] |= S_008F28_COMPRESSION_EN(1);
277 state
[7] = meta_va
>> 8;
278 state
[7] |= image
->surface
.tile_swizzle
;
282 if (chip_class
>= GFX9
) {
283 state
[3] &= C_008F1C_SW_MODE
;
284 state
[4] &= C_008F20_PITCH_GFX9
;
287 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
288 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
290 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
291 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
294 state
[5] &= C_008F24_META_DATA_ADDRESS
&
295 C_008F24_META_PIPE_ALIGNED
&
296 C_008F24_META_RB_ALIGNED
;
298 struct gfx9_surf_meta_flags meta
;
300 if (image
->dcc_offset
)
301 meta
= image
->surface
.u
.gfx9
.dcc
;
303 meta
= image
->surface
.u
.gfx9
.htile
;
305 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
306 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
307 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
311 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
312 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
314 state
[3] &= C_008F1C_TILING_INDEX
;
315 state
[3] |= S_008F1C_TILING_INDEX(index
);
316 state
[4] &= C_008F20_PITCH_GFX6
;
317 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
321 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
322 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
324 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
325 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
327 /* GFX9 allocates 1D textures as 2D. */
328 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
329 image_type
= VK_IMAGE_TYPE_2D
;
330 switch (image_type
) {
331 case VK_IMAGE_TYPE_1D
:
332 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
333 case VK_IMAGE_TYPE_2D
:
335 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
337 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
338 case VK_IMAGE_TYPE_3D
:
339 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
340 return V_008F1C_SQ_RSRC_IMG_3D
;
342 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
344 unreachable("illegale image type");
348 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
350 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
352 if (swizzle
[3] == VK_SWIZZLE_X
) {
353 /* For the pre-defined border color values (white, opaque
354 * black, transparent black), the only thing that matters is
355 * that the alpha channel winds up in the correct place
356 * (because the RGB channels are all the same) so either of
357 * these enumerations will work.
359 if (swizzle
[2] == VK_SWIZZLE_Y
)
360 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
362 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
363 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
364 if (swizzle
[1] == VK_SWIZZLE_Y
)
365 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
367 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
368 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
369 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
370 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
371 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
378 * Build the sampler view descriptor for a texture.
381 si_make_texture_descriptor(struct radv_device
*device
,
382 struct radv_image
*image
,
383 bool is_storage_image
,
384 VkImageViewType view_type
,
386 const VkComponentMapping
*mapping
,
387 unsigned first_level
, unsigned last_level
,
388 unsigned first_layer
, unsigned last_layer
,
389 unsigned width
, unsigned height
, unsigned depth
,
391 uint32_t *fmask_state
)
393 const struct vk_format_description
*desc
;
394 enum vk_swizzle swizzle
[4];
396 unsigned num_format
, data_format
, type
;
398 desc
= vk_format_description(vk_format
);
400 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
401 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
402 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
404 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
407 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
409 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
410 if (num_format
== ~0) {
414 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
415 if (data_format
== ~0) {
419 /* S8 with either Z16 or Z32 HTILE need a special format. */
420 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
421 vk_format
== VK_FORMAT_S8_UINT
&&
422 image
->tc_compatible_htile
) {
423 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
424 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
425 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
426 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
428 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
429 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
430 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
432 depth
= image
->info
.array_size
;
433 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
434 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
435 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
436 depth
= image
->info
.array_size
;
437 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
438 depth
= image
->info
.array_size
/ 6;
441 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
442 S_008F14_NUM_FORMAT_GFX6(num_format
));
443 state
[2] = (S_008F18_WIDTH(width
- 1) |
444 S_008F18_HEIGHT(height
- 1) |
445 S_008F18_PERF_MOD(4));
446 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
447 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
448 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
449 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
450 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
452 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
453 util_logbase2(image
->info
.samples
) :
455 S_008F1C_TYPE(type
));
457 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
461 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
462 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
464 /* Depth is the the last accessible layer on Gfx9.
465 * The hw doesn't need to know the total number of layers.
467 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
468 state
[4] |= S_008F20_DEPTH(depth
- 1);
470 state
[4] |= S_008F20_DEPTH(last_layer
);
472 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
473 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
474 util_logbase2(image
->info
.samples
) :
475 image
->info
.levels
- 1);
477 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
478 state
[4] |= S_008F20_DEPTH(depth
- 1);
479 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
481 if (image
->dcc_offset
) {
482 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
484 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
486 /* The last dword is unused by hw. The shader uses it to clear
487 * bits in the first dword of sampler state.
489 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
490 if (first_level
== last_level
)
491 state
[7] = C_008F30_MAX_ANISO_RATIO
;
493 state
[7] = 0xffffffff;
497 /* Initialize the sampler view for FMASK. */
498 if (image
->fmask
.size
) {
499 uint32_t fmask_format
, num_format
;
500 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
503 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
505 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
506 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
507 switch (image
->info
.samples
) {
509 num_format
= V_008F14_IMG_FMASK_8_2_2
;
512 num_format
= V_008F14_IMG_FMASK_8_4_4
;
515 num_format
= V_008F14_IMG_FMASK_32_8_8
;
518 unreachable("invalid nr_samples");
521 switch (image
->info
.samples
) {
523 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
526 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
529 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
533 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
535 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
538 fmask_state
[0] = va
>> 8;
539 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
540 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
541 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
542 S_008F14_NUM_FORMAT_GFX6(num_format
);
543 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
544 S_008F18_HEIGHT(height
- 1);
545 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
546 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
547 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
548 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
549 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false, false));
551 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
555 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
556 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
557 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
558 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
559 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
560 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
562 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
563 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
564 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
565 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
567 } else if (fmask_state
)
568 memset(fmask_state
, 0, 8 * 4);
572 radv_query_opaque_metadata(struct radv_device
*device
,
573 struct radv_image
*image
,
574 struct radeon_bo_metadata
*md
)
576 static const VkComponentMapping fixedmapping
;
579 /* Metadata image format format version 1:
580 * [0] = 1 (metadata format identifier)
581 * [1] = (VENDOR_ID << 16) | PCI_ID
582 * [2:9] = image descriptor for the whole resource
583 * [2] is always 0, because the base address is cleared
584 * [9] is the DCC offset bits [39:8] from the beginning of
586 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
588 md
->metadata
[0] = 1; /* metadata image format version 1 */
590 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
591 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
594 si_make_texture_descriptor(device
, image
, false,
595 (VkImageViewType
)image
->type
, image
->vk_format
,
596 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
597 image
->info
.array_size
,
598 image
->info
.width
, image
->info
.height
,
602 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
603 image
->surface
.blk_w
, false, false, desc
);
605 /* Clear the base address and set the relative DCC offset. */
607 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
608 desc
[7] = image
->dcc_offset
>> 8;
610 /* Dwords [2:9] contain the image descriptor. */
611 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
613 /* Dwords [10:..] contain the mipmap level offsets. */
614 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
615 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
616 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
617 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
622 radv_init_metadata(struct radv_device
*device
,
623 struct radv_image
*image
,
624 struct radeon_bo_metadata
*metadata
)
626 struct radeon_surf
*surface
= &image
->surface
;
628 memset(metadata
, 0, sizeof(*metadata
));
630 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
631 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
633 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
634 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
635 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
636 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
637 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
638 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
639 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
640 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
641 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
642 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
643 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
644 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
646 radv_query_opaque_metadata(device
, image
, metadata
);
649 /* The number of samples can be specified independently of the texture. */
651 radv_image_get_fmask_info(struct radv_device
*device
,
652 struct radv_image
*image
,
654 struct radv_fmask_info
*out
)
656 /* FMASK is allocated like an ordinary texture. */
657 struct radeon_surf fmask
= {};
658 struct ac_surf_info info
= image
->info
;
659 memset(out
, 0, sizeof(*out
));
661 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
662 out
->alignment
= image
->surface
.u
.gfx9
.fmask_alignment
;
663 out
->size
= image
->surface
.u
.gfx9
.fmask_size
;
667 fmask
.blk_w
= image
->surface
.blk_w
;
668 fmask
.blk_h
= image
->surface
.blk_h
;
670 fmask
.flags
= image
->surface
.flags
| RADEON_SURF_FMASK
;
672 if (!image
->shareable
)
673 info
.surf_index
= &device
->fmask_mrt_offset_counter
;
675 /* Force 2D tiling if it wasn't set. This may occur when creating
676 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
677 * destination buffer must have an FMASK too. */
678 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
679 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
681 switch (nr_samples
) {
693 device
->ws
->surface_init(device
->ws
, &info
, &fmask
);
694 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
696 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
697 if (out
->slice_tile_max
)
698 out
->slice_tile_max
-= 1;
700 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
701 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
702 out
->bank_height
= fmask
.u
.legacy
.bankh
;
703 out
->tile_swizzle
= fmask
.tile_swizzle
;
704 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
705 out
->size
= fmask
.surf_size
;
707 assert(!out
->tile_swizzle
|| !image
->shareable
);
711 radv_image_alloc_fmask(struct radv_device
*device
,
712 struct radv_image
*image
)
714 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
716 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
717 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
718 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
722 radv_image_get_cmask_info(struct radv_device
*device
,
723 struct radv_image
*image
,
724 struct radv_cmask_info
*out
)
726 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
727 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
728 unsigned cl_width
, cl_height
;
730 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
731 out
->alignment
= image
->surface
.u
.gfx9
.cmask_alignment
;
732 out
->size
= image
->surface
.u
.gfx9
.cmask_size
;
749 case 16: /* Hawaii */
758 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
760 unsigned width
= align(image
->info
.width
, cl_width
*8);
761 unsigned height
= align(image
->info
.height
, cl_height
*8);
762 unsigned slice_elements
= (width
* height
) / (8*8);
764 /* Each element of CMASK is a nibble. */
765 unsigned slice_bytes
= slice_elements
/ 2;
767 out
->slice_tile_max
= (width
* height
) / (128*128);
768 if (out
->slice_tile_max
)
769 out
->slice_tile_max
-= 1;
771 out
->alignment
= MAX2(256, base_align
);
772 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
773 align(slice_bytes
, base_align
);
777 radv_image_alloc_cmask(struct radv_device
*device
,
778 struct radv_image
*image
)
780 uint32_t clear_value_size
= 0;
781 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
783 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
784 /* + 8 for storing the clear values */
785 if (!image
->clear_value_offset
) {
786 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
787 clear_value_size
= 8;
789 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
790 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
794 radv_image_alloc_dcc(struct radv_image
*image
)
796 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
797 /* + 16 for storing the clear values + dcc pred */
798 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
799 image
->dcc_pred_offset
= image
->clear_value_offset
+ 8;
800 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
801 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
805 radv_image_alloc_htile(struct radv_image
*image
)
807 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
809 /* + 8 for storing the clear values */
810 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
811 image
->size
= image
->clear_value_offset
+ 8;
812 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
816 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
818 if (image
->info
.samples
<= 1 &&
819 image
->info
.width
* image
->info
.height
<= 512 * 512) {
820 /* Do not enable CMASK or DCC for small surfaces where the cost
821 * of the eliminate pass can be higher than the benefit of fast
822 * clear. RadeonSI does this, but the image threshold is
828 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
829 (image
->exclusive
|| image
->queue_family_mask
== 1);
833 radv_image_can_enable_dcc(struct radv_image
*image
)
835 return radv_image_can_enable_dcc_or_cmask(image
) &&
836 image
->surface
.dcc_size
;
840 radv_image_can_enable_cmask(struct radv_image
*image
)
842 if (image
->surface
.bpe
> 8 && image
->info
.samples
== 1) {
843 /* Do not enable CMASK for non-MSAA images (fast color clear)
844 * because 128 bit formats are not supported, but FMASK might
850 return radv_image_can_enable_dcc_or_cmask(image
) &&
851 image
->info
.levels
== 1 &&
852 image
->info
.depth
== 1 &&
853 !image
->surface
.is_linear
;
857 radv_image_can_enable_fmask(struct radv_image
*image
)
859 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
863 radv_image_can_enable_htile(struct radv_image
*image
)
865 return image
->info
.levels
== 1 && vk_format_is_depth(image
->vk_format
);
869 radv_image_create(VkDevice _device
,
870 const struct radv_image_create_info
*create_info
,
871 const VkAllocationCallbacks
* alloc
,
874 RADV_FROM_HANDLE(radv_device
, device
, _device
);
875 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
876 struct radv_image
*image
= NULL
;
877 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
879 radv_assert(pCreateInfo
->mipLevels
> 0);
880 radv_assert(pCreateInfo
->arrayLayers
> 0);
881 radv_assert(pCreateInfo
->samples
> 0);
882 radv_assert(pCreateInfo
->extent
.width
> 0);
883 radv_assert(pCreateInfo
->extent
.height
> 0);
884 radv_assert(pCreateInfo
->extent
.depth
> 0);
886 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
887 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
889 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
891 image
->type
= pCreateInfo
->imageType
;
892 image
->info
.width
= pCreateInfo
->extent
.width
;
893 image
->info
.height
= pCreateInfo
->extent
.height
;
894 image
->info
.depth
= pCreateInfo
->extent
.depth
;
895 image
->info
.samples
= pCreateInfo
->samples
;
896 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
897 image
->info
.levels
= pCreateInfo
->mipLevels
;
899 image
->vk_format
= pCreateInfo
->format
;
900 image
->tiling
= pCreateInfo
->tiling
;
901 image
->usage
= pCreateInfo
->usage
;
902 image
->flags
= pCreateInfo
->flags
;
904 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
905 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
906 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
907 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
908 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
910 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
913 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
914 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
915 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
916 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
919 radv_init_surface(device
, &image
->surface
, create_info
);
921 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
923 image
->size
= image
->surface
.surf_size
;
924 image
->alignment
= image
->surface
.surf_alignment
;
926 if (!create_info
->no_metadata_planes
) {
927 /* Try to enable DCC first. */
928 if (radv_image_can_enable_dcc(image
)) {
929 radv_image_alloc_dcc(image
);
931 /* When DCC cannot be enabled, try CMASK. */
932 image
->surface
.dcc_size
= 0;
933 if (radv_image_can_enable_cmask(image
)) {
934 radv_image_alloc_cmask(device
, image
);
938 /* Try to enable FMASK for multisampled images. */
939 if (radv_image_can_enable_fmask(image
)) {
940 radv_image_alloc_fmask(device
, image
);
942 /* Otherwise, try to enable HTILE for depth surfaces. */
943 if (radv_image_can_enable_htile(image
) &&
944 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
945 radv_image_alloc_htile(image
);
946 image
->tc_compatible_htile
= image
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
948 image
->surface
.htile_size
= 0;
952 image
->surface
.dcc_size
= 0;
953 image
->surface
.htile_size
= 0;
956 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
957 image
->alignment
= MAX2(image
->alignment
, 4096);
958 image
->size
= align64(image
->size
, image
->alignment
);
961 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
962 0, RADEON_FLAG_VIRTUAL
);
964 vk_free2(&device
->alloc
, alloc
, image
);
965 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
969 *pImage
= radv_image_to_handle(image
);
975 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
976 struct radv_device
*device
,
977 const VkComponentMapping
*components
,
978 bool is_storage_image
)
980 struct radv_image
*image
= iview
->image
;
981 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
983 uint32_t *descriptor
;
984 uint32_t hw_level
= 0;
986 if (is_storage_image
) {
987 descriptor
= iview
->storage_descriptor
;
989 descriptor
= iview
->descriptor
;
992 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
993 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
995 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
996 hw_level
= iview
->base_mip
;
997 si_make_texture_descriptor(device
, image
, is_storage_image
,
1001 hw_level
, hw_level
+ iview
->level_count
- 1,
1003 iview
->base_layer
+ iview
->layer_count
- 1,
1004 iview
->extent
.width
,
1005 iview
->extent
.height
,
1006 iview
->extent
.depth
,
1010 const struct legacy_surf_level
*base_level_info
= NULL
;
1011 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1013 base_level_info
= &image
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1015 base_level_info
= &image
->surface
.u
.legacy
.level
[iview
->base_mip
];
1017 si_set_mutable_tex_desc_fields(device
, image
,
1021 blk_w
, is_stencil
, is_storage_image
, descriptor
);
1025 radv_image_view_init(struct radv_image_view
*iview
,
1026 struct radv_device
*device
,
1027 const VkImageViewCreateInfo
* pCreateInfo
)
1029 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1030 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1032 switch (image
->type
) {
1033 case VK_IMAGE_TYPE_1D
:
1034 case VK_IMAGE_TYPE_2D
:
1035 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1037 case VK_IMAGE_TYPE_3D
:
1038 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1039 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1042 unreachable("bad VkImageType");
1044 iview
->image
= image
;
1045 iview
->bo
= image
->bo
;
1046 iview
->type
= pCreateInfo
->viewType
;
1047 iview
->vk_format
= pCreateInfo
->format
;
1048 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1050 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1051 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1052 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1053 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1056 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1057 iview
->extent
= (VkExtent3D
) {
1058 .width
= image
->info
.width
,
1059 .height
= image
->info
.height
,
1060 .depth
= image
->info
.depth
,
1063 iview
->extent
= (VkExtent3D
) {
1064 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1065 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1066 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1070 if (iview
->vk_format
!= image
->vk_format
) {
1071 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
1072 vk_format_get_blockwidth(image
->vk_format
));
1073 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
1074 vk_format_get_blockheight(image
->vk_format
));
1077 iview
->base_layer
= range
->baseArrayLayer
;
1078 iview
->layer_count
= radv_get_layerCount(image
, range
);
1079 iview
->base_mip
= range
->baseMipLevel
;
1080 iview
->level_count
= radv_get_levelCount(image
, range
);
1082 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, false);
1083 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, true);
1086 bool radv_layout_has_htile(const struct radv_image
*image
,
1087 VkImageLayout layout
,
1088 unsigned queue_mask
)
1090 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1091 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1093 return image
->surface
.htile_size
&&
1094 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1095 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1096 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1099 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1100 VkImageLayout layout
,
1101 unsigned queue_mask
)
1103 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1104 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1106 return image
->surface
.htile_size
&&
1107 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1108 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1109 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1112 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1113 VkImageLayout layout
,
1114 unsigned queue_mask
)
1116 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
1117 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1120 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1121 VkImageLayout layout
,
1122 unsigned queue_mask
)
1124 /* Don't compress compute transfer dst, as image stores are not supported. */
1125 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1126 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1129 return image
->surface
.num_dcc_levels
> 0 && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1133 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1135 if (!image
->exclusive
)
1136 return image
->queue_family_mask
;
1137 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
1138 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1139 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1140 return 1u << queue_family
;
1141 return 1u << family
;
1145 radv_CreateImage(VkDevice device
,
1146 const VkImageCreateInfo
*pCreateInfo
,
1147 const VkAllocationCallbacks
*pAllocator
,
1150 const struct wsi_image_create_info
*wsi_info
=
1151 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1152 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1154 return radv_image_create(device
,
1155 &(struct radv_image_create_info
) {
1156 .vk_info
= pCreateInfo
,
1164 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1165 const VkAllocationCallbacks
*pAllocator
)
1167 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1168 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1173 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1174 device
->ws
->buffer_destroy(image
->bo
);
1176 vk_free2(&device
->alloc
, pAllocator
, image
);
1179 void radv_GetImageSubresourceLayout(
1182 const VkImageSubresource
* pSubresource
,
1183 VkSubresourceLayout
* pLayout
)
1185 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1186 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1187 int level
= pSubresource
->mipLevel
;
1188 int layer
= pSubresource
->arrayLayer
;
1189 struct radeon_surf
*surface
= &image
->surface
;
1191 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1192 pLayout
->offset
= surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1193 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1194 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1195 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1196 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1197 if (image
->type
== VK_IMAGE_TYPE_3D
)
1198 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1200 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1201 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1202 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1203 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1204 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1205 if (image
->type
== VK_IMAGE_TYPE_3D
)
1206 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1212 radv_CreateImageView(VkDevice _device
,
1213 const VkImageViewCreateInfo
*pCreateInfo
,
1214 const VkAllocationCallbacks
*pAllocator
,
1217 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1218 struct radv_image_view
*view
;
1220 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1221 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1223 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1225 radv_image_view_init(view
, device
, pCreateInfo
);
1227 *pView
= radv_image_view_to_handle(view
);
1233 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1234 const VkAllocationCallbacks
*pAllocator
)
1236 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1237 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1241 vk_free2(&device
->alloc
, pAllocator
, iview
);
1244 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1245 struct radv_device
*device
,
1246 const VkBufferViewCreateInfo
* pCreateInfo
)
1248 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1250 view
->bo
= buffer
->bo
;
1251 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1252 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1253 view
->vk_format
= pCreateInfo
->format
;
1255 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1256 pCreateInfo
->offset
, view
->range
, view
->state
);
1260 radv_CreateBufferView(VkDevice _device
,
1261 const VkBufferViewCreateInfo
*pCreateInfo
,
1262 const VkAllocationCallbacks
*pAllocator
,
1263 VkBufferView
*pView
)
1265 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1266 struct radv_buffer_view
*view
;
1268 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1269 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1271 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1273 radv_buffer_view_init(view
, device
, pCreateInfo
);
1275 *pView
= radv_buffer_view_to_handle(view
);
1281 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1282 const VkAllocationCallbacks
*pAllocator
)
1284 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1285 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1290 vk_free2(&device
->alloc
, pAllocator
, view
);