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radv: Generate storage image descriptors unconditionally
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "vk_util.h"
31 #include "radv_radeon_winsys.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36 static unsigned
37 radv_choose_tiling(struct radv_device *Device,
38 const struct radv_image_create_info *create_info)
39 {
40 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
41
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
49 /* Only very thin and long 2D textures should benefit from
50 * linear_aligned. */
51 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED;
53
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo->samples > 1)
56 return RADEON_SURF_MODE_2D;
57
58 return RADEON_SURF_MODE_2D;
59 }
60 static int
61 radv_init_surface(struct radv_device *device,
62 struct radeon_surf *surface,
63 const struct radv_image_create_info *create_info)
64 {
65 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
66 unsigned array_mode = radv_choose_tiling(device, create_info);
67 const struct vk_format_description *desc =
68 vk_format_description(pCreateInfo->format);
69 bool is_depth, is_stencil, blendable;
70
71 is_depth = vk_format_has_depth(desc);
72 is_stencil = vk_format_has_stencil(desc);
73
74 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
75 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
76
77 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
78 /* align byte per element on dword */
79 if (surface->bpe == 3) {
80 surface->bpe = 4;
81 }
82 surface->flags = RADEON_SURF_SET(array_mode, MODE);
83
84 switch (pCreateInfo->imageType){
85 case VK_IMAGE_TYPE_1D:
86 if (pCreateInfo->arrayLayers > 1)
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
88 else
89 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
90 break;
91 case VK_IMAGE_TYPE_2D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_3D:
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
99 break;
100 default:
101 unreachable("unhandled image type");
102 }
103
104 if (is_depth) {
105 surface->flags |= RADEON_SURF_ZBUFFER;
106 }
107
108 if (is_stencil)
109 surface->flags |= RADEON_SURF_SBUFFER;
110
111 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
112 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
113
114 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
115 VK_IMAGE_USAGE_STORAGE_BIT)) ||
116 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
117 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
118 device->physical_device->rad_info.chip_class < VI ||
119 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
120 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
121 surface->flags |= RADEON_SURF_DISABLE_DCC;
122 if (create_info->scanout)
123 surface->flags |= RADEON_SURF_SCANOUT;
124 return 0;
125 }
126 #define ATI_VENDOR_ID 0x1002
127 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
128 {
129 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
130 }
131
132 static inline unsigned
133 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
134 {
135 if (stencil)
136 return image->surface.u.legacy.stencil_tiling_index[level];
137 else
138 return image->surface.u.legacy.tiling_index[level];
139 }
140
141 static unsigned radv_map_swizzle(unsigned swizzle)
142 {
143 switch (swizzle) {
144 case VK_SWIZZLE_Y:
145 return V_008F0C_SQ_SEL_Y;
146 case VK_SWIZZLE_Z:
147 return V_008F0C_SQ_SEL_Z;
148 case VK_SWIZZLE_W:
149 return V_008F0C_SQ_SEL_W;
150 case VK_SWIZZLE_0:
151 return V_008F0C_SQ_SEL_0;
152 case VK_SWIZZLE_1:
153 return V_008F0C_SQ_SEL_1;
154 default: /* VK_SWIZZLE_X */
155 return V_008F0C_SQ_SEL_X;
156 }
157 }
158
159 static void
160 radv_make_buffer_descriptor(struct radv_device *device,
161 struct radv_buffer *buffer,
162 VkFormat vk_format,
163 unsigned offset,
164 unsigned range,
165 uint32_t *state)
166 {
167 const struct vk_format_description *desc;
168 unsigned stride;
169 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
170 uint64_t va = gpu_address + buffer->offset;
171 unsigned num_format, data_format;
172 int first_non_void;
173 desc = vk_format_description(vk_format);
174 first_non_void = vk_format_get_first_non_void_channel(vk_format);
175 stride = desc->block.bits / 8;
176
177 num_format = radv_translate_buffer_numformat(desc, first_non_void);
178 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
179
180 va += offset;
181 state[0] = va;
182 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
183 S_008F04_STRIDE(stride);
184 state[2] = range;
185 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
186 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
187 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
188 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
189 S_008F0C_NUM_FORMAT(num_format) |
190 S_008F0C_DATA_FORMAT(data_format);
191 }
192
193 static void
194 si_set_mutable_tex_desc_fields(struct radv_device *device,
195 struct radv_image *image,
196 const struct legacy_surf_level *base_level_info,
197 unsigned base_level, unsigned first_level,
198 unsigned block_width, bool is_stencil,
199 uint32_t *state)
200 {
201 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
202 uint64_t va = gpu_address;
203 unsigned pitch = base_level_info->nblk_x * block_width;
204 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
205 uint64_t meta_va = 0;
206 if (chip_class >= GFX9) {
207 if (is_stencil)
208 va += image->surface.u.gfx9.stencil_offset;
209 else
210 va += image->surface.u.gfx9.surf_offset;
211 } else
212 va += base_level_info->offset;
213
214 state[0] = va >> 8;
215 if (chip_class < GFX9)
216 state[0] |= image->surface.u.legacy.tile_swizzle;
217 state[1] &= C_008F14_BASE_ADDRESS_HI;
218 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
219 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
220 is_stencil));
221 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
222
223 if (chip_class >= VI) {
224 state[6] &= C_008F28_COMPRESSION_EN;
225 state[7] = 0;
226 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
227 meta_va = gpu_address + image->dcc_offset;
228 if (chip_class <= VI)
229 meta_va += base_level_info->dcc_offset;
230 state[6] |= S_008F28_COMPRESSION_EN(1);
231 state[7] = meta_va >> 8;
232 if (chip_class < GFX9)
233 state[7] |= image->surface.u.legacy.tile_swizzle;
234 }
235 }
236
237 if (chip_class >= GFX9) {
238 state[3] &= C_008F1C_SW_MODE;
239 state[4] &= C_008F20_PITCH_GFX9;
240
241 if (is_stencil) {
242 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
243 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
244 } else {
245 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
246 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
247 }
248
249 state[5] &= C_008F24_META_DATA_ADDRESS &
250 C_008F24_META_PIPE_ALIGNED &
251 C_008F24_META_RB_ALIGNED;
252 if (meta_va) {
253 struct gfx9_surf_meta_flags meta;
254
255 if (image->dcc_offset)
256 meta = image->surface.u.gfx9.dcc;
257 else
258 meta = image->surface.u.gfx9.htile;
259
260 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
261 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
262 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
263 }
264 } else {
265 /* SI-CI-VI */
266 unsigned pitch = base_level_info->nblk_x * block_width;
267 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
268
269 state[3] &= C_008F1C_TILING_INDEX;
270 state[3] |= S_008F1C_TILING_INDEX(index);
271 state[4] &= C_008F20_PITCH_GFX6;
272 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
273 }
274 }
275
276 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
277 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
278 {
279 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
280 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
281 switch (image_type) {
282 case VK_IMAGE_TYPE_1D:
283 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
284 case VK_IMAGE_TYPE_2D:
285 if (nr_samples > 1)
286 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
287 else
288 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
289 case VK_IMAGE_TYPE_3D:
290 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
291 return V_008F1C_SQ_RSRC_IMG_3D;
292 else
293 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
294 default:
295 unreachable("illegale image type");
296 }
297 }
298
299 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
300 {
301 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
302
303 if (swizzle[3] == VK_SWIZZLE_X) {
304 /* For the pre-defined border color values (white, opaque
305 * black, transparent black), the only thing that matters is
306 * that the alpha channel winds up in the correct place
307 * (because the RGB channels are all the same) so either of
308 * these enumerations will work.
309 */
310 if (swizzle[2] == VK_SWIZZLE_Y)
311 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
312 else
313 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
314 } else if (swizzle[0] == VK_SWIZZLE_X) {
315 if (swizzle[1] == VK_SWIZZLE_Y)
316 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
317 else
318 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
319 } else if (swizzle[1] == VK_SWIZZLE_X) {
320 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
321 } else if (swizzle[2] == VK_SWIZZLE_X) {
322 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
323 }
324
325 return bc_swizzle;
326 }
327
328 /**
329 * Build the sampler view descriptor for a texture.
330 */
331 static void
332 si_make_texture_descriptor(struct radv_device *device,
333 struct radv_image *image,
334 bool is_storage_image,
335 VkImageViewType view_type,
336 VkFormat vk_format,
337 const VkComponentMapping *mapping,
338 unsigned first_level, unsigned last_level,
339 unsigned first_layer, unsigned last_layer,
340 unsigned width, unsigned height, unsigned depth,
341 uint32_t *state,
342 uint32_t *fmask_state)
343 {
344 const struct vk_format_description *desc;
345 enum vk_swizzle swizzle[4];
346 int first_non_void;
347 unsigned num_format, data_format, type;
348
349 desc = vk_format_description(vk_format);
350
351 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
352 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
353 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
354 } else {
355 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
356 }
357
358 first_non_void = vk_format_get_first_non_void_channel(vk_format);
359
360 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
361 if (num_format == ~0) {
362 num_format = 0;
363 }
364
365 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
366 if (data_format == ~0) {
367 data_format = 0;
368 }
369
370 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
371 is_storage_image);
372 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
373 height = 1;
374 depth = image->info.array_size;
375 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
376 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
377 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
378 depth = image->info.array_size;
379 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
380 depth = image->info.array_size / 6;
381
382 state[0] = 0;
383 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
384 S_008F14_NUM_FORMAT_GFX6(num_format));
385 state[2] = (S_008F18_WIDTH(width - 1) |
386 S_008F18_HEIGHT(height - 1) |
387 S_008F18_PERF_MOD(4));
388 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
389 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
390 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
391 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
392 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
393 0 : first_level) |
394 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
395 util_logbase2(image->info.samples) :
396 last_level) |
397 S_008F1C_TYPE(type));
398 state[4] = 0;
399 state[5] = S_008F24_BASE_ARRAY(first_layer);
400 state[6] = 0;
401 state[7] = 0;
402
403 if (device->physical_device->rad_info.chip_class >= GFX9) {
404 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
405
406 /* Depth is the the last accessible layer on Gfx9.
407 * The hw doesn't need to know the total number of layers.
408 */
409 if (type == V_008F1C_SQ_RSRC_IMG_3D)
410 state[4] |= S_008F20_DEPTH(depth - 1);
411 else
412 state[4] |= S_008F20_DEPTH(last_layer);
413
414 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
415 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
416 util_logbase2(image->info.samples) :
417 last_level);
418 } else {
419 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
420 state[4] |= S_008F20_DEPTH(depth - 1);
421 state[5] |= S_008F24_LAST_ARRAY(last_layer);
422 }
423 if (image->dcc_offset) {
424 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
425
426 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
427 } else {
428 /* The last dword is unused by hw. The shader uses it to clear
429 * bits in the first dword of sampler state.
430 */
431 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
432 if (first_level == last_level)
433 state[7] = C_008F30_MAX_ANISO_RATIO;
434 else
435 state[7] = 0xffffffff;
436 }
437 }
438
439 /* Initialize the sampler view for FMASK. */
440 if (image->fmask.size) {
441 uint32_t fmask_format, num_format;
442 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
443 uint64_t va;
444
445 va = gpu_address + image->offset + image->fmask.offset;
446
447 if (device->physical_device->rad_info.chip_class >= GFX9) {
448 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
449 switch (image->info.samples) {
450 case 2:
451 num_format = V_008F14_IMG_FMASK_8_2_2;
452 break;
453 case 4:
454 num_format = V_008F14_IMG_FMASK_8_4_4;
455 break;
456 case 8:
457 num_format = V_008F14_IMG_FMASK_32_8_8;
458 break;
459 default:
460 unreachable("invalid nr_samples");
461 }
462 } else {
463 switch (image->info.samples) {
464 case 2:
465 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
466 break;
467 case 4:
468 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
469 break;
470 case 8:
471 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
472 break;
473 default:
474 assert(0);
475 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
476 }
477 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
478 }
479
480 fmask_state[0] = va >> 8;
481 if (device->physical_device->rad_info.chip_class < GFX9)
482 fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
483 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
484 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
485 S_008F14_NUM_FORMAT_GFX6(num_format);
486 fmask_state[2] = S_008F18_WIDTH(width - 1) |
487 S_008F18_HEIGHT(height - 1);
488 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
489 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
490 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
491 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
492 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
493 fmask_state[4] = 0;
494 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
495 fmask_state[6] = 0;
496 fmask_state[7] = 0;
497
498 if (device->physical_device->rad_info.chip_class >= GFX9) {
499 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
500 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
501 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
502 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
503 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
504 } else {
505 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
506 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
507 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
508 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
509 }
510 } else if (fmask_state)
511 memset(fmask_state, 0, 8 * 4);
512 }
513
514 static void
515 radv_query_opaque_metadata(struct radv_device *device,
516 struct radv_image *image,
517 struct radeon_bo_metadata *md)
518 {
519 static const VkComponentMapping fixedmapping;
520 uint32_t desc[8], i;
521
522 /* Metadata image format format version 1:
523 * [0] = 1 (metadata format identifier)
524 * [1] = (VENDOR_ID << 16) | PCI_ID
525 * [2:9] = image descriptor for the whole resource
526 * [2] is always 0, because the base address is cleared
527 * [9] is the DCC offset bits [39:8] from the beginning of
528 * the buffer
529 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
530 */
531 md->metadata[0] = 1; /* metadata image format version 1 */
532
533 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
534 md->metadata[1] = si_get_bo_metadata_word1(device);
535
536
537 si_make_texture_descriptor(device, image, false,
538 (VkImageViewType)image->type, image->vk_format,
539 &fixedmapping, 0, image->info.levels - 1, 0,
540 image->info.array_size,
541 image->info.width, image->info.height,
542 image->info.depth,
543 desc, NULL);
544
545 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
546 image->surface.blk_w, false, desc);
547
548 /* Clear the base address and set the relative DCC offset. */
549 desc[0] = 0;
550 desc[1] &= C_008F14_BASE_ADDRESS_HI;
551 desc[7] = image->dcc_offset >> 8;
552
553 /* Dwords [2:9] contain the image descriptor. */
554 memcpy(&md->metadata[2], desc, sizeof(desc));
555
556 /* Dwords [10:..] contain the mipmap level offsets. */
557 for (i = 0; i <= image->info.levels - 1; i++)
558 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
559
560 md->size_metadata = (11 + image->info.levels - 1) * 4;
561 }
562
563 void
564 radv_init_metadata(struct radv_device *device,
565 struct radv_image *image,
566 struct radeon_bo_metadata *metadata)
567 {
568 struct radeon_surf *surface = &image->surface;
569
570 memset(metadata, 0, sizeof(*metadata));
571
572 if (device->physical_device->rad_info.chip_class >= GFX9) {
573 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
574 } else {
575 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
576 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
577 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
578 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
579 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
580 metadata->u.legacy.bankw = surface->u.legacy.bankw;
581 metadata->u.legacy.bankh = surface->u.legacy.bankh;
582 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
583 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
584 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
585 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
586 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
587 }
588 radv_query_opaque_metadata(device, image, metadata);
589 }
590
591 /* The number of samples can be specified independently of the texture. */
592 static void
593 radv_image_get_fmask_info(struct radv_device *device,
594 struct radv_image *image,
595 unsigned nr_samples,
596 struct radv_fmask_info *out)
597 {
598 /* FMASK is allocated like an ordinary texture. */
599 struct radeon_surf fmask = {};
600 struct ac_surf_info info = image->info;
601 memset(out, 0, sizeof(*out));
602
603 if (device->physical_device->rad_info.chip_class >= GFX9) {
604 out->alignment = image->surface.u.gfx9.fmask_alignment;
605 out->size = image->surface.u.gfx9.fmask_size;
606 return;
607 }
608
609 fmask.blk_w = image->surface.blk_w;
610 fmask.blk_h = image->surface.blk_h;
611 info.samples = 1;
612 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
613
614 /* Force 2D tiling if it wasn't set. This may occur when creating
615 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
616 * destination buffer must have an FMASK too. */
617 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
618 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
619
620 switch (nr_samples) {
621 case 2:
622 case 4:
623 fmask.bpe = 1;
624 break;
625 case 8:
626 fmask.bpe = 4;
627 break;
628 default:
629 return;
630 }
631
632 device->ws->surface_init(device->ws, &info, &fmask);
633 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
634
635 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
636 if (out->slice_tile_max)
637 out->slice_tile_max -= 1;
638
639 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
640 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
641 out->bank_height = fmask.u.legacy.bankh;
642 out->alignment = MAX2(256, fmask.surf_alignment);
643 out->size = fmask.surf_size;
644 }
645
646 static void
647 radv_image_alloc_fmask(struct radv_device *device,
648 struct radv_image *image)
649 {
650 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
651
652 image->fmask.offset = align64(image->size, image->fmask.alignment);
653 image->size = image->fmask.offset + image->fmask.size;
654 image->alignment = MAX2(image->alignment, image->fmask.alignment);
655 }
656
657 static void
658 radv_image_get_cmask_info(struct radv_device *device,
659 struct radv_image *image,
660 struct radv_cmask_info *out)
661 {
662 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
663 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
664 unsigned cl_width, cl_height;
665
666 if (device->physical_device->rad_info.chip_class >= GFX9) {
667 out->alignment = image->surface.u.gfx9.cmask_alignment;
668 out->size = image->surface.u.gfx9.cmask_size;
669 return;
670 }
671
672 switch (num_pipes) {
673 case 2:
674 cl_width = 32;
675 cl_height = 16;
676 break;
677 case 4:
678 cl_width = 32;
679 cl_height = 32;
680 break;
681 case 8:
682 cl_width = 64;
683 cl_height = 32;
684 break;
685 case 16: /* Hawaii */
686 cl_width = 64;
687 cl_height = 64;
688 break;
689 default:
690 assert(0);
691 return;
692 }
693
694 unsigned base_align = num_pipes * pipe_interleave_bytes;
695
696 unsigned width = align(image->info.width, cl_width*8);
697 unsigned height = align(image->info.height, cl_height*8);
698 unsigned slice_elements = (width * height) / (8*8);
699
700 /* Each element of CMASK is a nibble. */
701 unsigned slice_bytes = slice_elements / 2;
702
703 out->slice_tile_max = (width * height) / (128*128);
704 if (out->slice_tile_max)
705 out->slice_tile_max -= 1;
706
707 out->alignment = MAX2(256, base_align);
708 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
709 align(slice_bytes, base_align);
710 }
711
712 static void
713 radv_image_alloc_cmask(struct radv_device *device,
714 struct radv_image *image)
715 {
716 uint32_t clear_value_size = 0;
717 radv_image_get_cmask_info(device, image, &image->cmask);
718
719 image->cmask.offset = align64(image->size, image->cmask.alignment);
720 /* + 8 for storing the clear values */
721 if (!image->clear_value_offset) {
722 image->clear_value_offset = image->cmask.offset + image->cmask.size;
723 clear_value_size = 8;
724 }
725 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
726 image->alignment = MAX2(image->alignment, image->cmask.alignment);
727 }
728
729 static void
730 radv_image_alloc_dcc(struct radv_device *device,
731 struct radv_image *image)
732 {
733 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
734 /* + 16 for storing the clear values + dcc pred */
735 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
736 image->dcc_pred_offset = image->clear_value_offset + 8;
737 image->size = image->dcc_offset + image->surface.dcc_size + 16;
738 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
739 }
740
741 static void
742 radv_image_alloc_htile(struct radv_device *device,
743 struct radv_image *image)
744 {
745 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
746 image->surface.htile_size = 0;
747 return;
748 }
749
750 image->htile_offset = align64(image->size, image->surface.htile_alignment);
751
752 /* + 8 for storing the clear values */
753 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
754 image->size = image->clear_value_offset + 8;
755 image->alignment = align64(image->alignment, image->surface.htile_alignment);
756 }
757
758 VkResult
759 radv_image_create(VkDevice _device,
760 const struct radv_image_create_info *create_info,
761 const VkAllocationCallbacks* alloc,
762 VkImage *pImage)
763 {
764 RADV_FROM_HANDLE(radv_device, device, _device);
765 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
766 struct radv_image *image = NULL;
767 bool can_cmask_dcc = false;
768 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
769
770 radv_assert(pCreateInfo->mipLevels > 0);
771 radv_assert(pCreateInfo->arrayLayers > 0);
772 radv_assert(pCreateInfo->samples > 0);
773 radv_assert(pCreateInfo->extent.width > 0);
774 radv_assert(pCreateInfo->extent.height > 0);
775 radv_assert(pCreateInfo->extent.depth > 0);
776
777 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
778 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
779 if (!image)
780 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
781
782 memset(image, 0, sizeof(*image));
783 image->type = pCreateInfo->imageType;
784 image->info.width = pCreateInfo->extent.width;
785 image->info.height = pCreateInfo->extent.height;
786 image->info.depth = pCreateInfo->extent.depth;
787 image->info.samples = pCreateInfo->samples;
788 image->info.array_size = pCreateInfo->arrayLayers;
789 image->info.levels = pCreateInfo->mipLevels;
790
791 image->vk_format = pCreateInfo->format;
792 image->tiling = pCreateInfo->tiling;
793 image->usage = pCreateInfo->usage;
794 image->flags = pCreateInfo->flags;
795
796 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
797 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
798 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
799 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
800 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
801 else
802 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
803 }
804
805 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
806 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
807 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
808 image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
809 }
810
811 radv_init_surface(device, &image->surface, create_info);
812
813 device->ws->surface_init(device->ws, &image->info, &image->surface);
814
815 image->size = image->surface.surf_size;
816 image->alignment = image->surface.surf_alignment;
817
818 if (image->exclusive || image->queue_family_mask == 1)
819 can_cmask_dcc = true;
820
821 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
822 image->surface.dcc_size && can_cmask_dcc)
823 radv_image_alloc_dcc(device, image);
824 else
825 image->surface.dcc_size = 0;
826
827 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
828 pCreateInfo->mipLevels == 1 &&
829 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
830 radv_image_alloc_cmask(device, image);
831 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
832 radv_image_alloc_fmask(device, image);
833 } else if (vk_format_is_depth(pCreateInfo->format)) {
834
835 radv_image_alloc_htile(device, image);
836 }
837
838 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
839 image->alignment = MAX2(image->alignment, 4096);
840 image->size = align64(image->size, image->alignment);
841 image->offset = 0;
842
843 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
844 0, RADEON_FLAG_VIRTUAL);
845 if (!image->bo) {
846 vk_free2(&device->alloc, alloc, image);
847 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
848 }
849 }
850
851 *pImage = radv_image_to_handle(image);
852
853 return VK_SUCCESS;
854 }
855
856 static void
857 radv_image_view_make_descriptor(struct radv_image_view *iview,
858 struct radv_device *device,
859 const VkImageViewCreateInfo* pCreateInfo,
860 bool is_storage_image)
861 {
862 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
863 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
864 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
865 uint32_t blk_w;
866 uint32_t *descriptor;
867 uint32_t *fmask_descriptor;
868
869 if (is_storage_image) {
870 descriptor = iview->storage_descriptor;
871 fmask_descriptor = iview->storage_fmask_descriptor;
872 } else {
873 descriptor = iview->descriptor;
874 fmask_descriptor = iview->fmask_descriptor;
875 }
876
877 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
878 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
879
880 si_make_texture_descriptor(device, image, is_storage_image,
881 iview->type,
882 iview->vk_format,
883 &pCreateInfo->components,
884 0, radv_get_levelCount(image, range) - 1,
885 range->baseArrayLayer,
886 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
887 iview->extent.width,
888 iview->extent.height,
889 iview->extent.depth,
890 descriptor,
891 fmask_descriptor);
892 si_set_mutable_tex_desc_fields(device, image,
893 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
894 : &image->surface.u.legacy.level[range->baseMipLevel],
895 range->baseMipLevel,
896 range->baseMipLevel,
897 blk_w, is_stencil, descriptor);
898 }
899
900 void
901 radv_image_view_init(struct radv_image_view *iview,
902 struct radv_device *device,
903 const VkImageViewCreateInfo* pCreateInfo)
904 {
905 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
906 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
907
908 switch (image->type) {
909 case VK_IMAGE_TYPE_1D:
910 case VK_IMAGE_TYPE_2D:
911 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
912 break;
913 case VK_IMAGE_TYPE_3D:
914 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
915 <= radv_minify(image->info.depth, range->baseMipLevel));
916 break;
917 default:
918 unreachable("bad VkImageType");
919 }
920 iview->image = image;
921 iview->bo = image->bo;
922 iview->type = pCreateInfo->viewType;
923 iview->vk_format = pCreateInfo->format;
924 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
925
926 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
927 iview->vk_format = vk_format_stencil_only(iview->vk_format);
928 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
929 iview->vk_format = vk_format_depth_only(iview->vk_format);
930 }
931
932 iview->extent = (VkExtent3D) {
933 .width = radv_minify(image->info.width , range->baseMipLevel),
934 .height = radv_minify(image->info.height, range->baseMipLevel),
935 .depth = radv_minify(image->info.depth , range->baseMipLevel),
936 };
937
938 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
939 vk_format_get_blockwidth(image->vk_format));
940 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
941 vk_format_get_blockheight(image->vk_format));
942
943 iview->base_layer = range->baseArrayLayer;
944 iview->layer_count = radv_get_layerCount(image, range);
945 iview->base_mip = range->baseMipLevel;
946
947 radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
948 radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
949 }
950
951 bool radv_layout_has_htile(const struct radv_image *image,
952 VkImageLayout layout,
953 unsigned queue_mask)
954 {
955 return image->surface.htile_size &&
956 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
957 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
958 queue_mask == (1u << RADV_QUEUE_GENERAL);
959 }
960
961 bool radv_layout_is_htile_compressed(const struct radv_image *image,
962 VkImageLayout layout,
963 unsigned queue_mask)
964 {
965 return image->surface.htile_size &&
966 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
967 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
968 queue_mask == (1u << RADV_QUEUE_GENERAL);
969 }
970
971 bool radv_layout_can_fast_clear(const struct radv_image *image,
972 VkImageLayout layout,
973 unsigned queue_mask)
974 {
975 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
976 queue_mask == (1u << RADV_QUEUE_GENERAL);
977 }
978
979
980 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
981 {
982 if (!image->exclusive)
983 return image->queue_family_mask;
984 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
985 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
986 if (family == VK_QUEUE_FAMILY_IGNORED)
987 return 1u << queue_family;
988 return 1u << family;
989 }
990
991 VkResult
992 radv_CreateImage(VkDevice device,
993 const VkImageCreateInfo *pCreateInfo,
994 const VkAllocationCallbacks *pAllocator,
995 VkImage *pImage)
996 {
997 return radv_image_create(device,
998 &(struct radv_image_create_info) {
999 .vk_info = pCreateInfo,
1000 .scanout = false,
1001 },
1002 pAllocator,
1003 pImage);
1004 }
1005
1006 void
1007 radv_DestroyImage(VkDevice _device, VkImage _image,
1008 const VkAllocationCallbacks *pAllocator)
1009 {
1010 RADV_FROM_HANDLE(radv_device, device, _device);
1011 RADV_FROM_HANDLE(radv_image, image, _image);
1012
1013 if (!image)
1014 return;
1015
1016 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1017 device->ws->buffer_destroy(image->bo);
1018
1019 vk_free2(&device->alloc, pAllocator, image);
1020 }
1021
1022 void radv_GetImageSubresourceLayout(
1023 VkDevice device,
1024 VkImage _image,
1025 const VkImageSubresource* pSubresource,
1026 VkSubresourceLayout* pLayout)
1027 {
1028 RADV_FROM_HANDLE(radv_image, image, _image);
1029 int level = pSubresource->mipLevel;
1030 int layer = pSubresource->arrayLayer;
1031 struct radeon_surf *surface = &image->surface;
1032
1033 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1034 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1035 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1036 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1037 pLayout->size = surface->u.legacy.level[level].slice_size;
1038 if (image->type == VK_IMAGE_TYPE_3D)
1039 pLayout->size *= u_minify(image->info.depth, level);
1040 }
1041
1042
1043 VkResult
1044 radv_CreateImageView(VkDevice _device,
1045 const VkImageViewCreateInfo *pCreateInfo,
1046 const VkAllocationCallbacks *pAllocator,
1047 VkImageView *pView)
1048 {
1049 RADV_FROM_HANDLE(radv_device, device, _device);
1050 struct radv_image_view *view;
1051
1052 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1053 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1054 if (view == NULL)
1055 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1056
1057 radv_image_view_init(view, device, pCreateInfo);
1058
1059 *pView = radv_image_view_to_handle(view);
1060
1061 return VK_SUCCESS;
1062 }
1063
1064 void
1065 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1066 const VkAllocationCallbacks *pAllocator)
1067 {
1068 RADV_FROM_HANDLE(radv_device, device, _device);
1069 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1070
1071 if (!iview)
1072 return;
1073 vk_free2(&device->alloc, pAllocator, iview);
1074 }
1075
1076 void radv_buffer_view_init(struct radv_buffer_view *view,
1077 struct radv_device *device,
1078 const VkBufferViewCreateInfo* pCreateInfo,
1079 struct radv_cmd_buffer *cmd_buffer)
1080 {
1081 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1082
1083 view->bo = buffer->bo;
1084 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1085 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1086 view->vk_format = pCreateInfo->format;
1087
1088 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1089 pCreateInfo->offset, view->range, view->state);
1090 }
1091
1092 VkResult
1093 radv_CreateBufferView(VkDevice _device,
1094 const VkBufferViewCreateInfo *pCreateInfo,
1095 const VkAllocationCallbacks *pAllocator,
1096 VkBufferView *pView)
1097 {
1098 RADV_FROM_HANDLE(radv_device, device, _device);
1099 struct radv_buffer_view *view;
1100
1101 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1102 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1103 if (!view)
1104 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1105
1106 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1107
1108 *pView = radv_buffer_view_to_handle(view);
1109
1110 return VK_SUCCESS;
1111 }
1112
1113 void
1114 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1115 const VkAllocationCallbacks *pAllocator)
1116 {
1117 RADV_FROM_HANDLE(radv_device, device, _device);
1118 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1119
1120 if (!view)
1121 return;
1122
1123 vk_free2(&device->alloc, pAllocator, view);
1124 }