2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= VI
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_image_is_tc_compat_htile(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< VI
)
75 if (pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
78 if (pCreateInfo
->flags
& (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
|
79 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
))
82 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
85 if (pCreateInfo
->mipLevels
> 1)
88 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
89 * tests - disable for now */
90 if (pCreateInfo
->samples
>= 2 &&
91 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
98 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
99 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
100 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
107 radv_init_surface(struct radv_device
*device
,
108 struct radeon_surf
*surface
,
109 const struct radv_image_create_info
*create_info
)
111 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
112 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
113 const struct vk_format_description
*desc
=
114 vk_format_description(pCreateInfo
->format
);
115 bool is_depth
, is_stencil
, blendable
;
117 is_depth
= vk_format_has_depth(desc
);
118 is_stencil
= vk_format_has_stencil(desc
);
120 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
121 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
123 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
124 /* align byte per element on dword */
125 if (surface
->bpe
== 3) {
128 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
130 switch (pCreateInfo
->imageType
){
131 case VK_IMAGE_TYPE_1D
:
132 if (pCreateInfo
->arrayLayers
> 1)
133 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
135 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
137 case VK_IMAGE_TYPE_2D
:
138 if (pCreateInfo
->arrayLayers
> 1)
139 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
141 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
143 case VK_IMAGE_TYPE_3D
:
144 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
147 unreachable("unhandled image type");
151 surface
->flags
|= RADEON_SURF_ZBUFFER
;
152 if (radv_image_is_tc_compat_htile(device
, pCreateInfo
))
153 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
157 surface
->flags
|= RADEON_SURF_SBUFFER
;
159 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
161 bool dcc_compatible_formats
= radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
);
162 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
163 const struct VkImageFormatListCreateInfoKHR
*format_list
=
164 (const struct VkImageFormatListCreateInfoKHR
*)
165 vk_find_struct_const(pCreateInfo
->pNext
,
166 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
168 /* We have to ignore the existence of the list if viewFormatCount = 0 */
169 if (format_list
&& format_list
->viewFormatCount
) {
170 /* compatibility is transitive, so we only need to check
171 * one format with everything else. */
172 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
173 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
174 format_list
->pViewFormats
[i
]))
175 dcc_compatible_formats
= false;
178 dcc_compatible_formats
= false;
182 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
183 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
) ||
184 !dcc_compatible_formats
||
185 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
186 pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1 ||
187 device
->physical_device
->rad_info
.chip_class
< VI
||
188 create_info
->scanout
|| (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
189 pCreateInfo
->samples
>= 2)
190 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
191 if (create_info
->scanout
)
192 surface
->flags
|= RADEON_SURF_SCANOUT
;
196 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
198 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
201 static inline unsigned
202 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
205 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
207 return image
->surface
.u
.legacy
.tiling_index
[level
];
210 static unsigned radv_map_swizzle(unsigned swizzle
)
214 return V_008F0C_SQ_SEL_Y
;
216 return V_008F0C_SQ_SEL_Z
;
218 return V_008F0C_SQ_SEL_W
;
220 return V_008F0C_SQ_SEL_0
;
222 return V_008F0C_SQ_SEL_1
;
223 default: /* VK_SWIZZLE_X */
224 return V_008F0C_SQ_SEL_X
;
229 radv_make_buffer_descriptor(struct radv_device
*device
,
230 struct radv_buffer
*buffer
,
236 const struct vk_format_description
*desc
;
238 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
239 uint64_t va
= gpu_address
+ buffer
->offset
;
240 unsigned num_format
, data_format
;
242 desc
= vk_format_description(vk_format
);
243 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
244 stride
= desc
->block
.bits
/ 8;
246 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
247 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
251 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
252 S_008F04_STRIDE(stride
);
254 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
259 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
260 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
261 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
262 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
263 S_008F0C_NUM_FORMAT(num_format
) |
264 S_008F0C_DATA_FORMAT(data_format
);
268 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
269 struct radv_image
*image
,
270 const struct legacy_surf_level
*base_level_info
,
271 unsigned base_level
, unsigned first_level
,
272 unsigned block_width
, bool is_stencil
,
273 bool is_storage_image
, uint32_t *state
)
275 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
276 uint64_t va
= gpu_address
;
277 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
278 uint64_t meta_va
= 0;
279 if (chip_class
>= GFX9
) {
281 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
283 va
+= image
->surface
.u
.gfx9
.surf_offset
;
285 va
+= base_level_info
->offset
;
288 if (chip_class
>= GFX9
||
289 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
290 state
[0] |= image
->surface
.tile_swizzle
;
291 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
294 if (chip_class
>= VI
) {
295 state
[6] &= C_008F28_COMPRESSION_EN
;
297 if (!is_storage_image
&& radv_vi_dcc_enabled(image
, first_level
)) {
298 meta_va
= gpu_address
+ image
->dcc_offset
;
299 if (chip_class
<= VI
)
300 meta_va
+= base_level_info
->dcc_offset
;
301 } else if(!is_storage_image
&& image
->tc_compatible_htile
&&
302 image
->surface
.htile_size
) {
303 meta_va
= gpu_address
+ image
->htile_offset
;
307 state
[6] |= S_008F28_COMPRESSION_EN(1);
308 state
[7] = meta_va
>> 8;
309 state
[7] |= image
->surface
.tile_swizzle
;
313 if (chip_class
>= GFX9
) {
314 state
[3] &= C_008F1C_SW_MODE
;
315 state
[4] &= C_008F20_PITCH_GFX9
;
318 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
319 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
321 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
322 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
325 state
[5] &= C_008F24_META_DATA_ADDRESS
&
326 C_008F24_META_PIPE_ALIGNED
&
327 C_008F24_META_RB_ALIGNED
;
329 struct gfx9_surf_meta_flags meta
;
331 if (image
->dcc_offset
)
332 meta
= image
->surface
.u
.gfx9
.dcc
;
334 meta
= image
->surface
.u
.gfx9
.htile
;
336 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
337 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
338 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
342 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
343 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
345 state
[3] &= C_008F1C_TILING_INDEX
;
346 state
[3] |= S_008F1C_TILING_INDEX(index
);
347 state
[4] &= C_008F20_PITCH_GFX6
;
348 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
352 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
353 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
355 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
356 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
358 /* GFX9 allocates 1D textures as 2D. */
359 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
360 image_type
= VK_IMAGE_TYPE_2D
;
361 switch (image_type
) {
362 case VK_IMAGE_TYPE_1D
:
363 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
364 case VK_IMAGE_TYPE_2D
:
366 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
368 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
369 case VK_IMAGE_TYPE_3D
:
370 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
371 return V_008F1C_SQ_RSRC_IMG_3D
;
373 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
375 unreachable("illegale image type");
379 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
381 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
383 if (swizzle
[3] == VK_SWIZZLE_X
) {
384 /* For the pre-defined border color values (white, opaque
385 * black, transparent black), the only thing that matters is
386 * that the alpha channel winds up in the correct place
387 * (because the RGB channels are all the same) so either of
388 * these enumerations will work.
390 if (swizzle
[2] == VK_SWIZZLE_Y
)
391 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
393 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
394 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
395 if (swizzle
[1] == VK_SWIZZLE_Y
)
396 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
398 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
399 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
400 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
401 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
402 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
409 * Build the sampler view descriptor for a texture.
412 si_make_texture_descriptor(struct radv_device
*device
,
413 struct radv_image
*image
,
414 bool is_storage_image
,
415 VkImageViewType view_type
,
417 const VkComponentMapping
*mapping
,
418 unsigned first_level
, unsigned last_level
,
419 unsigned first_layer
, unsigned last_layer
,
420 unsigned width
, unsigned height
, unsigned depth
,
422 uint32_t *fmask_state
)
424 const struct vk_format_description
*desc
;
425 enum vk_swizzle swizzle
[4];
427 unsigned num_format
, data_format
, type
;
429 desc
= vk_format_description(vk_format
);
431 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
432 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
433 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
435 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
438 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
440 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
441 if (num_format
== ~0) {
445 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
446 if (data_format
== ~0) {
450 /* S8 with either Z16 or Z32 HTILE need a special format. */
451 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
452 vk_format
== VK_FORMAT_S8_UINT
&&
453 image
->tc_compatible_htile
) {
454 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
455 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
456 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
457 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
459 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
460 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
461 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
463 depth
= image
->info
.array_size
;
464 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
465 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
466 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
467 depth
= image
->info
.array_size
;
468 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
469 depth
= image
->info
.array_size
/ 6;
472 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
473 S_008F14_NUM_FORMAT_GFX6(num_format
));
474 state
[2] = (S_008F18_WIDTH(width
- 1) |
475 S_008F18_HEIGHT(height
- 1) |
476 S_008F18_PERF_MOD(4));
477 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
478 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
479 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
480 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
481 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
483 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
484 util_logbase2(image
->info
.samples
) :
486 S_008F1C_TYPE(type
));
488 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
492 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
493 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
495 /* Depth is the the last accessible layer on Gfx9.
496 * The hw doesn't need to know the total number of layers.
498 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
499 state
[4] |= S_008F20_DEPTH(depth
- 1);
501 state
[4] |= S_008F20_DEPTH(last_layer
);
503 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
504 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
505 util_logbase2(image
->info
.samples
) :
506 image
->info
.levels
- 1);
508 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
509 state
[4] |= S_008F20_DEPTH(depth
- 1);
510 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
512 if (image
->dcc_offset
) {
513 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
515 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
517 /* The last dword is unused by hw. The shader uses it to clear
518 * bits in the first dword of sampler state.
520 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
521 if (first_level
== last_level
)
522 state
[7] = C_008F30_MAX_ANISO_RATIO
;
524 state
[7] = 0xffffffff;
528 /* Initialize the sampler view for FMASK. */
529 if (image
->fmask
.size
) {
530 uint32_t fmask_format
, num_format
;
531 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
534 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
536 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
537 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
538 switch (image
->info
.samples
) {
540 num_format
= V_008F14_IMG_FMASK_8_2_2
;
543 num_format
= V_008F14_IMG_FMASK_8_4_4
;
546 num_format
= V_008F14_IMG_FMASK_32_8_8
;
549 unreachable("invalid nr_samples");
552 switch (image
->info
.samples
) {
554 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
557 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
560 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
564 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
566 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
569 fmask_state
[0] = va
>> 8;
570 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
571 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
572 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
573 S_008F14_NUM_FORMAT_GFX6(num_format
);
574 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
575 S_008F18_HEIGHT(height
- 1);
576 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
577 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
578 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
579 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
580 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false, false));
582 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
586 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
587 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
588 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
589 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
590 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
591 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
593 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
594 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
595 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
596 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
598 } else if (fmask_state
)
599 memset(fmask_state
, 0, 8 * 4);
603 radv_query_opaque_metadata(struct radv_device
*device
,
604 struct radv_image
*image
,
605 struct radeon_bo_metadata
*md
)
607 static const VkComponentMapping fixedmapping
;
610 /* Metadata image format format version 1:
611 * [0] = 1 (metadata format identifier)
612 * [1] = (VENDOR_ID << 16) | PCI_ID
613 * [2:9] = image descriptor for the whole resource
614 * [2] is always 0, because the base address is cleared
615 * [9] is the DCC offset bits [39:8] from the beginning of
617 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
619 md
->metadata
[0] = 1; /* metadata image format version 1 */
621 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
622 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
625 si_make_texture_descriptor(device
, image
, false,
626 (VkImageViewType
)image
->type
, image
->vk_format
,
627 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
628 image
->info
.array_size
,
629 image
->info
.width
, image
->info
.height
,
633 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
634 image
->surface
.blk_w
, false, false, desc
);
636 /* Clear the base address and set the relative DCC offset. */
638 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
639 desc
[7] = image
->dcc_offset
>> 8;
641 /* Dwords [2:9] contain the image descriptor. */
642 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
644 /* Dwords [10:..] contain the mipmap level offsets. */
645 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
646 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
647 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
648 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
653 radv_init_metadata(struct radv_device
*device
,
654 struct radv_image
*image
,
655 struct radeon_bo_metadata
*metadata
)
657 struct radeon_surf
*surface
= &image
->surface
;
659 memset(metadata
, 0, sizeof(*metadata
));
661 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
662 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
664 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
665 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
666 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
667 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
668 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
669 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
670 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
671 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
672 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
673 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
674 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
675 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
677 radv_query_opaque_metadata(device
, image
, metadata
);
680 /* The number of samples can be specified independently of the texture. */
682 radv_image_get_fmask_info(struct radv_device
*device
,
683 struct radv_image
*image
,
685 struct radv_fmask_info
*out
)
687 /* FMASK is allocated like an ordinary texture. */
688 struct radeon_surf fmask
= {};
689 struct ac_surf_info info
= image
->info
;
690 memset(out
, 0, sizeof(*out
));
692 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
693 out
->alignment
= image
->surface
.u
.gfx9
.fmask_alignment
;
694 out
->size
= image
->surface
.u
.gfx9
.fmask_size
;
698 fmask
.blk_w
= image
->surface
.blk_w
;
699 fmask
.blk_h
= image
->surface
.blk_h
;
701 fmask
.flags
= image
->surface
.flags
| RADEON_SURF_FMASK
;
703 if (!image
->shareable
)
704 info
.surf_index
= &device
->fmask_mrt_offset_counter
;
706 /* Force 2D tiling if it wasn't set. This may occur when creating
707 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
708 * destination buffer must have an FMASK too. */
709 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
710 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
712 switch (nr_samples
) {
724 device
->ws
->surface_init(device
->ws
, &info
, &fmask
);
725 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
727 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
728 if (out
->slice_tile_max
)
729 out
->slice_tile_max
-= 1;
731 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
732 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
733 out
->bank_height
= fmask
.u
.legacy
.bankh
;
734 out
->tile_swizzle
= fmask
.tile_swizzle
;
735 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
736 out
->size
= fmask
.surf_size
;
738 assert(!out
->tile_swizzle
|| !image
->shareable
);
742 radv_image_alloc_fmask(struct radv_device
*device
,
743 struct radv_image
*image
)
745 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
747 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
748 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
749 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
753 radv_image_get_cmask_info(struct radv_device
*device
,
754 struct radv_image
*image
,
755 struct radv_cmask_info
*out
)
757 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
758 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
759 unsigned cl_width
, cl_height
;
761 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
762 out
->alignment
= image
->surface
.u
.gfx9
.cmask_alignment
;
763 out
->size
= image
->surface
.u
.gfx9
.cmask_size
;
780 case 16: /* Hawaii */
789 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
791 unsigned width
= align(image
->info
.width
, cl_width
*8);
792 unsigned height
= align(image
->info
.height
, cl_height
*8);
793 unsigned slice_elements
= (width
* height
) / (8*8);
795 /* Each element of CMASK is a nibble. */
796 unsigned slice_bytes
= slice_elements
/ 2;
798 out
->slice_tile_max
= (width
* height
) / (128*128);
799 if (out
->slice_tile_max
)
800 out
->slice_tile_max
-= 1;
802 out
->alignment
= MAX2(256, base_align
);
803 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
804 align(slice_bytes
, base_align
);
808 radv_image_alloc_cmask(struct radv_device
*device
,
809 struct radv_image
*image
)
811 uint32_t clear_value_size
= 0;
812 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
814 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
815 /* + 8 for storing the clear values */
816 if (!image
->clear_value_offset
) {
817 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
818 clear_value_size
= 8;
820 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
821 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
825 radv_image_alloc_dcc(struct radv_image
*image
)
827 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
828 /* + 16 for storing the clear values + dcc pred */
829 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
830 image
->dcc_pred_offset
= image
->clear_value_offset
+ 8;
831 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
832 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
836 radv_image_alloc_htile(struct radv_image
*image
)
838 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
840 /* + 8 for storing the clear values */
841 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
842 image
->size
= image
->clear_value_offset
+ 8;
843 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
847 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
849 if (image
->info
.samples
<= 1 &&
850 image
->info
.width
* image
->info
.height
<= 512 * 512) {
851 /* Do not enable CMASK or DCC for small surfaces where the cost
852 * of the eliminate pass can be higher than the benefit of fast
853 * clear. RadeonSI does this, but the image threshold is
859 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
860 (image
->exclusive
|| image
->queue_family_mask
== 1);
864 radv_image_can_enable_dcc(struct radv_image
*image
)
866 return radv_image_can_enable_dcc_or_cmask(image
) &&
867 image
->surface
.dcc_size
;
871 radv_image_can_enable_cmask(struct radv_image
*image
)
873 if (image
->surface
.bpe
> 8 && image
->info
.samples
== 1) {
874 /* Do not enable CMASK for non-MSAA images (fast color clear)
875 * because 128 bit formats are not supported, but FMASK might
881 return radv_image_can_enable_dcc_or_cmask(image
) &&
882 image
->info
.levels
== 1 &&
883 image
->info
.depth
== 1 &&
884 !image
->surface
.is_linear
;
888 radv_image_can_enable_fmask(struct radv_image
*image
)
890 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
894 radv_image_can_enable_htile(struct radv_image
*image
)
896 return image
->info
.levels
== 1 && vk_format_is_depth(image
->vk_format
);
900 radv_image_create(VkDevice _device
,
901 const struct radv_image_create_info
*create_info
,
902 const VkAllocationCallbacks
* alloc
,
905 RADV_FROM_HANDLE(radv_device
, device
, _device
);
906 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
907 struct radv_image
*image
= NULL
;
908 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
910 radv_assert(pCreateInfo
->mipLevels
> 0);
911 radv_assert(pCreateInfo
->arrayLayers
> 0);
912 radv_assert(pCreateInfo
->samples
> 0);
913 radv_assert(pCreateInfo
->extent
.width
> 0);
914 radv_assert(pCreateInfo
->extent
.height
> 0);
915 radv_assert(pCreateInfo
->extent
.depth
> 0);
917 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
918 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
920 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
922 image
->type
= pCreateInfo
->imageType
;
923 image
->info
.width
= pCreateInfo
->extent
.width
;
924 image
->info
.height
= pCreateInfo
->extent
.height
;
925 image
->info
.depth
= pCreateInfo
->extent
.depth
;
926 image
->info
.samples
= pCreateInfo
->samples
;
927 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
928 image
->info
.levels
= pCreateInfo
->mipLevels
;
930 image
->vk_format
= pCreateInfo
->format
;
931 image
->tiling
= pCreateInfo
->tiling
;
932 image
->usage
= pCreateInfo
->usage
;
933 image
->flags
= pCreateInfo
->flags
;
935 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
936 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
937 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
938 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
939 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
941 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
944 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
945 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
946 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
947 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
950 radv_init_surface(device
, &image
->surface
, create_info
);
952 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
954 image
->size
= image
->surface
.surf_size
;
955 image
->alignment
= image
->surface
.surf_alignment
;
957 if (!create_info
->no_metadata_planes
) {
958 /* Try to enable DCC first. */
959 if (radv_image_can_enable_dcc(image
)) {
960 radv_image_alloc_dcc(image
);
962 /* When DCC cannot be enabled, try CMASK. */
963 image
->surface
.dcc_size
= 0;
964 if (radv_image_can_enable_cmask(image
)) {
965 radv_image_alloc_cmask(device
, image
);
969 /* Try to enable FMASK for multisampled images. */
970 if (radv_image_can_enable_fmask(image
)) {
971 radv_image_alloc_fmask(device
, image
);
973 /* Otherwise, try to enable HTILE for depth surfaces. */
974 if (radv_image_can_enable_htile(image
) &&
975 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
976 radv_image_alloc_htile(image
);
977 image
->tc_compatible_htile
= image
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
979 image
->surface
.htile_size
= 0;
983 image
->surface
.dcc_size
= 0;
984 image
->surface
.htile_size
= 0;
987 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
988 image
->alignment
= MAX2(image
->alignment
, 4096);
989 image
->size
= align64(image
->size
, image
->alignment
);
992 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
993 0, RADEON_FLAG_VIRTUAL
);
995 vk_free2(&device
->alloc
, alloc
, image
);
996 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1000 *pImage
= radv_image_to_handle(image
);
1006 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1007 struct radv_device
*device
,
1008 const VkComponentMapping
*components
,
1009 bool is_storage_image
)
1011 struct radv_image
*image
= iview
->image
;
1012 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1014 uint32_t *descriptor
;
1015 uint32_t hw_level
= 0;
1017 if (is_storage_image
) {
1018 descriptor
= iview
->storage_descriptor
;
1020 descriptor
= iview
->descriptor
;
1023 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
1024 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
1026 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1027 hw_level
= iview
->base_mip
;
1028 si_make_texture_descriptor(device
, image
, is_storage_image
,
1032 hw_level
, hw_level
+ iview
->level_count
- 1,
1034 iview
->base_layer
+ iview
->layer_count
- 1,
1035 iview
->extent
.width
,
1036 iview
->extent
.height
,
1037 iview
->extent
.depth
,
1041 const struct legacy_surf_level
*base_level_info
= NULL
;
1042 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1044 base_level_info
= &image
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1046 base_level_info
= &image
->surface
.u
.legacy
.level
[iview
->base_mip
];
1048 si_set_mutable_tex_desc_fields(device
, image
,
1052 blk_w
, is_stencil
, is_storage_image
, descriptor
);
1056 radv_image_view_init(struct radv_image_view
*iview
,
1057 struct radv_device
*device
,
1058 const VkImageViewCreateInfo
* pCreateInfo
)
1060 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1061 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1063 switch (image
->type
) {
1064 case VK_IMAGE_TYPE_1D
:
1065 case VK_IMAGE_TYPE_2D
:
1066 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1068 case VK_IMAGE_TYPE_3D
:
1069 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1070 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1073 unreachable("bad VkImageType");
1075 iview
->image
= image
;
1076 iview
->bo
= image
->bo
;
1077 iview
->type
= pCreateInfo
->viewType
;
1078 iview
->vk_format
= pCreateInfo
->format
;
1079 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1081 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1082 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1083 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1084 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1087 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1088 iview
->extent
= (VkExtent3D
) {
1089 .width
= image
->info
.width
,
1090 .height
= image
->info
.height
,
1091 .depth
= image
->info
.depth
,
1094 iview
->extent
= (VkExtent3D
) {
1095 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1096 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1097 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1101 if (iview
->vk_format
!= image
->vk_format
) {
1102 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1103 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1104 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1105 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1107 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1108 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1110 /* Comment ported from amdvlk -
1111 * If we have the following image:
1112 * Uncompressed pixels Compressed block sizes (4x4)
1113 * mip0: 22 x 22 6 x 6
1114 * mip1: 11 x 11 3 x 3
1119 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1120 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1121 * divide-by-two integer math):
1127 * This means that mip2 will be missing texels.
1129 * Fix this by calculating the base mip's width and height, then convert that, and round it
1130 * back up to get the level 0 size.
1131 * Clamp the converted size between the original values, and next power of two, which
1132 * means we don't oversize the image.
1134 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1135 vk_format_is_compressed(image
->vk_format
) &&
1136 !vk_format_is_compressed(iview
->vk_format
)) {
1137 unsigned rounded_img_w
= util_next_power_of_two(iview
->extent
.width
);
1138 unsigned rounded_img_h
= util_next_power_of_two(iview
->extent
.height
);
1139 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1140 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1142 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1143 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1145 lvl_width
<<= range
->baseMipLevel
;
1146 lvl_height
<<= range
->baseMipLevel
;
1148 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, rounded_img_w
);
1149 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, rounded_img_h
);
1153 iview
->base_layer
= range
->baseArrayLayer
;
1154 iview
->layer_count
= radv_get_layerCount(image
, range
);
1155 iview
->base_mip
= range
->baseMipLevel
;
1156 iview
->level_count
= radv_get_levelCount(image
, range
);
1158 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, false);
1159 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, true);
1162 bool radv_layout_has_htile(const struct radv_image
*image
,
1163 VkImageLayout layout
,
1164 unsigned queue_mask
)
1166 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1167 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1169 return image
->surface
.htile_size
&&
1170 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1171 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1172 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1175 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1176 VkImageLayout layout
,
1177 unsigned queue_mask
)
1179 if (image
->surface
.htile_size
&& image
->tc_compatible_htile
)
1180 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1182 return image
->surface
.htile_size
&&
1183 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1184 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1185 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1188 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1189 VkImageLayout layout
,
1190 unsigned queue_mask
)
1192 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
1193 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1196 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1197 VkImageLayout layout
,
1198 unsigned queue_mask
)
1200 /* Don't compress compute transfer dst, as image stores are not supported. */
1201 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1202 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1205 return image
->surface
.num_dcc_levels
> 0 && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1209 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1211 if (!image
->exclusive
)
1212 return image
->queue_family_mask
;
1213 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
1214 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1215 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1216 return 1u << queue_family
;
1217 return 1u << family
;
1221 radv_CreateImage(VkDevice device
,
1222 const VkImageCreateInfo
*pCreateInfo
,
1223 const VkAllocationCallbacks
*pAllocator
,
1227 const VkNativeBufferANDROID
*gralloc_info
=
1228 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1231 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1232 pAllocator
, pImage
);
1235 const struct wsi_image_create_info
*wsi_info
=
1236 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1237 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1239 return radv_image_create(device
,
1240 &(struct radv_image_create_info
) {
1241 .vk_info
= pCreateInfo
,
1249 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1250 const VkAllocationCallbacks
*pAllocator
)
1252 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1253 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1258 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1259 device
->ws
->buffer_destroy(image
->bo
);
1261 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1262 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1264 vk_free2(&device
->alloc
, pAllocator
, image
);
1267 void radv_GetImageSubresourceLayout(
1270 const VkImageSubresource
* pSubresource
,
1271 VkSubresourceLayout
* pLayout
)
1273 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1274 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1275 int level
= pSubresource
->mipLevel
;
1276 int layer
= pSubresource
->arrayLayer
;
1277 struct radeon_surf
*surface
= &image
->surface
;
1279 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1280 pLayout
->offset
= surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1281 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1282 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1283 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1284 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1285 if (image
->type
== VK_IMAGE_TYPE_3D
)
1286 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1288 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1289 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1290 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1291 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1292 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1293 if (image
->type
== VK_IMAGE_TYPE_3D
)
1294 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1300 radv_CreateImageView(VkDevice _device
,
1301 const VkImageViewCreateInfo
*pCreateInfo
,
1302 const VkAllocationCallbacks
*pAllocator
,
1305 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1306 struct radv_image_view
*view
;
1308 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1309 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1311 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1313 radv_image_view_init(view
, device
, pCreateInfo
);
1315 *pView
= radv_image_view_to_handle(view
);
1321 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1322 const VkAllocationCallbacks
*pAllocator
)
1324 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1325 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1329 vk_free2(&device
->alloc
, pAllocator
, iview
);
1332 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1333 struct radv_device
*device
,
1334 const VkBufferViewCreateInfo
* pCreateInfo
)
1336 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1338 view
->bo
= buffer
->bo
;
1339 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1340 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1341 view
->vk_format
= pCreateInfo
->format
;
1343 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1344 pCreateInfo
->offset
, view
->range
, view
->state
);
1348 radv_CreateBufferView(VkDevice _device
,
1349 const VkBufferViewCreateInfo
*pCreateInfo
,
1350 const VkAllocationCallbacks
*pAllocator
,
1351 VkBufferView
*pView
)
1353 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1354 struct radv_buffer_view
*view
;
1356 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1357 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1359 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1361 radv_buffer_view_init(view
, device
, pCreateInfo
);
1363 *pView
= radv_buffer_view_to_handle(view
);
1369 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1370 const VkAllocationCallbacks
*pAllocator
)
1372 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1373 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1378 vk_free2(&device
->alloc
, pAllocator
, view
);