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ddf15bc8361e265a26a0f0182303c892b0278d04
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "vk_util.h"
31 #include "radv_radeon_winsys.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36 static unsigned
37 radv_choose_tiling(struct radv_device *Device,
38 const struct radv_image_create_info *create_info)
39 {
40 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
41
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
49 /* Only very thin and long 2D textures should benefit from
50 * linear_aligned. */
51 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED;
53
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo->samples > 1)
56 return RADEON_SURF_MODE_2D;
57
58 return RADEON_SURF_MODE_2D;
59 }
60 static int
61 radv_init_surface(struct radv_device *device,
62 struct radeon_surf *surface,
63 const struct radv_image_create_info *create_info)
64 {
65 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
66 unsigned array_mode = radv_choose_tiling(device, create_info);
67 const struct vk_format_description *desc =
68 vk_format_description(pCreateInfo->format);
69 bool is_depth, is_stencil, blendable;
70
71 is_depth = vk_format_has_depth(desc);
72 is_stencil = vk_format_has_stencil(desc);
73
74 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
75 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
76
77 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
78 /* align byte per element on dword */
79 if (surface->bpe == 3) {
80 surface->bpe = 4;
81 }
82 surface->flags = RADEON_SURF_SET(array_mode, MODE);
83
84 switch (pCreateInfo->imageType){
85 case VK_IMAGE_TYPE_1D:
86 if (pCreateInfo->arrayLayers > 1)
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
88 else
89 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
90 break;
91 case VK_IMAGE_TYPE_2D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_3D:
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
99 break;
100 default:
101 unreachable("unhandled image type");
102 }
103
104 if (is_depth) {
105 surface->flags |= RADEON_SURF_ZBUFFER;
106 }
107
108 if (is_stencil)
109 surface->flags |= RADEON_SURF_SBUFFER;
110
111 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
112
113 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
114 VK_IMAGE_USAGE_STORAGE_BIT)) ||
115 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
116 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
117 device->physical_device->rad_info.chip_class < VI ||
118 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
119 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
120 surface->flags |= RADEON_SURF_DISABLE_DCC;
121 if (create_info->scanout)
122 surface->flags |= RADEON_SURF_SCANOUT;
123 return 0;
124 }
125 #define ATI_VENDOR_ID 0x1002
126 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
127 {
128 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
129 }
130
131 static inline unsigned
132 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
133 {
134 if (stencil)
135 return image->surface.u.legacy.stencil_tiling_index[level];
136 else
137 return image->surface.u.legacy.tiling_index[level];
138 }
139
140 static unsigned radv_map_swizzle(unsigned swizzle)
141 {
142 switch (swizzle) {
143 case VK_SWIZZLE_Y:
144 return V_008F0C_SQ_SEL_Y;
145 case VK_SWIZZLE_Z:
146 return V_008F0C_SQ_SEL_Z;
147 case VK_SWIZZLE_W:
148 return V_008F0C_SQ_SEL_W;
149 case VK_SWIZZLE_0:
150 return V_008F0C_SQ_SEL_0;
151 case VK_SWIZZLE_1:
152 return V_008F0C_SQ_SEL_1;
153 default: /* VK_SWIZZLE_X */
154 return V_008F0C_SQ_SEL_X;
155 }
156 }
157
158 static void
159 radv_make_buffer_descriptor(struct radv_device *device,
160 struct radv_buffer *buffer,
161 VkFormat vk_format,
162 unsigned offset,
163 unsigned range,
164 uint32_t *state)
165 {
166 const struct vk_format_description *desc;
167 unsigned stride;
168 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
169 uint64_t va = gpu_address + buffer->offset;
170 unsigned num_format, data_format;
171 int first_non_void;
172 desc = vk_format_description(vk_format);
173 first_non_void = vk_format_get_first_non_void_channel(vk_format);
174 stride = desc->block.bits / 8;
175
176 num_format = radv_translate_buffer_numformat(desc, first_non_void);
177 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
178
179 va += offset;
180 state[0] = va;
181 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
182 S_008F04_STRIDE(stride);
183
184 if (device->physical_device->rad_info.chip_class < VI && stride) {
185 range /= stride;
186 }
187
188 state[2] = range;
189 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
190 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
191 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
192 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
193 S_008F0C_NUM_FORMAT(num_format) |
194 S_008F0C_DATA_FORMAT(data_format);
195 }
196
197 static void
198 si_set_mutable_tex_desc_fields(struct radv_device *device,
199 struct radv_image *image,
200 const struct legacy_surf_level *base_level_info,
201 unsigned base_level, unsigned first_level,
202 unsigned block_width, bool is_stencil,
203 uint32_t *state)
204 {
205 uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
206 uint64_t va = gpu_address;
207 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
208 uint64_t meta_va = 0;
209 if (chip_class >= GFX9) {
210 if (is_stencil)
211 va += image->surface.u.gfx9.stencil_offset;
212 else
213 va += image->surface.u.gfx9.surf_offset;
214 } else
215 va += base_level_info->offset;
216
217 state[0] = va >> 8;
218 if (chip_class >= GFX9 ||
219 base_level_info->mode == RADEON_SURF_MODE_2D)
220 state[0] |= image->surface.tile_swizzle;
221 state[1] &= C_008F14_BASE_ADDRESS_HI;
222 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
223
224 if (chip_class >= VI) {
225 state[6] &= C_008F28_COMPRESSION_EN;
226 state[7] = 0;
227 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
228 meta_va = gpu_address + image->dcc_offset;
229 if (chip_class <= VI)
230 meta_va += base_level_info->dcc_offset;
231 state[6] |= S_008F28_COMPRESSION_EN(1);
232 state[7] = meta_va >> 8;
233 state[7] |= image->surface.tile_swizzle;
234 }
235 }
236
237 if (chip_class >= GFX9) {
238 state[3] &= C_008F1C_SW_MODE;
239 state[4] &= C_008F20_PITCH_GFX9;
240
241 if (is_stencil) {
242 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
243 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
244 } else {
245 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
246 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
247 }
248
249 state[5] &= C_008F24_META_DATA_ADDRESS &
250 C_008F24_META_PIPE_ALIGNED &
251 C_008F24_META_RB_ALIGNED;
252 if (meta_va) {
253 struct gfx9_surf_meta_flags meta;
254
255 if (image->dcc_offset)
256 meta = image->surface.u.gfx9.dcc;
257 else
258 meta = image->surface.u.gfx9.htile;
259
260 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
261 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
262 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
263 }
264 } else {
265 /* SI-CI-VI */
266 unsigned pitch = base_level_info->nblk_x * block_width;
267 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
268
269 state[3] &= C_008F1C_TILING_INDEX;
270 state[3] |= S_008F1C_TILING_INDEX(index);
271 state[4] &= C_008F20_PITCH_GFX6;
272 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
273 }
274 }
275
276 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
277 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
278 {
279 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
280 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
281 switch (image_type) {
282 case VK_IMAGE_TYPE_1D:
283 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
284 case VK_IMAGE_TYPE_2D:
285 if (nr_samples > 1)
286 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
287 else
288 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
289 case VK_IMAGE_TYPE_3D:
290 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
291 return V_008F1C_SQ_RSRC_IMG_3D;
292 else
293 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
294 default:
295 unreachable("illegale image type");
296 }
297 }
298
299 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
300 {
301 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
302
303 if (swizzle[3] == VK_SWIZZLE_X) {
304 /* For the pre-defined border color values (white, opaque
305 * black, transparent black), the only thing that matters is
306 * that the alpha channel winds up in the correct place
307 * (because the RGB channels are all the same) so either of
308 * these enumerations will work.
309 */
310 if (swizzle[2] == VK_SWIZZLE_Y)
311 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
312 else
313 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
314 } else if (swizzle[0] == VK_SWIZZLE_X) {
315 if (swizzle[1] == VK_SWIZZLE_Y)
316 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
317 else
318 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
319 } else if (swizzle[1] == VK_SWIZZLE_X) {
320 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
321 } else if (swizzle[2] == VK_SWIZZLE_X) {
322 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
323 }
324
325 return bc_swizzle;
326 }
327
328 /**
329 * Build the sampler view descriptor for a texture.
330 */
331 static void
332 si_make_texture_descriptor(struct radv_device *device,
333 struct radv_image *image,
334 bool is_storage_image,
335 VkImageViewType view_type,
336 VkFormat vk_format,
337 const VkComponentMapping *mapping,
338 unsigned first_level, unsigned last_level,
339 unsigned first_layer, unsigned last_layer,
340 unsigned width, unsigned height, unsigned depth,
341 uint32_t *state,
342 uint32_t *fmask_state)
343 {
344 const struct vk_format_description *desc;
345 enum vk_swizzle swizzle[4];
346 int first_non_void;
347 unsigned num_format, data_format, type;
348
349 desc = vk_format_description(vk_format);
350
351 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
352 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
353 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
354 } else {
355 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
356 }
357
358 first_non_void = vk_format_get_first_non_void_channel(vk_format);
359
360 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
361 if (num_format == ~0) {
362 num_format = 0;
363 }
364
365 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
366 if (data_format == ~0) {
367 data_format = 0;
368 }
369
370 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
371 is_storage_image);
372 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
373 height = 1;
374 depth = image->info.array_size;
375 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
376 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
377 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
378 depth = image->info.array_size;
379 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
380 depth = image->info.array_size / 6;
381
382 state[0] = 0;
383 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
384 S_008F14_NUM_FORMAT_GFX6(num_format));
385 state[2] = (S_008F18_WIDTH(width - 1) |
386 S_008F18_HEIGHT(height - 1) |
387 S_008F18_PERF_MOD(4));
388 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
389 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
390 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
391 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
392 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
393 0 : first_level) |
394 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
395 util_logbase2(image->info.samples) :
396 last_level) |
397 S_008F1C_TYPE(type));
398 state[4] = 0;
399 state[5] = S_008F24_BASE_ARRAY(first_layer);
400 state[6] = 0;
401 state[7] = 0;
402
403 if (device->physical_device->rad_info.chip_class >= GFX9) {
404 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
405
406 /* Depth is the the last accessible layer on Gfx9.
407 * The hw doesn't need to know the total number of layers.
408 */
409 if (type == V_008F1C_SQ_RSRC_IMG_3D)
410 state[4] |= S_008F20_DEPTH(depth - 1);
411 else
412 state[4] |= S_008F20_DEPTH(last_layer);
413
414 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
415 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
416 util_logbase2(image->info.samples) :
417 image->info.levels - 1);
418 } else {
419 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
420 state[4] |= S_008F20_DEPTH(depth - 1);
421 state[5] |= S_008F24_LAST_ARRAY(last_layer);
422 }
423 if (image->dcc_offset) {
424 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
425
426 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
427 } else {
428 /* The last dword is unused by hw. The shader uses it to clear
429 * bits in the first dword of sampler state.
430 */
431 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
432 if (first_level == last_level)
433 state[7] = C_008F30_MAX_ANISO_RATIO;
434 else
435 state[7] = 0xffffffff;
436 }
437 }
438
439 /* Initialize the sampler view for FMASK. */
440 if (image->fmask.size) {
441 uint32_t fmask_format, num_format;
442 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
443 uint64_t va;
444
445 va = gpu_address + image->offset + image->fmask.offset;
446
447 if (device->physical_device->rad_info.chip_class >= GFX9) {
448 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
449 switch (image->info.samples) {
450 case 2:
451 num_format = V_008F14_IMG_FMASK_8_2_2;
452 break;
453 case 4:
454 num_format = V_008F14_IMG_FMASK_8_4_4;
455 break;
456 case 8:
457 num_format = V_008F14_IMG_FMASK_32_8_8;
458 break;
459 default:
460 unreachable("invalid nr_samples");
461 }
462 } else {
463 switch (image->info.samples) {
464 case 2:
465 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
466 break;
467 case 4:
468 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
469 break;
470 case 8:
471 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
472 break;
473 default:
474 assert(0);
475 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
476 }
477 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
478 }
479
480 fmask_state[0] = va >> 8;
481 fmask_state[0] |= image->fmask.tile_swizzle;
482 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
483 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
484 S_008F14_NUM_FORMAT_GFX6(num_format);
485 fmask_state[2] = S_008F18_WIDTH(width - 1) |
486 S_008F18_HEIGHT(height - 1);
487 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
488 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
489 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
490 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
491 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
492 fmask_state[4] = 0;
493 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
494 fmask_state[6] = 0;
495 fmask_state[7] = 0;
496
497 if (device->physical_device->rad_info.chip_class >= GFX9) {
498 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
499 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
500 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
501 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
502 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
503 } else {
504 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
505 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
506 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
507 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
508 }
509 } else if (fmask_state)
510 memset(fmask_state, 0, 8 * 4);
511 }
512
513 static void
514 radv_query_opaque_metadata(struct radv_device *device,
515 struct radv_image *image,
516 struct radeon_bo_metadata *md)
517 {
518 static const VkComponentMapping fixedmapping;
519 uint32_t desc[8], i;
520
521 /* Metadata image format format version 1:
522 * [0] = 1 (metadata format identifier)
523 * [1] = (VENDOR_ID << 16) | PCI_ID
524 * [2:9] = image descriptor for the whole resource
525 * [2] is always 0, because the base address is cleared
526 * [9] is the DCC offset bits [39:8] from the beginning of
527 * the buffer
528 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
529 */
530 md->metadata[0] = 1; /* metadata image format version 1 */
531
532 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
533 md->metadata[1] = si_get_bo_metadata_word1(device);
534
535
536 si_make_texture_descriptor(device, image, false,
537 (VkImageViewType)image->type, image->vk_format,
538 &fixedmapping, 0, image->info.levels - 1, 0,
539 image->info.array_size,
540 image->info.width, image->info.height,
541 image->info.depth,
542 desc, NULL);
543
544 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
545 image->surface.blk_w, false, desc);
546
547 /* Clear the base address and set the relative DCC offset. */
548 desc[0] = 0;
549 desc[1] &= C_008F14_BASE_ADDRESS_HI;
550 desc[7] = image->dcc_offset >> 8;
551
552 /* Dwords [2:9] contain the image descriptor. */
553 memcpy(&md->metadata[2], desc, sizeof(desc));
554
555 /* Dwords [10:..] contain the mipmap level offsets. */
556 if (device->physical_device->rad_info.chip_class <= VI) {
557 for (i = 0; i <= image->info.levels - 1; i++)
558 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
559 md->size_metadata = (11 + image->info.levels - 1) * 4;
560 }
561 }
562
563 void
564 radv_init_metadata(struct radv_device *device,
565 struct radv_image *image,
566 struct radeon_bo_metadata *metadata)
567 {
568 struct radeon_surf *surface = &image->surface;
569
570 memset(metadata, 0, sizeof(*metadata));
571
572 if (device->physical_device->rad_info.chip_class >= GFX9) {
573 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
574 } else {
575 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
576 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
577 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
578 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
579 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
580 metadata->u.legacy.bankw = surface->u.legacy.bankw;
581 metadata->u.legacy.bankh = surface->u.legacy.bankh;
582 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
583 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
584 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
585 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
586 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
587 }
588 radv_query_opaque_metadata(device, image, metadata);
589 }
590
591 /* The number of samples can be specified independently of the texture. */
592 static void
593 radv_image_get_fmask_info(struct radv_device *device,
594 struct radv_image *image,
595 unsigned nr_samples,
596 struct radv_fmask_info *out)
597 {
598 /* FMASK is allocated like an ordinary texture. */
599 struct radeon_surf fmask = {};
600 struct ac_surf_info info = image->info;
601 memset(out, 0, sizeof(*out));
602
603 if (device->physical_device->rad_info.chip_class >= GFX9) {
604 out->alignment = image->surface.u.gfx9.fmask_alignment;
605 out->size = image->surface.u.gfx9.fmask_size;
606 return;
607 }
608
609 fmask.blk_w = image->surface.blk_w;
610 fmask.blk_h = image->surface.blk_h;
611 info.samples = 1;
612 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
613
614 if (!image->shareable)
615 info.surf_index = &device->fmask_mrt_offset_counter;
616
617 /* Force 2D tiling if it wasn't set. This may occur when creating
618 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
619 * destination buffer must have an FMASK too. */
620 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
621 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
622
623 switch (nr_samples) {
624 case 2:
625 case 4:
626 fmask.bpe = 1;
627 break;
628 case 8:
629 fmask.bpe = 4;
630 break;
631 default:
632 return;
633 }
634
635 device->ws->surface_init(device->ws, &info, &fmask);
636 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
637
638 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
639 if (out->slice_tile_max)
640 out->slice_tile_max -= 1;
641
642 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
643 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
644 out->bank_height = fmask.u.legacy.bankh;
645 out->tile_swizzle = fmask.tile_swizzle;
646 out->alignment = MAX2(256, fmask.surf_alignment);
647 out->size = fmask.surf_size;
648
649 assert(!out->tile_swizzle || !image->shareable);
650 }
651
652 static void
653 radv_image_alloc_fmask(struct radv_device *device,
654 struct radv_image *image)
655 {
656 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
657
658 image->fmask.offset = align64(image->size, image->fmask.alignment);
659 image->size = image->fmask.offset + image->fmask.size;
660 image->alignment = MAX2(image->alignment, image->fmask.alignment);
661 }
662
663 static void
664 radv_image_get_cmask_info(struct radv_device *device,
665 struct radv_image *image,
666 struct radv_cmask_info *out)
667 {
668 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
669 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
670 unsigned cl_width, cl_height;
671
672 if (device->physical_device->rad_info.chip_class >= GFX9) {
673 out->alignment = image->surface.u.gfx9.cmask_alignment;
674 out->size = image->surface.u.gfx9.cmask_size;
675 return;
676 }
677
678 switch (num_pipes) {
679 case 2:
680 cl_width = 32;
681 cl_height = 16;
682 break;
683 case 4:
684 cl_width = 32;
685 cl_height = 32;
686 break;
687 case 8:
688 cl_width = 64;
689 cl_height = 32;
690 break;
691 case 16: /* Hawaii */
692 cl_width = 64;
693 cl_height = 64;
694 break;
695 default:
696 assert(0);
697 return;
698 }
699
700 unsigned base_align = num_pipes * pipe_interleave_bytes;
701
702 unsigned width = align(image->info.width, cl_width*8);
703 unsigned height = align(image->info.height, cl_height*8);
704 unsigned slice_elements = (width * height) / (8*8);
705
706 /* Each element of CMASK is a nibble. */
707 unsigned slice_bytes = slice_elements / 2;
708
709 out->slice_tile_max = (width * height) / (128*128);
710 if (out->slice_tile_max)
711 out->slice_tile_max -= 1;
712
713 out->alignment = MAX2(256, base_align);
714 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
715 align(slice_bytes, base_align);
716 }
717
718 static void
719 radv_image_alloc_cmask(struct radv_device *device,
720 struct radv_image *image)
721 {
722 uint32_t clear_value_size = 0;
723 radv_image_get_cmask_info(device, image, &image->cmask);
724
725 image->cmask.offset = align64(image->size, image->cmask.alignment);
726 /* + 8 for storing the clear values */
727 if (!image->clear_value_offset) {
728 image->clear_value_offset = image->cmask.offset + image->cmask.size;
729 clear_value_size = 8;
730 }
731 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
732 image->alignment = MAX2(image->alignment, image->cmask.alignment);
733 }
734
735 static void
736 radv_image_alloc_dcc(struct radv_device *device,
737 struct radv_image *image)
738 {
739 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
740 /* + 16 for storing the clear values + dcc pred */
741 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
742 image->dcc_pred_offset = image->clear_value_offset + 8;
743 image->size = image->dcc_offset + image->surface.dcc_size + 16;
744 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
745 }
746
747 static void
748 radv_image_alloc_htile(struct radv_device *device,
749 struct radv_image *image)
750 {
751 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
752 image->surface.htile_size = 0;
753 return;
754 }
755
756 image->htile_offset = align64(image->size, image->surface.htile_alignment);
757
758 /* + 8 for storing the clear values */
759 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
760 image->size = image->clear_value_offset + 8;
761 image->alignment = align64(image->alignment, image->surface.htile_alignment);
762 }
763
764 VkResult
765 radv_image_create(VkDevice _device,
766 const struct radv_image_create_info *create_info,
767 const VkAllocationCallbacks* alloc,
768 VkImage *pImage)
769 {
770 RADV_FROM_HANDLE(radv_device, device, _device);
771 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
772 struct radv_image *image = NULL;
773 bool can_cmask_dcc = false;
774 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
775
776 radv_assert(pCreateInfo->mipLevels > 0);
777 radv_assert(pCreateInfo->arrayLayers > 0);
778 radv_assert(pCreateInfo->samples > 0);
779 radv_assert(pCreateInfo->extent.width > 0);
780 radv_assert(pCreateInfo->extent.height > 0);
781 radv_assert(pCreateInfo->extent.depth > 0);
782
783 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
784 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
785 if (!image)
786 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
787
788 memset(image, 0, sizeof(*image));
789 image->type = pCreateInfo->imageType;
790 image->info.width = pCreateInfo->extent.width;
791 image->info.height = pCreateInfo->extent.height;
792 image->info.depth = pCreateInfo->extent.depth;
793 image->info.samples = pCreateInfo->samples;
794 image->info.array_size = pCreateInfo->arrayLayers;
795 image->info.levels = pCreateInfo->mipLevels;
796
797 image->vk_format = pCreateInfo->format;
798 image->tiling = pCreateInfo->tiling;
799 image->usage = pCreateInfo->usage;
800 image->flags = pCreateInfo->flags;
801
802 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
803 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
804 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
805 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
806 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
807 else
808 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
809 }
810
811 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
812 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
813 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
814 image->info.surf_index = &device->image_mrt_offset_counter;
815 }
816
817 radv_init_surface(device, &image->surface, create_info);
818
819 device->ws->surface_init(device->ws, &image->info, &image->surface);
820
821 image->size = image->surface.surf_size;
822 image->alignment = image->surface.surf_alignment;
823
824 if (image->exclusive || image->queue_family_mask == 1)
825 can_cmask_dcc = true;
826
827 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
828 image->surface.dcc_size && can_cmask_dcc)
829 radv_image_alloc_dcc(device, image);
830 else
831 image->surface.dcc_size = 0;
832
833 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
834 pCreateInfo->mipLevels == 1 &&
835 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
836 radv_image_alloc_cmask(device, image);
837 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
838 radv_image_alloc_fmask(device, image);
839 } else if (vk_format_is_depth(pCreateInfo->format)) {
840
841 radv_image_alloc_htile(device, image);
842 }
843
844 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
845 image->alignment = MAX2(image->alignment, 4096);
846 image->size = align64(image->size, image->alignment);
847 image->offset = 0;
848
849 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
850 0, RADEON_FLAG_VIRTUAL);
851 if (!image->bo) {
852 vk_free2(&device->alloc, alloc, image);
853 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
854 }
855 }
856
857 *pImage = radv_image_to_handle(image);
858
859 return VK_SUCCESS;
860 }
861
862 static void
863 radv_image_view_make_descriptor(struct radv_image_view *iview,
864 struct radv_device *device,
865 const VkComponentMapping *components,
866 bool is_storage_image)
867 {
868 struct radv_image *image = iview->image;
869 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
870 uint32_t blk_w;
871 uint32_t *descriptor;
872 uint32_t *fmask_descriptor;
873
874 if (is_storage_image) {
875 descriptor = iview->storage_descriptor;
876 fmask_descriptor = iview->storage_fmask_descriptor;
877 } else {
878 descriptor = iview->descriptor;
879 fmask_descriptor = iview->fmask_descriptor;
880 }
881
882 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
883 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
884
885 si_make_texture_descriptor(device, image, is_storage_image,
886 iview->type,
887 iview->vk_format,
888 components,
889 0, iview->level_count - 1,
890 iview->base_layer,
891 iview->base_layer + iview->layer_count - 1,
892 iview->extent.width,
893 iview->extent.height,
894 iview->extent.depth,
895 descriptor,
896 fmask_descriptor);
897
898 const struct legacy_surf_level *base_level_info = NULL;
899 if (device->physical_device->rad_info.chip_class <= GFX9) {
900 if (is_stencil)
901 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
902 else
903 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
904 }
905 si_set_mutable_tex_desc_fields(device, image,
906 base_level_info,
907 iview->base_mip,
908 iview->base_mip,
909 blk_w, is_stencil, descriptor);
910 }
911
912 void
913 radv_image_view_init(struct radv_image_view *iview,
914 struct radv_device *device,
915 const VkImageViewCreateInfo* pCreateInfo)
916 {
917 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
918 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
919
920 switch (image->type) {
921 case VK_IMAGE_TYPE_1D:
922 case VK_IMAGE_TYPE_2D:
923 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
924 break;
925 case VK_IMAGE_TYPE_3D:
926 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
927 <= radv_minify(image->info.depth, range->baseMipLevel));
928 break;
929 default:
930 unreachable("bad VkImageType");
931 }
932 iview->image = image;
933 iview->bo = image->bo;
934 iview->type = pCreateInfo->viewType;
935 iview->vk_format = pCreateInfo->format;
936 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
937
938 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
939 iview->vk_format = vk_format_stencil_only(iview->vk_format);
940 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
941 iview->vk_format = vk_format_depth_only(iview->vk_format);
942 }
943
944 iview->extent = (VkExtent3D) {
945 .width = radv_minify(image->info.width , range->baseMipLevel),
946 .height = radv_minify(image->info.height, range->baseMipLevel),
947 .depth = radv_minify(image->info.depth , range->baseMipLevel),
948 };
949
950 if (iview->vk_format != image->vk_format) {
951 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
952 vk_format_get_blockwidth(image->vk_format));
953 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
954 vk_format_get_blockheight(image->vk_format));
955 }
956
957 iview->base_layer = range->baseArrayLayer;
958 iview->layer_count = radv_get_layerCount(image, range);
959 iview->base_mip = range->baseMipLevel;
960 iview->level_count = radv_get_levelCount(image, range);
961
962 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
963 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
964 }
965
966 bool radv_layout_has_htile(const struct radv_image *image,
967 VkImageLayout layout,
968 unsigned queue_mask)
969 {
970 return image->surface.htile_size &&
971 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
972 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
973 queue_mask == (1u << RADV_QUEUE_GENERAL);
974 }
975
976 bool radv_layout_is_htile_compressed(const struct radv_image *image,
977 VkImageLayout layout,
978 unsigned queue_mask)
979 {
980 return image->surface.htile_size &&
981 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
982 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
983 queue_mask == (1u << RADV_QUEUE_GENERAL);
984 }
985
986 bool radv_layout_can_fast_clear(const struct radv_image *image,
987 VkImageLayout layout,
988 unsigned queue_mask)
989 {
990 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
991 queue_mask == (1u << RADV_QUEUE_GENERAL);
992 }
993
994
995 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
996 {
997 if (!image->exclusive)
998 return image->queue_family_mask;
999 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1000 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1001 if (family == VK_QUEUE_FAMILY_IGNORED)
1002 return 1u << queue_family;
1003 return 1u << family;
1004 }
1005
1006 VkResult
1007 radv_CreateImage(VkDevice device,
1008 const VkImageCreateInfo *pCreateInfo,
1009 const VkAllocationCallbacks *pAllocator,
1010 VkImage *pImage)
1011 {
1012 return radv_image_create(device,
1013 &(struct radv_image_create_info) {
1014 .vk_info = pCreateInfo,
1015 .scanout = false,
1016 },
1017 pAllocator,
1018 pImage);
1019 }
1020
1021 void
1022 radv_DestroyImage(VkDevice _device, VkImage _image,
1023 const VkAllocationCallbacks *pAllocator)
1024 {
1025 RADV_FROM_HANDLE(radv_device, device, _device);
1026 RADV_FROM_HANDLE(radv_image, image, _image);
1027
1028 if (!image)
1029 return;
1030
1031 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1032 device->ws->buffer_destroy(image->bo);
1033
1034 vk_free2(&device->alloc, pAllocator, image);
1035 }
1036
1037 void radv_GetImageSubresourceLayout(
1038 VkDevice device,
1039 VkImage _image,
1040 const VkImageSubresource* pSubresource,
1041 VkSubresourceLayout* pLayout)
1042 {
1043 RADV_FROM_HANDLE(radv_image, image, _image);
1044 int level = pSubresource->mipLevel;
1045 int layer = pSubresource->arrayLayer;
1046 struct radeon_surf *surface = &image->surface;
1047
1048 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1049 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1050 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1051 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1052 pLayout->size = surface->u.legacy.level[level].slice_size;
1053 if (image->type == VK_IMAGE_TYPE_3D)
1054 pLayout->size *= u_minify(image->info.depth, level);
1055 }
1056
1057
1058 VkResult
1059 radv_CreateImageView(VkDevice _device,
1060 const VkImageViewCreateInfo *pCreateInfo,
1061 const VkAllocationCallbacks *pAllocator,
1062 VkImageView *pView)
1063 {
1064 RADV_FROM_HANDLE(radv_device, device, _device);
1065 struct radv_image_view *view;
1066
1067 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1068 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1069 if (view == NULL)
1070 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1071
1072 radv_image_view_init(view, device, pCreateInfo);
1073
1074 *pView = radv_image_view_to_handle(view);
1075
1076 return VK_SUCCESS;
1077 }
1078
1079 void
1080 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1081 const VkAllocationCallbacks *pAllocator)
1082 {
1083 RADV_FROM_HANDLE(radv_device, device, _device);
1084 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1085
1086 if (!iview)
1087 return;
1088 vk_free2(&device->alloc, pAllocator, iview);
1089 }
1090
1091 void radv_buffer_view_init(struct radv_buffer_view *view,
1092 struct radv_device *device,
1093 const VkBufferViewCreateInfo* pCreateInfo,
1094 struct radv_cmd_buffer *cmd_buffer)
1095 {
1096 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1097
1098 view->bo = buffer->bo;
1099 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1100 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1101 view->vk_format = pCreateInfo->format;
1102
1103 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1104 pCreateInfo->offset, view->range, view->state);
1105 }
1106
1107 VkResult
1108 radv_CreateBufferView(VkDevice _device,
1109 const VkBufferViewCreateInfo *pCreateInfo,
1110 const VkAllocationCallbacks *pAllocator,
1111 VkBufferView *pView)
1112 {
1113 RADV_FROM_HANDLE(radv_device, device, _device);
1114 struct radv_buffer_view *view;
1115
1116 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1117 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1118 if (!view)
1119 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1120
1121 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1122
1123 *pView = radv_buffer_view_to_handle(view);
1124
1125 return VK_SUCCESS;
1126 }
1127
1128 void
1129 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1130 const VkAllocationCallbacks *pAllocator)
1131 {
1132 RADV_FROM_HANDLE(radv_device, device, _device);
1133 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1134
1135 if (!view)
1136 return;
1137
1138 vk_free2(&device->alloc, pAllocator, view);
1139 }