2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= VI
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< VI
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
124 radv_use_dcc_for_image(struct radv_device
*device
,
125 const struct radv_image_create_info
*create_info
,
126 const VkImageCreateInfo
*pCreateInfo
)
128 bool dcc_compatible_formats
;
130 bool shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
131 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
133 /* DCC (Delta Color Compression) is only available for GFX8+. */
134 if (device
->physical_device
->rad_info
.chip_class
< VI
)
137 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
140 /* FIXME: DCC is broken for shareable images starting with GFX9 */
141 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
145 /* TODO: Enable DCC for storage images. */
146 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
147 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR
))
150 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
153 /* TODO: Enable DCC for mipmaps and array layers. */
154 if (pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1)
157 if (create_info
->scanout
)
160 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
161 * 2x can be enabled with an option.
163 if (pCreateInfo
->samples
> 2 ||
164 (pCreateInfo
->samples
== 2 &&
165 !device
->physical_device
->dcc_msaa_allowed
))
168 /* Determine if the formats are DCC compatible. */
169 dcc_compatible_formats
=
170 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
173 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
174 const struct VkImageFormatListCreateInfoKHR
*format_list
=
175 (const struct VkImageFormatListCreateInfoKHR
*)
176 vk_find_struct_const(pCreateInfo
->pNext
,
177 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
179 /* We have to ignore the existence of the list if viewFormatCount = 0 */
180 if (format_list
&& format_list
->viewFormatCount
) {
181 /* compatibility is transitive, so we only need to check
182 * one format with everything else. */
183 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
184 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
185 format_list
->pViewFormats
[i
]))
186 dcc_compatible_formats
= false;
189 dcc_compatible_formats
= false;
193 if (!dcc_compatible_formats
)
200 radv_init_surface(struct radv_device
*device
,
201 struct radeon_surf
*surface
,
202 const struct radv_image_create_info
*create_info
)
204 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
205 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
206 const struct vk_format_description
*desc
=
207 vk_format_description(pCreateInfo
->format
);
208 bool is_depth
, is_stencil
;
210 is_depth
= vk_format_has_depth(desc
);
211 is_stencil
= vk_format_has_stencil(desc
);
213 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
214 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
216 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
217 /* align byte per element on dword */
218 if (surface
->bpe
== 3) {
221 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
223 switch (pCreateInfo
->imageType
){
224 case VK_IMAGE_TYPE_1D
:
225 if (pCreateInfo
->arrayLayers
> 1)
226 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
228 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
230 case VK_IMAGE_TYPE_2D
:
231 if (pCreateInfo
->arrayLayers
> 1)
232 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
234 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
236 case VK_IMAGE_TYPE_3D
:
237 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
240 unreachable("unhandled image type");
244 surface
->flags
|= RADEON_SURF_ZBUFFER
;
245 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
246 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
250 surface
->flags
|= RADEON_SURF_SBUFFER
;
252 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
254 if (!radv_use_dcc_for_image(device
, create_info
, pCreateInfo
))
255 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
257 if (create_info
->scanout
)
258 surface
->flags
|= RADEON_SURF_SCANOUT
;
262 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
264 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
267 static inline unsigned
268 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
271 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
273 return image
->surface
.u
.legacy
.tiling_index
[level
];
276 static unsigned radv_map_swizzle(unsigned swizzle
)
280 return V_008F0C_SQ_SEL_Y
;
282 return V_008F0C_SQ_SEL_Z
;
284 return V_008F0C_SQ_SEL_W
;
286 return V_008F0C_SQ_SEL_0
;
288 return V_008F0C_SQ_SEL_1
;
289 default: /* VK_SWIZZLE_X */
290 return V_008F0C_SQ_SEL_X
;
295 radv_make_buffer_descriptor(struct radv_device
*device
,
296 struct radv_buffer
*buffer
,
302 const struct vk_format_description
*desc
;
304 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
305 uint64_t va
= gpu_address
+ buffer
->offset
;
306 unsigned num_format
, data_format
;
308 desc
= vk_format_description(vk_format
);
309 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
310 stride
= desc
->block
.bits
/ 8;
312 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
313 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
317 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
318 S_008F04_STRIDE(stride
);
320 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
325 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
326 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
327 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
328 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
329 S_008F0C_NUM_FORMAT(num_format
) |
330 S_008F0C_DATA_FORMAT(data_format
);
334 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
335 struct radv_image
*image
,
336 const struct legacy_surf_level
*base_level_info
,
337 unsigned base_level
, unsigned first_level
,
338 unsigned block_width
, bool is_stencil
,
339 bool is_storage_image
, uint32_t *state
)
341 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
342 uint64_t va
= gpu_address
;
343 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
344 uint64_t meta_va
= 0;
345 if (chip_class
>= GFX9
) {
347 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
349 va
+= image
->surface
.u
.gfx9
.surf_offset
;
351 va
+= base_level_info
->offset
;
354 if (chip_class
>= GFX9
||
355 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
356 state
[0] |= image
->surface
.tile_swizzle
;
357 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
358 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
360 if (chip_class
>= VI
) {
361 state
[6] &= C_008F28_COMPRESSION_EN
;
363 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
364 meta_va
= gpu_address
+ image
->dcc_offset
;
365 if (chip_class
<= VI
)
366 meta_va
+= base_level_info
->dcc_offset
;
367 } else if (!is_storage_image
&&
368 radv_image_is_tc_compat_htile(image
)) {
369 meta_va
= gpu_address
+ image
->htile_offset
;
373 state
[6] |= S_008F28_COMPRESSION_EN(1);
374 state
[7] = meta_va
>> 8;
375 state
[7] |= image
->surface
.tile_swizzle
;
379 if (chip_class
>= GFX9
) {
380 state
[3] &= C_008F1C_SW_MODE
;
381 state
[4] &= C_008F20_PITCH_GFX9
;
384 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
385 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
387 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
388 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
391 state
[5] &= C_008F24_META_DATA_ADDRESS
&
392 C_008F24_META_PIPE_ALIGNED
&
393 C_008F24_META_RB_ALIGNED
;
395 struct gfx9_surf_meta_flags meta
;
397 if (image
->dcc_offset
)
398 meta
= image
->surface
.u
.gfx9
.dcc
;
400 meta
= image
->surface
.u
.gfx9
.htile
;
402 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
403 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
404 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
408 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
409 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
411 state
[3] &= C_008F1C_TILING_INDEX
;
412 state
[3] |= S_008F1C_TILING_INDEX(index
);
413 state
[4] &= C_008F20_PITCH_GFX6
;
414 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
418 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
419 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
421 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
422 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
424 /* GFX9 allocates 1D textures as 2D. */
425 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
426 image_type
= VK_IMAGE_TYPE_2D
;
427 switch (image_type
) {
428 case VK_IMAGE_TYPE_1D
:
429 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
430 case VK_IMAGE_TYPE_2D
:
432 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
434 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
435 case VK_IMAGE_TYPE_3D
:
436 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
437 return V_008F1C_SQ_RSRC_IMG_3D
;
439 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
441 unreachable("illegal image type");
445 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
447 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
449 if (swizzle
[3] == VK_SWIZZLE_X
) {
450 /* For the pre-defined border color values (white, opaque
451 * black, transparent black), the only thing that matters is
452 * that the alpha channel winds up in the correct place
453 * (because the RGB channels are all the same) so either of
454 * these enumerations will work.
456 if (swizzle
[2] == VK_SWIZZLE_Y
)
457 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
459 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
460 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
461 if (swizzle
[1] == VK_SWIZZLE_Y
)
462 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
464 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
465 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
466 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
467 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
468 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
475 * Build the sampler view descriptor for a texture.
478 si_make_texture_descriptor(struct radv_device
*device
,
479 struct radv_image
*image
,
480 bool is_storage_image
,
481 VkImageViewType view_type
,
483 const VkComponentMapping
*mapping
,
484 unsigned first_level
, unsigned last_level
,
485 unsigned first_layer
, unsigned last_layer
,
486 unsigned width
, unsigned height
, unsigned depth
,
488 uint32_t *fmask_state
)
490 const struct vk_format_description
*desc
;
491 enum vk_swizzle swizzle
[4];
493 unsigned num_format
, data_format
, type
;
495 desc
= vk_format_description(vk_format
);
497 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
498 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
499 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
501 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
504 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
506 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
507 if (num_format
== ~0) {
511 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
512 if (data_format
== ~0) {
516 /* S8 with either Z16 or Z32 HTILE need a special format. */
517 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
518 vk_format
== VK_FORMAT_S8_UINT
&&
519 radv_image_is_tc_compat_htile(image
)) {
520 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
521 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
522 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
523 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
525 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
526 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
527 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
529 depth
= image
->info
.array_size
;
530 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
531 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
532 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
533 depth
= image
->info
.array_size
;
534 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
535 depth
= image
->info
.array_size
/ 6;
538 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
539 S_008F14_NUM_FORMAT_GFX6(num_format
));
540 state
[2] = (S_008F18_WIDTH(width
- 1) |
541 S_008F18_HEIGHT(height
- 1) |
542 S_008F18_PERF_MOD(4));
543 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
544 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
545 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
546 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
547 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
549 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
550 util_logbase2(image
->info
.samples
) :
552 S_008F1C_TYPE(type
));
554 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
558 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
559 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
561 /* Depth is the last accessible layer on Gfx9.
562 * The hw doesn't need to know the total number of layers.
564 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
565 state
[4] |= S_008F20_DEPTH(depth
- 1);
567 state
[4] |= S_008F20_DEPTH(last_layer
);
569 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
570 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
571 util_logbase2(image
->info
.samples
) :
572 image
->info
.levels
- 1);
574 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
575 state
[4] |= S_008F20_DEPTH(depth
- 1);
576 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
578 if (image
->dcc_offset
) {
579 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
581 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
583 /* The last dword is unused by hw. The shader uses it to clear
584 * bits in the first dword of sampler state.
586 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
587 if (first_level
== last_level
)
588 state
[7] = C_008F30_MAX_ANISO_RATIO
;
590 state
[7] = 0xffffffff;
594 /* Initialize the sampler view for FMASK. */
595 if (radv_image_has_fmask(image
)) {
596 uint32_t fmask_format
, num_format
;
597 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
600 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
602 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
603 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
604 switch (image
->info
.samples
) {
606 num_format
= V_008F14_IMG_FMASK_8_2_2
;
609 num_format
= V_008F14_IMG_FMASK_8_4_4
;
612 num_format
= V_008F14_IMG_FMASK_32_8_8
;
615 unreachable("invalid nr_samples");
618 switch (image
->info
.samples
) {
620 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
623 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
626 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
630 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
632 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
635 fmask_state
[0] = va
>> 8;
636 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
637 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
638 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
639 S_008F14_NUM_FORMAT_GFX6(num_format
);
640 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
641 S_008F18_HEIGHT(height
- 1);
642 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
643 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
644 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
645 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
646 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
648 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
652 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
653 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
654 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
655 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
656 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
657 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
659 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
660 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
661 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
662 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
664 } else if (fmask_state
)
665 memset(fmask_state
, 0, 8 * 4);
669 radv_query_opaque_metadata(struct radv_device
*device
,
670 struct radv_image
*image
,
671 struct radeon_bo_metadata
*md
)
673 static const VkComponentMapping fixedmapping
;
676 /* Metadata image format format version 1:
677 * [0] = 1 (metadata format identifier)
678 * [1] = (VENDOR_ID << 16) | PCI_ID
679 * [2:9] = image descriptor for the whole resource
680 * [2] is always 0, because the base address is cleared
681 * [9] is the DCC offset bits [39:8] from the beginning of
683 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
685 md
->metadata
[0] = 1; /* metadata image format version 1 */
687 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
688 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
691 si_make_texture_descriptor(device
, image
, false,
692 (VkImageViewType
)image
->type
, image
->vk_format
,
693 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
694 image
->info
.array_size
- 1,
695 image
->info
.width
, image
->info
.height
,
699 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
700 image
->surface
.blk_w
, false, false, desc
);
702 /* Clear the base address and set the relative DCC offset. */
704 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
705 desc
[7] = image
->dcc_offset
>> 8;
707 /* Dwords [2:9] contain the image descriptor. */
708 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
710 /* Dwords [10:..] contain the mipmap level offsets. */
711 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
712 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
713 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
714 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
719 radv_init_metadata(struct radv_device
*device
,
720 struct radv_image
*image
,
721 struct radeon_bo_metadata
*metadata
)
723 struct radeon_surf
*surface
= &image
->surface
;
725 memset(metadata
, 0, sizeof(*metadata
));
727 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
728 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
730 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
731 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
732 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
733 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
734 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
735 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
736 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
737 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
738 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
739 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
740 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
741 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
743 radv_query_opaque_metadata(device
, image
, metadata
);
746 /* The number of samples can be specified independently of the texture. */
748 radv_image_get_fmask_info(struct radv_device
*device
,
749 struct radv_image
*image
,
751 struct radv_fmask_info
*out
)
753 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
754 out
->alignment
= image
->surface
.fmask_alignment
;
755 out
->size
= image
->surface
.fmask_size
;
756 out
->tile_swizzle
= image
->surface
.fmask_tile_swizzle
;
760 out
->slice_tile_max
= image
->surface
.u
.legacy
.fmask
.slice_tile_max
;
761 out
->tile_mode_index
= image
->surface
.u
.legacy
.fmask
.tiling_index
;
762 out
->pitch_in_pixels
= image
->surface
.u
.legacy
.fmask
.pitch_in_pixels
;
763 out
->bank_height
= image
->surface
.u
.legacy
.fmask
.bankh
;
764 out
->tile_swizzle
= image
->surface
.fmask_tile_swizzle
;
765 out
->alignment
= image
->surface
.fmask_alignment
;
766 out
->size
= image
->surface
.fmask_size
;
768 assert(!out
->tile_swizzle
|| !image
->shareable
);
772 radv_image_alloc_fmask(struct radv_device
*device
,
773 struct radv_image
*image
)
775 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
777 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
778 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
779 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
783 radv_image_get_cmask_info(struct radv_device
*device
,
784 struct radv_image
*image
,
785 struct radv_cmask_info
*out
)
787 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
788 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
789 unsigned cl_width
, cl_height
;
791 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
792 out
->alignment
= image
->surface
.cmask_alignment
;
793 out
->size
= image
->surface
.cmask_size
;
810 case 16: /* Hawaii */
819 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
821 unsigned width
= align(image
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
*8);
822 unsigned height
= align(image
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
*8);
823 unsigned slice_elements
= (width
* height
) / (8*8);
825 /* Each element of CMASK is a nibble. */
826 unsigned slice_bytes
= slice_elements
/ 2;
828 out
->slice_tile_max
= (width
* height
) / (128*128);
829 if (out
->slice_tile_max
)
830 out
->slice_tile_max
-= 1;
832 out
->alignment
= MAX2(256, base_align
);
833 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
834 align(slice_bytes
, base_align
);
838 radv_image_alloc_cmask(struct radv_device
*device
,
839 struct radv_image
*image
)
841 uint32_t clear_value_size
= 0;
842 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
844 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
845 /* + 8 for storing the clear values */
846 if (!image
->clear_value_offset
) {
847 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
848 clear_value_size
= 8;
850 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
851 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
855 radv_image_alloc_dcc(struct radv_image
*image
)
857 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
858 /* + 16 for storing the clear values + dcc pred */
859 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
860 image
->fce_pred_offset
= image
->clear_value_offset
+ 8;
861 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
862 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
866 radv_image_alloc_htile(struct radv_image
*image
)
868 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
870 /* + 8 for storing the clear values */
871 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
872 image
->size
= image
->clear_value_offset
+ 8;
873 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
877 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
879 if (image
->info
.samples
<= 1 &&
880 image
->info
.width
* image
->info
.height
<= 512 * 512) {
881 /* Do not enable CMASK or DCC for small surfaces where the cost
882 * of the eliminate pass can be higher than the benefit of fast
883 * clear. RadeonSI does this, but the image threshold is
889 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
890 (image
->exclusive
|| image
->queue_family_mask
== 1);
894 radv_image_can_enable_dcc(struct radv_image
*image
)
896 return radv_image_can_enable_dcc_or_cmask(image
) &&
897 radv_image_has_dcc(image
);
901 radv_image_can_enable_cmask(struct radv_image
*image
)
903 if (image
->surface
.bpe
> 8 && image
->info
.samples
== 1) {
904 /* Do not enable CMASK for non-MSAA images (fast color clear)
905 * because 128 bit formats are not supported, but FMASK might
911 return radv_image_can_enable_dcc_or_cmask(image
) &&
912 image
->info
.levels
== 1 &&
913 image
->info
.depth
== 1 &&
914 !image
->surface
.is_linear
;
918 radv_image_can_enable_fmask(struct radv_image
*image
)
920 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
924 radv_image_can_enable_htile(struct radv_image
*image
)
926 return image
->info
.levels
== 1 &&
927 vk_format_is_depth(image
->vk_format
) &&
928 image
->info
.width
* image
->info
.height
>= 8 * 8;
932 radv_image_create(VkDevice _device
,
933 const struct radv_image_create_info
*create_info
,
934 const VkAllocationCallbacks
* alloc
,
937 RADV_FROM_HANDLE(radv_device
, device
, _device
);
938 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
939 struct radv_image
*image
= NULL
;
940 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
942 radv_assert(pCreateInfo
->mipLevels
> 0);
943 radv_assert(pCreateInfo
->arrayLayers
> 0);
944 radv_assert(pCreateInfo
->samples
> 0);
945 radv_assert(pCreateInfo
->extent
.width
> 0);
946 radv_assert(pCreateInfo
->extent
.height
> 0);
947 radv_assert(pCreateInfo
->extent
.depth
> 0);
949 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
950 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
952 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
954 image
->type
= pCreateInfo
->imageType
;
955 image
->info
.width
= pCreateInfo
->extent
.width
;
956 image
->info
.height
= pCreateInfo
->extent
.height
;
957 image
->info
.depth
= pCreateInfo
->extent
.depth
;
958 image
->info
.samples
= pCreateInfo
->samples
;
959 image
->info
.storage_samples
= pCreateInfo
->samples
;
960 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
961 image
->info
.levels
= pCreateInfo
->mipLevels
;
962 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
964 image
->vk_format
= pCreateInfo
->format
;
965 image
->tiling
= pCreateInfo
->tiling
;
966 image
->usage
= pCreateInfo
->usage
;
967 image
->flags
= pCreateInfo
->flags
;
969 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
970 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
971 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
972 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
973 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
975 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
978 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
979 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
980 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
981 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
984 radv_init_surface(device
, &image
->surface
, create_info
);
986 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
988 image
->size
= image
->surface
.surf_size
;
989 image
->alignment
= image
->surface
.surf_alignment
;
991 if (!create_info
->no_metadata_planes
) {
992 /* Try to enable DCC first. */
993 if (radv_image_can_enable_dcc(image
)) {
994 radv_image_alloc_dcc(image
);
995 if (image
->info
.samples
> 1) {
996 /* CMASK should be enabled because DCC fast
997 * clear with MSAA needs it.
999 assert(radv_image_can_enable_cmask(image
));
1000 radv_image_alloc_cmask(device
, image
);
1003 /* When DCC cannot be enabled, try CMASK. */
1004 image
->surface
.dcc_size
= 0;
1005 if (radv_image_can_enable_cmask(image
)) {
1006 radv_image_alloc_cmask(device
, image
);
1010 /* Try to enable FMASK for multisampled images. */
1011 if (radv_image_can_enable_fmask(image
)) {
1012 radv_image_alloc_fmask(device
, image
);
1014 /* Otherwise, try to enable HTILE for depth surfaces. */
1015 if (radv_image_can_enable_htile(image
) &&
1016 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1017 radv_image_alloc_htile(image
);
1018 image
->tc_compatible_htile
= image
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1020 image
->surface
.htile_size
= 0;
1024 image
->surface
.dcc_size
= 0;
1025 image
->surface
.htile_size
= 0;
1028 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1029 image
->alignment
= MAX2(image
->alignment
, 4096);
1030 image
->size
= align64(image
->size
, image
->alignment
);
1033 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1034 0, RADEON_FLAG_VIRTUAL
);
1036 vk_free2(&device
->alloc
, alloc
, image
);
1037 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1041 *pImage
= radv_image_to_handle(image
);
1047 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1048 struct radv_device
*device
,
1049 const VkComponentMapping
*components
,
1050 bool is_storage_image
)
1052 struct radv_image
*image
= iview
->image
;
1053 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1055 uint32_t *descriptor
;
1056 uint32_t hw_level
= 0;
1058 if (is_storage_image
) {
1059 descriptor
= iview
->storage_descriptor
;
1061 descriptor
= iview
->descriptor
;
1064 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
1065 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
1067 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1068 hw_level
= iview
->base_mip
;
1069 si_make_texture_descriptor(device
, image
, is_storage_image
,
1073 hw_level
, hw_level
+ iview
->level_count
- 1,
1075 iview
->base_layer
+ iview
->layer_count
- 1,
1076 iview
->extent
.width
,
1077 iview
->extent
.height
,
1078 iview
->extent
.depth
,
1082 const struct legacy_surf_level
*base_level_info
= NULL
;
1083 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1085 base_level_info
= &image
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1087 base_level_info
= &image
->surface
.u
.legacy
.level
[iview
->base_mip
];
1089 si_set_mutable_tex_desc_fields(device
, image
,
1093 blk_w
, is_stencil
, is_storage_image
, descriptor
);
1097 radv_image_view_init(struct radv_image_view
*iview
,
1098 struct radv_device
*device
,
1099 const VkImageViewCreateInfo
* pCreateInfo
)
1101 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1102 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1104 switch (image
->type
) {
1105 case VK_IMAGE_TYPE_1D
:
1106 case VK_IMAGE_TYPE_2D
:
1107 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1109 case VK_IMAGE_TYPE_3D
:
1110 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1111 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1114 unreachable("bad VkImageType");
1116 iview
->image
= image
;
1117 iview
->bo
= image
->bo
;
1118 iview
->type
= pCreateInfo
->viewType
;
1119 iview
->vk_format
= pCreateInfo
->format
;
1120 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1122 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1123 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1124 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1125 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1128 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1129 iview
->extent
= (VkExtent3D
) {
1130 .width
= image
->info
.width
,
1131 .height
= image
->info
.height
,
1132 .depth
= image
->info
.depth
,
1135 iview
->extent
= (VkExtent3D
) {
1136 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1137 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1138 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1142 if (iview
->vk_format
!= image
->vk_format
) {
1143 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1144 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1145 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1146 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1148 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1149 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1151 /* Comment ported from amdvlk -
1152 * If we have the following image:
1153 * Uncompressed pixels Compressed block sizes (4x4)
1154 * mip0: 22 x 22 6 x 6
1155 * mip1: 11 x 11 3 x 3
1160 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1161 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1162 * divide-by-two integer math):
1168 * This means that mip2 will be missing texels.
1170 * Fix this by calculating the base mip's width and height, then convert that, and round it
1171 * back up to get the level 0 size.
1172 * Clamp the converted size between the original values, and next power of two, which
1173 * means we don't oversize the image.
1175 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1176 vk_format_is_compressed(image
->vk_format
) &&
1177 !vk_format_is_compressed(iview
->vk_format
)) {
1178 unsigned rounded_img_w
= util_next_power_of_two(iview
->extent
.width
);
1179 unsigned rounded_img_h
= util_next_power_of_two(iview
->extent
.height
);
1180 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1181 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1183 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1184 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1186 lvl_width
<<= range
->baseMipLevel
;
1187 lvl_height
<<= range
->baseMipLevel
;
1189 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, rounded_img_w
);
1190 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, rounded_img_h
);
1194 iview
->base_layer
= range
->baseArrayLayer
;
1195 iview
->layer_count
= radv_get_layerCount(image
, range
);
1196 iview
->base_mip
= range
->baseMipLevel
;
1197 iview
->level_count
= radv_get_levelCount(image
, range
);
1199 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, false);
1200 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, true);
1203 bool radv_layout_has_htile(const struct radv_image
*image
,
1204 VkImageLayout layout
,
1205 unsigned queue_mask
)
1207 if (radv_image_is_tc_compat_htile(image
))
1208 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1210 return radv_image_has_htile(image
) &&
1211 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1212 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1213 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1216 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1217 VkImageLayout layout
,
1218 unsigned queue_mask
)
1220 if (radv_image_is_tc_compat_htile(image
))
1221 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1223 return radv_image_has_htile(image
) &&
1224 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1225 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
1226 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1229 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1230 VkImageLayout layout
,
1231 unsigned queue_mask
)
1233 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
1234 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1237 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1238 VkImageLayout layout
,
1239 unsigned queue_mask
)
1241 /* Don't compress compute transfer dst, as image stores are not supported. */
1242 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1243 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1246 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1250 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1252 if (!image
->exclusive
)
1253 return image
->queue_family_mask
;
1254 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
1255 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1256 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1257 return 1u << queue_family
;
1258 return 1u << family
;
1262 radv_CreateImage(VkDevice device
,
1263 const VkImageCreateInfo
*pCreateInfo
,
1264 const VkAllocationCallbacks
*pAllocator
,
1268 const VkNativeBufferANDROID
*gralloc_info
=
1269 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1272 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1273 pAllocator
, pImage
);
1276 const struct wsi_image_create_info
*wsi_info
=
1277 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1278 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1280 return radv_image_create(device
,
1281 &(struct radv_image_create_info
) {
1282 .vk_info
= pCreateInfo
,
1290 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1291 const VkAllocationCallbacks
*pAllocator
)
1293 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1294 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1299 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1300 device
->ws
->buffer_destroy(image
->bo
);
1302 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1303 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1305 vk_free2(&device
->alloc
, pAllocator
, image
);
1308 void radv_GetImageSubresourceLayout(
1311 const VkImageSubresource
* pSubresource
,
1312 VkSubresourceLayout
* pLayout
)
1314 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1315 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1316 int level
= pSubresource
->mipLevel
;
1317 int layer
= pSubresource
->arrayLayer
;
1318 struct radeon_surf
*surface
= &image
->surface
;
1320 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1321 pLayout
->offset
= surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1322 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1323 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1324 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1325 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1326 if (image
->type
== VK_IMAGE_TYPE_3D
)
1327 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1329 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1330 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1331 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1332 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1333 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1334 if (image
->type
== VK_IMAGE_TYPE_3D
)
1335 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1341 radv_CreateImageView(VkDevice _device
,
1342 const VkImageViewCreateInfo
*pCreateInfo
,
1343 const VkAllocationCallbacks
*pAllocator
,
1346 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1347 struct radv_image_view
*view
;
1349 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1350 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1352 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1354 radv_image_view_init(view
, device
, pCreateInfo
);
1356 *pView
= radv_image_view_to_handle(view
);
1362 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1363 const VkAllocationCallbacks
*pAllocator
)
1365 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1366 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1370 vk_free2(&device
->alloc
, pAllocator
, iview
);
1373 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1374 struct radv_device
*device
,
1375 const VkBufferViewCreateInfo
* pCreateInfo
)
1377 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1379 view
->bo
= buffer
->bo
;
1380 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1381 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1382 view
->vk_format
= pCreateInfo
->format
;
1384 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1385 pCreateInfo
->offset
, view
->range
, view
->state
);
1389 radv_CreateBufferView(VkDevice _device
,
1390 const VkBufferViewCreateInfo
*pCreateInfo
,
1391 const VkAllocationCallbacks
*pAllocator
,
1392 VkBufferView
*pView
)
1394 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1395 struct radv_buffer_view
*view
;
1397 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1398 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1400 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1402 radv_buffer_view_init(view
, device
, pCreateInfo
);
1404 *pView
= radv_buffer_view_to_handle(view
);
1410 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1411 const VkAllocationCallbacks
*pAllocator
)
1413 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1414 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1419 vk_free2(&device
->alloc
, pAllocator
, view
);