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radv: add some misc gfx9 pieces.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "util/debug.h"
34 static unsigned
35 radv_choose_tiling(struct radv_device *Device,
36 const struct radv_image_create_info *create_info)
37 {
38 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
39
40 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
41 assert(pCreateInfo->samples <= 1);
42 return RADEON_SURF_MODE_LINEAR_ALIGNED;
43 }
44
45 /* Textures with a very small height are recommended to be linear. */
46 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
47 /* Only very thin and long 2D textures should benefit from
48 * linear_aligned. */
49 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
50 return RADEON_SURF_MODE_LINEAR_ALIGNED;
51
52 /* MSAA resources must be 2D tiled. */
53 if (pCreateInfo->samples > 1)
54 return RADEON_SURF_MODE_2D;
55
56 return RADEON_SURF_MODE_2D;
57 }
58 static int
59 radv_init_surface(struct radv_device *device,
60 struct radeon_surf *surface,
61 const struct radv_image_create_info *create_info)
62 {
63 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
64 unsigned array_mode = radv_choose_tiling(device, create_info);
65 const struct vk_format_description *desc =
66 vk_format_description(pCreateInfo->format);
67 bool is_depth, is_stencil, blendable;
68
69 is_depth = vk_format_has_depth(desc);
70 is_stencil = vk_format_has_stencil(desc);
71
72 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
73 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
74
75 surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
76 /* align byte per element on dword */
77 if (surface->bpe == 3) {
78 surface->bpe = 4;
79 }
80 surface->flags = RADEON_SURF_SET(array_mode, MODE);
81
82 switch (pCreateInfo->imageType){
83 case VK_IMAGE_TYPE_1D:
84 if (pCreateInfo->arrayLayers > 1)
85 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
86 else
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
88 break;
89 case VK_IMAGE_TYPE_2D:
90 if (pCreateInfo->arrayLayers > 1)
91 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
92 else
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
94 break;
95 case VK_IMAGE_TYPE_3D:
96 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
97 break;
98 default:
99 unreachable("unhandled image type");
100 }
101
102 if (is_depth) {
103 surface->flags |= RADEON_SURF_ZBUFFER;
104 }
105
106 if (is_stencil)
107 surface->flags |= RADEON_SURF_SBUFFER;
108
109 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
110
111 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
112 VK_IMAGE_USAGE_STORAGE_BIT)) ||
113 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
114 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
115 device->physical_device->rad_info.chip_class < VI ||
116 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
117 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
118 surface->flags |= RADEON_SURF_DISABLE_DCC;
119 if (create_info->scanout)
120 surface->flags |= RADEON_SURF_SCANOUT;
121 return 0;
122 }
123 #define ATI_VENDOR_ID 0x1002
124 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
125 {
126 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
127 }
128
129 static inline unsigned
130 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
131 {
132 if (stencil)
133 return image->surface.u.legacy.stencil_tiling_index[level];
134 else
135 return image->surface.u.legacy.tiling_index[level];
136 }
137
138 static unsigned radv_map_swizzle(unsigned swizzle)
139 {
140 switch (swizzle) {
141 case VK_SWIZZLE_Y:
142 return V_008F0C_SQ_SEL_Y;
143 case VK_SWIZZLE_Z:
144 return V_008F0C_SQ_SEL_Z;
145 case VK_SWIZZLE_W:
146 return V_008F0C_SQ_SEL_W;
147 case VK_SWIZZLE_0:
148 return V_008F0C_SQ_SEL_0;
149 case VK_SWIZZLE_1:
150 return V_008F0C_SQ_SEL_1;
151 default: /* VK_SWIZZLE_X */
152 return V_008F0C_SQ_SEL_X;
153 }
154 }
155
156 static void
157 radv_make_buffer_descriptor(struct radv_device *device,
158 struct radv_buffer *buffer,
159 VkFormat vk_format,
160 unsigned offset,
161 unsigned range,
162 uint32_t *state)
163 {
164 const struct vk_format_description *desc;
165 unsigned stride;
166 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
167 uint64_t va = gpu_address + buffer->offset;
168 unsigned num_format, data_format;
169 int first_non_void;
170 desc = vk_format_description(vk_format);
171 first_non_void = vk_format_get_first_non_void_channel(vk_format);
172 stride = desc->block.bits / 8;
173
174 num_format = radv_translate_buffer_numformat(desc, first_non_void);
175 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
176
177 va += offset;
178 state[0] = va;
179 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
180 S_008F04_STRIDE(stride);
181 state[2] = range;
182 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
183 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
184 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
185 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
186 S_008F0C_NUM_FORMAT(num_format) |
187 S_008F0C_DATA_FORMAT(data_format);
188 }
189
190 static void
191 si_set_mutable_tex_desc_fields(struct radv_device *device,
192 struct radv_image *image,
193 const struct legacy_surf_level *base_level_info,
194 unsigned base_level, unsigned first_level,
195 unsigned block_width, bool is_stencil,
196 uint32_t *state)
197 {
198 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
199 uint64_t va = gpu_address + base_level_info->offset;
200 unsigned pitch = base_level_info->nblk_x * block_width;
201
202 state[1] &= C_008F14_BASE_ADDRESS_HI;
203 state[3] &= C_008F1C_TILING_INDEX;
204 state[4] &= C_008F20_PITCH_GFX6;
205 state[6] &= C_008F28_COMPRESSION_EN;
206
207 assert(!(va & 255));
208
209 state[0] = va >> 8;
210 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
211 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
212 is_stencil));
213 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
214
215 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
216 state[6] |= S_008F28_COMPRESSION_EN(1);
217 state[7] = (gpu_address +
218 image->dcc_offset +
219 base_level_info->dcc_offset) >> 8;
220 }
221 }
222
223 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
224 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
225 {
226 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
227 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
228 switch (image_type) {
229 case VK_IMAGE_TYPE_1D:
230 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
231 case VK_IMAGE_TYPE_2D:
232 if (nr_samples > 1)
233 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
234 else
235 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
236 case VK_IMAGE_TYPE_3D:
237 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
238 return V_008F1C_SQ_RSRC_IMG_3D;
239 else
240 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
241 default:
242 unreachable("illegale image type");
243 }
244 }
245 /**
246 * Build the sampler view descriptor for a texture.
247 */
248 static void
249 si_make_texture_descriptor(struct radv_device *device,
250 struct radv_image *image,
251 bool sampler,
252 VkImageViewType view_type,
253 VkFormat vk_format,
254 const VkComponentMapping *mapping,
255 unsigned first_level, unsigned last_level,
256 unsigned first_layer, unsigned last_layer,
257 unsigned width, unsigned height, unsigned depth,
258 uint32_t *state,
259 uint32_t *fmask_state)
260 {
261 const struct vk_format_description *desc;
262 enum vk_swizzle swizzle[4];
263 int first_non_void;
264 unsigned num_format, data_format, type;
265
266 desc = vk_format_description(vk_format);
267
268 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
269 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
270 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
271 } else {
272 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
273 }
274
275 first_non_void = vk_format_get_first_non_void_channel(vk_format);
276
277 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
278 if (num_format == ~0) {
279 num_format = 0;
280 }
281
282 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
283 if (data_format == ~0) {
284 data_format = 0;
285 }
286
287 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
288 (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
289 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
290 height = 1;
291 depth = image->info.array_size;
292 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
293 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
294 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
295 depth = image->info.array_size;
296 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
297 depth = image->info.array_size / 6;
298
299 state[0] = 0;
300 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
301 S_008F14_NUM_FORMAT_GFX6(num_format));
302 state[2] = (S_008F18_WIDTH(width - 1) |
303 S_008F18_HEIGHT(height - 1) |
304 S_008F18_PERF_MOD(4));
305 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
306 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
307 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
308 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
309 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
310 0 : first_level) |
311 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
312 util_logbase2(image->info.samples) :
313 last_level) |
314 S_008F1C_TYPE(type));
315 state[4] = 0;
316 state[5] = S_008F24_BASE_ARRAY(first_layer);
317
318 state[6] = 0;
319 state[7] = 0;
320
321 {
322 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
323 state[4] |= S_008F20_DEPTH(depth - 1);
324 state[5] |= S_008F24_LAST_ARRAY(last_layer);
325 }
326 if (image->dcc_offset) {
327 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
328
329 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
330 } else {
331 /* The last dword is unused by hw. The shader uses it to clear
332 * bits in the first dword of sampler state.
333 */
334 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
335 if (first_level == last_level)
336 state[7] = C_008F30_MAX_ANISO_RATIO;
337 else
338 state[7] = 0xffffffff;
339 }
340 }
341
342 /* Initialize the sampler view for FMASK. */
343 if (image->fmask.size) {
344 uint32_t fmask_format;
345 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
346 uint64_t va;
347
348 va = gpu_address + image->offset + image->fmask.offset;
349
350 switch (image->info.samples) {
351 case 2:
352 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
353 break;
354 case 4:
355 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
356 break;
357 case 8:
358 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
359 break;
360 default:
361 assert(0);
362 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
363 }
364
365 fmask_state[0] = va >> 8;
366 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
367 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
368 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_UINT);
369 fmask_state[2] = S_008F18_WIDTH(width - 1) |
370 S_008F18_HEIGHT(height - 1);
371 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
372 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
373 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
374 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
375 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
376 fmask_state[4] = 0;
377 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
378 fmask_state[6] = 0;
379 fmask_state[7] = 0;
380
381 {
382 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
383 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
384 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
385 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
386 }
387 }
388 }
389
390 static void
391 radv_query_opaque_metadata(struct radv_device *device,
392 struct radv_image *image,
393 struct radeon_bo_metadata *md)
394 {
395 static const VkComponentMapping fixedmapping;
396 uint32_t desc[8], i;
397
398 /* Metadata image format format version 1:
399 * [0] = 1 (metadata format identifier)
400 * [1] = (VENDOR_ID << 16) | PCI_ID
401 * [2:9] = image descriptor for the whole resource
402 * [2] is always 0, because the base address is cleared
403 * [9] is the DCC offset bits [39:8] from the beginning of
404 * the buffer
405 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
406 */
407 md->metadata[0] = 1; /* metadata image format version 1 */
408
409 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
410 md->metadata[1] = si_get_bo_metadata_word1(device);
411
412
413 si_make_texture_descriptor(device, image, true,
414 (VkImageViewType)image->type, image->vk_format,
415 &fixedmapping, 0, image->info.levels - 1, 0,
416 image->info.array_size,
417 image->info.width, image->info.height,
418 image->info.depth,
419 desc, NULL);
420
421 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
422 image->surface.blk_w, false, desc);
423
424 /* Clear the base address and set the relative DCC offset. */
425 desc[0] = 0;
426 desc[1] &= C_008F14_BASE_ADDRESS_HI;
427 desc[7] = image->dcc_offset >> 8;
428
429 /* Dwords [2:9] contain the image descriptor. */
430 memcpy(&md->metadata[2], desc, sizeof(desc));
431
432 /* Dwords [10:..] contain the mipmap level offsets. */
433 for (i = 0; i <= image->info.levels - 1; i++)
434 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
435
436 md->size_metadata = (11 + image->info.levels - 1) * 4;
437 }
438
439 void
440 radv_init_metadata(struct radv_device *device,
441 struct radv_image *image,
442 struct radeon_bo_metadata *metadata)
443 {
444 struct radeon_surf *surface = &image->surface;
445
446 memset(metadata, 0, sizeof(*metadata));
447
448 if (device->physical_device->rad_info.chip_class >= GFX9) {
449 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
450 } else {
451 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
452 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
453 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
454 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
455 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
456 metadata->u.legacy.bankw = surface->u.legacy.bankw;
457 metadata->u.legacy.bankh = surface->u.legacy.bankh;
458 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
459 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
460 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
461 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
462 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
463 }
464 radv_query_opaque_metadata(device, image, metadata);
465 }
466
467 /* The number of samples can be specified independently of the texture. */
468 static void
469 radv_image_get_fmask_info(struct radv_device *device,
470 struct radv_image *image,
471 unsigned nr_samples,
472 struct radv_fmask_info *out)
473 {
474 /* FMASK is allocated like an ordinary texture. */
475 struct radeon_surf fmask = {};
476 struct ac_surf_info info = image->info;
477 memset(out, 0, sizeof(*out));
478
479 fmask.blk_w = image->surface.blk_w;
480 fmask.blk_h = image->surface.blk_h;
481 info.samples = 1;
482 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
483
484 /* Force 2D tiling if it wasn't set. This may occur when creating
485 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
486 * destination buffer must have an FMASK too. */
487 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
488 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
489
490 switch (nr_samples) {
491 case 2:
492 case 4:
493 fmask.bpe = 1;
494 break;
495 case 8:
496 fmask.bpe = 4;
497 break;
498 default:
499 return;
500 }
501
502 device->ws->surface_init(device->ws, &info, &fmask);
503 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
504
505 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
506 if (out->slice_tile_max)
507 out->slice_tile_max -= 1;
508
509 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
510 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
511 out->bank_height = fmask.u.legacy.bankh;
512 out->alignment = MAX2(256, fmask.surf_alignment);
513 out->size = fmask.surf_size;
514 }
515
516 static void
517 radv_image_alloc_fmask(struct radv_device *device,
518 struct radv_image *image)
519 {
520 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
521
522 image->fmask.offset = align64(image->size, image->fmask.alignment);
523 image->size = image->fmask.offset + image->fmask.size;
524 image->alignment = MAX2(image->alignment, image->fmask.alignment);
525 }
526
527 static void
528 radv_image_get_cmask_info(struct radv_device *device,
529 struct radv_image *image,
530 struct radv_cmask_info *out)
531 {
532 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
533 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
534 unsigned cl_width, cl_height;
535
536 switch (num_pipes) {
537 case 2:
538 cl_width = 32;
539 cl_height = 16;
540 break;
541 case 4:
542 cl_width = 32;
543 cl_height = 32;
544 break;
545 case 8:
546 cl_width = 64;
547 cl_height = 32;
548 break;
549 case 16: /* Hawaii */
550 cl_width = 64;
551 cl_height = 64;
552 break;
553 default:
554 assert(0);
555 return;
556 }
557
558 unsigned base_align = num_pipes * pipe_interleave_bytes;
559
560 unsigned width = align(image->info.width, cl_width*8);
561 unsigned height = align(image->info.height, cl_height*8);
562 unsigned slice_elements = (width * height) / (8*8);
563
564 /* Each element of CMASK is a nibble. */
565 unsigned slice_bytes = slice_elements / 2;
566
567 out->slice_tile_max = (width * height) / (128*128);
568 if (out->slice_tile_max)
569 out->slice_tile_max -= 1;
570
571 out->alignment = MAX2(256, base_align);
572 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
573 align(slice_bytes, base_align);
574 }
575
576 static void
577 radv_image_alloc_cmask(struct radv_device *device,
578 struct radv_image *image)
579 {
580 radv_image_get_cmask_info(device, image, &image->cmask);
581
582 image->cmask.offset = align64(image->size, image->cmask.alignment);
583 /* + 8 for storing the clear values */
584 image->clear_value_offset = image->cmask.offset + image->cmask.size;
585 image->size = image->cmask.offset + image->cmask.size + 8;
586 image->alignment = MAX2(image->alignment, image->cmask.alignment);
587 }
588
589 static void
590 radv_image_alloc_dcc(struct radv_device *device,
591 struct radv_image *image)
592 {
593 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
594 /* + 8 for storing the clear values */
595 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
596 image->size = image->dcc_offset + image->surface.dcc_size + 8;
597 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
598 }
599
600 static void
601 radv_image_alloc_htile(struct radv_device *device,
602 struct radv_image *image)
603 {
604 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
605 image->surface.htile_size = 0;
606 return;
607 }
608
609 image->htile_offset = align64(image->size, image->surface.htile_alignment);
610
611 /* + 8 for storing the clear values */
612 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
613 image->size = image->clear_value_offset + 8;
614 image->alignment = align64(image->alignment, image->surface.htile_alignment);
615 }
616
617 VkResult
618 radv_image_create(VkDevice _device,
619 const struct radv_image_create_info *create_info,
620 const VkAllocationCallbacks* alloc,
621 VkImage *pImage)
622 {
623 RADV_FROM_HANDLE(radv_device, device, _device);
624 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
625 struct radv_image *image = NULL;
626 bool can_cmask_dcc = false;
627 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
628
629 radv_assert(pCreateInfo->mipLevels > 0);
630 radv_assert(pCreateInfo->arrayLayers > 0);
631 radv_assert(pCreateInfo->samples > 0);
632 radv_assert(pCreateInfo->extent.width > 0);
633 radv_assert(pCreateInfo->extent.height > 0);
634 radv_assert(pCreateInfo->extent.depth > 0);
635
636 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
637 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
638 if (!image)
639 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
640
641 memset(image, 0, sizeof(*image));
642 image->type = pCreateInfo->imageType;
643 image->info.width = pCreateInfo->extent.width;
644 image->info.height = pCreateInfo->extent.height;
645 image->info.depth = pCreateInfo->extent.depth;
646 image->info.samples = pCreateInfo->samples;
647 image->info.array_size = pCreateInfo->arrayLayers;
648 image->info.levels = pCreateInfo->mipLevels;
649
650 image->vk_format = pCreateInfo->format;
651 image->tiling = pCreateInfo->tiling;
652 image->usage = pCreateInfo->usage;
653 image->flags = pCreateInfo->flags;
654
655 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
656 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
657 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
658 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHX)
659 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
660 else
661 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
662 }
663
664 radv_init_surface(device, &image->surface, create_info);
665
666 device->ws->surface_init(device->ws, &image->info, &image->surface);
667
668 image->size = image->surface.surf_size;
669 image->alignment = image->surface.surf_alignment;
670
671 if (image->exclusive || image->queue_family_mask == 1)
672 can_cmask_dcc = true;
673
674 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
675 image->surface.dcc_size && can_cmask_dcc)
676 radv_image_alloc_dcc(device, image);
677 else
678 image->surface.dcc_size = 0;
679
680 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
681 pCreateInfo->mipLevels == 1 &&
682 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
683 radv_image_alloc_cmask(device, image);
684 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
685 radv_image_alloc_fmask(device, image);
686 } else if (vk_format_is_depth(pCreateInfo->format)) {
687
688 radv_image_alloc_htile(device, image);
689 }
690
691 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
692 image->alignment = MAX2(image->alignment, 4096);
693 image->size = align64(image->size, image->alignment);
694 image->offset = 0;
695
696 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
697 0, RADEON_FLAG_VIRTUAL);
698 if (!image->bo) {
699 vk_free2(&device->alloc, alloc, image);
700 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
701 }
702 }
703
704 *pImage = radv_image_to_handle(image);
705
706 return VK_SUCCESS;
707 }
708
709 void
710 radv_image_view_init(struct radv_image_view *iview,
711 struct radv_device *device,
712 const VkImageViewCreateInfo* pCreateInfo,
713 struct radv_cmd_buffer *cmd_buffer,
714 VkImageUsageFlags usage_mask)
715 {
716 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
717 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
718 uint32_t blk_w;
719 bool is_stencil = false;
720 switch (image->type) {
721 case VK_IMAGE_TYPE_1D:
722 case VK_IMAGE_TYPE_2D:
723 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
724 break;
725 case VK_IMAGE_TYPE_3D:
726 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
727 <= radv_minify(image->info.depth, range->baseMipLevel));
728 break;
729 default:
730 unreachable("bad VkImageType");
731 }
732 iview->image = image;
733 iview->bo = image->bo;
734 iview->type = pCreateInfo->viewType;
735 iview->vk_format = pCreateInfo->format;
736 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
737
738 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
739 is_stencil = true;
740 iview->vk_format = vk_format_stencil_only(iview->vk_format);
741 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
742 iview->vk_format = vk_format_depth_only(iview->vk_format);
743 }
744
745 iview->extent = (VkExtent3D) {
746 .width = radv_minify(image->info.width , range->baseMipLevel),
747 .height = radv_minify(image->info.height, range->baseMipLevel),
748 .depth = radv_minify(image->info.depth , range->baseMipLevel),
749 };
750
751 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
752 vk_format_get_blockwidth(image->vk_format));
753 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
754 vk_format_get_blockheight(image->vk_format));
755
756 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
757 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
758 iview->base_layer = range->baseArrayLayer;
759 iview->layer_count = radv_get_layerCount(image, range);
760 iview->base_mip = range->baseMipLevel;
761
762 si_make_texture_descriptor(device, image, false,
763 iview->type,
764 iview->vk_format,
765 &pCreateInfo->components,
766 0, radv_get_levelCount(image, range) - 1,
767 range->baseArrayLayer,
768 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
769 iview->extent.width,
770 iview->extent.height,
771 iview->extent.depth,
772 iview->descriptor,
773 iview->fmask_descriptor);
774 si_set_mutable_tex_desc_fields(device, image,
775 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
776 : &image->surface.u.legacy.level[range->baseMipLevel],
777 range->baseMipLevel,
778 range->baseMipLevel,
779 blk_w, is_stencil, iview->descriptor);
780 }
781
782 bool radv_layout_has_htile(const struct radv_image *image,
783 VkImageLayout layout,
784 unsigned queue_mask)
785 {
786 return image->surface.htile_size &&
787 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
788 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
789 queue_mask == (1u << RADV_QUEUE_GENERAL);
790 }
791
792 bool radv_layout_is_htile_compressed(const struct radv_image *image,
793 VkImageLayout layout,
794 unsigned queue_mask)
795 {
796 return image->surface.htile_size &&
797 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
798 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
799 queue_mask == (1u << RADV_QUEUE_GENERAL);
800 }
801
802 bool radv_layout_can_fast_clear(const struct radv_image *image,
803 VkImageLayout layout,
804 unsigned queue_mask)
805 {
806 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
807 queue_mask == (1u << RADV_QUEUE_GENERAL);
808 }
809
810
811 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
812 {
813 if (!image->exclusive)
814 return image->queue_family_mask;
815 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHX)
816 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
817 if (family == VK_QUEUE_FAMILY_IGNORED)
818 return 1u << queue_family;
819 return 1u << family;
820 }
821
822 VkResult
823 radv_CreateImage(VkDevice device,
824 const VkImageCreateInfo *pCreateInfo,
825 const VkAllocationCallbacks *pAllocator,
826 VkImage *pImage)
827 {
828 return radv_image_create(device,
829 &(struct radv_image_create_info) {
830 .vk_info = pCreateInfo,
831 .scanout = false,
832 },
833 pAllocator,
834 pImage);
835 }
836
837 void
838 radv_DestroyImage(VkDevice _device, VkImage _image,
839 const VkAllocationCallbacks *pAllocator)
840 {
841 RADV_FROM_HANDLE(radv_device, device, _device);
842 RADV_FROM_HANDLE(radv_image, image, _image);
843
844 if (!image)
845 return;
846
847 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
848 device->ws->buffer_destroy(image->bo);
849
850 vk_free2(&device->alloc, pAllocator, image);
851 }
852
853 void radv_GetImageSubresourceLayout(
854 VkDevice device,
855 VkImage _image,
856 const VkImageSubresource* pSubresource,
857 VkSubresourceLayout* pLayout)
858 {
859 RADV_FROM_HANDLE(radv_image, image, _image);
860 int level = pSubresource->mipLevel;
861 int layer = pSubresource->arrayLayer;
862 struct radeon_surf *surface = &image->surface;
863
864 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
865 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
866 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
867 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
868 pLayout->size = surface->u.legacy.level[level].slice_size;
869 if (image->type == VK_IMAGE_TYPE_3D)
870 pLayout->size *= u_minify(image->info.depth, level);
871 }
872
873
874 VkResult
875 radv_CreateImageView(VkDevice _device,
876 const VkImageViewCreateInfo *pCreateInfo,
877 const VkAllocationCallbacks *pAllocator,
878 VkImageView *pView)
879 {
880 RADV_FROM_HANDLE(radv_device, device, _device);
881 struct radv_image_view *view;
882
883 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
884 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
885 if (view == NULL)
886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
887
888 radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
889
890 *pView = radv_image_view_to_handle(view);
891
892 return VK_SUCCESS;
893 }
894
895 void
896 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
897 const VkAllocationCallbacks *pAllocator)
898 {
899 RADV_FROM_HANDLE(radv_device, device, _device);
900 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
901
902 if (!iview)
903 return;
904 vk_free2(&device->alloc, pAllocator, iview);
905 }
906
907 void radv_buffer_view_init(struct radv_buffer_view *view,
908 struct radv_device *device,
909 const VkBufferViewCreateInfo* pCreateInfo,
910 struct radv_cmd_buffer *cmd_buffer)
911 {
912 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
913
914 view->bo = buffer->bo;
915 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
916 buffer->size - pCreateInfo->offset : pCreateInfo->range;
917 view->vk_format = pCreateInfo->format;
918
919 radv_make_buffer_descriptor(device, buffer, view->vk_format,
920 pCreateInfo->offset, view->range, view->state);
921 }
922
923 VkResult
924 radv_CreateBufferView(VkDevice _device,
925 const VkBufferViewCreateInfo *pCreateInfo,
926 const VkAllocationCallbacks *pAllocator,
927 VkBufferView *pView)
928 {
929 RADV_FROM_HANDLE(radv_device, device, _device);
930 struct radv_buffer_view *view;
931
932 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
933 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
934 if (!view)
935 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
936
937 radv_buffer_view_init(view, device, pCreateInfo, NULL);
938
939 *pView = radv_buffer_view_to_handle(view);
940
941 return VK_SUCCESS;
942 }
943
944 void
945 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
946 const VkAllocationCallbacks *pAllocator)
947 {
948 RADV_FROM_HANDLE(radv_device, device, _device);
949 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
950
951 if (!view)
952 return;
953
954 vk_free2(&device->alloc, pAllocator, view);
955 }