2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "vk_format.h"
31 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
37 radv_choose_tiling(struct radv_device
*Device
,
38 const struct radv_image_create_info
*create_info
)
40 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
42 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
43 assert(pCreateInfo
->samples
<= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
47 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
48 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)) {
49 /* Textures with a very small height are recommended to be linear. */
50 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
51 /* Only very thin and long 2D textures should benefit from
53 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
54 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
58 /* MSAA resources must be 2D tiled. */
59 if (pCreateInfo
->samples
> 1)
60 return RADEON_SURF_MODE_2D
;
62 return RADEON_SURF_MODE_2D
;
65 radv_init_surface(struct radv_device
*device
,
66 struct radeon_surf
*surface
,
67 const struct radv_image_create_info
*create_info
)
69 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
70 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
71 const struct vk_format_description
*desc
=
72 vk_format_description(pCreateInfo
->format
);
73 bool is_depth
, is_stencil
, blendable
;
75 is_depth
= vk_format_has_depth(desc
);
76 is_stencil
= vk_format_has_stencil(desc
);
78 surface
->blk_w
= vk_format_get_blockwidth(pCreateInfo
->format
);
79 surface
->blk_h
= vk_format_get_blockheight(pCreateInfo
->format
);
81 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(pCreateInfo
->format
));
82 /* align byte per element on dword */
83 if (surface
->bpe
== 3) {
86 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
88 switch (pCreateInfo
->imageType
){
89 case VK_IMAGE_TYPE_1D
:
90 if (pCreateInfo
->arrayLayers
> 1)
91 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
93 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
95 case VK_IMAGE_TYPE_2D
:
96 if (pCreateInfo
->arrayLayers
> 1)
97 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
99 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
101 case VK_IMAGE_TYPE_3D
:
102 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
105 unreachable("unhandled image type");
109 surface
->flags
|= RADEON_SURF_ZBUFFER
;
113 surface
->flags
|= RADEON_SURF_SBUFFER
;
115 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
117 if ((pCreateInfo
->usage
& (VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
118 VK_IMAGE_USAGE_STORAGE_BIT
)) ||
119 (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) ||
120 (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) ||
121 device
->physical_device
->rad_info
.chip_class
< VI
||
122 create_info
->scanout
|| (device
->debug_flags
& RADV_DEBUG_NO_DCC
) ||
123 !radv_is_colorbuffer_format_supported(pCreateInfo
->format
, &blendable
))
124 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
125 if (create_info
->scanout
)
126 surface
->flags
|= RADEON_SURF_SCANOUT
;
129 #define ATI_VENDOR_ID 0x1002
130 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
132 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
135 static inline unsigned
136 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
139 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
141 return image
->surface
.u
.legacy
.tiling_index
[level
];
144 static unsigned radv_map_swizzle(unsigned swizzle
)
148 return V_008F0C_SQ_SEL_Y
;
150 return V_008F0C_SQ_SEL_Z
;
152 return V_008F0C_SQ_SEL_W
;
154 return V_008F0C_SQ_SEL_0
;
156 return V_008F0C_SQ_SEL_1
;
157 default: /* VK_SWIZZLE_X */
158 return V_008F0C_SQ_SEL_X
;
163 radv_make_buffer_descriptor(struct radv_device
*device
,
164 struct radv_buffer
*buffer
,
170 const struct vk_format_description
*desc
;
172 uint64_t gpu_address
= device
->ws
->buffer_get_va(buffer
->bo
);
173 uint64_t va
= gpu_address
+ buffer
->offset
;
174 unsigned num_format
, data_format
;
176 desc
= vk_format_description(vk_format
);
177 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
178 stride
= desc
->block
.bits
/ 8;
180 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
181 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
185 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
186 S_008F04_STRIDE(stride
);
188 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
193 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
194 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
195 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
196 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
197 S_008F0C_NUM_FORMAT(num_format
) |
198 S_008F0C_DATA_FORMAT(data_format
);
202 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
203 struct radv_image
*image
,
204 const struct legacy_surf_level
*base_level_info
,
205 unsigned base_level
, unsigned first_level
,
206 unsigned block_width
, bool is_stencil
,
209 uint64_t gpu_address
= image
->bo
? device
->ws
->buffer_get_va(image
->bo
) + image
->offset
: 0;
210 uint64_t va
= gpu_address
;
211 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
212 uint64_t meta_va
= 0;
213 if (chip_class
>= GFX9
) {
215 va
+= image
->surface
.u
.gfx9
.stencil_offset
;
217 va
+= image
->surface
.u
.gfx9
.surf_offset
;
219 va
+= base_level_info
->offset
;
222 if (chip_class
>= GFX9
||
223 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
224 state
[0] |= image
->surface
.tile_swizzle
;
225 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
226 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
228 if (chip_class
>= VI
) {
229 state
[6] &= C_008F28_COMPRESSION_EN
;
231 if (image
->surface
.dcc_size
&& first_level
< image
->surface
.num_dcc_levels
) {
232 meta_va
= gpu_address
+ image
->dcc_offset
;
233 if (chip_class
<= VI
)
234 meta_va
+= base_level_info
->dcc_offset
;
235 state
[6] |= S_008F28_COMPRESSION_EN(1);
236 state
[7] = meta_va
>> 8;
237 state
[7] |= image
->surface
.tile_swizzle
;
241 if (chip_class
>= GFX9
) {
242 state
[3] &= C_008F1C_SW_MODE
;
243 state
[4] &= C_008F20_PITCH_GFX9
;
246 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
247 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.stencil
.epitch
);
249 state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.surf
.swizzle_mode
);
250 state
[4] |= S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.surf
.epitch
);
253 state
[5] &= C_008F24_META_DATA_ADDRESS
&
254 C_008F24_META_PIPE_ALIGNED
&
255 C_008F24_META_RB_ALIGNED
;
257 struct gfx9_surf_meta_flags meta
;
259 if (image
->dcc_offset
)
260 meta
= image
->surface
.u
.gfx9
.dcc
;
262 meta
= image
->surface
.u
.gfx9
.htile
;
264 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
265 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
266 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
270 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
271 unsigned index
= si_tile_mode_index(image
, base_level
, is_stencil
);
273 state
[3] &= C_008F1C_TILING_INDEX
;
274 state
[3] |= S_008F1C_TILING_INDEX(index
);
275 state
[4] &= C_008F20_PITCH_GFX6
;
276 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
280 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
281 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
)
283 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
284 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
285 switch (image_type
) {
286 case VK_IMAGE_TYPE_1D
:
287 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
288 case VK_IMAGE_TYPE_2D
:
290 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
292 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
293 case VK_IMAGE_TYPE_3D
:
294 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
295 return V_008F1C_SQ_RSRC_IMG_3D
;
297 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
299 unreachable("illegale image type");
303 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
305 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
307 if (swizzle
[3] == VK_SWIZZLE_X
) {
308 /* For the pre-defined border color values (white, opaque
309 * black, transparent black), the only thing that matters is
310 * that the alpha channel winds up in the correct place
311 * (because the RGB channels are all the same) so either of
312 * these enumerations will work.
314 if (swizzle
[2] == VK_SWIZZLE_Y
)
315 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
317 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
318 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
319 if (swizzle
[1] == VK_SWIZZLE_Y
)
320 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
322 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
323 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
324 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
325 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
326 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
333 * Build the sampler view descriptor for a texture.
336 si_make_texture_descriptor(struct radv_device
*device
,
337 struct radv_image
*image
,
338 bool is_storage_image
,
339 VkImageViewType view_type
,
341 const VkComponentMapping
*mapping
,
342 unsigned first_level
, unsigned last_level
,
343 unsigned first_layer
, unsigned last_layer
,
344 unsigned width
, unsigned height
, unsigned depth
,
346 uint32_t *fmask_state
)
348 const struct vk_format_description
*desc
;
349 enum vk_swizzle swizzle
[4];
351 unsigned num_format
, data_format
, type
;
353 desc
= vk_format_description(vk_format
);
355 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
356 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
357 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
359 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
362 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
364 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
365 if (num_format
== ~0) {
369 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
370 if (data_format
== ~0) {
374 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
376 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
378 depth
= image
->info
.array_size
;
379 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
380 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
381 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
382 depth
= image
->info
.array_size
;
383 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
384 depth
= image
->info
.array_size
/ 6;
387 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
388 S_008F14_NUM_FORMAT_GFX6(num_format
));
389 state
[2] = (S_008F18_WIDTH(width
- 1) |
390 S_008F18_HEIGHT(height
- 1) |
391 S_008F18_PERF_MOD(4));
392 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
393 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
394 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
395 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
396 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
398 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
399 util_logbase2(image
->info
.samples
) :
401 S_008F1C_TYPE(type
));
403 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
407 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
408 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
410 /* Depth is the the last accessible layer on Gfx9.
411 * The hw doesn't need to know the total number of layers.
413 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
414 state
[4] |= S_008F20_DEPTH(depth
- 1);
416 state
[4] |= S_008F20_DEPTH(last_layer
);
418 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
419 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
420 util_logbase2(image
->info
.samples
) :
421 image
->info
.levels
- 1);
423 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
424 state
[4] |= S_008F20_DEPTH(depth
- 1);
425 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
427 if (image
->dcc_offset
) {
428 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
430 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
432 /* The last dword is unused by hw. The shader uses it to clear
433 * bits in the first dword of sampler state.
435 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
436 if (first_level
== last_level
)
437 state
[7] = C_008F30_MAX_ANISO_RATIO
;
439 state
[7] = 0xffffffff;
443 /* Initialize the sampler view for FMASK. */
444 if (image
->fmask
.size
) {
445 uint32_t fmask_format
, num_format
;
446 uint64_t gpu_address
= device
->ws
->buffer_get_va(image
->bo
);
449 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
451 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
452 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
453 switch (image
->info
.samples
) {
455 num_format
= V_008F14_IMG_FMASK_8_2_2
;
458 num_format
= V_008F14_IMG_FMASK_8_4_4
;
461 num_format
= V_008F14_IMG_FMASK_32_8_8
;
464 unreachable("invalid nr_samples");
467 switch (image
->info
.samples
) {
469 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
472 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
475 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
479 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
481 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
484 fmask_state
[0] = va
>> 8;
485 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
486 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
487 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
488 S_008F14_NUM_FORMAT_GFX6(num_format
);
489 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
490 S_008F18_HEIGHT(height
- 1);
491 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
492 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
493 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
494 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
495 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, 1, 0, false));
497 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
501 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
502 fmask_state
[3] |= S_008F1C_SW_MODE(image
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
503 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
504 S_008F20_PITCH_GFX9(image
->surface
.u
.gfx9
.fmask
.epitch
);
505 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
506 S_008F24_META_RB_ALIGNED(image
->surface
.u
.gfx9
.cmask
.rb_aligned
);
508 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
509 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
510 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
511 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
513 } else if (fmask_state
)
514 memset(fmask_state
, 0, 8 * 4);
518 radv_query_opaque_metadata(struct radv_device
*device
,
519 struct radv_image
*image
,
520 struct radeon_bo_metadata
*md
)
522 static const VkComponentMapping fixedmapping
;
525 /* Metadata image format format version 1:
526 * [0] = 1 (metadata format identifier)
527 * [1] = (VENDOR_ID << 16) | PCI_ID
528 * [2:9] = image descriptor for the whole resource
529 * [2] is always 0, because the base address is cleared
530 * [9] is the DCC offset bits [39:8] from the beginning of
532 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
534 md
->metadata
[0] = 1; /* metadata image format version 1 */
536 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
537 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
540 si_make_texture_descriptor(device
, image
, false,
541 (VkImageViewType
)image
->type
, image
->vk_format
,
542 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
543 image
->info
.array_size
,
544 image
->info
.width
, image
->info
.height
,
548 si_set_mutable_tex_desc_fields(device
, image
, &image
->surface
.u
.legacy
.level
[0], 0, 0,
549 image
->surface
.blk_w
, false, desc
);
551 /* Clear the base address and set the relative DCC offset. */
553 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
554 desc
[7] = image
->dcc_offset
>> 8;
556 /* Dwords [2:9] contain the image descriptor. */
557 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
559 /* Dwords [10:..] contain the mipmap level offsets. */
560 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
561 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
562 md
->metadata
[10+i
] = image
->surface
.u
.legacy
.level
[i
].offset
>> 8;
563 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
568 radv_init_metadata(struct radv_device
*device
,
569 struct radv_image
*image
,
570 struct radeon_bo_metadata
*metadata
)
572 struct radeon_surf
*surface
= &image
->surface
;
574 memset(metadata
, 0, sizeof(*metadata
));
576 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
577 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
579 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
580 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
581 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
582 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
583 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
584 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
585 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
586 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
587 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
588 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
589 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
590 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
592 radv_query_opaque_metadata(device
, image
, metadata
);
595 /* The number of samples can be specified independently of the texture. */
597 radv_image_get_fmask_info(struct radv_device
*device
,
598 struct radv_image
*image
,
600 struct radv_fmask_info
*out
)
602 /* FMASK is allocated like an ordinary texture. */
603 struct radeon_surf fmask
= {};
604 struct ac_surf_info info
= image
->info
;
605 memset(out
, 0, sizeof(*out
));
607 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
608 out
->alignment
= image
->surface
.u
.gfx9
.fmask_alignment
;
609 out
->size
= image
->surface
.u
.gfx9
.fmask_size
;
613 fmask
.blk_w
= image
->surface
.blk_w
;
614 fmask
.blk_h
= image
->surface
.blk_h
;
616 fmask
.flags
= image
->surface
.flags
| RADEON_SURF_FMASK
;
618 if (!image
->shareable
)
619 info
.surf_index
= &device
->fmask_mrt_offset_counter
;
621 /* Force 2D tiling if it wasn't set. This may occur when creating
622 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
623 * destination buffer must have an FMASK too. */
624 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
625 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
627 switch (nr_samples
) {
639 device
->ws
->surface_init(device
->ws
, &info
, &fmask
);
640 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
642 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
643 if (out
->slice_tile_max
)
644 out
->slice_tile_max
-= 1;
646 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
647 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
648 out
->bank_height
= fmask
.u
.legacy
.bankh
;
649 out
->tile_swizzle
= fmask
.tile_swizzle
;
650 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
651 out
->size
= fmask
.surf_size
;
653 assert(!out
->tile_swizzle
|| !image
->shareable
);
657 radv_image_alloc_fmask(struct radv_device
*device
,
658 struct radv_image
*image
)
660 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
662 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
663 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
664 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
668 radv_image_get_cmask_info(struct radv_device
*device
,
669 struct radv_image
*image
,
670 struct radv_cmask_info
*out
)
672 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
673 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
674 unsigned cl_width
, cl_height
;
676 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
677 out
->alignment
= image
->surface
.u
.gfx9
.cmask_alignment
;
678 out
->size
= image
->surface
.u
.gfx9
.cmask_size
;
695 case 16: /* Hawaii */
704 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
706 unsigned width
= align(image
->info
.width
, cl_width
*8);
707 unsigned height
= align(image
->info
.height
, cl_height
*8);
708 unsigned slice_elements
= (width
* height
) / (8*8);
710 /* Each element of CMASK is a nibble. */
711 unsigned slice_bytes
= slice_elements
/ 2;
713 out
->slice_tile_max
= (width
* height
) / (128*128);
714 if (out
->slice_tile_max
)
715 out
->slice_tile_max
-= 1;
717 out
->alignment
= MAX2(256, base_align
);
718 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
719 align(slice_bytes
, base_align
);
723 radv_image_alloc_cmask(struct radv_device
*device
,
724 struct radv_image
*image
)
726 uint32_t clear_value_size
= 0;
727 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
729 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
730 /* + 8 for storing the clear values */
731 if (!image
->clear_value_offset
) {
732 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
733 clear_value_size
= 8;
735 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
736 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
740 radv_image_alloc_dcc(struct radv_device
*device
,
741 struct radv_image
*image
)
743 image
->dcc_offset
= align64(image
->size
, image
->surface
.dcc_alignment
);
744 /* + 16 for storing the clear values + dcc pred */
745 image
->clear_value_offset
= image
->dcc_offset
+ image
->surface
.dcc_size
;
746 image
->dcc_pred_offset
= image
->clear_value_offset
+ 8;
747 image
->size
= image
->dcc_offset
+ image
->surface
.dcc_size
+ 16;
748 image
->alignment
= MAX2(image
->alignment
, image
->surface
.dcc_alignment
);
752 radv_image_alloc_htile(struct radv_device
*device
,
753 struct radv_image
*image
)
755 if ((device
->debug_flags
& RADV_DEBUG_NO_HIZ
) || image
->info
.levels
> 1) {
756 image
->surface
.htile_size
= 0;
760 image
->htile_offset
= align64(image
->size
, image
->surface
.htile_alignment
);
762 /* + 8 for storing the clear values */
763 image
->clear_value_offset
= image
->htile_offset
+ image
->surface
.htile_size
;
764 image
->size
= image
->clear_value_offset
+ 8;
765 image
->alignment
= align64(image
->alignment
, image
->surface
.htile_alignment
);
769 radv_image_create(VkDevice _device
,
770 const struct radv_image_create_info
*create_info
,
771 const VkAllocationCallbacks
* alloc
,
774 RADV_FROM_HANDLE(radv_device
, device
, _device
);
775 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
776 struct radv_image
*image
= NULL
;
777 bool can_cmask_dcc
= false;
778 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
780 radv_assert(pCreateInfo
->mipLevels
> 0);
781 radv_assert(pCreateInfo
->arrayLayers
> 0);
782 radv_assert(pCreateInfo
->samples
> 0);
783 radv_assert(pCreateInfo
->extent
.width
> 0);
784 radv_assert(pCreateInfo
->extent
.height
> 0);
785 radv_assert(pCreateInfo
->extent
.depth
> 0);
787 image
= vk_alloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
788 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
790 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
792 memset(image
, 0, sizeof(*image
));
793 image
->type
= pCreateInfo
->imageType
;
794 image
->info
.width
= pCreateInfo
->extent
.width
;
795 image
->info
.height
= pCreateInfo
->extent
.height
;
796 image
->info
.depth
= pCreateInfo
->extent
.depth
;
797 image
->info
.samples
= pCreateInfo
->samples
;
798 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
799 image
->info
.levels
= pCreateInfo
->mipLevels
;
801 image
->vk_format
= pCreateInfo
->format
;
802 image
->tiling
= pCreateInfo
->tiling
;
803 image
->usage
= pCreateInfo
->usage
;
804 image
->flags
= pCreateInfo
->flags
;
806 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
807 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
808 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
809 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL_KHR
)
810 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
812 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
815 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
816 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR
) != NULL
;
817 if (!vk_format_is_depth(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
818 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
821 radv_init_surface(device
, &image
->surface
, create_info
);
823 device
->ws
->surface_init(device
->ws
, &image
->info
, &image
->surface
);
825 image
->size
= image
->surface
.surf_size
;
826 image
->alignment
= image
->surface
.surf_alignment
;
828 if (image
->exclusive
|| image
->queue_family_mask
== 1)
829 can_cmask_dcc
= true;
831 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
832 image
->surface
.dcc_size
&& can_cmask_dcc
)
833 radv_image_alloc_dcc(device
, image
);
835 image
->surface
.dcc_size
= 0;
837 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) &&
838 pCreateInfo
->mipLevels
== 1 &&
839 !image
->surface
.dcc_size
&& image
->info
.depth
== 1 && can_cmask_dcc
)
840 radv_image_alloc_cmask(device
, image
);
841 if (image
->info
.samples
> 1 && vk_format_is_color(pCreateInfo
->format
)) {
842 radv_image_alloc_fmask(device
, image
);
843 } else if (vk_format_is_depth(pCreateInfo
->format
)) {
845 radv_image_alloc_htile(device
, image
);
848 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
849 image
->alignment
= MAX2(image
->alignment
, 4096);
850 image
->size
= align64(image
->size
, image
->alignment
);
853 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
854 0, RADEON_FLAG_VIRTUAL
);
856 vk_free2(&device
->alloc
, alloc
, image
);
857 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
861 *pImage
= radv_image_to_handle(image
);
867 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
868 struct radv_device
*device
,
869 const VkComponentMapping
*components
,
870 bool is_storage_image
)
872 struct radv_image
*image
= iview
->image
;
873 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
875 uint32_t *descriptor
;
876 uint32_t *fmask_descriptor
;
878 if (is_storage_image
) {
879 descriptor
= iview
->storage_descriptor
;
880 fmask_descriptor
= iview
->storage_fmask_descriptor
;
882 descriptor
= iview
->descriptor
;
883 fmask_descriptor
= iview
->fmask_descriptor
;
886 assert(image
->surface
.blk_w
% vk_format_get_blockwidth(image
->vk_format
) == 0);
887 blk_w
= image
->surface
.blk_w
/ vk_format_get_blockwidth(image
->vk_format
) * vk_format_get_blockwidth(iview
->vk_format
);
889 si_make_texture_descriptor(device
, image
, is_storage_image
,
893 0, iview
->level_count
- 1,
895 iview
->base_layer
+ iview
->layer_count
- 1,
897 iview
->extent
.height
,
902 const struct legacy_surf_level
*base_level_info
= NULL
;
903 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
905 base_level_info
= &image
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
907 base_level_info
= &image
->surface
.u
.legacy
.level
[iview
->base_mip
];
909 si_set_mutable_tex_desc_fields(device
, image
,
913 blk_w
, is_stencil
, descriptor
);
917 radv_image_view_init(struct radv_image_view
*iview
,
918 struct radv_device
*device
,
919 const VkImageViewCreateInfo
* pCreateInfo
)
921 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
922 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
924 switch (image
->type
) {
925 case VK_IMAGE_TYPE_1D
:
926 case VK_IMAGE_TYPE_2D
:
927 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
929 case VK_IMAGE_TYPE_3D
:
930 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
931 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
934 unreachable("bad VkImageType");
936 iview
->image
= image
;
937 iview
->bo
= image
->bo
;
938 iview
->type
= pCreateInfo
->viewType
;
939 iview
->vk_format
= pCreateInfo
->format
;
940 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
942 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
943 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
944 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
945 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
948 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
949 iview
->extent
= (VkExtent3D
) {
950 .width
= image
->info
.width
,
951 .height
= image
->info
.height
,
952 .depth
= image
->info
.depth
,
955 iview
->extent
= (VkExtent3D
) {
956 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
957 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
958 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
962 if (iview
->vk_format
!= image
->vk_format
) {
963 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* vk_format_get_blockwidth(iview
->vk_format
),
964 vk_format_get_blockwidth(image
->vk_format
));
965 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* vk_format_get_blockheight(iview
->vk_format
),
966 vk_format_get_blockheight(image
->vk_format
));
969 iview
->base_layer
= range
->baseArrayLayer
;
970 iview
->layer_count
= radv_get_layerCount(image
, range
);
971 iview
->base_mip
= range
->baseMipLevel
;
972 iview
->level_count
= radv_get_levelCount(image
, range
);
974 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, false);
975 radv_image_view_make_descriptor(iview
, device
, &pCreateInfo
->components
, true);
978 bool radv_layout_has_htile(const struct radv_image
*image
,
979 VkImageLayout layout
,
982 return image
->surface
.htile_size
&&
983 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
984 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
985 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
988 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
989 VkImageLayout layout
,
992 return image
->surface
.htile_size
&&
993 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
994 layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
) &&
995 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
998 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
999 VkImageLayout layout
,
1000 unsigned queue_mask
)
1002 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
&&
1003 queue_mask
== (1u << RADV_QUEUE_GENERAL
);
1007 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1009 if (!image
->exclusive
)
1010 return image
->queue_family_mask
;
1011 if (family
== VK_QUEUE_FAMILY_EXTERNAL_KHR
)
1012 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1013 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1014 return 1u << queue_family
;
1015 return 1u << family
;
1019 radv_CreateImage(VkDevice device
,
1020 const VkImageCreateInfo
*pCreateInfo
,
1021 const VkAllocationCallbacks
*pAllocator
,
1024 return radv_image_create(device
,
1025 &(struct radv_image_create_info
) {
1026 .vk_info
= pCreateInfo
,
1034 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1035 const VkAllocationCallbacks
*pAllocator
)
1037 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1038 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1043 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1044 device
->ws
->buffer_destroy(image
->bo
);
1046 vk_free2(&device
->alloc
, pAllocator
, image
);
1049 void radv_GetImageSubresourceLayout(
1052 const VkImageSubresource
* pSubresource
,
1053 VkSubresourceLayout
* pLayout
)
1055 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1056 int level
= pSubresource
->mipLevel
;
1057 int layer
= pSubresource
->arrayLayer
;
1058 struct radeon_surf
*surface
= &image
->surface
;
1060 pLayout
->offset
= surface
->u
.legacy
.level
[level
].offset
+ surface
->u
.legacy
.level
[level
].slice_size
* layer
;
1061 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1062 pLayout
->arrayPitch
= surface
->u
.legacy
.level
[level
].slice_size
;
1063 pLayout
->depthPitch
= surface
->u
.legacy
.level
[level
].slice_size
;
1064 pLayout
->size
= surface
->u
.legacy
.level
[level
].slice_size
;
1065 if (image
->type
== VK_IMAGE_TYPE_3D
)
1066 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1071 radv_CreateImageView(VkDevice _device
,
1072 const VkImageViewCreateInfo
*pCreateInfo
,
1073 const VkAllocationCallbacks
*pAllocator
,
1076 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1077 struct radv_image_view
*view
;
1079 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1080 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1082 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1084 radv_image_view_init(view
, device
, pCreateInfo
);
1086 *pView
= radv_image_view_to_handle(view
);
1092 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1093 const VkAllocationCallbacks
*pAllocator
)
1095 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1096 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1100 vk_free2(&device
->alloc
, pAllocator
, iview
);
1103 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1104 struct radv_device
*device
,
1105 const VkBufferViewCreateInfo
* pCreateInfo
,
1106 struct radv_cmd_buffer
*cmd_buffer
)
1108 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1110 view
->bo
= buffer
->bo
;
1111 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1112 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1113 view
->vk_format
= pCreateInfo
->format
;
1115 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1116 pCreateInfo
->offset
, view
->range
, view
->state
);
1120 radv_CreateBufferView(VkDevice _device
,
1121 const VkBufferViewCreateInfo
*pCreateInfo
,
1122 const VkAllocationCallbacks
*pAllocator
,
1123 VkBufferView
*pView
)
1125 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1126 struct radv_buffer_view
*view
;
1128 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1129 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1131 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1133 radv_buffer_view_init(view
, device
, pCreateInfo
, NULL
);
1135 *pView
= radv_buffer_view_to_handle(view
);
1141 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1142 const VkAllocationCallbacks
*pAllocator
)
1144 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1145 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1150 vk_free2(&device
->alloc
, pAllocator
, view
);