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radv: set fmask state to all 0s when no fmask. (v2)
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "util/debug.h"
34 static unsigned
35 radv_choose_tiling(struct radv_device *Device,
36 const struct radv_image_create_info *create_info)
37 {
38 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
39
40 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
41 assert(pCreateInfo->samples <= 1);
42 return RADEON_SURF_MODE_LINEAR_ALIGNED;
43 }
44
45 /* Textures with a very small height are recommended to be linear. */
46 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
47 /* Only very thin and long 2D textures should benefit from
48 * linear_aligned. */
49 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
50 return RADEON_SURF_MODE_LINEAR_ALIGNED;
51
52 /* MSAA resources must be 2D tiled. */
53 if (pCreateInfo->samples > 1)
54 return RADEON_SURF_MODE_2D;
55
56 return RADEON_SURF_MODE_2D;
57 }
58 static int
59 radv_init_surface(struct radv_device *device,
60 struct radeon_surf *surface,
61 const struct radv_image_create_info *create_info)
62 {
63 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
64 unsigned array_mode = radv_choose_tiling(device, create_info);
65 const struct vk_format_description *desc =
66 vk_format_description(pCreateInfo->format);
67 bool is_depth, is_stencil, blendable;
68
69 is_depth = vk_format_has_depth(desc);
70 is_stencil = vk_format_has_stencil(desc);
71
72 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
73 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
74
75 surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
76 /* align byte per element on dword */
77 if (surface->bpe == 3) {
78 surface->bpe = 4;
79 }
80 surface->flags = RADEON_SURF_SET(array_mode, MODE);
81
82 switch (pCreateInfo->imageType){
83 case VK_IMAGE_TYPE_1D:
84 if (pCreateInfo->arrayLayers > 1)
85 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
86 else
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
88 break;
89 case VK_IMAGE_TYPE_2D:
90 if (pCreateInfo->arrayLayers > 1)
91 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
92 else
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
94 break;
95 case VK_IMAGE_TYPE_3D:
96 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
97 break;
98 default:
99 unreachable("unhandled image type");
100 }
101
102 if (is_depth) {
103 surface->flags |= RADEON_SURF_ZBUFFER;
104 }
105
106 if (is_stencil)
107 surface->flags |= RADEON_SURF_SBUFFER;
108
109 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
110
111 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
112 VK_IMAGE_USAGE_STORAGE_BIT)) ||
113 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
114 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
115 device->physical_device->rad_info.chip_class < VI ||
116 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
117 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
118 surface->flags |= RADEON_SURF_DISABLE_DCC;
119 if (create_info->scanout)
120 surface->flags |= RADEON_SURF_SCANOUT;
121 return 0;
122 }
123 #define ATI_VENDOR_ID 0x1002
124 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
125 {
126 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
127 }
128
129 static inline unsigned
130 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
131 {
132 if (stencil)
133 return image->surface.u.legacy.stencil_tiling_index[level];
134 else
135 return image->surface.u.legacy.tiling_index[level];
136 }
137
138 static unsigned radv_map_swizzle(unsigned swizzle)
139 {
140 switch (swizzle) {
141 case VK_SWIZZLE_Y:
142 return V_008F0C_SQ_SEL_Y;
143 case VK_SWIZZLE_Z:
144 return V_008F0C_SQ_SEL_Z;
145 case VK_SWIZZLE_W:
146 return V_008F0C_SQ_SEL_W;
147 case VK_SWIZZLE_0:
148 return V_008F0C_SQ_SEL_0;
149 case VK_SWIZZLE_1:
150 return V_008F0C_SQ_SEL_1;
151 default: /* VK_SWIZZLE_X */
152 return V_008F0C_SQ_SEL_X;
153 }
154 }
155
156 static void
157 radv_make_buffer_descriptor(struct radv_device *device,
158 struct radv_buffer *buffer,
159 VkFormat vk_format,
160 unsigned offset,
161 unsigned range,
162 uint32_t *state)
163 {
164 const struct vk_format_description *desc;
165 unsigned stride;
166 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
167 uint64_t va = gpu_address + buffer->offset;
168 unsigned num_format, data_format;
169 int first_non_void;
170 desc = vk_format_description(vk_format);
171 first_non_void = vk_format_get_first_non_void_channel(vk_format);
172 stride = desc->block.bits / 8;
173
174 num_format = radv_translate_buffer_numformat(desc, first_non_void);
175 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
176
177 va += offset;
178 state[0] = va;
179 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
180 S_008F04_STRIDE(stride);
181 state[2] = range;
182 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
183 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
184 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
185 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
186 S_008F0C_NUM_FORMAT(num_format) |
187 S_008F0C_DATA_FORMAT(data_format);
188 }
189
190 static void
191 si_set_mutable_tex_desc_fields(struct radv_device *device,
192 struct radv_image *image,
193 const struct legacy_surf_level *base_level_info,
194 unsigned base_level, unsigned first_level,
195 unsigned block_width, bool is_stencil,
196 uint32_t *state)
197 {
198 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
199 uint64_t va = gpu_address;
200 unsigned pitch = base_level_info->nblk_x * block_width;
201 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
202 uint64_t meta_va = 0;
203 if (chip_class >= GFX9) {
204 if (is_stencil)
205 va += image->surface.u.gfx9.stencil_offset;
206 else
207 va += image->surface.u.gfx9.surf_offset;
208 } else
209 va += base_level_info->offset;
210
211 state[0] = va >> 8;
212 state[1] &= C_008F14_BASE_ADDRESS_HI;
213 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
214 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
215 is_stencil));
216 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
217
218 if (chip_class >= VI) {
219 state[6] &= C_008F28_COMPRESSION_EN;
220 state[7] = 0;
221 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
222 uint64_t meta_va = gpu_address + image->dcc_offset;
223 if (chip_class <= VI)
224 meta_va += base_level_info->dcc_offset;
225 state[6] |= S_008F28_COMPRESSION_EN(1);
226 state[7] = meta_va >> 8;
227
228 }
229 }
230
231 if (chip_class >= GFX9) {
232 state[3] &= C_008F1C_SW_MODE;
233 state[4] &= C_008F20_PITCH_GFX9;
234
235 if (is_stencil) {
236 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
237 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
238 } else {
239 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
240 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
241 }
242
243 state[5] &= C_008F24_META_DATA_ADDRESS &
244 C_008F24_META_PIPE_ALIGNED &
245 C_008F24_META_RB_ALIGNED;
246 if (meta_va) {
247 struct gfx9_surf_meta_flags meta;
248
249 if (image->dcc_offset)
250 meta = image->surface.u.gfx9.dcc;
251 else
252 meta = image->surface.u.gfx9.htile;
253
254 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
255 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
256 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
257 }
258 } else {
259 /* SI-CI-VI */
260 unsigned pitch = base_level_info->nblk_x * block_width;
261 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
262
263 state[3] &= C_008F1C_TILING_INDEX;
264 state[3] |= S_008F1C_TILING_INDEX(index);
265 state[4] &= C_008F20_PITCH_GFX6;
266 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
267 }
268 }
269
270 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
271 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
272 {
273 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
274 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
275 switch (image_type) {
276 case VK_IMAGE_TYPE_1D:
277 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
278 case VK_IMAGE_TYPE_2D:
279 if (nr_samples > 1)
280 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
281 else
282 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
283 case VK_IMAGE_TYPE_3D:
284 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
285 return V_008F1C_SQ_RSRC_IMG_3D;
286 else
287 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
288 default:
289 unreachable("illegale image type");
290 }
291 }
292
293 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
294 {
295 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
296
297 if (swizzle[3] == VK_SWIZZLE_X) {
298 /* For the pre-defined border color values (white, opaque
299 * black, transparent black), the only thing that matters is
300 * that the alpha channel winds up in the correct place
301 * (because the RGB channels are all the same) so either of
302 * these enumerations will work.
303 */
304 if (swizzle[2] == VK_SWIZZLE_Y)
305 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
306 else
307 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
308 } else if (swizzle[0] == VK_SWIZZLE_X) {
309 if (swizzle[1] == VK_SWIZZLE_Y)
310 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
311 else
312 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
313 } else if (swizzle[1] == VK_SWIZZLE_X) {
314 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
315 } else if (swizzle[2] == VK_SWIZZLE_X) {
316 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
317 }
318
319 return bc_swizzle;
320 }
321
322 /**
323 * Build the sampler view descriptor for a texture.
324 */
325 static void
326 si_make_texture_descriptor(struct radv_device *device,
327 struct radv_image *image,
328 bool sampler,
329 VkImageViewType view_type,
330 VkFormat vk_format,
331 const VkComponentMapping *mapping,
332 unsigned first_level, unsigned last_level,
333 unsigned first_layer, unsigned last_layer,
334 unsigned width, unsigned height, unsigned depth,
335 uint32_t *state,
336 uint32_t *fmask_state)
337 {
338 const struct vk_format_description *desc;
339 enum vk_swizzle swizzle[4];
340 int first_non_void;
341 unsigned num_format, data_format, type;
342
343 desc = vk_format_description(vk_format);
344
345 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
346 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
347 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
348 } else {
349 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
350 }
351
352 first_non_void = vk_format_get_first_non_void_channel(vk_format);
353
354 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
355 if (num_format == ~0) {
356 num_format = 0;
357 }
358
359 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
360 if (data_format == ~0) {
361 data_format = 0;
362 }
363
364 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
365 (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
366 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
367 height = 1;
368 depth = image->info.array_size;
369 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
370 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
371 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
372 depth = image->info.array_size;
373 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
374 depth = image->info.array_size / 6;
375
376 state[0] = 0;
377 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
378 S_008F14_NUM_FORMAT_GFX6(num_format));
379 state[2] = (S_008F18_WIDTH(width - 1) |
380 S_008F18_HEIGHT(height - 1) |
381 S_008F18_PERF_MOD(4));
382 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
383 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
384 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
385 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
386 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
387 0 : first_level) |
388 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
389 util_logbase2(image->info.samples) :
390 last_level) |
391 S_008F1C_TYPE(type));
392 state[4] = 0;
393 state[5] = S_008F24_BASE_ARRAY(first_layer);
394 state[6] = 0;
395 state[7] = 0;
396
397 if (device->physical_device->rad_info.chip_class >= GFX9) {
398 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
399
400 /* Depth is the the last accessible layer on Gfx9.
401 * The hw doesn't need to know the total number of layers.
402 */
403 if (type == V_008F1C_SQ_RSRC_IMG_3D)
404 state[4] |= S_008F20_DEPTH(depth - 1);
405 else
406 state[4] |= S_008F20_DEPTH(last_layer);
407
408 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
409 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
410 util_logbase2(image->info.samples) :
411 last_level);
412 } else {
413 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
414 state[4] |= S_008F20_DEPTH(depth - 1);
415 state[5] |= S_008F24_LAST_ARRAY(last_layer);
416 }
417 if (image->dcc_offset) {
418 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
419
420 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
421 } else {
422 /* The last dword is unused by hw. The shader uses it to clear
423 * bits in the first dword of sampler state.
424 */
425 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
426 if (first_level == last_level)
427 state[7] = C_008F30_MAX_ANISO_RATIO;
428 else
429 state[7] = 0xffffffff;
430 }
431 }
432
433 /* Initialize the sampler view for FMASK. */
434 if (image->fmask.size) {
435 uint32_t fmask_format, num_format;
436 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
437 uint64_t va;
438
439 va = gpu_address + image->offset + image->fmask.offset;
440
441 if (device->physical_device->rad_info.chip_class >= GFX9) {
442 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
443 switch (image->info.samples) {
444 case 2:
445 num_format = V_008F14_IMG_FMASK_8_2_2;
446 break;
447 case 4:
448 num_format = V_008F14_IMG_FMASK_8_4_4;
449 break;
450 case 8:
451 num_format = V_008F14_IMG_FMASK_32_8_8;
452 break;
453 default:
454 unreachable("invalid nr_samples");
455 }
456 } else {
457 switch (image->info.samples) {
458 case 2:
459 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
460 break;
461 case 4:
462 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
463 break;
464 case 8:
465 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
466 break;
467 default:
468 assert(0);
469 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
470 }
471 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
472 }
473
474 fmask_state[0] = va >> 8;
475 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
476 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
477 S_008F14_NUM_FORMAT_GFX6(num_format);
478 fmask_state[2] = S_008F18_WIDTH(width - 1) |
479 S_008F18_HEIGHT(height - 1);
480 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
481 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
482 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
483 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
484 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
485 fmask_state[4] = 0;
486 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
487 fmask_state[6] = 0;
488 fmask_state[7] = 0;
489
490 if (device->physical_device->rad_info.chip_class >= GFX9) {
491 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
492 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
493 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
494 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
495 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
496 } else {
497 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
498 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
499 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
500 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
501 }
502 } else if (fmask_state)
503 memset(fmask_state, 0, 8 * 4);
504 }
505
506 static void
507 radv_query_opaque_metadata(struct radv_device *device,
508 struct radv_image *image,
509 struct radeon_bo_metadata *md)
510 {
511 static const VkComponentMapping fixedmapping;
512 uint32_t desc[8], i;
513
514 /* Metadata image format format version 1:
515 * [0] = 1 (metadata format identifier)
516 * [1] = (VENDOR_ID << 16) | PCI_ID
517 * [2:9] = image descriptor for the whole resource
518 * [2] is always 0, because the base address is cleared
519 * [9] is the DCC offset bits [39:8] from the beginning of
520 * the buffer
521 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
522 */
523 md->metadata[0] = 1; /* metadata image format version 1 */
524
525 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
526 md->metadata[1] = si_get_bo_metadata_word1(device);
527
528
529 si_make_texture_descriptor(device, image, true,
530 (VkImageViewType)image->type, image->vk_format,
531 &fixedmapping, 0, image->info.levels - 1, 0,
532 image->info.array_size,
533 image->info.width, image->info.height,
534 image->info.depth,
535 desc, NULL);
536
537 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
538 image->surface.blk_w, false, desc);
539
540 /* Clear the base address and set the relative DCC offset. */
541 desc[0] = 0;
542 desc[1] &= C_008F14_BASE_ADDRESS_HI;
543 desc[7] = image->dcc_offset >> 8;
544
545 /* Dwords [2:9] contain the image descriptor. */
546 memcpy(&md->metadata[2], desc, sizeof(desc));
547
548 /* Dwords [10:..] contain the mipmap level offsets. */
549 for (i = 0; i <= image->info.levels - 1; i++)
550 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
551
552 md->size_metadata = (11 + image->info.levels - 1) * 4;
553 }
554
555 void
556 radv_init_metadata(struct radv_device *device,
557 struct radv_image *image,
558 struct radeon_bo_metadata *metadata)
559 {
560 struct radeon_surf *surface = &image->surface;
561
562 memset(metadata, 0, sizeof(*metadata));
563
564 if (device->physical_device->rad_info.chip_class >= GFX9) {
565 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
566 } else {
567 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
568 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
569 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
570 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
571 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
572 metadata->u.legacy.bankw = surface->u.legacy.bankw;
573 metadata->u.legacy.bankh = surface->u.legacy.bankh;
574 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
575 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
576 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
577 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
578 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
579 }
580 radv_query_opaque_metadata(device, image, metadata);
581 }
582
583 /* The number of samples can be specified independently of the texture. */
584 static void
585 radv_image_get_fmask_info(struct radv_device *device,
586 struct radv_image *image,
587 unsigned nr_samples,
588 struct radv_fmask_info *out)
589 {
590 /* FMASK is allocated like an ordinary texture. */
591 struct radeon_surf fmask = {};
592 struct ac_surf_info info = image->info;
593 memset(out, 0, sizeof(*out));
594
595 if (device->physical_device->rad_info.chip_class >= GFX9) {
596 out->alignment = image->surface.u.gfx9.fmask_alignment;
597 out->size = image->surface.u.gfx9.fmask_size;
598 return;
599 }
600
601 fmask.blk_w = image->surface.blk_w;
602 fmask.blk_h = image->surface.blk_h;
603 info.samples = 1;
604 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
605
606 /* Force 2D tiling if it wasn't set. This may occur when creating
607 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
608 * destination buffer must have an FMASK too. */
609 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
610 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
611
612 switch (nr_samples) {
613 case 2:
614 case 4:
615 fmask.bpe = 1;
616 break;
617 case 8:
618 fmask.bpe = 4;
619 break;
620 default:
621 return;
622 }
623
624 device->ws->surface_init(device->ws, &info, &fmask);
625 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
626
627 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
628 if (out->slice_tile_max)
629 out->slice_tile_max -= 1;
630
631 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
632 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
633 out->bank_height = fmask.u.legacy.bankh;
634 out->alignment = MAX2(256, fmask.surf_alignment);
635 out->size = fmask.surf_size;
636 }
637
638 static void
639 radv_image_alloc_fmask(struct radv_device *device,
640 struct radv_image *image)
641 {
642 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
643
644 image->fmask.offset = align64(image->size, image->fmask.alignment);
645 image->size = image->fmask.offset + image->fmask.size;
646 image->alignment = MAX2(image->alignment, image->fmask.alignment);
647 }
648
649 static void
650 radv_image_get_cmask_info(struct radv_device *device,
651 struct radv_image *image,
652 struct radv_cmask_info *out)
653 {
654 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
655 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
656 unsigned cl_width, cl_height;
657
658 if (device->physical_device->rad_info.chip_class >= GFX9) {
659 out->alignment = image->surface.u.gfx9.cmask_alignment;
660 out->size = image->surface.u.gfx9.cmask_size;
661 return;
662 }
663
664 switch (num_pipes) {
665 case 2:
666 cl_width = 32;
667 cl_height = 16;
668 break;
669 case 4:
670 cl_width = 32;
671 cl_height = 32;
672 break;
673 case 8:
674 cl_width = 64;
675 cl_height = 32;
676 break;
677 case 16: /* Hawaii */
678 cl_width = 64;
679 cl_height = 64;
680 break;
681 default:
682 assert(0);
683 return;
684 }
685
686 unsigned base_align = num_pipes * pipe_interleave_bytes;
687
688 unsigned width = align(image->info.width, cl_width*8);
689 unsigned height = align(image->info.height, cl_height*8);
690 unsigned slice_elements = (width * height) / (8*8);
691
692 /* Each element of CMASK is a nibble. */
693 unsigned slice_bytes = slice_elements / 2;
694
695 out->slice_tile_max = (width * height) / (128*128);
696 if (out->slice_tile_max)
697 out->slice_tile_max -= 1;
698
699 out->alignment = MAX2(256, base_align);
700 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
701 align(slice_bytes, base_align);
702 }
703
704 static void
705 radv_image_alloc_cmask(struct radv_device *device,
706 struct radv_image *image)
707 {
708 radv_image_get_cmask_info(device, image, &image->cmask);
709
710 image->cmask.offset = align64(image->size, image->cmask.alignment);
711 /* + 8 for storing the clear values */
712 image->clear_value_offset = image->cmask.offset + image->cmask.size;
713 image->size = image->cmask.offset + image->cmask.size + 8;
714 image->alignment = MAX2(image->alignment, image->cmask.alignment);
715 }
716
717 static void
718 radv_image_alloc_dcc(struct radv_device *device,
719 struct radv_image *image)
720 {
721 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
722 /* + 8 for storing the clear values */
723 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
724 image->size = image->dcc_offset + image->surface.dcc_size + 8;
725 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
726 }
727
728 static void
729 radv_image_alloc_htile(struct radv_device *device,
730 struct radv_image *image)
731 {
732 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
733 image->surface.htile_size = 0;
734 return;
735 }
736
737 image->htile_offset = align64(image->size, image->surface.htile_alignment);
738
739 /* + 8 for storing the clear values */
740 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
741 image->size = image->clear_value_offset + 8;
742 image->alignment = align64(image->alignment, image->surface.htile_alignment);
743 }
744
745 VkResult
746 radv_image_create(VkDevice _device,
747 const struct radv_image_create_info *create_info,
748 const VkAllocationCallbacks* alloc,
749 VkImage *pImage)
750 {
751 RADV_FROM_HANDLE(radv_device, device, _device);
752 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
753 struct radv_image *image = NULL;
754 bool can_cmask_dcc = false;
755 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
756
757 radv_assert(pCreateInfo->mipLevels > 0);
758 radv_assert(pCreateInfo->arrayLayers > 0);
759 radv_assert(pCreateInfo->samples > 0);
760 radv_assert(pCreateInfo->extent.width > 0);
761 radv_assert(pCreateInfo->extent.height > 0);
762 radv_assert(pCreateInfo->extent.depth > 0);
763
764 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
765 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
766 if (!image)
767 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
768
769 memset(image, 0, sizeof(*image));
770 image->type = pCreateInfo->imageType;
771 image->info.width = pCreateInfo->extent.width;
772 image->info.height = pCreateInfo->extent.height;
773 image->info.depth = pCreateInfo->extent.depth;
774 image->info.samples = pCreateInfo->samples;
775 image->info.array_size = pCreateInfo->arrayLayers;
776 image->info.levels = pCreateInfo->mipLevels;
777
778 image->vk_format = pCreateInfo->format;
779 image->tiling = pCreateInfo->tiling;
780 image->usage = pCreateInfo->usage;
781 image->flags = pCreateInfo->flags;
782
783 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
784 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
785 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
786 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHX)
787 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
788 else
789 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
790 }
791
792 radv_init_surface(device, &image->surface, create_info);
793
794 device->ws->surface_init(device->ws, &image->info, &image->surface);
795
796 image->size = image->surface.surf_size;
797 image->alignment = image->surface.surf_alignment;
798
799 if (image->exclusive || image->queue_family_mask == 1)
800 can_cmask_dcc = true;
801
802 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
803 image->surface.dcc_size && can_cmask_dcc)
804 radv_image_alloc_dcc(device, image);
805 else
806 image->surface.dcc_size = 0;
807
808 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
809 pCreateInfo->mipLevels == 1 &&
810 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
811 radv_image_alloc_cmask(device, image);
812 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
813 radv_image_alloc_fmask(device, image);
814 } else if (vk_format_is_depth(pCreateInfo->format)) {
815
816 radv_image_alloc_htile(device, image);
817 }
818
819 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
820 image->alignment = MAX2(image->alignment, 4096);
821 image->size = align64(image->size, image->alignment);
822 image->offset = 0;
823
824 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
825 0, RADEON_FLAG_VIRTUAL);
826 if (!image->bo) {
827 vk_free2(&device->alloc, alloc, image);
828 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
829 }
830 }
831
832 *pImage = radv_image_to_handle(image);
833
834 return VK_SUCCESS;
835 }
836
837 void
838 radv_image_view_init(struct radv_image_view *iview,
839 struct radv_device *device,
840 const VkImageViewCreateInfo* pCreateInfo,
841 struct radv_cmd_buffer *cmd_buffer,
842 VkImageUsageFlags usage_mask)
843 {
844 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
845 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
846 uint32_t blk_w;
847 bool is_stencil = false;
848 switch (image->type) {
849 case VK_IMAGE_TYPE_1D:
850 case VK_IMAGE_TYPE_2D:
851 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
852 break;
853 case VK_IMAGE_TYPE_3D:
854 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
855 <= radv_minify(image->info.depth, range->baseMipLevel));
856 break;
857 default:
858 unreachable("bad VkImageType");
859 }
860 iview->image = image;
861 iview->bo = image->bo;
862 iview->type = pCreateInfo->viewType;
863 iview->vk_format = pCreateInfo->format;
864 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
865
866 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
867 is_stencil = true;
868 iview->vk_format = vk_format_stencil_only(iview->vk_format);
869 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
870 iview->vk_format = vk_format_depth_only(iview->vk_format);
871 }
872
873 iview->extent = (VkExtent3D) {
874 .width = radv_minify(image->info.width , range->baseMipLevel),
875 .height = radv_minify(image->info.height, range->baseMipLevel),
876 .depth = radv_minify(image->info.depth , range->baseMipLevel),
877 };
878
879 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
880 vk_format_get_blockwidth(image->vk_format));
881 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
882 vk_format_get_blockheight(image->vk_format));
883
884 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
885 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
886 iview->base_layer = range->baseArrayLayer;
887 iview->layer_count = radv_get_layerCount(image, range);
888 iview->base_mip = range->baseMipLevel;
889
890 si_make_texture_descriptor(device, image, false,
891 iview->type,
892 iview->vk_format,
893 &pCreateInfo->components,
894 0, radv_get_levelCount(image, range) - 1,
895 range->baseArrayLayer,
896 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
897 iview->extent.width,
898 iview->extent.height,
899 iview->extent.depth,
900 iview->descriptor,
901 iview->fmask_descriptor);
902 si_set_mutable_tex_desc_fields(device, image,
903 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
904 : &image->surface.u.legacy.level[range->baseMipLevel],
905 range->baseMipLevel,
906 range->baseMipLevel,
907 blk_w, is_stencil, iview->descriptor);
908 }
909
910 bool radv_layout_has_htile(const struct radv_image *image,
911 VkImageLayout layout,
912 unsigned queue_mask)
913 {
914 return image->surface.htile_size &&
915 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
916 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
917 queue_mask == (1u << RADV_QUEUE_GENERAL);
918 }
919
920 bool radv_layout_is_htile_compressed(const struct radv_image *image,
921 VkImageLayout layout,
922 unsigned queue_mask)
923 {
924 return image->surface.htile_size &&
925 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
926 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
927 queue_mask == (1u << RADV_QUEUE_GENERAL);
928 }
929
930 bool radv_layout_can_fast_clear(const struct radv_image *image,
931 VkImageLayout layout,
932 unsigned queue_mask)
933 {
934 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
935 queue_mask == (1u << RADV_QUEUE_GENERAL);
936 }
937
938
939 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
940 {
941 if (!image->exclusive)
942 return image->queue_family_mask;
943 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHX)
944 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
945 if (family == VK_QUEUE_FAMILY_IGNORED)
946 return 1u << queue_family;
947 return 1u << family;
948 }
949
950 VkResult
951 radv_CreateImage(VkDevice device,
952 const VkImageCreateInfo *pCreateInfo,
953 const VkAllocationCallbacks *pAllocator,
954 VkImage *pImage)
955 {
956 return radv_image_create(device,
957 &(struct radv_image_create_info) {
958 .vk_info = pCreateInfo,
959 .scanout = false,
960 },
961 pAllocator,
962 pImage);
963 }
964
965 void
966 radv_DestroyImage(VkDevice _device, VkImage _image,
967 const VkAllocationCallbacks *pAllocator)
968 {
969 RADV_FROM_HANDLE(radv_device, device, _device);
970 RADV_FROM_HANDLE(radv_image, image, _image);
971
972 if (!image)
973 return;
974
975 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
976 device->ws->buffer_destroy(image->bo);
977
978 vk_free2(&device->alloc, pAllocator, image);
979 }
980
981 void radv_GetImageSubresourceLayout(
982 VkDevice device,
983 VkImage _image,
984 const VkImageSubresource* pSubresource,
985 VkSubresourceLayout* pLayout)
986 {
987 RADV_FROM_HANDLE(radv_image, image, _image);
988 int level = pSubresource->mipLevel;
989 int layer = pSubresource->arrayLayer;
990 struct radeon_surf *surface = &image->surface;
991
992 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
993 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
994 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
995 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
996 pLayout->size = surface->u.legacy.level[level].slice_size;
997 if (image->type == VK_IMAGE_TYPE_3D)
998 pLayout->size *= u_minify(image->info.depth, level);
999 }
1000
1001
1002 VkResult
1003 radv_CreateImageView(VkDevice _device,
1004 const VkImageViewCreateInfo *pCreateInfo,
1005 const VkAllocationCallbacks *pAllocator,
1006 VkImageView *pView)
1007 {
1008 RADV_FROM_HANDLE(radv_device, device, _device);
1009 struct radv_image_view *view;
1010
1011 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1012 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1013 if (view == NULL)
1014 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1015
1016 radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
1017
1018 *pView = radv_image_view_to_handle(view);
1019
1020 return VK_SUCCESS;
1021 }
1022
1023 void
1024 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1025 const VkAllocationCallbacks *pAllocator)
1026 {
1027 RADV_FROM_HANDLE(radv_device, device, _device);
1028 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1029
1030 if (!iview)
1031 return;
1032 vk_free2(&device->alloc, pAllocator, iview);
1033 }
1034
1035 void radv_buffer_view_init(struct radv_buffer_view *view,
1036 struct radv_device *device,
1037 const VkBufferViewCreateInfo* pCreateInfo,
1038 struct radv_cmd_buffer *cmd_buffer)
1039 {
1040 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1041
1042 view->bo = buffer->bo;
1043 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1044 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1045 view->vk_format = pCreateInfo->format;
1046
1047 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1048 pCreateInfo->offset, view->range, view->state);
1049 }
1050
1051 VkResult
1052 radv_CreateBufferView(VkDevice _device,
1053 const VkBufferViewCreateInfo *pCreateInfo,
1054 const VkAllocationCallbacks *pAllocator,
1055 VkBufferView *pView)
1056 {
1057 RADV_FROM_HANDLE(radv_device, device, _device);
1058 struct radv_buffer_view *view;
1059
1060 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1062 if (!view)
1063 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1064
1065 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1066
1067 *pView = radv_buffer_view_to_handle(view);
1068
1069 return VK_SUCCESS;
1070 }
1071
1072 void
1073 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1074 const VkAllocationCallbacks *pAllocator)
1075 {
1076 RADV_FROM_HANDLE(radv_device, device, _device);
1077 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1078
1079 if (!view)
1080 return;
1081
1082 vk_free2(&device->alloc, pAllocator, view);
1083 }