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radv: rework the TC-compat HTILE hardware bug with COND_EXEC
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (pCreateInfo->format != format_list->pViewFormats[i])
113 return false;
114 }
115 } else {
116 return false;
117 }
118 }
119
120 return true;
121 }
122
123 static bool
124 radv_use_dcc_for_image(struct radv_device *device,
125 const struct radv_image *image,
126 const struct radv_image_create_info *create_info,
127 const VkImageCreateInfo *pCreateInfo)
128 {
129 bool dcc_compatible_formats;
130 bool blendable;
131
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device->physical_device->rad_info.chip_class < VI)
134 return false;
135
136 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
137 return false;
138
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
141 image->shareable)
142 return false;
143
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
146 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
147 return false;
148
149 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
150 return false;
151
152 /* TODO: Enable DCC for mipmaps and array layers. */
153 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
154 return false;
155
156 if (create_info->scanout)
157 return false;
158
159 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
160 * 2x can be enabled with an option.
161 */
162 if (pCreateInfo->samples > 2 ||
163 (pCreateInfo->samples == 2 &&
164 !device->physical_device->dcc_msaa_allowed))
165 return false;
166
167 /* Determine if the formats are DCC compatible. */
168 dcc_compatible_formats =
169 radv_is_colorbuffer_format_supported(pCreateInfo->format,
170 &blendable);
171
172 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
173 const struct VkImageFormatListCreateInfoKHR *format_list =
174 (const struct VkImageFormatListCreateInfoKHR *)
175 vk_find_struct_const(pCreateInfo->pNext,
176 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
177
178 /* We have to ignore the existence of the list if viewFormatCount = 0 */
179 if (format_list && format_list->viewFormatCount) {
180 /* compatibility is transitive, so we only need to check
181 * one format with everything else. */
182 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
183 if (!radv_dcc_formats_compatible(pCreateInfo->format,
184 format_list->pViewFormats[i]))
185 dcc_compatible_formats = false;
186 }
187 } else {
188 dcc_compatible_formats = false;
189 }
190 }
191
192 if (!dcc_compatible_formats)
193 return false;
194
195 return true;
196 }
197
198 static int
199 radv_init_surface(struct radv_device *device,
200 const struct radv_image *image,
201 struct radeon_surf *surface,
202 const struct radv_image_create_info *create_info)
203 {
204 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
205 unsigned array_mode = radv_choose_tiling(device, create_info);
206 const struct vk_format_description *desc =
207 vk_format_description(pCreateInfo->format);
208 bool is_depth, is_stencil;
209
210 is_depth = vk_format_has_depth(desc);
211 is_stencil = vk_format_has_stencil(desc);
212
213 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
214 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
215
216 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
217 /* align byte per element on dword */
218 if (surface->bpe == 3) {
219 surface->bpe = 4;
220 }
221 surface->flags = RADEON_SURF_SET(array_mode, MODE);
222
223 switch (pCreateInfo->imageType){
224 case VK_IMAGE_TYPE_1D:
225 if (pCreateInfo->arrayLayers > 1)
226 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
227 else
228 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
229 break;
230 case VK_IMAGE_TYPE_2D:
231 if (pCreateInfo->arrayLayers > 1)
232 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
233 else
234 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
235 break;
236 case VK_IMAGE_TYPE_3D:
237 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
238 break;
239 default:
240 unreachable("unhandled image type");
241 }
242
243 if (is_depth) {
244 surface->flags |= RADEON_SURF_ZBUFFER;
245 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
246 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
247 }
248
249 if (is_stencil)
250 surface->flags |= RADEON_SURF_SBUFFER;
251
252 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
253
254 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
255 surface->flags |= RADEON_SURF_DISABLE_DCC;
256
257 if (create_info->scanout)
258 surface->flags |= RADEON_SURF_SCANOUT;
259 return 0;
260 }
261
262 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
263 {
264 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
265 }
266
267 static inline unsigned
268 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
269 {
270 if (stencil)
271 return image->surface.u.legacy.stencil_tiling_index[level];
272 else
273 return image->surface.u.legacy.tiling_index[level];
274 }
275
276 static unsigned radv_map_swizzle(unsigned swizzle)
277 {
278 switch (swizzle) {
279 case VK_SWIZZLE_Y:
280 return V_008F0C_SQ_SEL_Y;
281 case VK_SWIZZLE_Z:
282 return V_008F0C_SQ_SEL_Z;
283 case VK_SWIZZLE_W:
284 return V_008F0C_SQ_SEL_W;
285 case VK_SWIZZLE_0:
286 return V_008F0C_SQ_SEL_0;
287 case VK_SWIZZLE_1:
288 return V_008F0C_SQ_SEL_1;
289 default: /* VK_SWIZZLE_X */
290 return V_008F0C_SQ_SEL_X;
291 }
292 }
293
294 static void
295 radv_make_buffer_descriptor(struct radv_device *device,
296 struct radv_buffer *buffer,
297 VkFormat vk_format,
298 unsigned offset,
299 unsigned range,
300 uint32_t *state)
301 {
302 const struct vk_format_description *desc;
303 unsigned stride;
304 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
305 uint64_t va = gpu_address + buffer->offset;
306 unsigned num_format, data_format;
307 int first_non_void;
308 desc = vk_format_description(vk_format);
309 first_non_void = vk_format_get_first_non_void_channel(vk_format);
310 stride = desc->block.bits / 8;
311
312 num_format = radv_translate_buffer_numformat(desc, first_non_void);
313 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
314
315 va += offset;
316 state[0] = va;
317 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
318 S_008F04_STRIDE(stride);
319
320 if (device->physical_device->rad_info.chip_class != VI && stride) {
321 range /= stride;
322 }
323
324 state[2] = range;
325 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
326 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
327 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
328 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
329 S_008F0C_NUM_FORMAT(num_format) |
330 S_008F0C_DATA_FORMAT(data_format);
331 }
332
333 static void
334 si_set_mutable_tex_desc_fields(struct radv_device *device,
335 struct radv_image *image,
336 const struct legacy_surf_level *base_level_info,
337 unsigned base_level, unsigned first_level,
338 unsigned block_width, bool is_stencil,
339 bool is_storage_image, uint32_t *state)
340 {
341 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
342 uint64_t va = gpu_address;
343 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
344 uint64_t meta_va = 0;
345 if (chip_class >= GFX9) {
346 if (is_stencil)
347 va += image->surface.u.gfx9.stencil_offset;
348 else
349 va += image->surface.u.gfx9.surf_offset;
350 } else
351 va += base_level_info->offset;
352
353 state[0] = va >> 8;
354 if (chip_class >= GFX9 ||
355 base_level_info->mode == RADEON_SURF_MODE_2D)
356 state[0] |= image->surface.tile_swizzle;
357 state[1] &= C_008F14_BASE_ADDRESS_HI;
358 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
359
360 if (chip_class >= VI) {
361 state[6] &= C_008F28_COMPRESSION_EN;
362 state[7] = 0;
363 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
364 meta_va = gpu_address + image->dcc_offset;
365 if (chip_class <= VI)
366 meta_va += base_level_info->dcc_offset;
367 } else if (!is_storage_image &&
368 radv_image_is_tc_compat_htile(image)) {
369 meta_va = gpu_address + image->htile_offset;
370 }
371
372 if (meta_va) {
373 state[6] |= S_008F28_COMPRESSION_EN(1);
374 state[7] = meta_va >> 8;
375 state[7] |= image->surface.tile_swizzle;
376 }
377 }
378
379 if (chip_class >= GFX9) {
380 state[3] &= C_008F1C_SW_MODE;
381 state[4] &= C_008F20_PITCH_GFX9;
382
383 if (is_stencil) {
384 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
385 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
386 } else {
387 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
388 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
389 }
390
391 state[5] &= C_008F24_META_DATA_ADDRESS &
392 C_008F24_META_PIPE_ALIGNED &
393 C_008F24_META_RB_ALIGNED;
394 if (meta_va) {
395 struct gfx9_surf_meta_flags meta;
396
397 if (image->dcc_offset)
398 meta = image->surface.u.gfx9.dcc;
399 else
400 meta = image->surface.u.gfx9.htile;
401
402 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
403 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
404 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
405 }
406 } else {
407 /* SI-CI-VI */
408 unsigned pitch = base_level_info->nblk_x * block_width;
409 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
410
411 state[3] &= C_008F1C_TILING_INDEX;
412 state[3] |= S_008F1C_TILING_INDEX(index);
413 state[4] &= C_008F20_PITCH_GFX6;
414 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
415 }
416 }
417
418 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
419 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
420 {
421 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
422 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
423
424 /* GFX9 allocates 1D textures as 2D. */
425 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
426 image_type = VK_IMAGE_TYPE_2D;
427 switch (image_type) {
428 case VK_IMAGE_TYPE_1D:
429 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
430 case VK_IMAGE_TYPE_2D:
431 if (nr_samples > 1)
432 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
433 else
434 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
435 case VK_IMAGE_TYPE_3D:
436 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
437 return V_008F1C_SQ_RSRC_IMG_3D;
438 else
439 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
440 default:
441 unreachable("illegal image type");
442 }
443 }
444
445 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
446 {
447 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
448
449 if (swizzle[3] == VK_SWIZZLE_X) {
450 /* For the pre-defined border color values (white, opaque
451 * black, transparent black), the only thing that matters is
452 * that the alpha channel winds up in the correct place
453 * (because the RGB channels are all the same) so either of
454 * these enumerations will work.
455 */
456 if (swizzle[2] == VK_SWIZZLE_Y)
457 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
458 else
459 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
460 } else if (swizzle[0] == VK_SWIZZLE_X) {
461 if (swizzle[1] == VK_SWIZZLE_Y)
462 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
463 else
464 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
465 } else if (swizzle[1] == VK_SWIZZLE_X) {
466 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
467 } else if (swizzle[2] == VK_SWIZZLE_X) {
468 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
469 }
470
471 return bc_swizzle;
472 }
473
474 /**
475 * Build the sampler view descriptor for a texture.
476 */
477 static void
478 si_make_texture_descriptor(struct radv_device *device,
479 struct radv_image *image,
480 bool is_storage_image,
481 VkImageViewType view_type,
482 VkFormat vk_format,
483 const VkComponentMapping *mapping,
484 unsigned first_level, unsigned last_level,
485 unsigned first_layer, unsigned last_layer,
486 unsigned width, unsigned height, unsigned depth,
487 uint32_t *state,
488 uint32_t *fmask_state)
489 {
490 const struct vk_format_description *desc;
491 enum vk_swizzle swizzle[4];
492 int first_non_void;
493 unsigned num_format, data_format, type;
494
495 desc = vk_format_description(vk_format);
496
497 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
498 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
499 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
500 } else {
501 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
502 }
503
504 first_non_void = vk_format_get_first_non_void_channel(vk_format);
505
506 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
507 if (num_format == ~0) {
508 num_format = 0;
509 }
510
511 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
512 if (data_format == ~0) {
513 data_format = 0;
514 }
515
516 /* S8 with either Z16 or Z32 HTILE need a special format. */
517 if (device->physical_device->rad_info.chip_class >= GFX9 &&
518 vk_format == VK_FORMAT_S8_UINT &&
519 radv_image_is_tc_compat_htile(image)) {
520 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
521 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
522 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
523 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
524 }
525 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
526 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
527 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
528 height = 1;
529 depth = image->info.array_size;
530 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
531 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
532 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
533 depth = image->info.array_size;
534 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
535 depth = image->info.array_size / 6;
536
537 state[0] = 0;
538 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
539 S_008F14_NUM_FORMAT_GFX6(num_format));
540 state[2] = (S_008F18_WIDTH(width - 1) |
541 S_008F18_HEIGHT(height - 1) |
542 S_008F18_PERF_MOD(4));
543 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
544 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
545 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
546 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
547 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
548 0 : first_level) |
549 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
550 util_logbase2(image->info.samples) :
551 last_level) |
552 S_008F1C_TYPE(type));
553 state[4] = 0;
554 state[5] = S_008F24_BASE_ARRAY(first_layer);
555 state[6] = 0;
556 state[7] = 0;
557
558 if (device->physical_device->rad_info.chip_class >= GFX9) {
559 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
560
561 /* Depth is the last accessible layer on Gfx9.
562 * The hw doesn't need to know the total number of layers.
563 */
564 if (type == V_008F1C_SQ_RSRC_IMG_3D)
565 state[4] |= S_008F20_DEPTH(depth - 1);
566 else
567 state[4] |= S_008F20_DEPTH(last_layer);
568
569 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
570 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
571 util_logbase2(image->info.samples) :
572 image->info.levels - 1);
573 } else {
574 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
575 state[4] |= S_008F20_DEPTH(depth - 1);
576 state[5] |= S_008F24_LAST_ARRAY(last_layer);
577 }
578 if (image->dcc_offset) {
579 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
580
581 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
582 } else {
583 /* The last dword is unused by hw. The shader uses it to clear
584 * bits in the first dword of sampler state.
585 */
586 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
587 if (first_level == last_level)
588 state[7] = C_008F30_MAX_ANISO_RATIO;
589 else
590 state[7] = 0xffffffff;
591 }
592 }
593
594 /* Initialize the sampler view for FMASK. */
595 if (radv_image_has_fmask(image)) {
596 uint32_t fmask_format, num_format;
597 uint64_t gpu_address = radv_buffer_get_va(image->bo);
598 uint64_t va;
599
600 va = gpu_address + image->offset + image->fmask.offset;
601
602 if (device->physical_device->rad_info.chip_class >= GFX9) {
603 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
604 switch (image->info.samples) {
605 case 2:
606 num_format = V_008F14_IMG_FMASK_8_2_2;
607 break;
608 case 4:
609 num_format = V_008F14_IMG_FMASK_8_4_4;
610 break;
611 case 8:
612 num_format = V_008F14_IMG_FMASK_32_8_8;
613 break;
614 default:
615 unreachable("invalid nr_samples");
616 }
617 } else {
618 switch (image->info.samples) {
619 case 2:
620 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
621 break;
622 case 4:
623 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
624 break;
625 case 8:
626 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
627 break;
628 default:
629 assert(0);
630 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
631 }
632 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
633 }
634
635 fmask_state[0] = va >> 8;
636 fmask_state[0] |= image->fmask.tile_swizzle;
637 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
638 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
639 S_008F14_NUM_FORMAT_GFX6(num_format);
640 fmask_state[2] = S_008F18_WIDTH(width - 1) |
641 S_008F18_HEIGHT(height - 1);
642 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
643 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
644 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
645 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
646 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
647 fmask_state[4] = 0;
648 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
649 fmask_state[6] = 0;
650 fmask_state[7] = 0;
651
652 if (device->physical_device->rad_info.chip_class >= GFX9) {
653 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
654 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
655 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
656 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
657 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
658 } else {
659 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
660 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
661 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
662 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
663 }
664 } else if (fmask_state)
665 memset(fmask_state, 0, 8 * 4);
666 }
667
668 static void
669 radv_query_opaque_metadata(struct radv_device *device,
670 struct radv_image *image,
671 struct radeon_bo_metadata *md)
672 {
673 static const VkComponentMapping fixedmapping;
674 uint32_t desc[8], i;
675
676 /* Metadata image format format version 1:
677 * [0] = 1 (metadata format identifier)
678 * [1] = (VENDOR_ID << 16) | PCI_ID
679 * [2:9] = image descriptor for the whole resource
680 * [2] is always 0, because the base address is cleared
681 * [9] is the DCC offset bits [39:8] from the beginning of
682 * the buffer
683 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
684 */
685 md->metadata[0] = 1; /* metadata image format version 1 */
686
687 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
688 md->metadata[1] = si_get_bo_metadata_word1(device);
689
690
691 si_make_texture_descriptor(device, image, false,
692 (VkImageViewType)image->type, image->vk_format,
693 &fixedmapping, 0, image->info.levels - 1, 0,
694 image->info.array_size - 1,
695 image->info.width, image->info.height,
696 image->info.depth,
697 desc, NULL);
698
699 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
700 image->surface.blk_w, false, false, desc);
701
702 /* Clear the base address and set the relative DCC offset. */
703 desc[0] = 0;
704 desc[1] &= C_008F14_BASE_ADDRESS_HI;
705 desc[7] = image->dcc_offset >> 8;
706
707 /* Dwords [2:9] contain the image descriptor. */
708 memcpy(&md->metadata[2], desc, sizeof(desc));
709
710 /* Dwords [10:..] contain the mipmap level offsets. */
711 if (device->physical_device->rad_info.chip_class <= VI) {
712 for (i = 0; i <= image->info.levels - 1; i++)
713 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
714 md->size_metadata = (11 + image->info.levels - 1) * 4;
715 }
716 }
717
718 void
719 radv_init_metadata(struct radv_device *device,
720 struct radv_image *image,
721 struct radeon_bo_metadata *metadata)
722 {
723 struct radeon_surf *surface = &image->surface;
724
725 memset(metadata, 0, sizeof(*metadata));
726
727 if (device->physical_device->rad_info.chip_class >= GFX9) {
728 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
729 } else {
730 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
731 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
732 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
733 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
734 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
735 metadata->u.legacy.bankw = surface->u.legacy.bankw;
736 metadata->u.legacy.bankh = surface->u.legacy.bankh;
737 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
738 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
739 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
740 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
741 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
742 }
743 radv_query_opaque_metadata(device, image, metadata);
744 }
745
746 /* The number of samples can be specified independently of the texture. */
747 static void
748 radv_image_get_fmask_info(struct radv_device *device,
749 struct radv_image *image,
750 unsigned nr_samples,
751 struct radv_fmask_info *out)
752 {
753 if (device->physical_device->rad_info.chip_class >= GFX9) {
754 out->alignment = image->surface.fmask_alignment;
755 out->size = image->surface.fmask_size;
756 out->tile_swizzle = image->surface.fmask_tile_swizzle;
757 return;
758 }
759
760 out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
761 out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
762 out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
763 out->bank_height = image->surface.u.legacy.fmask.bankh;
764 out->tile_swizzle = image->surface.fmask_tile_swizzle;
765 out->alignment = image->surface.fmask_alignment;
766 out->size = image->surface.fmask_size;
767
768 assert(!out->tile_swizzle || !image->shareable);
769 }
770
771 static void
772 radv_image_alloc_fmask(struct radv_device *device,
773 struct radv_image *image)
774 {
775 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
776
777 image->fmask.offset = align64(image->size, image->fmask.alignment);
778 image->size = image->fmask.offset + image->fmask.size;
779 image->alignment = MAX2(image->alignment, image->fmask.alignment);
780 }
781
782 static void
783 radv_image_get_cmask_info(struct radv_device *device,
784 struct radv_image *image,
785 struct radv_cmask_info *out)
786 {
787 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
788 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
789 unsigned cl_width, cl_height;
790
791 if (device->physical_device->rad_info.chip_class >= GFX9) {
792 out->alignment = image->surface.cmask_alignment;
793 out->size = image->surface.cmask_size;
794 return;
795 }
796
797 switch (num_pipes) {
798 case 2:
799 cl_width = 32;
800 cl_height = 16;
801 break;
802 case 4:
803 cl_width = 32;
804 cl_height = 32;
805 break;
806 case 8:
807 cl_width = 64;
808 cl_height = 32;
809 break;
810 case 16: /* Hawaii */
811 cl_width = 64;
812 cl_height = 64;
813 break;
814 default:
815 assert(0);
816 return;
817 }
818
819 unsigned base_align = num_pipes * pipe_interleave_bytes;
820
821 unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
822 unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
823 unsigned slice_elements = (width * height) / (8*8);
824
825 /* Each element of CMASK is a nibble. */
826 unsigned slice_bytes = slice_elements / 2;
827
828 out->slice_tile_max = (width * height) / (128*128);
829 if (out->slice_tile_max)
830 out->slice_tile_max -= 1;
831
832 out->alignment = MAX2(256, base_align);
833 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
834 align(slice_bytes, base_align);
835 }
836
837 static void
838 radv_image_alloc_cmask(struct radv_device *device,
839 struct radv_image *image)
840 {
841 uint32_t clear_value_size = 0;
842 radv_image_get_cmask_info(device, image, &image->cmask);
843
844 image->cmask.offset = align64(image->size, image->cmask.alignment);
845 /* + 8 for storing the clear values */
846 if (!image->clear_value_offset) {
847 image->clear_value_offset = image->cmask.offset + image->cmask.size;
848 clear_value_size = 8;
849 }
850 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
851 image->alignment = MAX2(image->alignment, image->cmask.alignment);
852 }
853
854 static void
855 radv_image_alloc_dcc(struct radv_image *image)
856 {
857 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
858 /* + 16 for storing the clear values + dcc pred */
859 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
860 image->fce_pred_offset = image->clear_value_offset + 8;
861 image->size = image->dcc_offset + image->surface.dcc_size + 16;
862 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
863 }
864
865 static void
866 radv_image_alloc_htile(struct radv_image *image)
867 {
868 image->htile_offset = align64(image->size, image->surface.htile_alignment);
869
870 /* + 8 for storing the clear values */
871 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
872 image->size = image->clear_value_offset + 8;
873 if (radv_image_is_tc_compat_htile(image)) {
874 /* Metadata for the TC-compatible HTILE hardware bug which
875 * have to be fixed by updating ZRANGE_PRECISION when doing
876 * fast depth clears to 0.0f.
877 */
878 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
879 image->size = image->clear_value_offset + 16;
880 }
881 image->alignment = align64(image->alignment, image->surface.htile_alignment);
882 }
883
884 static inline bool
885 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
886 {
887 if (image->info.samples <= 1 &&
888 image->info.width * image->info.height <= 512 * 512) {
889 /* Do not enable CMASK or DCC for small surfaces where the cost
890 * of the eliminate pass can be higher than the benefit of fast
891 * clear. RadeonSI does this, but the image threshold is
892 * different.
893 */
894 return false;
895 }
896
897 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
898 (image->exclusive || image->queue_family_mask == 1);
899 }
900
901 static inline bool
902 radv_image_can_enable_dcc(struct radv_image *image)
903 {
904 return radv_image_can_enable_dcc_or_cmask(image) &&
905 radv_image_has_dcc(image);
906 }
907
908 static inline bool
909 radv_image_can_enable_cmask(struct radv_image *image)
910 {
911 if (image->surface.bpe > 8 && image->info.samples == 1) {
912 /* Do not enable CMASK for non-MSAA images (fast color clear)
913 * because 128 bit formats are not supported, but FMASK might
914 * still be used.
915 */
916 return false;
917 }
918
919 return radv_image_can_enable_dcc_or_cmask(image) &&
920 image->info.levels == 1 &&
921 image->info.depth == 1 &&
922 !image->surface.is_linear;
923 }
924
925 static inline bool
926 radv_image_can_enable_fmask(struct radv_image *image)
927 {
928 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
929 }
930
931 static inline bool
932 radv_image_can_enable_htile(struct radv_image *image)
933 {
934 return image->info.levels == 1 &&
935 vk_format_is_depth(image->vk_format) &&
936 image->info.width * image->info.height >= 8 * 8;
937 }
938
939 VkResult
940 radv_image_create(VkDevice _device,
941 const struct radv_image_create_info *create_info,
942 const VkAllocationCallbacks* alloc,
943 VkImage *pImage)
944 {
945 RADV_FROM_HANDLE(radv_device, device, _device);
946 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
947 struct radv_image *image = NULL;
948 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
949
950 radv_assert(pCreateInfo->mipLevels > 0);
951 radv_assert(pCreateInfo->arrayLayers > 0);
952 radv_assert(pCreateInfo->samples > 0);
953 radv_assert(pCreateInfo->extent.width > 0);
954 radv_assert(pCreateInfo->extent.height > 0);
955 radv_assert(pCreateInfo->extent.depth > 0);
956
957 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
958 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
959 if (!image)
960 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
961
962 image->type = pCreateInfo->imageType;
963 image->info.width = pCreateInfo->extent.width;
964 image->info.height = pCreateInfo->extent.height;
965 image->info.depth = pCreateInfo->extent.depth;
966 image->info.samples = pCreateInfo->samples;
967 image->info.storage_samples = pCreateInfo->samples;
968 image->info.array_size = pCreateInfo->arrayLayers;
969 image->info.levels = pCreateInfo->mipLevels;
970 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
971
972 image->vk_format = pCreateInfo->format;
973 image->tiling = pCreateInfo->tiling;
974 image->usage = pCreateInfo->usage;
975 image->flags = pCreateInfo->flags;
976
977 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
978 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
979 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
980 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
981 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
982 else
983 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
984 }
985
986 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
987 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
988 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
989 image->info.surf_index = &device->image_mrt_offset_counter;
990 }
991
992 radv_init_surface(device, image, &image->surface, create_info);
993
994 device->ws->surface_init(device->ws, &image->info, &image->surface);
995
996 image->size = image->surface.surf_size;
997 image->alignment = image->surface.surf_alignment;
998
999 if (!create_info->no_metadata_planes) {
1000 /* Try to enable DCC first. */
1001 if (radv_image_can_enable_dcc(image)) {
1002 radv_image_alloc_dcc(image);
1003 if (image->info.samples > 1) {
1004 /* CMASK should be enabled because DCC fast
1005 * clear with MSAA needs it.
1006 */
1007 assert(radv_image_can_enable_cmask(image));
1008 radv_image_alloc_cmask(device, image);
1009 }
1010 } else {
1011 /* When DCC cannot be enabled, try CMASK. */
1012 image->surface.dcc_size = 0;
1013 if (radv_image_can_enable_cmask(image)) {
1014 radv_image_alloc_cmask(device, image);
1015 }
1016 }
1017
1018 /* Try to enable FMASK for multisampled images. */
1019 if (radv_image_can_enable_fmask(image)) {
1020 radv_image_alloc_fmask(device, image);
1021 } else {
1022 /* Otherwise, try to enable HTILE for depth surfaces. */
1023 if (radv_image_can_enable_htile(image) &&
1024 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1025 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1026 radv_image_alloc_htile(image);
1027 } else {
1028 image->surface.htile_size = 0;
1029 }
1030 }
1031 } else {
1032 image->surface.dcc_size = 0;
1033 image->surface.htile_size = 0;
1034 }
1035
1036 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1037 image->alignment = MAX2(image->alignment, 4096);
1038 image->size = align64(image->size, image->alignment);
1039 image->offset = 0;
1040
1041 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1042 0, RADEON_FLAG_VIRTUAL);
1043 if (!image->bo) {
1044 vk_free2(&device->alloc, alloc, image);
1045 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1046 }
1047 }
1048
1049 *pImage = radv_image_to_handle(image);
1050
1051 return VK_SUCCESS;
1052 }
1053
1054 static void
1055 radv_image_view_make_descriptor(struct radv_image_view *iview,
1056 struct radv_device *device,
1057 const VkComponentMapping *components,
1058 bool is_storage_image)
1059 {
1060 struct radv_image *image = iview->image;
1061 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1062 uint32_t blk_w;
1063 uint32_t *descriptor;
1064 uint32_t hw_level = 0;
1065
1066 if (is_storage_image) {
1067 descriptor = iview->storage_descriptor;
1068 } else {
1069 descriptor = iview->descriptor;
1070 }
1071
1072 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1073 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1074
1075 if (device->physical_device->rad_info.chip_class >= GFX9)
1076 hw_level = iview->base_mip;
1077 si_make_texture_descriptor(device, image, is_storage_image,
1078 iview->type,
1079 iview->vk_format,
1080 components,
1081 hw_level, hw_level + iview->level_count - 1,
1082 iview->base_layer,
1083 iview->base_layer + iview->layer_count - 1,
1084 iview->extent.width,
1085 iview->extent.height,
1086 iview->extent.depth,
1087 descriptor,
1088 descriptor + 8);
1089
1090 const struct legacy_surf_level *base_level_info = NULL;
1091 if (device->physical_device->rad_info.chip_class <= GFX9) {
1092 if (is_stencil)
1093 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1094 else
1095 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1096 }
1097 si_set_mutable_tex_desc_fields(device, image,
1098 base_level_info,
1099 iview->base_mip,
1100 iview->base_mip,
1101 blk_w, is_stencil, is_storage_image, descriptor);
1102 }
1103
1104 void
1105 radv_image_view_init(struct radv_image_view *iview,
1106 struct radv_device *device,
1107 const VkImageViewCreateInfo* pCreateInfo)
1108 {
1109 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1110 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1111
1112 switch (image->type) {
1113 case VK_IMAGE_TYPE_1D:
1114 case VK_IMAGE_TYPE_2D:
1115 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1116 break;
1117 case VK_IMAGE_TYPE_3D:
1118 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1119 <= radv_minify(image->info.depth, range->baseMipLevel));
1120 break;
1121 default:
1122 unreachable("bad VkImageType");
1123 }
1124 iview->image = image;
1125 iview->bo = image->bo;
1126 iview->type = pCreateInfo->viewType;
1127 iview->vk_format = pCreateInfo->format;
1128 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1129
1130 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1131 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1132 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1133 iview->vk_format = vk_format_depth_only(iview->vk_format);
1134 }
1135
1136 if (device->physical_device->rad_info.chip_class >= GFX9) {
1137 iview->extent = (VkExtent3D) {
1138 .width = image->info.width,
1139 .height = image->info.height,
1140 .depth = image->info.depth,
1141 };
1142 } else {
1143 iview->extent = (VkExtent3D) {
1144 .width = radv_minify(image->info.width , range->baseMipLevel),
1145 .height = radv_minify(image->info.height, range->baseMipLevel),
1146 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1147 };
1148 }
1149
1150 if (iview->vk_format != image->vk_format) {
1151 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1152 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1153 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1154 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1155
1156 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1157 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1158
1159 /* Comment ported from amdvlk -
1160 * If we have the following image:
1161 * Uncompressed pixels Compressed block sizes (4x4)
1162 * mip0: 22 x 22 6 x 6
1163 * mip1: 11 x 11 3 x 3
1164 * mip2: 5 x 5 2 x 2
1165 * mip3: 2 x 2 1 x 1
1166 * mip4: 1 x 1 1 x 1
1167 *
1168 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1169 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1170 * divide-by-two integer math):
1171 * mip0: 6x6
1172 * mip1: 3x3
1173 * mip2: 1x1
1174 * mip3: 1x1
1175 *
1176 * This means that mip2 will be missing texels.
1177 *
1178 * Fix this by calculating the base mip's width and height, then convert that, and round it
1179 * back up to get the level 0 size.
1180 * Clamp the converted size between the original values, and next power of two, which
1181 * means we don't oversize the image.
1182 */
1183 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1184 vk_format_is_compressed(image->vk_format) &&
1185 !vk_format_is_compressed(iview->vk_format)) {
1186 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1187 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1188
1189 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1190 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1191
1192 lvl_width <<= range->baseMipLevel;
1193 lvl_height <<= range->baseMipLevel;
1194
1195 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
1196 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
1197 }
1198 }
1199
1200 iview->base_layer = range->baseArrayLayer;
1201 iview->layer_count = radv_get_layerCount(image, range);
1202 iview->base_mip = range->baseMipLevel;
1203 iview->level_count = radv_get_levelCount(image, range);
1204
1205 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1206 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1207 }
1208
1209 bool radv_layout_has_htile(const struct radv_image *image,
1210 VkImageLayout layout,
1211 unsigned queue_mask)
1212 {
1213 if (radv_image_is_tc_compat_htile(image))
1214 return layout != VK_IMAGE_LAYOUT_GENERAL;
1215
1216 return radv_image_has_htile(image) &&
1217 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1218 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1219 queue_mask == (1u << RADV_QUEUE_GENERAL);
1220 }
1221
1222 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1223 VkImageLayout layout,
1224 unsigned queue_mask)
1225 {
1226 if (radv_image_is_tc_compat_htile(image))
1227 return layout != VK_IMAGE_LAYOUT_GENERAL;
1228
1229 return radv_image_has_htile(image) &&
1230 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1231 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1232 queue_mask == (1u << RADV_QUEUE_GENERAL);
1233 }
1234
1235 bool radv_layout_can_fast_clear(const struct radv_image *image,
1236 VkImageLayout layout,
1237 unsigned queue_mask)
1238 {
1239 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1240 queue_mask == (1u << RADV_QUEUE_GENERAL);
1241 }
1242
1243 bool radv_layout_dcc_compressed(const struct radv_image *image,
1244 VkImageLayout layout,
1245 unsigned queue_mask)
1246 {
1247 /* Don't compress compute transfer dst, as image stores are not supported. */
1248 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1249 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1250 return false;
1251
1252 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1253 }
1254
1255
1256 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1257 {
1258 if (!image->exclusive)
1259 return image->queue_family_mask;
1260 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1261 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1262 if (family == VK_QUEUE_FAMILY_IGNORED)
1263 return 1u << queue_family;
1264 return 1u << family;
1265 }
1266
1267 VkResult
1268 radv_CreateImage(VkDevice device,
1269 const VkImageCreateInfo *pCreateInfo,
1270 const VkAllocationCallbacks *pAllocator,
1271 VkImage *pImage)
1272 {
1273 #ifdef ANDROID
1274 const VkNativeBufferANDROID *gralloc_info =
1275 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1276
1277 if (gralloc_info)
1278 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1279 pAllocator, pImage);
1280 #endif
1281
1282 const struct wsi_image_create_info *wsi_info =
1283 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1284 bool scanout = wsi_info && wsi_info->scanout;
1285
1286 return radv_image_create(device,
1287 &(struct radv_image_create_info) {
1288 .vk_info = pCreateInfo,
1289 .scanout = scanout,
1290 },
1291 pAllocator,
1292 pImage);
1293 }
1294
1295 void
1296 radv_DestroyImage(VkDevice _device, VkImage _image,
1297 const VkAllocationCallbacks *pAllocator)
1298 {
1299 RADV_FROM_HANDLE(radv_device, device, _device);
1300 RADV_FROM_HANDLE(radv_image, image, _image);
1301
1302 if (!image)
1303 return;
1304
1305 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1306 device->ws->buffer_destroy(image->bo);
1307
1308 if (image->owned_memory != VK_NULL_HANDLE)
1309 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1310
1311 vk_free2(&device->alloc, pAllocator, image);
1312 }
1313
1314 void radv_GetImageSubresourceLayout(
1315 VkDevice _device,
1316 VkImage _image,
1317 const VkImageSubresource* pSubresource,
1318 VkSubresourceLayout* pLayout)
1319 {
1320 RADV_FROM_HANDLE(radv_image, image, _image);
1321 RADV_FROM_HANDLE(radv_device, device, _device);
1322 int level = pSubresource->mipLevel;
1323 int layer = pSubresource->arrayLayer;
1324 struct radeon_surf *surface = &image->surface;
1325
1326 if (device->physical_device->rad_info.chip_class >= GFX9) {
1327 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1328 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1329 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1330 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1331 pLayout->size = surface->u.gfx9.surf_slice_size;
1332 if (image->type == VK_IMAGE_TYPE_3D)
1333 pLayout->size *= u_minify(image->info.depth, level);
1334 } else {
1335 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1336 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1337 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1338 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1339 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1340 if (image->type == VK_IMAGE_TYPE_3D)
1341 pLayout->size *= u_minify(image->info.depth, level);
1342 }
1343 }
1344
1345
1346 VkResult
1347 radv_CreateImageView(VkDevice _device,
1348 const VkImageViewCreateInfo *pCreateInfo,
1349 const VkAllocationCallbacks *pAllocator,
1350 VkImageView *pView)
1351 {
1352 RADV_FROM_HANDLE(radv_device, device, _device);
1353 struct radv_image_view *view;
1354
1355 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1356 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1357 if (view == NULL)
1358 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1359
1360 radv_image_view_init(view, device, pCreateInfo);
1361
1362 *pView = radv_image_view_to_handle(view);
1363
1364 return VK_SUCCESS;
1365 }
1366
1367 void
1368 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1369 const VkAllocationCallbacks *pAllocator)
1370 {
1371 RADV_FROM_HANDLE(radv_device, device, _device);
1372 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1373
1374 if (!iview)
1375 return;
1376 vk_free2(&device->alloc, pAllocator, iview);
1377 }
1378
1379 void radv_buffer_view_init(struct radv_buffer_view *view,
1380 struct radv_device *device,
1381 const VkBufferViewCreateInfo* pCreateInfo)
1382 {
1383 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1384
1385 view->bo = buffer->bo;
1386 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1387 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1388 view->vk_format = pCreateInfo->format;
1389
1390 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1391 pCreateInfo->offset, view->range, view->state);
1392 }
1393
1394 VkResult
1395 radv_CreateBufferView(VkDevice _device,
1396 const VkBufferViewCreateInfo *pCreateInfo,
1397 const VkAllocationCallbacks *pAllocator,
1398 VkBufferView *pView)
1399 {
1400 RADV_FROM_HANDLE(radv_device, device, _device);
1401 struct radv_buffer_view *view;
1402
1403 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1405 if (!view)
1406 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1407
1408 radv_buffer_view_init(view, device, pCreateInfo);
1409
1410 *pView = radv_buffer_view_to_handle(view);
1411
1412 return VK_SUCCESS;
1413 }
1414
1415 void
1416 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1417 const VkAllocationCallbacks *pAllocator)
1418 {
1419 RADV_FROM_HANDLE(radv_device, device, _device);
1420 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1421
1422 if (!view)
1423 return;
1424
1425 vk_free2(&device->alloc, pAllocator, view);
1426 }