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radv: Allow fast clears with concurrent queue mask for some layouts.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (pCreateInfo->format != format_list->pViewFormats[i])
113 return false;
114 }
115 } else {
116 return false;
117 }
118 }
119
120 return true;
121 }
122
123 static bool
124 radv_use_dcc_for_image(struct radv_device *device,
125 const struct radv_image *image,
126 const struct radv_image_create_info *create_info,
127 const VkImageCreateInfo *pCreateInfo)
128 {
129 bool dcc_compatible_formats;
130 bool blendable;
131
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device->physical_device->rad_info.chip_class < VI)
134 return false;
135
136 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
137 return false;
138
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
141 image->shareable)
142 return false;
143
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
146 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
147 return false;
148
149 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
150 return false;
151
152 /* TODO: Enable DCC for mipmaps and array layers. */
153 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
154 return false;
155
156 if (create_info->scanout)
157 return false;
158
159 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
160 * 2x can be enabled with an option.
161 */
162 if (pCreateInfo->samples > 2 ||
163 (pCreateInfo->samples == 2 &&
164 !device->physical_device->dcc_msaa_allowed))
165 return false;
166
167 /* Determine if the formats are DCC compatible. */
168 dcc_compatible_formats =
169 radv_is_colorbuffer_format_supported(pCreateInfo->format,
170 &blendable);
171
172 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
173 const struct VkImageFormatListCreateInfoKHR *format_list =
174 (const struct VkImageFormatListCreateInfoKHR *)
175 vk_find_struct_const(pCreateInfo->pNext,
176 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
177
178 /* We have to ignore the existence of the list if viewFormatCount = 0 */
179 if (format_list && format_list->viewFormatCount) {
180 /* compatibility is transitive, so we only need to check
181 * one format with everything else. */
182 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
183 if (!radv_dcc_formats_compatible(pCreateInfo->format,
184 format_list->pViewFormats[i]))
185 dcc_compatible_formats = false;
186 }
187 } else {
188 dcc_compatible_formats = false;
189 }
190 }
191
192 if (!dcc_compatible_formats)
193 return false;
194
195 return true;
196 }
197
198 static int
199 radv_init_surface(struct radv_device *device,
200 const struct radv_image *image,
201 struct radeon_surf *surface,
202 const struct radv_image_create_info *create_info)
203 {
204 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
205 unsigned array_mode = radv_choose_tiling(device, create_info);
206 const struct vk_format_description *desc =
207 vk_format_description(pCreateInfo->format);
208 bool is_depth, is_stencil;
209
210 is_depth = vk_format_has_depth(desc);
211 is_stencil = vk_format_has_stencil(desc);
212
213 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
214 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
215
216 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
217 /* align byte per element on dword */
218 if (surface->bpe == 3) {
219 surface->bpe = 4;
220 }
221 surface->flags = RADEON_SURF_SET(array_mode, MODE);
222
223 switch (pCreateInfo->imageType){
224 case VK_IMAGE_TYPE_1D:
225 if (pCreateInfo->arrayLayers > 1)
226 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
227 else
228 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
229 break;
230 case VK_IMAGE_TYPE_2D:
231 if (pCreateInfo->arrayLayers > 1)
232 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
233 else
234 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
235 break;
236 case VK_IMAGE_TYPE_3D:
237 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
238 break;
239 default:
240 unreachable("unhandled image type");
241 }
242
243 if (is_depth) {
244 surface->flags |= RADEON_SURF_ZBUFFER;
245 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
246 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
247 }
248
249 if (is_stencil)
250 surface->flags |= RADEON_SURF_SBUFFER;
251
252 if (device->physical_device->rad_info.chip_class >= GFX9 &&
253 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
254 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
255 vk_format_is_compressed(pCreateInfo->format))
256 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
257
258 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
259
260 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
261 surface->flags |= RADEON_SURF_DISABLE_DCC;
262
263 if (create_info->scanout)
264 surface->flags |= RADEON_SURF_SCANOUT;
265 return 0;
266 }
267
268 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
269 {
270 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
271 }
272
273 static inline unsigned
274 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
275 {
276 if (stencil)
277 return image->surface.u.legacy.stencil_tiling_index[level];
278 else
279 return image->surface.u.legacy.tiling_index[level];
280 }
281
282 static unsigned radv_map_swizzle(unsigned swizzle)
283 {
284 switch (swizzle) {
285 case VK_SWIZZLE_Y:
286 return V_008F0C_SQ_SEL_Y;
287 case VK_SWIZZLE_Z:
288 return V_008F0C_SQ_SEL_Z;
289 case VK_SWIZZLE_W:
290 return V_008F0C_SQ_SEL_W;
291 case VK_SWIZZLE_0:
292 return V_008F0C_SQ_SEL_0;
293 case VK_SWIZZLE_1:
294 return V_008F0C_SQ_SEL_1;
295 default: /* VK_SWIZZLE_X */
296 return V_008F0C_SQ_SEL_X;
297 }
298 }
299
300 static void
301 radv_make_buffer_descriptor(struct radv_device *device,
302 struct radv_buffer *buffer,
303 VkFormat vk_format,
304 unsigned offset,
305 unsigned range,
306 uint32_t *state)
307 {
308 const struct vk_format_description *desc;
309 unsigned stride;
310 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
311 uint64_t va = gpu_address + buffer->offset;
312 unsigned num_format, data_format;
313 int first_non_void;
314 desc = vk_format_description(vk_format);
315 first_non_void = vk_format_get_first_non_void_channel(vk_format);
316 stride = desc->block.bits / 8;
317
318 num_format = radv_translate_buffer_numformat(desc, first_non_void);
319 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
320
321 va += offset;
322 state[0] = va;
323 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
324 S_008F04_STRIDE(stride);
325
326 if (device->physical_device->rad_info.chip_class != VI && stride) {
327 range /= stride;
328 }
329
330 state[2] = range;
331 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
332 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
333 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
334 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
335 S_008F0C_NUM_FORMAT(num_format) |
336 S_008F0C_DATA_FORMAT(data_format);
337 }
338
339 static void
340 si_set_mutable_tex_desc_fields(struct radv_device *device,
341 struct radv_image *image,
342 const struct legacy_surf_level *base_level_info,
343 unsigned base_level, unsigned first_level,
344 unsigned block_width, bool is_stencil,
345 bool is_storage_image, uint32_t *state)
346 {
347 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
348 uint64_t va = gpu_address;
349 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
350 uint64_t meta_va = 0;
351 if (chip_class >= GFX9) {
352 if (is_stencil)
353 va += image->surface.u.gfx9.stencil_offset;
354 else
355 va += image->surface.u.gfx9.surf_offset;
356 } else
357 va += base_level_info->offset;
358
359 state[0] = va >> 8;
360 if (chip_class >= GFX9 ||
361 base_level_info->mode == RADEON_SURF_MODE_2D)
362 state[0] |= image->surface.tile_swizzle;
363 state[1] &= C_008F14_BASE_ADDRESS_HI;
364 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
365
366 if (chip_class >= VI) {
367 state[6] &= C_008F28_COMPRESSION_EN;
368 state[7] = 0;
369 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
370 meta_va = gpu_address + image->dcc_offset;
371 if (chip_class <= VI)
372 meta_va += base_level_info->dcc_offset;
373 } else if (!is_storage_image &&
374 radv_image_is_tc_compat_htile(image)) {
375 meta_va = gpu_address + image->htile_offset;
376 }
377
378 if (meta_va) {
379 state[6] |= S_008F28_COMPRESSION_EN(1);
380 state[7] = meta_va >> 8;
381 state[7] |= image->surface.tile_swizzle;
382 }
383 }
384
385 if (chip_class >= GFX9) {
386 state[3] &= C_008F1C_SW_MODE;
387 state[4] &= C_008F20_PITCH_GFX9;
388
389 if (is_stencil) {
390 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
391 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
392 } else {
393 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
394 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
395 }
396
397 state[5] &= C_008F24_META_DATA_ADDRESS &
398 C_008F24_META_PIPE_ALIGNED &
399 C_008F24_META_RB_ALIGNED;
400 if (meta_va) {
401 struct gfx9_surf_meta_flags meta;
402
403 if (image->dcc_offset)
404 meta = image->surface.u.gfx9.dcc;
405 else
406 meta = image->surface.u.gfx9.htile;
407
408 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
409 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
410 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
411 }
412 } else {
413 /* SI-CI-VI */
414 unsigned pitch = base_level_info->nblk_x * block_width;
415 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
416
417 state[3] &= C_008F1C_TILING_INDEX;
418 state[3] |= S_008F1C_TILING_INDEX(index);
419 state[4] &= C_008F20_PITCH_GFX6;
420 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
421 }
422 }
423
424 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
425 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
426 {
427 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
428 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
429
430 /* GFX9 allocates 1D textures as 2D. */
431 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
432 image_type = VK_IMAGE_TYPE_2D;
433 switch (image_type) {
434 case VK_IMAGE_TYPE_1D:
435 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
436 case VK_IMAGE_TYPE_2D:
437 if (nr_samples > 1)
438 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
439 else
440 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
441 case VK_IMAGE_TYPE_3D:
442 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
443 return V_008F1C_SQ_RSRC_IMG_3D;
444 else
445 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
446 default:
447 unreachable("illegal image type");
448 }
449 }
450
451 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
452 {
453 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
454
455 if (swizzle[3] == VK_SWIZZLE_X) {
456 /* For the pre-defined border color values (white, opaque
457 * black, transparent black), the only thing that matters is
458 * that the alpha channel winds up in the correct place
459 * (because the RGB channels are all the same) so either of
460 * these enumerations will work.
461 */
462 if (swizzle[2] == VK_SWIZZLE_Y)
463 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
464 else
465 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
466 } else if (swizzle[0] == VK_SWIZZLE_X) {
467 if (swizzle[1] == VK_SWIZZLE_Y)
468 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
469 else
470 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
471 } else if (swizzle[1] == VK_SWIZZLE_X) {
472 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
473 } else if (swizzle[2] == VK_SWIZZLE_X) {
474 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
475 }
476
477 return bc_swizzle;
478 }
479
480 /**
481 * Build the sampler view descriptor for a texture.
482 */
483 static void
484 si_make_texture_descriptor(struct radv_device *device,
485 struct radv_image *image,
486 bool is_storage_image,
487 VkImageViewType view_type,
488 VkFormat vk_format,
489 const VkComponentMapping *mapping,
490 unsigned first_level, unsigned last_level,
491 unsigned first_layer, unsigned last_layer,
492 unsigned width, unsigned height, unsigned depth,
493 uint32_t *state,
494 uint32_t *fmask_state)
495 {
496 const struct vk_format_description *desc;
497 enum vk_swizzle swizzle[4];
498 int first_non_void;
499 unsigned num_format, data_format, type;
500
501 desc = vk_format_description(vk_format);
502
503 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
504 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
505 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
506 } else {
507 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
508 }
509
510 first_non_void = vk_format_get_first_non_void_channel(vk_format);
511
512 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
513 if (num_format == ~0) {
514 num_format = 0;
515 }
516
517 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
518 if (data_format == ~0) {
519 data_format = 0;
520 }
521
522 /* S8 with either Z16 or Z32 HTILE need a special format. */
523 if (device->physical_device->rad_info.chip_class >= GFX9 &&
524 vk_format == VK_FORMAT_S8_UINT &&
525 radv_image_is_tc_compat_htile(image)) {
526 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
527 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
528 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
529 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
530 }
531 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
532 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
533 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
534 height = 1;
535 depth = image->info.array_size;
536 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
537 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
538 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
539 depth = image->info.array_size;
540 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
541 depth = image->info.array_size / 6;
542
543 state[0] = 0;
544 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
545 S_008F14_NUM_FORMAT_GFX6(num_format));
546 state[2] = (S_008F18_WIDTH(width - 1) |
547 S_008F18_HEIGHT(height - 1) |
548 S_008F18_PERF_MOD(4));
549 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
550 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
551 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
552 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
553 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
554 0 : first_level) |
555 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
556 util_logbase2(image->info.samples) :
557 last_level) |
558 S_008F1C_TYPE(type));
559 state[4] = 0;
560 state[5] = S_008F24_BASE_ARRAY(first_layer);
561 state[6] = 0;
562 state[7] = 0;
563
564 if (device->physical_device->rad_info.chip_class >= GFX9) {
565 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
566
567 /* Depth is the last accessible layer on Gfx9.
568 * The hw doesn't need to know the total number of layers.
569 */
570 if (type == V_008F1C_SQ_RSRC_IMG_3D)
571 state[4] |= S_008F20_DEPTH(depth - 1);
572 else
573 state[4] |= S_008F20_DEPTH(last_layer);
574
575 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
576 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
577 util_logbase2(image->info.samples) :
578 image->info.levels - 1);
579 } else {
580 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
581 state[4] |= S_008F20_DEPTH(depth - 1);
582 state[5] |= S_008F24_LAST_ARRAY(last_layer);
583 }
584 if (image->dcc_offset) {
585 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
586
587 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
588 } else {
589 /* The last dword is unused by hw. The shader uses it to clear
590 * bits in the first dword of sampler state.
591 */
592 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
593 if (first_level == last_level)
594 state[7] = C_008F30_MAX_ANISO_RATIO;
595 else
596 state[7] = 0xffffffff;
597 }
598 }
599
600 /* Initialize the sampler view for FMASK. */
601 if (radv_image_has_fmask(image)) {
602 uint32_t fmask_format, num_format;
603 uint64_t gpu_address = radv_buffer_get_va(image->bo);
604 uint64_t va;
605
606 va = gpu_address + image->offset + image->fmask.offset;
607
608 if (device->physical_device->rad_info.chip_class >= GFX9) {
609 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
610 switch (image->info.samples) {
611 case 2:
612 num_format = V_008F14_IMG_FMASK_8_2_2;
613 break;
614 case 4:
615 num_format = V_008F14_IMG_FMASK_8_4_4;
616 break;
617 case 8:
618 num_format = V_008F14_IMG_FMASK_32_8_8;
619 break;
620 default:
621 unreachable("invalid nr_samples");
622 }
623 } else {
624 switch (image->info.samples) {
625 case 2:
626 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
627 break;
628 case 4:
629 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
630 break;
631 case 8:
632 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
633 break;
634 default:
635 assert(0);
636 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
637 }
638 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
639 }
640
641 fmask_state[0] = va >> 8;
642 fmask_state[0] |= image->fmask.tile_swizzle;
643 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
644 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
645 S_008F14_NUM_FORMAT_GFX6(num_format);
646 fmask_state[2] = S_008F18_WIDTH(width - 1) |
647 S_008F18_HEIGHT(height - 1);
648 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
649 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
650 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
651 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
652 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
653 fmask_state[4] = 0;
654 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
655 fmask_state[6] = 0;
656 fmask_state[7] = 0;
657
658 if (device->physical_device->rad_info.chip_class >= GFX9) {
659 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
660 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
661 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
662 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
663 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
664 } else {
665 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
666 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
667 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
668 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
669 }
670 } else if (fmask_state)
671 memset(fmask_state, 0, 8 * 4);
672 }
673
674 static void
675 radv_query_opaque_metadata(struct radv_device *device,
676 struct radv_image *image,
677 struct radeon_bo_metadata *md)
678 {
679 static const VkComponentMapping fixedmapping;
680 uint32_t desc[8], i;
681
682 /* Metadata image format format version 1:
683 * [0] = 1 (metadata format identifier)
684 * [1] = (VENDOR_ID << 16) | PCI_ID
685 * [2:9] = image descriptor for the whole resource
686 * [2] is always 0, because the base address is cleared
687 * [9] is the DCC offset bits [39:8] from the beginning of
688 * the buffer
689 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
690 */
691 md->metadata[0] = 1; /* metadata image format version 1 */
692
693 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
694 md->metadata[1] = si_get_bo_metadata_word1(device);
695
696
697 si_make_texture_descriptor(device, image, false,
698 (VkImageViewType)image->type, image->vk_format,
699 &fixedmapping, 0, image->info.levels - 1, 0,
700 image->info.array_size - 1,
701 image->info.width, image->info.height,
702 image->info.depth,
703 desc, NULL);
704
705 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
706 image->surface.blk_w, false, false, desc);
707
708 /* Clear the base address and set the relative DCC offset. */
709 desc[0] = 0;
710 desc[1] &= C_008F14_BASE_ADDRESS_HI;
711 desc[7] = image->dcc_offset >> 8;
712
713 /* Dwords [2:9] contain the image descriptor. */
714 memcpy(&md->metadata[2], desc, sizeof(desc));
715
716 /* Dwords [10:..] contain the mipmap level offsets. */
717 if (device->physical_device->rad_info.chip_class <= VI) {
718 for (i = 0; i <= image->info.levels - 1; i++)
719 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
720 md->size_metadata = (11 + image->info.levels - 1) * 4;
721 }
722 }
723
724 void
725 radv_init_metadata(struct radv_device *device,
726 struct radv_image *image,
727 struct radeon_bo_metadata *metadata)
728 {
729 struct radeon_surf *surface = &image->surface;
730
731 memset(metadata, 0, sizeof(*metadata));
732
733 if (device->physical_device->rad_info.chip_class >= GFX9) {
734 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
735 } else {
736 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
737 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
738 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
739 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
740 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
741 metadata->u.legacy.bankw = surface->u.legacy.bankw;
742 metadata->u.legacy.bankh = surface->u.legacy.bankh;
743 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
744 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
745 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
746 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
747 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
748 }
749 radv_query_opaque_metadata(device, image, metadata);
750 }
751
752 /* The number of samples can be specified independently of the texture. */
753 static void
754 radv_image_get_fmask_info(struct radv_device *device,
755 struct radv_image *image,
756 unsigned nr_samples,
757 struct radv_fmask_info *out)
758 {
759 if (device->physical_device->rad_info.chip_class >= GFX9) {
760 out->alignment = image->surface.fmask_alignment;
761 out->size = image->surface.fmask_size;
762 out->tile_swizzle = image->surface.fmask_tile_swizzle;
763 return;
764 }
765
766 out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
767 out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
768 out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
769 out->bank_height = image->surface.u.legacy.fmask.bankh;
770 out->tile_swizzle = image->surface.fmask_tile_swizzle;
771 out->alignment = image->surface.fmask_alignment;
772 out->size = image->surface.fmask_size;
773
774 assert(!out->tile_swizzle || !image->shareable);
775 }
776
777 static void
778 radv_image_alloc_fmask(struct radv_device *device,
779 struct radv_image *image)
780 {
781 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
782
783 image->fmask.offset = align64(image->size, image->fmask.alignment);
784 image->size = image->fmask.offset + image->fmask.size;
785 image->alignment = MAX2(image->alignment, image->fmask.alignment);
786 }
787
788 static void
789 radv_image_get_cmask_info(struct radv_device *device,
790 struct radv_image *image,
791 struct radv_cmask_info *out)
792 {
793 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
794 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
795 unsigned cl_width, cl_height;
796
797 if (device->physical_device->rad_info.chip_class >= GFX9) {
798 out->alignment = image->surface.cmask_alignment;
799 out->size = image->surface.cmask_size;
800 return;
801 }
802
803 switch (num_pipes) {
804 case 2:
805 cl_width = 32;
806 cl_height = 16;
807 break;
808 case 4:
809 cl_width = 32;
810 cl_height = 32;
811 break;
812 case 8:
813 cl_width = 64;
814 cl_height = 32;
815 break;
816 case 16: /* Hawaii */
817 cl_width = 64;
818 cl_height = 64;
819 break;
820 default:
821 assert(0);
822 return;
823 }
824
825 unsigned base_align = num_pipes * pipe_interleave_bytes;
826
827 unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
828 unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
829 unsigned slice_elements = (width * height) / (8*8);
830
831 /* Each element of CMASK is a nibble. */
832 unsigned slice_bytes = slice_elements / 2;
833
834 out->slice_tile_max = (width * height) / (128*128);
835 if (out->slice_tile_max)
836 out->slice_tile_max -= 1;
837
838 out->alignment = MAX2(256, base_align);
839 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
840 align(slice_bytes, base_align);
841 }
842
843 static void
844 radv_image_alloc_cmask(struct radv_device *device,
845 struct radv_image *image)
846 {
847 uint32_t clear_value_size = 0;
848 radv_image_get_cmask_info(device, image, &image->cmask);
849
850 image->cmask.offset = align64(image->size, image->cmask.alignment);
851 /* + 8 for storing the clear values */
852 if (!image->clear_value_offset) {
853 image->clear_value_offset = image->cmask.offset + image->cmask.size;
854 clear_value_size = 8;
855 }
856 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
857 image->alignment = MAX2(image->alignment, image->cmask.alignment);
858 }
859
860 static void
861 radv_image_alloc_dcc(struct radv_image *image)
862 {
863 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
864 /* + 16 for storing the clear values + dcc pred */
865 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
866 image->fce_pred_offset = image->clear_value_offset + 8;
867 image->dcc_pred_offset = image->clear_value_offset + 16;
868 image->size = image->dcc_offset + image->surface.dcc_size + 24;
869 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
870 }
871
872 static void
873 radv_image_alloc_htile(struct radv_image *image)
874 {
875 image->htile_offset = align64(image->size, image->surface.htile_alignment);
876
877 /* + 8 for storing the clear values */
878 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
879 image->size = image->clear_value_offset + 8;
880 if (radv_image_is_tc_compat_htile(image)) {
881 /* Metadata for the TC-compatible HTILE hardware bug which
882 * have to be fixed by updating ZRANGE_PRECISION when doing
883 * fast depth clears to 0.0f.
884 */
885 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
886 image->size = image->clear_value_offset + 16;
887 }
888 image->alignment = align64(image->alignment, image->surface.htile_alignment);
889 }
890
891 static inline bool
892 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
893 {
894 if (image->info.samples <= 1 &&
895 image->info.width * image->info.height <= 512 * 512) {
896 /* Do not enable CMASK or DCC for small surfaces where the cost
897 * of the eliminate pass can be higher than the benefit of fast
898 * clear. RadeonSI does this, but the image threshold is
899 * different.
900 */
901 return false;
902 }
903
904 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
905 (image->exclusive || image->queue_family_mask == 1);
906 }
907
908 static inline bool
909 radv_image_can_enable_dcc(struct radv_image *image)
910 {
911 return radv_image_can_enable_dcc_or_cmask(image) &&
912 radv_image_has_dcc(image);
913 }
914
915 static inline bool
916 radv_image_can_enable_cmask(struct radv_image *image)
917 {
918 if (image->surface.bpe > 8 && image->info.samples == 1) {
919 /* Do not enable CMASK for non-MSAA images (fast color clear)
920 * because 128 bit formats are not supported, but FMASK might
921 * still be used.
922 */
923 return false;
924 }
925
926 return radv_image_can_enable_dcc_or_cmask(image) &&
927 image->info.levels == 1 &&
928 image->info.depth == 1 &&
929 !image->surface.is_linear;
930 }
931
932 static inline bool
933 radv_image_can_enable_fmask(struct radv_image *image)
934 {
935 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
936 }
937
938 static inline bool
939 radv_image_can_enable_htile(struct radv_image *image)
940 {
941 return radv_image_has_htile(image) &&
942 image->info.levels == 1 &&
943 image->info.width * image->info.height >= 8 * 8;
944 }
945
946 VkResult
947 radv_image_create(VkDevice _device,
948 const struct radv_image_create_info *create_info,
949 const VkAllocationCallbacks* alloc,
950 VkImage *pImage)
951 {
952 RADV_FROM_HANDLE(radv_device, device, _device);
953 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
954 struct radv_image *image = NULL;
955 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
956
957 radv_assert(pCreateInfo->mipLevels > 0);
958 radv_assert(pCreateInfo->arrayLayers > 0);
959 radv_assert(pCreateInfo->samples > 0);
960 radv_assert(pCreateInfo->extent.width > 0);
961 radv_assert(pCreateInfo->extent.height > 0);
962 radv_assert(pCreateInfo->extent.depth > 0);
963
964 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
965 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
966 if (!image)
967 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
968
969 image->type = pCreateInfo->imageType;
970 image->info.width = pCreateInfo->extent.width;
971 image->info.height = pCreateInfo->extent.height;
972 image->info.depth = pCreateInfo->extent.depth;
973 image->info.samples = pCreateInfo->samples;
974 image->info.storage_samples = pCreateInfo->samples;
975 image->info.array_size = pCreateInfo->arrayLayers;
976 image->info.levels = pCreateInfo->mipLevels;
977 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
978
979 image->vk_format = pCreateInfo->format;
980 image->tiling = pCreateInfo->tiling;
981 image->usage = pCreateInfo->usage;
982 image->flags = pCreateInfo->flags;
983
984 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
985 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
986 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
987 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
988 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
989 else
990 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
991 }
992
993 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
994 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
995 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
996 image->info.surf_index = &device->image_mrt_offset_counter;
997 }
998
999 radv_init_surface(device, image, &image->surface, create_info);
1000
1001 device->ws->surface_init(device->ws, &image->info, &image->surface);
1002
1003 image->size = image->surface.surf_size;
1004 image->alignment = image->surface.surf_alignment;
1005
1006 if (!create_info->no_metadata_planes) {
1007 /* Try to enable DCC first. */
1008 if (radv_image_can_enable_dcc(image)) {
1009 radv_image_alloc_dcc(image);
1010 if (image->info.samples > 1) {
1011 /* CMASK should be enabled because DCC fast
1012 * clear with MSAA needs it.
1013 */
1014 assert(radv_image_can_enable_cmask(image));
1015 radv_image_alloc_cmask(device, image);
1016 }
1017 } else {
1018 /* When DCC cannot be enabled, try CMASK. */
1019 image->surface.dcc_size = 0;
1020 if (radv_image_can_enable_cmask(image)) {
1021 radv_image_alloc_cmask(device, image);
1022 }
1023 }
1024
1025 /* Try to enable FMASK for multisampled images. */
1026 if (radv_image_can_enable_fmask(image)) {
1027 radv_image_alloc_fmask(device, image);
1028 } else {
1029 /* Otherwise, try to enable HTILE for depth surfaces. */
1030 if (radv_image_can_enable_htile(image) &&
1031 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1032 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1033 radv_image_alloc_htile(image);
1034 } else {
1035 image->surface.htile_size = 0;
1036 }
1037 }
1038 } else {
1039 image->surface.dcc_size = 0;
1040 image->surface.htile_size = 0;
1041 }
1042
1043 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1044 image->alignment = MAX2(image->alignment, 4096);
1045 image->size = align64(image->size, image->alignment);
1046 image->offset = 0;
1047
1048 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1049 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1050 if (!image->bo) {
1051 vk_free2(&device->alloc, alloc, image);
1052 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1053 }
1054 }
1055
1056 *pImage = radv_image_to_handle(image);
1057
1058 return VK_SUCCESS;
1059 }
1060
1061 static void
1062 radv_image_view_make_descriptor(struct radv_image_view *iview,
1063 struct radv_device *device,
1064 const VkComponentMapping *components,
1065 bool is_storage_image)
1066 {
1067 struct radv_image *image = iview->image;
1068 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1069 uint32_t blk_w;
1070 uint32_t *descriptor;
1071 uint32_t hw_level = 0;
1072
1073 if (is_storage_image) {
1074 descriptor = iview->storage_descriptor;
1075 } else {
1076 descriptor = iview->descriptor;
1077 }
1078
1079 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1080 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1081
1082 if (device->physical_device->rad_info.chip_class >= GFX9)
1083 hw_level = iview->base_mip;
1084 si_make_texture_descriptor(device, image, is_storage_image,
1085 iview->type,
1086 iview->vk_format,
1087 components,
1088 hw_level, hw_level + iview->level_count - 1,
1089 iview->base_layer,
1090 iview->base_layer + iview->layer_count - 1,
1091 iview->extent.width,
1092 iview->extent.height,
1093 iview->extent.depth,
1094 descriptor,
1095 descriptor + 8);
1096
1097 const struct legacy_surf_level *base_level_info = NULL;
1098 if (device->physical_device->rad_info.chip_class <= GFX9) {
1099 if (is_stencil)
1100 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1101 else
1102 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1103 }
1104 si_set_mutable_tex_desc_fields(device, image,
1105 base_level_info,
1106 iview->base_mip,
1107 iview->base_mip,
1108 blk_w, is_stencil, is_storage_image, descriptor);
1109 }
1110
1111 void
1112 radv_image_view_init(struct radv_image_view *iview,
1113 struct radv_device *device,
1114 const VkImageViewCreateInfo* pCreateInfo)
1115 {
1116 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1117 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1118
1119 switch (image->type) {
1120 case VK_IMAGE_TYPE_1D:
1121 case VK_IMAGE_TYPE_2D:
1122 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1123 break;
1124 case VK_IMAGE_TYPE_3D:
1125 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1126 <= radv_minify(image->info.depth, range->baseMipLevel));
1127 break;
1128 default:
1129 unreachable("bad VkImageType");
1130 }
1131 iview->image = image;
1132 iview->bo = image->bo;
1133 iview->type = pCreateInfo->viewType;
1134 iview->vk_format = pCreateInfo->format;
1135 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1136
1137 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1138 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1139 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1140 iview->vk_format = vk_format_depth_only(iview->vk_format);
1141 }
1142
1143 if (device->physical_device->rad_info.chip_class >= GFX9) {
1144 iview->extent = (VkExtent3D) {
1145 .width = image->info.width,
1146 .height = image->info.height,
1147 .depth = image->info.depth,
1148 };
1149 } else {
1150 iview->extent = (VkExtent3D) {
1151 .width = radv_minify(image->info.width , range->baseMipLevel),
1152 .height = radv_minify(image->info.height, range->baseMipLevel),
1153 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1154 };
1155 }
1156
1157 if (iview->vk_format != image->vk_format) {
1158 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1159 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1160 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1161 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1162
1163 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1164 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1165
1166 /* Comment ported from amdvlk -
1167 * If we have the following image:
1168 * Uncompressed pixels Compressed block sizes (4x4)
1169 * mip0: 22 x 22 6 x 6
1170 * mip1: 11 x 11 3 x 3
1171 * mip2: 5 x 5 2 x 2
1172 * mip3: 2 x 2 1 x 1
1173 * mip4: 1 x 1 1 x 1
1174 *
1175 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1176 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1177 * divide-by-two integer math):
1178 * mip0: 6x6
1179 * mip1: 3x3
1180 * mip2: 1x1
1181 * mip3: 1x1
1182 *
1183 * This means that mip2 will be missing texels.
1184 *
1185 * Fix this by calculating the base mip's width and height, then convert that, and round it
1186 * back up to get the level 0 size.
1187 * Clamp the converted size between the original values, and next power of two, which
1188 * means we don't oversize the image.
1189 */
1190 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1191 vk_format_is_compressed(image->vk_format) &&
1192 !vk_format_is_compressed(iview->vk_format)) {
1193 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1194 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1195
1196 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1197 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1198
1199 lvl_width <<= range->baseMipLevel;
1200 lvl_height <<= range->baseMipLevel;
1201
1202 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
1203 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
1204 }
1205 }
1206
1207 iview->base_layer = range->baseArrayLayer;
1208 iview->layer_count = radv_get_layerCount(image, range);
1209 iview->base_mip = range->baseMipLevel;
1210 iview->level_count = radv_get_levelCount(image, range);
1211
1212 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1213 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1214 }
1215
1216 bool radv_layout_has_htile(const struct radv_image *image,
1217 VkImageLayout layout,
1218 unsigned queue_mask)
1219 {
1220 if (radv_image_is_tc_compat_htile(image))
1221 return layout != VK_IMAGE_LAYOUT_GENERAL;
1222
1223 return radv_image_has_htile(image) &&
1224 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1225 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1226 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1227 }
1228
1229 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1230 VkImageLayout layout,
1231 unsigned queue_mask)
1232 {
1233 if (radv_image_is_tc_compat_htile(image))
1234 return layout != VK_IMAGE_LAYOUT_GENERAL;
1235
1236 return radv_image_has_htile(image) &&
1237 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1238 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1239 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1240 }
1241
1242 bool radv_layout_can_fast_clear(const struct radv_image *image,
1243 VkImageLayout layout,
1244 unsigned queue_mask)
1245 {
1246 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1247 }
1248
1249 bool radv_layout_dcc_compressed(const struct radv_image *image,
1250 VkImageLayout layout,
1251 unsigned queue_mask)
1252 {
1253 /* Don't compress compute transfer dst, as image stores are not supported. */
1254 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1255 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1256 return false;
1257
1258 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1259 }
1260
1261
1262 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1263 {
1264 if (!image->exclusive)
1265 return image->queue_family_mask;
1266 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1267 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1268 if (family == VK_QUEUE_FAMILY_IGNORED)
1269 return 1u << queue_family;
1270 return 1u << family;
1271 }
1272
1273 VkResult
1274 radv_CreateImage(VkDevice device,
1275 const VkImageCreateInfo *pCreateInfo,
1276 const VkAllocationCallbacks *pAllocator,
1277 VkImage *pImage)
1278 {
1279 #ifdef ANDROID
1280 const VkNativeBufferANDROID *gralloc_info =
1281 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1282
1283 if (gralloc_info)
1284 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1285 pAllocator, pImage);
1286 #endif
1287
1288 const struct wsi_image_create_info *wsi_info =
1289 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1290 bool scanout = wsi_info && wsi_info->scanout;
1291
1292 return radv_image_create(device,
1293 &(struct radv_image_create_info) {
1294 .vk_info = pCreateInfo,
1295 .scanout = scanout,
1296 },
1297 pAllocator,
1298 pImage);
1299 }
1300
1301 void
1302 radv_DestroyImage(VkDevice _device, VkImage _image,
1303 const VkAllocationCallbacks *pAllocator)
1304 {
1305 RADV_FROM_HANDLE(radv_device, device, _device);
1306 RADV_FROM_HANDLE(radv_image, image, _image);
1307
1308 if (!image)
1309 return;
1310
1311 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1312 device->ws->buffer_destroy(image->bo);
1313
1314 if (image->owned_memory != VK_NULL_HANDLE)
1315 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1316
1317 vk_free2(&device->alloc, pAllocator, image);
1318 }
1319
1320 void radv_GetImageSubresourceLayout(
1321 VkDevice _device,
1322 VkImage _image,
1323 const VkImageSubresource* pSubresource,
1324 VkSubresourceLayout* pLayout)
1325 {
1326 RADV_FROM_HANDLE(radv_image, image, _image);
1327 RADV_FROM_HANDLE(radv_device, device, _device);
1328 int level = pSubresource->mipLevel;
1329 int layer = pSubresource->arrayLayer;
1330 struct radeon_surf *surface = &image->surface;
1331
1332 if (device->physical_device->rad_info.chip_class >= GFX9) {
1333 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1334 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1335 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1336 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1337 pLayout->size = surface->u.gfx9.surf_slice_size;
1338 if (image->type == VK_IMAGE_TYPE_3D)
1339 pLayout->size *= u_minify(image->info.depth, level);
1340 } else {
1341 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1342 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1343 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1344 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1345 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1346 if (image->type == VK_IMAGE_TYPE_3D)
1347 pLayout->size *= u_minify(image->info.depth, level);
1348 }
1349 }
1350
1351
1352 VkResult
1353 radv_CreateImageView(VkDevice _device,
1354 const VkImageViewCreateInfo *pCreateInfo,
1355 const VkAllocationCallbacks *pAllocator,
1356 VkImageView *pView)
1357 {
1358 RADV_FROM_HANDLE(radv_device, device, _device);
1359 struct radv_image_view *view;
1360
1361 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1362 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1363 if (view == NULL)
1364 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1365
1366 radv_image_view_init(view, device, pCreateInfo);
1367
1368 *pView = radv_image_view_to_handle(view);
1369
1370 return VK_SUCCESS;
1371 }
1372
1373 void
1374 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1375 const VkAllocationCallbacks *pAllocator)
1376 {
1377 RADV_FROM_HANDLE(radv_device, device, _device);
1378 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1379
1380 if (!iview)
1381 return;
1382 vk_free2(&device->alloc, pAllocator, iview);
1383 }
1384
1385 void radv_buffer_view_init(struct radv_buffer_view *view,
1386 struct radv_device *device,
1387 const VkBufferViewCreateInfo* pCreateInfo)
1388 {
1389 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1390
1391 view->bo = buffer->bo;
1392 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1393 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1394 view->vk_format = pCreateInfo->format;
1395
1396 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1397 pCreateInfo->offset, view->range, view->state);
1398 }
1399
1400 VkResult
1401 radv_CreateBufferView(VkDevice _device,
1402 const VkBufferViewCreateInfo *pCreateInfo,
1403 const VkAllocationCallbacks *pAllocator,
1404 VkBufferView *pView)
1405 {
1406 RADV_FROM_HANDLE(radv_device, device, _device);
1407 struct radv_buffer_view *view;
1408
1409 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1410 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1411 if (!view)
1412 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1413
1414 radv_buffer_view_init(view, device, pCreateInfo);
1415
1416 *pView = radv_buffer_view_to_handle(view);
1417
1418 return VK_SUCCESS;
1419 }
1420
1421 void
1422 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1423 const VkAllocationCallbacks *pAllocator)
1424 {
1425 RADV_FROM_HANDLE(radv_device, device, _device);
1426 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1427
1428 if (!view)
1429 return;
1430
1431 vk_free2(&device->alloc, pAllocator, view);
1432 }