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radv: predicate cmask eliminate when using DCC.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "vk_util.h"
31 #include "radv_radeon_winsys.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36 static unsigned
37 radv_choose_tiling(struct radv_device *Device,
38 const struct radv_image_create_info *create_info)
39 {
40 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
41
42 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
43 assert(pCreateInfo->samples <= 1);
44 return RADEON_SURF_MODE_LINEAR_ALIGNED;
45 }
46
47 /* Textures with a very small height are recommended to be linear. */
48 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
49 /* Only very thin and long 2D textures should benefit from
50 * linear_aligned. */
51 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
52 return RADEON_SURF_MODE_LINEAR_ALIGNED;
53
54 /* MSAA resources must be 2D tiled. */
55 if (pCreateInfo->samples > 1)
56 return RADEON_SURF_MODE_2D;
57
58 return RADEON_SURF_MODE_2D;
59 }
60 static int
61 radv_init_surface(struct radv_device *device,
62 struct radeon_surf *surface,
63 const struct radv_image_create_info *create_info)
64 {
65 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
66 unsigned array_mode = radv_choose_tiling(device, create_info);
67 const struct vk_format_description *desc =
68 vk_format_description(pCreateInfo->format);
69 bool is_depth, is_stencil, blendable;
70
71 is_depth = vk_format_has_depth(desc);
72 is_stencil = vk_format_has_stencil(desc);
73
74 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
75 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
76
77 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
78 /* align byte per element on dword */
79 if (surface->bpe == 3) {
80 surface->bpe = 4;
81 }
82 surface->flags = RADEON_SURF_SET(array_mode, MODE);
83
84 switch (pCreateInfo->imageType){
85 case VK_IMAGE_TYPE_1D:
86 if (pCreateInfo->arrayLayers > 1)
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
88 else
89 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
90 break;
91 case VK_IMAGE_TYPE_2D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_3D:
98 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
99 break;
100 default:
101 unreachable("unhandled image type");
102 }
103
104 if (is_depth) {
105 surface->flags |= RADEON_SURF_ZBUFFER;
106 }
107
108 if (is_stencil)
109 surface->flags |= RADEON_SURF_SBUFFER;
110
111 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
112
113 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
114 VK_IMAGE_USAGE_STORAGE_BIT)) ||
115 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
116 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
117 device->physical_device->rad_info.chip_class < VI ||
118 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
119 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
120 surface->flags |= RADEON_SURF_DISABLE_DCC;
121 if (create_info->scanout)
122 surface->flags |= RADEON_SURF_SCANOUT;
123 return 0;
124 }
125 #define ATI_VENDOR_ID 0x1002
126 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
127 {
128 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
129 }
130
131 static inline unsigned
132 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
133 {
134 if (stencil)
135 return image->surface.u.legacy.stencil_tiling_index[level];
136 else
137 return image->surface.u.legacy.tiling_index[level];
138 }
139
140 static unsigned radv_map_swizzle(unsigned swizzle)
141 {
142 switch (swizzle) {
143 case VK_SWIZZLE_Y:
144 return V_008F0C_SQ_SEL_Y;
145 case VK_SWIZZLE_Z:
146 return V_008F0C_SQ_SEL_Z;
147 case VK_SWIZZLE_W:
148 return V_008F0C_SQ_SEL_W;
149 case VK_SWIZZLE_0:
150 return V_008F0C_SQ_SEL_0;
151 case VK_SWIZZLE_1:
152 return V_008F0C_SQ_SEL_1;
153 default: /* VK_SWIZZLE_X */
154 return V_008F0C_SQ_SEL_X;
155 }
156 }
157
158 static void
159 radv_make_buffer_descriptor(struct radv_device *device,
160 struct radv_buffer *buffer,
161 VkFormat vk_format,
162 unsigned offset,
163 unsigned range,
164 uint32_t *state)
165 {
166 const struct vk_format_description *desc;
167 unsigned stride;
168 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
169 uint64_t va = gpu_address + buffer->offset;
170 unsigned num_format, data_format;
171 int first_non_void;
172 desc = vk_format_description(vk_format);
173 first_non_void = vk_format_get_first_non_void_channel(vk_format);
174 stride = desc->block.bits / 8;
175
176 num_format = radv_translate_buffer_numformat(desc, first_non_void);
177 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
178
179 va += offset;
180 state[0] = va;
181 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
182 S_008F04_STRIDE(stride);
183 state[2] = range;
184 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
185 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
186 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
187 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
188 S_008F0C_NUM_FORMAT(num_format) |
189 S_008F0C_DATA_FORMAT(data_format);
190 }
191
192 static void
193 si_set_mutable_tex_desc_fields(struct radv_device *device,
194 struct radv_image *image,
195 const struct legacy_surf_level *base_level_info,
196 unsigned base_level, unsigned first_level,
197 unsigned block_width, bool is_stencil,
198 uint32_t *state)
199 {
200 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
201 uint64_t va = gpu_address;
202 unsigned pitch = base_level_info->nblk_x * block_width;
203 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
204 uint64_t meta_va = 0;
205 if (chip_class >= GFX9) {
206 if (is_stencil)
207 va += image->surface.u.gfx9.stencil_offset;
208 else
209 va += image->surface.u.gfx9.surf_offset;
210 } else
211 va += base_level_info->offset;
212
213 state[0] = va >> 8;
214 if (chip_class < GFX9)
215 state[0] |= image->surface.u.legacy.tile_swizzle;
216 state[1] &= C_008F14_BASE_ADDRESS_HI;
217 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
218 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
219 is_stencil));
220 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
221
222 if (chip_class >= VI) {
223 state[6] &= C_008F28_COMPRESSION_EN;
224 state[7] = 0;
225 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
226 uint64_t meta_va = gpu_address + image->dcc_offset;
227 if (chip_class <= VI)
228 meta_va += base_level_info->dcc_offset;
229 state[6] |= S_008F28_COMPRESSION_EN(1);
230 state[7] = meta_va >> 8;
231 if (chip_class < GFX9)
232 state[7] |= image->surface.u.legacy.tile_swizzle;
233 }
234 }
235
236 if (chip_class >= GFX9) {
237 state[3] &= C_008F1C_SW_MODE;
238 state[4] &= C_008F20_PITCH_GFX9;
239
240 if (is_stencil) {
241 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
242 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
243 } else {
244 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
245 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
246 }
247
248 state[5] &= C_008F24_META_DATA_ADDRESS &
249 C_008F24_META_PIPE_ALIGNED &
250 C_008F24_META_RB_ALIGNED;
251 if (meta_va) {
252 struct gfx9_surf_meta_flags meta;
253
254 if (image->dcc_offset)
255 meta = image->surface.u.gfx9.dcc;
256 else
257 meta = image->surface.u.gfx9.htile;
258
259 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
260 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
261 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
262 }
263 } else {
264 /* SI-CI-VI */
265 unsigned pitch = base_level_info->nblk_x * block_width;
266 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
267
268 state[3] &= C_008F1C_TILING_INDEX;
269 state[3] |= S_008F1C_TILING_INDEX(index);
270 state[4] &= C_008F20_PITCH_GFX6;
271 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
272 }
273 }
274
275 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
276 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
277 {
278 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
279 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
280 switch (image_type) {
281 case VK_IMAGE_TYPE_1D:
282 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
283 case VK_IMAGE_TYPE_2D:
284 if (nr_samples > 1)
285 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
286 else
287 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
288 case VK_IMAGE_TYPE_3D:
289 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
290 return V_008F1C_SQ_RSRC_IMG_3D;
291 else
292 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
293 default:
294 unreachable("illegale image type");
295 }
296 }
297
298 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
299 {
300 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
301
302 if (swizzle[3] == VK_SWIZZLE_X) {
303 /* For the pre-defined border color values (white, opaque
304 * black, transparent black), the only thing that matters is
305 * that the alpha channel winds up in the correct place
306 * (because the RGB channels are all the same) so either of
307 * these enumerations will work.
308 */
309 if (swizzle[2] == VK_SWIZZLE_Y)
310 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
311 else
312 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
313 } else if (swizzle[0] == VK_SWIZZLE_X) {
314 if (swizzle[1] == VK_SWIZZLE_Y)
315 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
316 else
317 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
318 } else if (swizzle[1] == VK_SWIZZLE_X) {
319 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
320 } else if (swizzle[2] == VK_SWIZZLE_X) {
321 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
322 }
323
324 return bc_swizzle;
325 }
326
327 /**
328 * Build the sampler view descriptor for a texture.
329 */
330 static void
331 si_make_texture_descriptor(struct radv_device *device,
332 struct radv_image *image,
333 bool is_storage_image,
334 VkImageViewType view_type,
335 VkFormat vk_format,
336 const VkComponentMapping *mapping,
337 unsigned first_level, unsigned last_level,
338 unsigned first_layer, unsigned last_layer,
339 unsigned width, unsigned height, unsigned depth,
340 uint32_t *state,
341 uint32_t *fmask_state)
342 {
343 const struct vk_format_description *desc;
344 enum vk_swizzle swizzle[4];
345 int first_non_void;
346 unsigned num_format, data_format, type;
347
348 desc = vk_format_description(vk_format);
349
350 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
351 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
352 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
353 } else {
354 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
355 }
356
357 first_non_void = vk_format_get_first_non_void_channel(vk_format);
358
359 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
360 if (num_format == ~0) {
361 num_format = 0;
362 }
363
364 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
365 if (data_format == ~0) {
366 data_format = 0;
367 }
368
369 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
370 is_storage_image);
371 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
372 height = 1;
373 depth = image->info.array_size;
374 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
375 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
376 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
377 depth = image->info.array_size;
378 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
379 depth = image->info.array_size / 6;
380
381 state[0] = 0;
382 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
383 S_008F14_NUM_FORMAT_GFX6(num_format));
384 state[2] = (S_008F18_WIDTH(width - 1) |
385 S_008F18_HEIGHT(height - 1) |
386 S_008F18_PERF_MOD(4));
387 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
388 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
389 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
390 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
391 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
392 0 : first_level) |
393 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
394 util_logbase2(image->info.samples) :
395 last_level) |
396 S_008F1C_TYPE(type));
397 state[4] = 0;
398 state[5] = S_008F24_BASE_ARRAY(first_layer);
399 state[6] = 0;
400 state[7] = 0;
401
402 if (device->physical_device->rad_info.chip_class >= GFX9) {
403 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
404
405 /* Depth is the the last accessible layer on Gfx9.
406 * The hw doesn't need to know the total number of layers.
407 */
408 if (type == V_008F1C_SQ_RSRC_IMG_3D)
409 state[4] |= S_008F20_DEPTH(depth - 1);
410 else
411 state[4] |= S_008F20_DEPTH(last_layer);
412
413 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
414 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
415 util_logbase2(image->info.samples) :
416 last_level);
417 } else {
418 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
419 state[4] |= S_008F20_DEPTH(depth - 1);
420 state[5] |= S_008F24_LAST_ARRAY(last_layer);
421 }
422 if (image->dcc_offset) {
423 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
424
425 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
426 } else {
427 /* The last dword is unused by hw. The shader uses it to clear
428 * bits in the first dword of sampler state.
429 */
430 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
431 if (first_level == last_level)
432 state[7] = C_008F30_MAX_ANISO_RATIO;
433 else
434 state[7] = 0xffffffff;
435 }
436 }
437
438 /* Initialize the sampler view for FMASK. */
439 if (image->fmask.size) {
440 uint32_t fmask_format, num_format;
441 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
442 uint64_t va;
443
444 va = gpu_address + image->offset + image->fmask.offset;
445
446 if (device->physical_device->rad_info.chip_class >= GFX9) {
447 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
448 switch (image->info.samples) {
449 case 2:
450 num_format = V_008F14_IMG_FMASK_8_2_2;
451 break;
452 case 4:
453 num_format = V_008F14_IMG_FMASK_8_4_4;
454 break;
455 case 8:
456 num_format = V_008F14_IMG_FMASK_32_8_8;
457 break;
458 default:
459 unreachable("invalid nr_samples");
460 }
461 } else {
462 switch (image->info.samples) {
463 case 2:
464 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
465 break;
466 case 4:
467 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
468 break;
469 case 8:
470 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
471 break;
472 default:
473 assert(0);
474 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
475 }
476 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
477 }
478
479 fmask_state[0] = va >> 8;
480 if (device->physical_device->rad_info.chip_class < GFX9)
481 fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
482 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
483 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
484 S_008F14_NUM_FORMAT_GFX6(num_format);
485 fmask_state[2] = S_008F18_WIDTH(width - 1) |
486 S_008F18_HEIGHT(height - 1);
487 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
488 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
489 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
490 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
491 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
492 fmask_state[4] = 0;
493 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
494 fmask_state[6] = 0;
495 fmask_state[7] = 0;
496
497 if (device->physical_device->rad_info.chip_class >= GFX9) {
498 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
499 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
500 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
501 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
502 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
503 } else {
504 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
505 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
506 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
507 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
508 }
509 } else if (fmask_state)
510 memset(fmask_state, 0, 8 * 4);
511 }
512
513 static void
514 radv_query_opaque_metadata(struct radv_device *device,
515 struct radv_image *image,
516 struct radeon_bo_metadata *md)
517 {
518 static const VkComponentMapping fixedmapping;
519 uint32_t desc[8], i;
520
521 /* Metadata image format format version 1:
522 * [0] = 1 (metadata format identifier)
523 * [1] = (VENDOR_ID << 16) | PCI_ID
524 * [2:9] = image descriptor for the whole resource
525 * [2] is always 0, because the base address is cleared
526 * [9] is the DCC offset bits [39:8] from the beginning of
527 * the buffer
528 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
529 */
530 md->metadata[0] = 1; /* metadata image format version 1 */
531
532 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
533 md->metadata[1] = si_get_bo_metadata_word1(device);
534
535
536 si_make_texture_descriptor(device, image, false,
537 (VkImageViewType)image->type, image->vk_format,
538 &fixedmapping, 0, image->info.levels - 1, 0,
539 image->info.array_size,
540 image->info.width, image->info.height,
541 image->info.depth,
542 desc, NULL);
543
544 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
545 image->surface.blk_w, false, desc);
546
547 /* Clear the base address and set the relative DCC offset. */
548 desc[0] = 0;
549 desc[1] &= C_008F14_BASE_ADDRESS_HI;
550 desc[7] = image->dcc_offset >> 8;
551
552 /* Dwords [2:9] contain the image descriptor. */
553 memcpy(&md->metadata[2], desc, sizeof(desc));
554
555 /* Dwords [10:..] contain the mipmap level offsets. */
556 for (i = 0; i <= image->info.levels - 1; i++)
557 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
558
559 md->size_metadata = (11 + image->info.levels - 1) * 4;
560 }
561
562 void
563 radv_init_metadata(struct radv_device *device,
564 struct radv_image *image,
565 struct radeon_bo_metadata *metadata)
566 {
567 struct radeon_surf *surface = &image->surface;
568
569 memset(metadata, 0, sizeof(*metadata));
570
571 if (device->physical_device->rad_info.chip_class >= GFX9) {
572 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
573 } else {
574 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
575 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
576 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
577 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
578 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
579 metadata->u.legacy.bankw = surface->u.legacy.bankw;
580 metadata->u.legacy.bankh = surface->u.legacy.bankh;
581 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
582 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
583 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
584 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
585 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
586 }
587 radv_query_opaque_metadata(device, image, metadata);
588 }
589
590 /* The number of samples can be specified independently of the texture. */
591 static void
592 radv_image_get_fmask_info(struct radv_device *device,
593 struct radv_image *image,
594 unsigned nr_samples,
595 struct radv_fmask_info *out)
596 {
597 /* FMASK is allocated like an ordinary texture. */
598 struct radeon_surf fmask = {};
599 struct ac_surf_info info = image->info;
600 memset(out, 0, sizeof(*out));
601
602 if (device->physical_device->rad_info.chip_class >= GFX9) {
603 out->alignment = image->surface.u.gfx9.fmask_alignment;
604 out->size = image->surface.u.gfx9.fmask_size;
605 return;
606 }
607
608 fmask.blk_w = image->surface.blk_w;
609 fmask.blk_h = image->surface.blk_h;
610 info.samples = 1;
611 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
612
613 /* Force 2D tiling if it wasn't set. This may occur when creating
614 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
615 * destination buffer must have an FMASK too. */
616 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
617 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
618
619 switch (nr_samples) {
620 case 2:
621 case 4:
622 fmask.bpe = 1;
623 break;
624 case 8:
625 fmask.bpe = 4;
626 break;
627 default:
628 return;
629 }
630
631 device->ws->surface_init(device->ws, &info, &fmask);
632 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
633
634 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
635 if (out->slice_tile_max)
636 out->slice_tile_max -= 1;
637
638 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
639 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
640 out->bank_height = fmask.u.legacy.bankh;
641 out->alignment = MAX2(256, fmask.surf_alignment);
642 out->size = fmask.surf_size;
643 }
644
645 static void
646 radv_image_alloc_fmask(struct radv_device *device,
647 struct radv_image *image)
648 {
649 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
650
651 image->fmask.offset = align64(image->size, image->fmask.alignment);
652 image->size = image->fmask.offset + image->fmask.size;
653 image->alignment = MAX2(image->alignment, image->fmask.alignment);
654 }
655
656 static void
657 radv_image_get_cmask_info(struct radv_device *device,
658 struct radv_image *image,
659 struct radv_cmask_info *out)
660 {
661 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
662 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
663 unsigned cl_width, cl_height;
664
665 if (device->physical_device->rad_info.chip_class >= GFX9) {
666 out->alignment = image->surface.u.gfx9.cmask_alignment;
667 out->size = image->surface.u.gfx9.cmask_size;
668 return;
669 }
670
671 switch (num_pipes) {
672 case 2:
673 cl_width = 32;
674 cl_height = 16;
675 break;
676 case 4:
677 cl_width = 32;
678 cl_height = 32;
679 break;
680 case 8:
681 cl_width = 64;
682 cl_height = 32;
683 break;
684 case 16: /* Hawaii */
685 cl_width = 64;
686 cl_height = 64;
687 break;
688 default:
689 assert(0);
690 return;
691 }
692
693 unsigned base_align = num_pipes * pipe_interleave_bytes;
694
695 unsigned width = align(image->info.width, cl_width*8);
696 unsigned height = align(image->info.height, cl_height*8);
697 unsigned slice_elements = (width * height) / (8*8);
698
699 /* Each element of CMASK is a nibble. */
700 unsigned slice_bytes = slice_elements / 2;
701
702 out->slice_tile_max = (width * height) / (128*128);
703 if (out->slice_tile_max)
704 out->slice_tile_max -= 1;
705
706 out->alignment = MAX2(256, base_align);
707 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
708 align(slice_bytes, base_align);
709 }
710
711 static void
712 radv_image_alloc_cmask(struct radv_device *device,
713 struct radv_image *image)
714 {
715 uint32_t clear_value_size = 0;
716 radv_image_get_cmask_info(device, image, &image->cmask);
717
718 image->cmask.offset = align64(image->size, image->cmask.alignment);
719 /* + 8 for storing the clear values */
720 if (!image->clear_value_offset) {
721 image->clear_value_offset = image->cmask.offset + image->cmask.size;
722 clear_value_size = 8;
723 }
724 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
725 image->alignment = MAX2(image->alignment, image->cmask.alignment);
726 }
727
728 static void
729 radv_image_alloc_dcc(struct radv_device *device,
730 struct radv_image *image)
731 {
732 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
733 /* + 16 for storing the clear values + dcc pred */
734 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
735 image->dcc_pred_offset = image->clear_value_offset + 8;
736 image->size = image->dcc_offset + image->surface.dcc_size + 16;
737 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
738 }
739
740 static void
741 radv_image_alloc_htile(struct radv_device *device,
742 struct radv_image *image)
743 {
744 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
745 image->surface.htile_size = 0;
746 return;
747 }
748
749 image->htile_offset = align64(image->size, image->surface.htile_alignment);
750
751 /* + 8 for storing the clear values */
752 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
753 image->size = image->clear_value_offset + 8;
754 image->alignment = align64(image->alignment, image->surface.htile_alignment);
755 }
756
757 VkResult
758 radv_image_create(VkDevice _device,
759 const struct radv_image_create_info *create_info,
760 const VkAllocationCallbacks* alloc,
761 VkImage *pImage)
762 {
763 RADV_FROM_HANDLE(radv_device, device, _device);
764 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
765 struct radv_image *image = NULL;
766 bool can_cmask_dcc = false;
767 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
768
769 radv_assert(pCreateInfo->mipLevels > 0);
770 radv_assert(pCreateInfo->arrayLayers > 0);
771 radv_assert(pCreateInfo->samples > 0);
772 radv_assert(pCreateInfo->extent.width > 0);
773 radv_assert(pCreateInfo->extent.height > 0);
774 radv_assert(pCreateInfo->extent.depth > 0);
775
776 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
777 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
778 if (!image)
779 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
780
781 memset(image, 0, sizeof(*image));
782 image->type = pCreateInfo->imageType;
783 image->info.width = pCreateInfo->extent.width;
784 image->info.height = pCreateInfo->extent.height;
785 image->info.depth = pCreateInfo->extent.depth;
786 image->info.samples = pCreateInfo->samples;
787 image->info.array_size = pCreateInfo->arrayLayers;
788 image->info.levels = pCreateInfo->mipLevels;
789
790 image->vk_format = pCreateInfo->format;
791 image->tiling = pCreateInfo->tiling;
792 image->usage = pCreateInfo->usage;
793 image->flags = pCreateInfo->flags;
794
795 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
796 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
797 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
798 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
799 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
800 else
801 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
802 }
803
804 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
805 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
806 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
807 image->info.surf_index = p_atomic_inc_return(&device->image_mrt_offset_counter) - 1;
808 }
809
810 radv_init_surface(device, &image->surface, create_info);
811
812 device->ws->surface_init(device->ws, &image->info, &image->surface);
813
814 image->size = image->surface.surf_size;
815 image->alignment = image->surface.surf_alignment;
816
817 if (image->exclusive || image->queue_family_mask == 1)
818 can_cmask_dcc = true;
819
820 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
821 image->surface.dcc_size && can_cmask_dcc)
822 radv_image_alloc_dcc(device, image);
823 else
824 image->surface.dcc_size = 0;
825
826 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
827 pCreateInfo->mipLevels == 1 &&
828 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
829 radv_image_alloc_cmask(device, image);
830 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
831 radv_image_alloc_fmask(device, image);
832 } else if (vk_format_is_depth(pCreateInfo->format)) {
833
834 radv_image_alloc_htile(device, image);
835 }
836
837 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
838 image->alignment = MAX2(image->alignment, 4096);
839 image->size = align64(image->size, image->alignment);
840 image->offset = 0;
841
842 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
843 0, RADEON_FLAG_VIRTUAL);
844 if (!image->bo) {
845 vk_free2(&device->alloc, alloc, image);
846 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
847 }
848 }
849
850 *pImage = radv_image_to_handle(image);
851
852 return VK_SUCCESS;
853 }
854
855 static void
856 radv_image_view_make_descriptor(struct radv_image_view *iview,
857 struct radv_device *device,
858 const VkImageViewCreateInfo* pCreateInfo,
859 bool is_storage_image)
860 {
861 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
862 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
863 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
864 uint32_t blk_w;
865 uint32_t *descriptor;
866 uint32_t *fmask_descriptor;
867
868 if (is_storage_image) {
869 descriptor = iview->storage_descriptor;
870 fmask_descriptor = iview->storage_fmask_descriptor;
871 } else {
872 descriptor = iview->descriptor;
873 fmask_descriptor = iview->fmask_descriptor;
874 }
875
876 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
877 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
878
879 si_make_texture_descriptor(device, image, is_storage_image,
880 iview->type,
881 iview->vk_format,
882 &pCreateInfo->components,
883 0, radv_get_levelCount(image, range) - 1,
884 range->baseArrayLayer,
885 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
886 iview->extent.width,
887 iview->extent.height,
888 iview->extent.depth,
889 descriptor,
890 fmask_descriptor);
891 si_set_mutable_tex_desc_fields(device, image,
892 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
893 : &image->surface.u.legacy.level[range->baseMipLevel],
894 range->baseMipLevel,
895 range->baseMipLevel,
896 blk_w, is_stencil, descriptor);
897 }
898
899 void
900 radv_image_view_init(struct radv_image_view *iview,
901 struct radv_device *device,
902 const VkImageViewCreateInfo* pCreateInfo)
903 {
904 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
905 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
906
907 switch (image->type) {
908 case VK_IMAGE_TYPE_1D:
909 case VK_IMAGE_TYPE_2D:
910 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
911 break;
912 case VK_IMAGE_TYPE_3D:
913 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
914 <= radv_minify(image->info.depth, range->baseMipLevel));
915 break;
916 default:
917 unreachable("bad VkImageType");
918 }
919 iview->image = image;
920 iview->bo = image->bo;
921 iview->type = pCreateInfo->viewType;
922 iview->vk_format = pCreateInfo->format;
923 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
924
925 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
926 iview->vk_format = vk_format_stencil_only(iview->vk_format);
927 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
928 iview->vk_format = vk_format_depth_only(iview->vk_format);
929 }
930
931 iview->extent = (VkExtent3D) {
932 .width = radv_minify(image->info.width , range->baseMipLevel),
933 .height = radv_minify(image->info.height, range->baseMipLevel),
934 .depth = radv_minify(image->info.depth , range->baseMipLevel),
935 };
936
937 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
938 vk_format_get_blockwidth(image->vk_format));
939 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
940 vk_format_get_blockheight(image->vk_format));
941
942 iview->base_layer = range->baseArrayLayer;
943 iview->layer_count = radv_get_layerCount(image, range);
944 iview->base_mip = range->baseMipLevel;
945
946 radv_image_view_make_descriptor(iview, device, pCreateInfo, false);
947
948 /* For transfers we may use the image as a storage image. */
949 if (image->usage & (VK_IMAGE_USAGE_STORAGE_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT))
950 radv_image_view_make_descriptor(iview, device, pCreateInfo, true);
951 }
952
953 bool radv_layout_has_htile(const struct radv_image *image,
954 VkImageLayout layout,
955 unsigned queue_mask)
956 {
957 return image->surface.htile_size &&
958 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
959 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
960 queue_mask == (1u << RADV_QUEUE_GENERAL);
961 }
962
963 bool radv_layout_is_htile_compressed(const struct radv_image *image,
964 VkImageLayout layout,
965 unsigned queue_mask)
966 {
967 return image->surface.htile_size &&
968 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
969 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
970 queue_mask == (1u << RADV_QUEUE_GENERAL);
971 }
972
973 bool radv_layout_can_fast_clear(const struct radv_image *image,
974 VkImageLayout layout,
975 unsigned queue_mask)
976 {
977 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
978 queue_mask == (1u << RADV_QUEUE_GENERAL);
979 }
980
981
982 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
983 {
984 if (!image->exclusive)
985 return image->queue_family_mask;
986 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
987 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
988 if (family == VK_QUEUE_FAMILY_IGNORED)
989 return 1u << queue_family;
990 return 1u << family;
991 }
992
993 VkResult
994 radv_CreateImage(VkDevice device,
995 const VkImageCreateInfo *pCreateInfo,
996 const VkAllocationCallbacks *pAllocator,
997 VkImage *pImage)
998 {
999 return radv_image_create(device,
1000 &(struct radv_image_create_info) {
1001 .vk_info = pCreateInfo,
1002 .scanout = false,
1003 },
1004 pAllocator,
1005 pImage);
1006 }
1007
1008 void
1009 radv_DestroyImage(VkDevice _device, VkImage _image,
1010 const VkAllocationCallbacks *pAllocator)
1011 {
1012 RADV_FROM_HANDLE(radv_device, device, _device);
1013 RADV_FROM_HANDLE(radv_image, image, _image);
1014
1015 if (!image)
1016 return;
1017
1018 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1019 device->ws->buffer_destroy(image->bo);
1020
1021 vk_free2(&device->alloc, pAllocator, image);
1022 }
1023
1024 void radv_GetImageSubresourceLayout(
1025 VkDevice device,
1026 VkImage _image,
1027 const VkImageSubresource* pSubresource,
1028 VkSubresourceLayout* pLayout)
1029 {
1030 RADV_FROM_HANDLE(radv_image, image, _image);
1031 int level = pSubresource->mipLevel;
1032 int layer = pSubresource->arrayLayer;
1033 struct radeon_surf *surface = &image->surface;
1034
1035 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
1036 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1037 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
1038 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
1039 pLayout->size = surface->u.legacy.level[level].slice_size;
1040 if (image->type == VK_IMAGE_TYPE_3D)
1041 pLayout->size *= u_minify(image->info.depth, level);
1042 }
1043
1044
1045 VkResult
1046 radv_CreateImageView(VkDevice _device,
1047 const VkImageViewCreateInfo *pCreateInfo,
1048 const VkAllocationCallbacks *pAllocator,
1049 VkImageView *pView)
1050 {
1051 RADV_FROM_HANDLE(radv_device, device, _device);
1052 struct radv_image_view *view;
1053
1054 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1055 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1056 if (view == NULL)
1057 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1058
1059 radv_image_view_init(view, device, pCreateInfo);
1060
1061 *pView = radv_image_view_to_handle(view);
1062
1063 return VK_SUCCESS;
1064 }
1065
1066 void
1067 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1068 const VkAllocationCallbacks *pAllocator)
1069 {
1070 RADV_FROM_HANDLE(radv_device, device, _device);
1071 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1072
1073 if (!iview)
1074 return;
1075 vk_free2(&device->alloc, pAllocator, iview);
1076 }
1077
1078 void radv_buffer_view_init(struct radv_buffer_view *view,
1079 struct radv_device *device,
1080 const VkBufferViewCreateInfo* pCreateInfo,
1081 struct radv_cmd_buffer *cmd_buffer)
1082 {
1083 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1084
1085 view->bo = buffer->bo;
1086 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1087 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1088 view->vk_format = pCreateInfo->format;
1089
1090 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1091 pCreateInfo->offset, view->range, view->state);
1092 }
1093
1094 VkResult
1095 radv_CreateBufferView(VkDevice _device,
1096 const VkBufferViewCreateInfo *pCreateInfo,
1097 const VkAllocationCallbacks *pAllocator,
1098 VkBufferView *pView)
1099 {
1100 RADV_FROM_HANDLE(radv_device, device, _device);
1101 struct radv_buffer_view *view;
1102
1103 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1104 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1105 if (!view)
1106 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1107
1108 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1109
1110 *pView = radv_buffer_view_to_handle(view);
1111
1112 return VK_SUCCESS;
1113 }
1114
1115 void
1116 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1117 const VkAllocationCallbacks *pAllocator)
1118 {
1119 RADV_FROM_HANDLE(radv_device, device, _device);
1120 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1121
1122 if (!view)
1123 return;
1124
1125 vk_free2(&device->alloc, pAllocator, view);
1126 }