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radv: Enable DCC with transfers.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66 static int
67 radv_init_surface(struct radv_device *device,
68 struct radeon_surf *surface,
69 const struct radv_image_create_info *create_info)
70 {
71 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
72 unsigned array_mode = radv_choose_tiling(device, create_info);
73 const struct vk_format_description *desc =
74 vk_format_description(pCreateInfo->format);
75 bool is_depth, is_stencil, blendable;
76
77 is_depth = vk_format_has_depth(desc);
78 is_stencil = vk_format_has_stencil(desc);
79
80 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
81 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
82
83 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
84 /* align byte per element on dword */
85 if (surface->bpe == 3) {
86 surface->bpe = 4;
87 }
88 surface->flags = RADEON_SURF_SET(array_mode, MODE);
89
90 switch (pCreateInfo->imageType){
91 case VK_IMAGE_TYPE_1D:
92 if (pCreateInfo->arrayLayers > 1)
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
94 else
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
96 break;
97 case VK_IMAGE_TYPE_2D:
98 if (pCreateInfo->arrayLayers > 1)
99 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
100 else
101 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
102 break;
103 case VK_IMAGE_TYPE_3D:
104 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
105 break;
106 default:
107 unreachable("unhandled image type");
108 }
109
110 if (is_depth) {
111 surface->flags |= RADEON_SURF_ZBUFFER;
112 if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
113 !(pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
114 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR)) &&
115 pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
116 pCreateInfo->mipLevels <= 1 &&
117 device->physical_device->rad_info.chip_class >= VI &&
118 ((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
119 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
120 (device->physical_device->rad_info.chip_class >= GFX9 &&
121 pCreateInfo->format == VK_FORMAT_D16_UNORM)))
122 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
123 }
124
125 if (is_stencil)
126 surface->flags |= RADEON_SURF_SBUFFER;
127
128 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
129
130 bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
131 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
132 const struct VkImageFormatListCreateInfoKHR *format_list =
133 (const struct VkImageFormatListCreateInfoKHR *)
134 vk_find_struct_const(pCreateInfo->pNext,
135 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
136
137 /* We have to ignore the existence of the list if viewFormatCount = 0 */
138 if (format_list && format_list->viewFormatCount) {
139 /* compatibility is transitive, so we only need to check
140 * one format with everything else. */
141 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
142 if (!radv_dcc_formats_compatible(pCreateInfo->format,
143 format_list->pViewFormats[i]))
144 dcc_compatible_formats = false;
145 }
146 } else {
147 dcc_compatible_formats = false;
148 }
149 }
150
151 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
152 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) ||
153 !dcc_compatible_formats ||
154 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
155 pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
156 device->physical_device->rad_info.chip_class < VI ||
157 create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) ||
158 pCreateInfo->samples >= 2)
159 surface->flags |= RADEON_SURF_DISABLE_DCC;
160 if (create_info->scanout)
161 surface->flags |= RADEON_SURF_SCANOUT;
162 return 0;
163 }
164
165 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
166 {
167 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
168 }
169
170 static inline unsigned
171 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
172 {
173 if (stencil)
174 return image->surface.u.legacy.stencil_tiling_index[level];
175 else
176 return image->surface.u.legacy.tiling_index[level];
177 }
178
179 static unsigned radv_map_swizzle(unsigned swizzle)
180 {
181 switch (swizzle) {
182 case VK_SWIZZLE_Y:
183 return V_008F0C_SQ_SEL_Y;
184 case VK_SWIZZLE_Z:
185 return V_008F0C_SQ_SEL_Z;
186 case VK_SWIZZLE_W:
187 return V_008F0C_SQ_SEL_W;
188 case VK_SWIZZLE_0:
189 return V_008F0C_SQ_SEL_0;
190 case VK_SWIZZLE_1:
191 return V_008F0C_SQ_SEL_1;
192 default: /* VK_SWIZZLE_X */
193 return V_008F0C_SQ_SEL_X;
194 }
195 }
196
197 static void
198 radv_make_buffer_descriptor(struct radv_device *device,
199 struct radv_buffer *buffer,
200 VkFormat vk_format,
201 unsigned offset,
202 unsigned range,
203 uint32_t *state)
204 {
205 const struct vk_format_description *desc;
206 unsigned stride;
207 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
208 uint64_t va = gpu_address + buffer->offset;
209 unsigned num_format, data_format;
210 int first_non_void;
211 desc = vk_format_description(vk_format);
212 first_non_void = vk_format_get_first_non_void_channel(vk_format);
213 stride = desc->block.bits / 8;
214
215 num_format = radv_translate_buffer_numformat(desc, first_non_void);
216 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
217
218 va += offset;
219 state[0] = va;
220 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
221 S_008F04_STRIDE(stride);
222
223 if (device->physical_device->rad_info.chip_class != VI && stride) {
224 range /= stride;
225 }
226
227 state[2] = range;
228 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
229 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
230 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
231 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
232 S_008F0C_NUM_FORMAT(num_format) |
233 S_008F0C_DATA_FORMAT(data_format);
234 }
235
236 static void
237 si_set_mutable_tex_desc_fields(struct radv_device *device,
238 struct radv_image *image,
239 const struct legacy_surf_level *base_level_info,
240 unsigned base_level, unsigned first_level,
241 unsigned block_width, bool is_stencil,
242 bool is_storage_image, uint32_t *state)
243 {
244 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
245 uint64_t va = gpu_address;
246 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
247 uint64_t meta_va = 0;
248 if (chip_class >= GFX9) {
249 if (is_stencil)
250 va += image->surface.u.gfx9.stencil_offset;
251 else
252 va += image->surface.u.gfx9.surf_offset;
253 } else
254 va += base_level_info->offset;
255
256 state[0] = va >> 8;
257 if (chip_class >= GFX9 ||
258 base_level_info->mode == RADEON_SURF_MODE_2D)
259 state[0] |= image->surface.tile_swizzle;
260 state[1] &= C_008F14_BASE_ADDRESS_HI;
261 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
262
263 if (chip_class >= VI) {
264 state[6] &= C_008F28_COMPRESSION_EN;
265 state[7] = 0;
266 if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) {
267 meta_va = gpu_address + image->dcc_offset;
268 if (chip_class <= VI)
269 meta_va += base_level_info->dcc_offset;
270 } else if(!is_storage_image && image->tc_compatible_htile &&
271 image->surface.htile_size) {
272 meta_va = gpu_address + image->htile_offset;
273 }
274
275 if (meta_va) {
276 state[6] |= S_008F28_COMPRESSION_EN(1);
277 state[7] = meta_va >> 8;
278 state[7] |= image->surface.tile_swizzle;
279 }
280 }
281
282 if (chip_class >= GFX9) {
283 state[3] &= C_008F1C_SW_MODE;
284 state[4] &= C_008F20_PITCH_GFX9;
285
286 if (is_stencil) {
287 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
288 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
289 } else {
290 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
291 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
292 }
293
294 state[5] &= C_008F24_META_DATA_ADDRESS &
295 C_008F24_META_PIPE_ALIGNED &
296 C_008F24_META_RB_ALIGNED;
297 if (meta_va) {
298 struct gfx9_surf_meta_flags meta;
299
300 if (image->dcc_offset)
301 meta = image->surface.u.gfx9.dcc;
302 else
303 meta = image->surface.u.gfx9.htile;
304
305 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
306 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
307 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
308 }
309 } else {
310 /* SI-CI-VI */
311 unsigned pitch = base_level_info->nblk_x * block_width;
312 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
313
314 state[3] &= C_008F1C_TILING_INDEX;
315 state[3] |= S_008F1C_TILING_INDEX(index);
316 state[4] &= C_008F20_PITCH_GFX6;
317 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
318 }
319 }
320
321 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
322 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
323 {
324 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
325 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
326
327 /* GFX9 allocates 1D textures as 2D. */
328 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
329 image_type = VK_IMAGE_TYPE_2D;
330 switch (image_type) {
331 case VK_IMAGE_TYPE_1D:
332 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
333 case VK_IMAGE_TYPE_2D:
334 if (nr_samples > 1)
335 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
336 else
337 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
338 case VK_IMAGE_TYPE_3D:
339 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
340 return V_008F1C_SQ_RSRC_IMG_3D;
341 else
342 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
343 default:
344 unreachable("illegale image type");
345 }
346 }
347
348 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
349 {
350 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
351
352 if (swizzle[3] == VK_SWIZZLE_X) {
353 /* For the pre-defined border color values (white, opaque
354 * black, transparent black), the only thing that matters is
355 * that the alpha channel winds up in the correct place
356 * (because the RGB channels are all the same) so either of
357 * these enumerations will work.
358 */
359 if (swizzle[2] == VK_SWIZZLE_Y)
360 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
361 else
362 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
363 } else if (swizzle[0] == VK_SWIZZLE_X) {
364 if (swizzle[1] == VK_SWIZZLE_Y)
365 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
366 else
367 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
368 } else if (swizzle[1] == VK_SWIZZLE_X) {
369 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
370 } else if (swizzle[2] == VK_SWIZZLE_X) {
371 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
372 }
373
374 return bc_swizzle;
375 }
376
377 /**
378 * Build the sampler view descriptor for a texture.
379 */
380 static void
381 si_make_texture_descriptor(struct radv_device *device,
382 struct radv_image *image,
383 bool is_storage_image,
384 VkImageViewType view_type,
385 VkFormat vk_format,
386 const VkComponentMapping *mapping,
387 unsigned first_level, unsigned last_level,
388 unsigned first_layer, unsigned last_layer,
389 unsigned width, unsigned height, unsigned depth,
390 uint32_t *state,
391 uint32_t *fmask_state)
392 {
393 const struct vk_format_description *desc;
394 enum vk_swizzle swizzle[4];
395 int first_non_void;
396 unsigned num_format, data_format, type;
397
398 desc = vk_format_description(vk_format);
399
400 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
401 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
402 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
403 } else {
404 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
405 }
406
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408
409 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
410 if (num_format == ~0) {
411 num_format = 0;
412 }
413
414 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
415 if (data_format == ~0) {
416 data_format = 0;
417 }
418
419 /* S8 with either Z16 or Z32 HTILE need a special format. */
420 if (device->physical_device->rad_info.chip_class >= GFX9 &&
421 vk_format == VK_FORMAT_S8_UINT &&
422 image->tc_compatible_htile) {
423 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
424 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
425 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
426 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
427 }
428 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
429 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
430 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
431 height = 1;
432 depth = image->info.array_size;
433 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
434 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
435 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
436 depth = image->info.array_size;
437 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
438 depth = image->info.array_size / 6;
439
440 state[0] = 0;
441 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
442 S_008F14_NUM_FORMAT_GFX6(num_format));
443 state[2] = (S_008F18_WIDTH(width - 1) |
444 S_008F18_HEIGHT(height - 1) |
445 S_008F18_PERF_MOD(4));
446 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
447 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
448 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
449 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
450 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
451 0 : first_level) |
452 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
453 util_logbase2(image->info.samples) :
454 last_level) |
455 S_008F1C_TYPE(type));
456 state[4] = 0;
457 state[5] = S_008F24_BASE_ARRAY(first_layer);
458 state[6] = 0;
459 state[7] = 0;
460
461 if (device->physical_device->rad_info.chip_class >= GFX9) {
462 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
463
464 /* Depth is the the last accessible layer on Gfx9.
465 * The hw doesn't need to know the total number of layers.
466 */
467 if (type == V_008F1C_SQ_RSRC_IMG_3D)
468 state[4] |= S_008F20_DEPTH(depth - 1);
469 else
470 state[4] |= S_008F20_DEPTH(last_layer);
471
472 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
473 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
474 util_logbase2(image->info.samples) :
475 image->info.levels - 1);
476 } else {
477 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
478 state[4] |= S_008F20_DEPTH(depth - 1);
479 state[5] |= S_008F24_LAST_ARRAY(last_layer);
480 }
481 if (image->dcc_offset) {
482 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
483
484 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
485 } else {
486 /* The last dword is unused by hw. The shader uses it to clear
487 * bits in the first dword of sampler state.
488 */
489 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
490 if (first_level == last_level)
491 state[7] = C_008F30_MAX_ANISO_RATIO;
492 else
493 state[7] = 0xffffffff;
494 }
495 }
496
497 /* Initialize the sampler view for FMASK. */
498 if (image->fmask.size) {
499 uint32_t fmask_format, num_format;
500 uint64_t gpu_address = radv_buffer_get_va(image->bo);
501 uint64_t va;
502
503 va = gpu_address + image->offset + image->fmask.offset;
504
505 if (device->physical_device->rad_info.chip_class >= GFX9) {
506 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
507 switch (image->info.samples) {
508 case 2:
509 num_format = V_008F14_IMG_FMASK_8_2_2;
510 break;
511 case 4:
512 num_format = V_008F14_IMG_FMASK_8_4_4;
513 break;
514 case 8:
515 num_format = V_008F14_IMG_FMASK_32_8_8;
516 break;
517 default:
518 unreachable("invalid nr_samples");
519 }
520 } else {
521 switch (image->info.samples) {
522 case 2:
523 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
524 break;
525 case 4:
526 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
527 break;
528 case 8:
529 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
530 break;
531 default:
532 assert(0);
533 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
534 }
535 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
536 }
537
538 fmask_state[0] = va >> 8;
539 fmask_state[0] |= image->fmask.tile_swizzle;
540 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
541 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
542 S_008F14_NUM_FORMAT_GFX6(num_format);
543 fmask_state[2] = S_008F18_WIDTH(width - 1) |
544 S_008F18_HEIGHT(height - 1);
545 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
546 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
547 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
548 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
549 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false));
550 fmask_state[4] = 0;
551 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
552 fmask_state[6] = 0;
553 fmask_state[7] = 0;
554
555 if (device->physical_device->rad_info.chip_class >= GFX9) {
556 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
557 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
558 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
559 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
560 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
561 } else {
562 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
563 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
564 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
565 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
566 }
567 } else if (fmask_state)
568 memset(fmask_state, 0, 8 * 4);
569 }
570
571 static void
572 radv_query_opaque_metadata(struct radv_device *device,
573 struct radv_image *image,
574 struct radeon_bo_metadata *md)
575 {
576 static const VkComponentMapping fixedmapping;
577 uint32_t desc[8], i;
578
579 /* Metadata image format format version 1:
580 * [0] = 1 (metadata format identifier)
581 * [1] = (VENDOR_ID << 16) | PCI_ID
582 * [2:9] = image descriptor for the whole resource
583 * [2] is always 0, because the base address is cleared
584 * [9] is the DCC offset bits [39:8] from the beginning of
585 * the buffer
586 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
587 */
588 md->metadata[0] = 1; /* metadata image format version 1 */
589
590 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
591 md->metadata[1] = si_get_bo_metadata_word1(device);
592
593
594 si_make_texture_descriptor(device, image, false,
595 (VkImageViewType)image->type, image->vk_format,
596 &fixedmapping, 0, image->info.levels - 1, 0,
597 image->info.array_size,
598 image->info.width, image->info.height,
599 image->info.depth,
600 desc, NULL);
601
602 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
603 image->surface.blk_w, false, false, desc);
604
605 /* Clear the base address and set the relative DCC offset. */
606 desc[0] = 0;
607 desc[1] &= C_008F14_BASE_ADDRESS_HI;
608 desc[7] = image->dcc_offset >> 8;
609
610 /* Dwords [2:9] contain the image descriptor. */
611 memcpy(&md->metadata[2], desc, sizeof(desc));
612
613 /* Dwords [10:..] contain the mipmap level offsets. */
614 if (device->physical_device->rad_info.chip_class <= VI) {
615 for (i = 0; i <= image->info.levels - 1; i++)
616 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
617 md->size_metadata = (11 + image->info.levels - 1) * 4;
618 }
619 }
620
621 void
622 radv_init_metadata(struct radv_device *device,
623 struct radv_image *image,
624 struct radeon_bo_metadata *metadata)
625 {
626 struct radeon_surf *surface = &image->surface;
627
628 memset(metadata, 0, sizeof(*metadata));
629
630 if (device->physical_device->rad_info.chip_class >= GFX9) {
631 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
632 } else {
633 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
634 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
635 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
636 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
637 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
638 metadata->u.legacy.bankw = surface->u.legacy.bankw;
639 metadata->u.legacy.bankh = surface->u.legacy.bankh;
640 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
641 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
642 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
643 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
644 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
645 }
646 radv_query_opaque_metadata(device, image, metadata);
647 }
648
649 /* The number of samples can be specified independently of the texture. */
650 static void
651 radv_image_get_fmask_info(struct radv_device *device,
652 struct radv_image *image,
653 unsigned nr_samples,
654 struct radv_fmask_info *out)
655 {
656 /* FMASK is allocated like an ordinary texture. */
657 struct radeon_surf fmask = {};
658 struct ac_surf_info info = image->info;
659 memset(out, 0, sizeof(*out));
660
661 if (device->physical_device->rad_info.chip_class >= GFX9) {
662 out->alignment = image->surface.u.gfx9.fmask_alignment;
663 out->size = image->surface.u.gfx9.fmask_size;
664 return;
665 }
666
667 fmask.blk_w = image->surface.blk_w;
668 fmask.blk_h = image->surface.blk_h;
669 info.samples = 1;
670 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
671
672 if (!image->shareable)
673 info.surf_index = &device->fmask_mrt_offset_counter;
674
675 /* Force 2D tiling if it wasn't set. This may occur when creating
676 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
677 * destination buffer must have an FMASK too. */
678 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
679 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
680
681 switch (nr_samples) {
682 case 2:
683 case 4:
684 fmask.bpe = 1;
685 break;
686 case 8:
687 fmask.bpe = 4;
688 break;
689 default:
690 return;
691 }
692
693 device->ws->surface_init(device->ws, &info, &fmask);
694 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
695
696 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
697 if (out->slice_tile_max)
698 out->slice_tile_max -= 1;
699
700 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
701 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
702 out->bank_height = fmask.u.legacy.bankh;
703 out->tile_swizzle = fmask.tile_swizzle;
704 out->alignment = MAX2(256, fmask.surf_alignment);
705 out->size = fmask.surf_size;
706
707 assert(!out->tile_swizzle || !image->shareable);
708 }
709
710 static void
711 radv_image_alloc_fmask(struct radv_device *device,
712 struct radv_image *image)
713 {
714 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
715
716 image->fmask.offset = align64(image->size, image->fmask.alignment);
717 image->size = image->fmask.offset + image->fmask.size;
718 image->alignment = MAX2(image->alignment, image->fmask.alignment);
719 }
720
721 static void
722 radv_image_get_cmask_info(struct radv_device *device,
723 struct radv_image *image,
724 struct radv_cmask_info *out)
725 {
726 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
727 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
728 unsigned cl_width, cl_height;
729
730 if (device->physical_device->rad_info.chip_class >= GFX9) {
731 out->alignment = image->surface.u.gfx9.cmask_alignment;
732 out->size = image->surface.u.gfx9.cmask_size;
733 return;
734 }
735
736 switch (num_pipes) {
737 case 2:
738 cl_width = 32;
739 cl_height = 16;
740 break;
741 case 4:
742 cl_width = 32;
743 cl_height = 32;
744 break;
745 case 8:
746 cl_width = 64;
747 cl_height = 32;
748 break;
749 case 16: /* Hawaii */
750 cl_width = 64;
751 cl_height = 64;
752 break;
753 default:
754 assert(0);
755 return;
756 }
757
758 unsigned base_align = num_pipes * pipe_interleave_bytes;
759
760 unsigned width = align(image->info.width, cl_width*8);
761 unsigned height = align(image->info.height, cl_height*8);
762 unsigned slice_elements = (width * height) / (8*8);
763
764 /* Each element of CMASK is a nibble. */
765 unsigned slice_bytes = slice_elements / 2;
766
767 out->slice_tile_max = (width * height) / (128*128);
768 if (out->slice_tile_max)
769 out->slice_tile_max -= 1;
770
771 out->alignment = MAX2(256, base_align);
772 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
773 align(slice_bytes, base_align);
774 }
775
776 static void
777 radv_image_alloc_cmask(struct radv_device *device,
778 struct radv_image *image)
779 {
780 uint32_t clear_value_size = 0;
781 radv_image_get_cmask_info(device, image, &image->cmask);
782
783 image->cmask.offset = align64(image->size, image->cmask.alignment);
784 /* + 8 for storing the clear values */
785 if (!image->clear_value_offset) {
786 image->clear_value_offset = image->cmask.offset + image->cmask.size;
787 clear_value_size = 8;
788 }
789 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
790 image->alignment = MAX2(image->alignment, image->cmask.alignment);
791 }
792
793 static void
794 radv_image_alloc_dcc(struct radv_image *image)
795 {
796 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
797 /* + 16 for storing the clear values + dcc pred */
798 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
799 image->dcc_pred_offset = image->clear_value_offset + 8;
800 image->size = image->dcc_offset + image->surface.dcc_size + 16;
801 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
802 }
803
804 static void
805 radv_image_alloc_htile(struct radv_image *image)
806 {
807 image->htile_offset = align64(image->size, image->surface.htile_alignment);
808
809 /* + 8 for storing the clear values */
810 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
811 image->size = image->clear_value_offset + 8;
812 image->alignment = align64(image->alignment, image->surface.htile_alignment);
813 }
814
815 static inline bool
816 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
817 {
818 if (image->info.samples <= 1 &&
819 image->info.width * image->info.height <= 512 * 512) {
820 /* Do not enable CMASK or DCC for small surfaces where the cost
821 * of the eliminate pass can be higher than the benefit of fast
822 * clear. RadeonSI does this, but the image threshold is
823 * different.
824 */
825 return false;
826 }
827
828 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
829 (image->exclusive || image->queue_family_mask == 1);
830 }
831
832 static inline bool
833 radv_image_can_enable_dcc(struct radv_image *image)
834 {
835 return radv_image_can_enable_dcc_or_cmask(image) &&
836 image->surface.dcc_size;
837 }
838
839 static inline bool
840 radv_image_can_enable_cmask(struct radv_image *image)
841 {
842 if (image->surface.bpe > 8 && image->info.samples == 1) {
843 /* Do not enable CMASK for non-MSAA images (fast color clear)
844 * because 128 bit formats are not supported, but FMASK might
845 * still be used.
846 */
847 return false;
848 }
849
850 return radv_image_can_enable_dcc_or_cmask(image) &&
851 image->info.levels == 1 &&
852 image->info.depth == 1 &&
853 !image->surface.is_linear;
854 }
855
856 static inline bool
857 radv_image_can_enable_fmask(struct radv_image *image)
858 {
859 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
860 }
861
862 static inline bool
863 radv_image_can_enable_htile(struct radv_image *image)
864 {
865 return image->info.levels == 1 && vk_format_is_depth(image->vk_format);
866 }
867
868 VkResult
869 radv_image_create(VkDevice _device,
870 const struct radv_image_create_info *create_info,
871 const VkAllocationCallbacks* alloc,
872 VkImage *pImage)
873 {
874 RADV_FROM_HANDLE(radv_device, device, _device);
875 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
876 struct radv_image *image = NULL;
877 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
878
879 radv_assert(pCreateInfo->mipLevels > 0);
880 radv_assert(pCreateInfo->arrayLayers > 0);
881 radv_assert(pCreateInfo->samples > 0);
882 radv_assert(pCreateInfo->extent.width > 0);
883 radv_assert(pCreateInfo->extent.height > 0);
884 radv_assert(pCreateInfo->extent.depth > 0);
885
886 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
887 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
888 if (!image)
889 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
890
891 image->type = pCreateInfo->imageType;
892 image->info.width = pCreateInfo->extent.width;
893 image->info.height = pCreateInfo->extent.height;
894 image->info.depth = pCreateInfo->extent.depth;
895 image->info.samples = pCreateInfo->samples;
896 image->info.array_size = pCreateInfo->arrayLayers;
897 image->info.levels = pCreateInfo->mipLevels;
898
899 image->vk_format = pCreateInfo->format;
900 image->tiling = pCreateInfo->tiling;
901 image->usage = pCreateInfo->usage;
902 image->flags = pCreateInfo->flags;
903
904 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
905 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
906 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
907 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
908 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
909 else
910 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
911 }
912
913 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
914 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
915 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
916 image->info.surf_index = &device->image_mrt_offset_counter;
917 }
918
919 radv_init_surface(device, &image->surface, create_info);
920
921 device->ws->surface_init(device->ws, &image->info, &image->surface);
922
923 image->size = image->surface.surf_size;
924 image->alignment = image->surface.surf_alignment;
925
926 /* Try to enable DCC first. */
927 if (radv_image_can_enable_dcc(image)) {
928 radv_image_alloc_dcc(image);
929 } else {
930 /* When DCC cannot be enabled, try CMASK. */
931 image->surface.dcc_size = 0;
932 if (radv_image_can_enable_cmask(image)) {
933 radv_image_alloc_cmask(device, image);
934 }
935 }
936
937 /* Try to enable FMASK for multisampled images. */
938 if (radv_image_can_enable_fmask(image)) {
939 radv_image_alloc_fmask(device, image);
940 } else {
941 /* Otherwise, try to enable HTILE for depth surfaces. */
942 if (radv_image_can_enable_htile(image) &&
943 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
944 radv_image_alloc_htile(image);
945 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
946 } else {
947 image->surface.htile_size = 0;
948 }
949 }
950
951 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
952 image->alignment = MAX2(image->alignment, 4096);
953 image->size = align64(image->size, image->alignment);
954 image->offset = 0;
955
956 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
957 0, RADEON_FLAG_VIRTUAL);
958 if (!image->bo) {
959 vk_free2(&device->alloc, alloc, image);
960 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
961 }
962 }
963
964 *pImage = radv_image_to_handle(image);
965
966 return VK_SUCCESS;
967 }
968
969 static void
970 radv_image_view_make_descriptor(struct radv_image_view *iview,
971 struct radv_device *device,
972 const VkComponentMapping *components,
973 bool is_storage_image)
974 {
975 struct radv_image *image = iview->image;
976 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
977 uint32_t blk_w;
978 uint32_t *descriptor;
979 uint32_t hw_level = 0;
980
981 if (is_storage_image) {
982 descriptor = iview->storage_descriptor;
983 } else {
984 descriptor = iview->descriptor;
985 }
986
987 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
988 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
989
990 if (device->physical_device->rad_info.chip_class >= GFX9)
991 hw_level = iview->base_mip;
992 si_make_texture_descriptor(device, image, is_storage_image,
993 iview->type,
994 iview->vk_format,
995 components,
996 hw_level, hw_level + iview->level_count - 1,
997 iview->base_layer,
998 iview->base_layer + iview->layer_count - 1,
999 iview->extent.width,
1000 iview->extent.height,
1001 iview->extent.depth,
1002 descriptor,
1003 descriptor + 8);
1004
1005 const struct legacy_surf_level *base_level_info = NULL;
1006 if (device->physical_device->rad_info.chip_class <= GFX9) {
1007 if (is_stencil)
1008 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1009 else
1010 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1011 }
1012 si_set_mutable_tex_desc_fields(device, image,
1013 base_level_info,
1014 iview->base_mip,
1015 iview->base_mip,
1016 blk_w, is_stencil, is_storage_image, descriptor);
1017 }
1018
1019 void
1020 radv_image_view_init(struct radv_image_view *iview,
1021 struct radv_device *device,
1022 const VkImageViewCreateInfo* pCreateInfo)
1023 {
1024 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1025 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1026
1027 switch (image->type) {
1028 case VK_IMAGE_TYPE_1D:
1029 case VK_IMAGE_TYPE_2D:
1030 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1031 break;
1032 case VK_IMAGE_TYPE_3D:
1033 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1034 <= radv_minify(image->info.depth, range->baseMipLevel));
1035 break;
1036 default:
1037 unreachable("bad VkImageType");
1038 }
1039 iview->image = image;
1040 iview->bo = image->bo;
1041 iview->type = pCreateInfo->viewType;
1042 iview->vk_format = pCreateInfo->format;
1043 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1044
1045 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1046 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1047 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1048 iview->vk_format = vk_format_depth_only(iview->vk_format);
1049 }
1050
1051 if (device->physical_device->rad_info.chip_class >= GFX9) {
1052 iview->extent = (VkExtent3D) {
1053 .width = image->info.width,
1054 .height = image->info.height,
1055 .depth = image->info.depth,
1056 };
1057 } else {
1058 iview->extent = (VkExtent3D) {
1059 .width = radv_minify(image->info.width , range->baseMipLevel),
1060 .height = radv_minify(image->info.height, range->baseMipLevel),
1061 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1062 };
1063 }
1064
1065 if (iview->vk_format != image->vk_format) {
1066 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
1067 vk_format_get_blockwidth(image->vk_format));
1068 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
1069 vk_format_get_blockheight(image->vk_format));
1070 }
1071
1072 iview->base_layer = range->baseArrayLayer;
1073 iview->layer_count = radv_get_layerCount(image, range);
1074 iview->base_mip = range->baseMipLevel;
1075 iview->level_count = radv_get_levelCount(image, range);
1076
1077 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1078 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1079 }
1080
1081 bool radv_layout_has_htile(const struct radv_image *image,
1082 VkImageLayout layout,
1083 unsigned queue_mask)
1084 {
1085 if (image->surface.htile_size && image->tc_compatible_htile)
1086 return layout != VK_IMAGE_LAYOUT_GENERAL;
1087
1088 return image->surface.htile_size &&
1089 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1090 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1091 queue_mask == (1u << RADV_QUEUE_GENERAL);
1092 }
1093
1094 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1095 VkImageLayout layout,
1096 unsigned queue_mask)
1097 {
1098 if (image->surface.htile_size && image->tc_compatible_htile)
1099 return layout != VK_IMAGE_LAYOUT_GENERAL;
1100
1101 return image->surface.htile_size &&
1102 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1103 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1104 queue_mask == (1u << RADV_QUEUE_GENERAL);
1105 }
1106
1107 bool radv_layout_can_fast_clear(const struct radv_image *image,
1108 VkImageLayout layout,
1109 unsigned queue_mask)
1110 {
1111 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1112 queue_mask == (1u << RADV_QUEUE_GENERAL);
1113 }
1114
1115 bool radv_layout_dcc_compressed(const struct radv_image *image,
1116 VkImageLayout layout,
1117 unsigned queue_mask)
1118 {
1119 /* Don't compress compute transfer dst, as image stores are not supported. */
1120 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1121 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1122 return false;
1123
1124 return image->surface.num_dcc_levels > 0 && layout != VK_IMAGE_LAYOUT_GENERAL;
1125 }
1126
1127
1128 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1129 {
1130 if (!image->exclusive)
1131 return image->queue_family_mask;
1132 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1133 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1134 if (family == VK_QUEUE_FAMILY_IGNORED)
1135 return 1u << queue_family;
1136 return 1u << family;
1137 }
1138
1139 VkResult
1140 radv_CreateImage(VkDevice device,
1141 const VkImageCreateInfo *pCreateInfo,
1142 const VkAllocationCallbacks *pAllocator,
1143 VkImage *pImage)
1144 {
1145 const struct wsi_image_create_info *wsi_info =
1146 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1147 bool scanout = wsi_info && wsi_info->scanout;
1148
1149 return radv_image_create(device,
1150 &(struct radv_image_create_info) {
1151 .vk_info = pCreateInfo,
1152 .scanout = scanout,
1153 },
1154 pAllocator,
1155 pImage);
1156 }
1157
1158 void
1159 radv_DestroyImage(VkDevice _device, VkImage _image,
1160 const VkAllocationCallbacks *pAllocator)
1161 {
1162 RADV_FROM_HANDLE(radv_device, device, _device);
1163 RADV_FROM_HANDLE(radv_image, image, _image);
1164
1165 if (!image)
1166 return;
1167
1168 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1169 device->ws->buffer_destroy(image->bo);
1170
1171 vk_free2(&device->alloc, pAllocator, image);
1172 }
1173
1174 void radv_GetImageSubresourceLayout(
1175 VkDevice _device,
1176 VkImage _image,
1177 const VkImageSubresource* pSubresource,
1178 VkSubresourceLayout* pLayout)
1179 {
1180 RADV_FROM_HANDLE(radv_image, image, _image);
1181 RADV_FROM_HANDLE(radv_device, device, _device);
1182 int level = pSubresource->mipLevel;
1183 int layer = pSubresource->arrayLayer;
1184 struct radeon_surf *surface = &image->surface;
1185
1186 if (device->physical_device->rad_info.chip_class >= GFX9) {
1187 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1188 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1189 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1190 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1191 pLayout->size = surface->u.gfx9.surf_slice_size;
1192 if (image->type == VK_IMAGE_TYPE_3D)
1193 pLayout->size *= u_minify(image->info.depth, level);
1194 } else {
1195 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1196 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1197 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1198 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1199 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1200 if (image->type == VK_IMAGE_TYPE_3D)
1201 pLayout->size *= u_minify(image->info.depth, level);
1202 }
1203 }
1204
1205
1206 VkResult
1207 radv_CreateImageView(VkDevice _device,
1208 const VkImageViewCreateInfo *pCreateInfo,
1209 const VkAllocationCallbacks *pAllocator,
1210 VkImageView *pView)
1211 {
1212 RADV_FROM_HANDLE(radv_device, device, _device);
1213 struct radv_image_view *view;
1214
1215 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1216 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1217 if (view == NULL)
1218 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1219
1220 radv_image_view_init(view, device, pCreateInfo);
1221
1222 *pView = radv_image_view_to_handle(view);
1223
1224 return VK_SUCCESS;
1225 }
1226
1227 void
1228 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1229 const VkAllocationCallbacks *pAllocator)
1230 {
1231 RADV_FROM_HANDLE(radv_device, device, _device);
1232 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1233
1234 if (!iview)
1235 return;
1236 vk_free2(&device->alloc, pAllocator, iview);
1237 }
1238
1239 void radv_buffer_view_init(struct radv_buffer_view *view,
1240 struct radv_device *device,
1241 const VkBufferViewCreateInfo* pCreateInfo)
1242 {
1243 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1244
1245 view->bo = buffer->bo;
1246 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1247 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1248 view->vk_format = pCreateInfo->format;
1249
1250 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1251 pCreateInfo->offset, view->range, view->state);
1252 }
1253
1254 VkResult
1255 radv_CreateBufferView(VkDevice _device,
1256 const VkBufferViewCreateInfo *pCreateInfo,
1257 const VkAllocationCallbacks *pAllocator,
1258 VkBufferView *pView)
1259 {
1260 RADV_FROM_HANDLE(radv_device, device, _device);
1261 struct radv_buffer_view *view;
1262
1263 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1265 if (!view)
1266 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1267
1268 radv_buffer_view_init(view, device, pCreateInfo);
1269
1270 *pView = radv_buffer_view_to_handle(view);
1271
1272 return VK_SUCCESS;
1273 }
1274
1275 void
1276 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1277 const VkAllocationCallbacks *pAllocator)
1278 {
1279 RADV_FROM_HANDLE(radv_device, device, _device);
1280 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1281
1282 if (!view)
1283 return;
1284
1285 vk_free2(&device->alloc, pAllocator, view);
1286 }