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radv: add texture descriptor/fmask/cmask support for GFX9
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
31 #include "sid.h"
32 #include "gfx9d.h"
33 #include "util/debug.h"
34 static unsigned
35 radv_choose_tiling(struct radv_device *Device,
36 const struct radv_image_create_info *create_info)
37 {
38 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
39
40 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
41 assert(pCreateInfo->samples <= 1);
42 return RADEON_SURF_MODE_LINEAR_ALIGNED;
43 }
44
45 /* Textures with a very small height are recommended to be linear. */
46 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
47 /* Only very thin and long 2D textures should benefit from
48 * linear_aligned. */
49 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
50 return RADEON_SURF_MODE_LINEAR_ALIGNED;
51
52 /* MSAA resources must be 2D tiled. */
53 if (pCreateInfo->samples > 1)
54 return RADEON_SURF_MODE_2D;
55
56 return RADEON_SURF_MODE_2D;
57 }
58 static int
59 radv_init_surface(struct radv_device *device,
60 struct radeon_surf *surface,
61 const struct radv_image_create_info *create_info)
62 {
63 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
64 unsigned array_mode = radv_choose_tiling(device, create_info);
65 const struct vk_format_description *desc =
66 vk_format_description(pCreateInfo->format);
67 bool is_depth, is_stencil, blendable;
68
69 is_depth = vk_format_has_depth(desc);
70 is_stencil = vk_format_has_stencil(desc);
71
72 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
73 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
74
75 surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
76 /* align byte per element on dword */
77 if (surface->bpe == 3) {
78 surface->bpe = 4;
79 }
80 surface->flags = RADEON_SURF_SET(array_mode, MODE);
81
82 switch (pCreateInfo->imageType){
83 case VK_IMAGE_TYPE_1D:
84 if (pCreateInfo->arrayLayers > 1)
85 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
86 else
87 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
88 break;
89 case VK_IMAGE_TYPE_2D:
90 if (pCreateInfo->arrayLayers > 1)
91 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
92 else
93 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
94 break;
95 case VK_IMAGE_TYPE_3D:
96 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
97 break;
98 default:
99 unreachable("unhandled image type");
100 }
101
102 if (is_depth) {
103 surface->flags |= RADEON_SURF_ZBUFFER;
104 }
105
106 if (is_stencil)
107 surface->flags |= RADEON_SURF_SBUFFER;
108
109 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
110
111 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
112 VK_IMAGE_USAGE_STORAGE_BIT)) ||
113 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
114 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
115 device->physical_device->rad_info.chip_class < VI ||
116 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
117 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
118 surface->flags |= RADEON_SURF_DISABLE_DCC;
119 if (create_info->scanout)
120 surface->flags |= RADEON_SURF_SCANOUT;
121 return 0;
122 }
123 #define ATI_VENDOR_ID 0x1002
124 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
125 {
126 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
127 }
128
129 static inline unsigned
130 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
131 {
132 if (stencil)
133 return image->surface.u.legacy.stencil_tiling_index[level];
134 else
135 return image->surface.u.legacy.tiling_index[level];
136 }
137
138 static unsigned radv_map_swizzle(unsigned swizzle)
139 {
140 switch (swizzle) {
141 case VK_SWIZZLE_Y:
142 return V_008F0C_SQ_SEL_Y;
143 case VK_SWIZZLE_Z:
144 return V_008F0C_SQ_SEL_Z;
145 case VK_SWIZZLE_W:
146 return V_008F0C_SQ_SEL_W;
147 case VK_SWIZZLE_0:
148 return V_008F0C_SQ_SEL_0;
149 case VK_SWIZZLE_1:
150 return V_008F0C_SQ_SEL_1;
151 default: /* VK_SWIZZLE_X */
152 return V_008F0C_SQ_SEL_X;
153 }
154 }
155
156 static void
157 radv_make_buffer_descriptor(struct radv_device *device,
158 struct radv_buffer *buffer,
159 VkFormat vk_format,
160 unsigned offset,
161 unsigned range,
162 uint32_t *state)
163 {
164 const struct vk_format_description *desc;
165 unsigned stride;
166 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
167 uint64_t va = gpu_address + buffer->offset;
168 unsigned num_format, data_format;
169 int first_non_void;
170 desc = vk_format_description(vk_format);
171 first_non_void = vk_format_get_first_non_void_channel(vk_format);
172 stride = desc->block.bits / 8;
173
174 num_format = radv_translate_buffer_numformat(desc, first_non_void);
175 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
176
177 va += offset;
178 state[0] = va;
179 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
180 S_008F04_STRIDE(stride);
181 state[2] = range;
182 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
183 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
184 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
185 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
186 S_008F0C_NUM_FORMAT(num_format) |
187 S_008F0C_DATA_FORMAT(data_format);
188 }
189
190 static void
191 si_set_mutable_tex_desc_fields(struct radv_device *device,
192 struct radv_image *image,
193 const struct legacy_surf_level *base_level_info,
194 unsigned base_level, unsigned first_level,
195 unsigned block_width, bool is_stencil,
196 uint32_t *state)
197 {
198 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
199 uint64_t va = gpu_address;
200 unsigned pitch = base_level_info->nblk_x * block_width;
201 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
202 uint64_t meta_va = 0;
203 if (chip_class >= GFX9) {
204 if (is_stencil)
205 va += image->surface.u.gfx9.stencil_offset;
206 else
207 va += image->surface.u.gfx9.surf_offset;
208 } else
209 va += base_level_info->offset;
210
211 state[0] = va >> 8;
212 state[1] &= C_008F14_BASE_ADDRESS_HI;
213 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
214 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
215 is_stencil));
216 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
217
218 if (chip_class >= VI) {
219 state[6] &= C_008F28_COMPRESSION_EN;
220 state[7] = 0;
221 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
222 uint64_t meta_va = gpu_address + image->dcc_offset;
223 if (chip_class <= VI)
224 meta_va += base_level_info->dcc_offset;
225 state[6] |= S_008F28_COMPRESSION_EN(1);
226 state[7] = meta_va >> 8;
227
228 }
229 }
230
231 if (chip_class >= GFX9) {
232 state[3] &= C_008F1C_SW_MODE;
233 state[4] &= C_008F20_PITCH_GFX9;
234
235 if (is_stencil) {
236 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
237 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
238 } else {
239 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
240 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
241 }
242
243 state[5] &= C_008F24_META_DATA_ADDRESS &
244 C_008F24_META_PIPE_ALIGNED &
245 C_008F24_META_RB_ALIGNED;
246 if (meta_va) {
247 struct gfx9_surf_meta_flags meta;
248
249 if (image->dcc_offset)
250 meta = image->surface.u.gfx9.dcc;
251 else
252 meta = image->surface.u.gfx9.htile;
253
254 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
255 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
256 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
257 }
258 } else {
259 /* SI-CI-VI */
260 unsigned pitch = base_level_info->nblk_x * block_width;
261 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
262
263 state[3] &= C_008F1C_TILING_INDEX;
264 state[3] |= S_008F1C_TILING_INDEX(index);
265 state[4] &= C_008F20_PITCH_GFX6;
266 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
267 }
268 }
269
270 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
271 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
272 {
273 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
274 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
275 switch (image_type) {
276 case VK_IMAGE_TYPE_1D:
277 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
278 case VK_IMAGE_TYPE_2D:
279 if (nr_samples > 1)
280 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
281 else
282 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
283 case VK_IMAGE_TYPE_3D:
284 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
285 return V_008F1C_SQ_RSRC_IMG_3D;
286 else
287 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
288 default:
289 unreachable("illegale image type");
290 }
291 }
292
293 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
294 {
295 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
296
297 if (swizzle[3] == VK_SWIZZLE_X) {
298 /* For the pre-defined border color values (white, opaque
299 * black, transparent black), the only thing that matters is
300 * that the alpha channel winds up in the correct place
301 * (because the RGB channels are all the same) so either of
302 * these enumerations will work.
303 */
304 if (swizzle[2] == VK_SWIZZLE_Y)
305 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
306 else
307 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
308 } else if (swizzle[0] == VK_SWIZZLE_X) {
309 if (swizzle[1] == VK_SWIZZLE_Y)
310 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
311 else
312 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
313 } else if (swizzle[1] == VK_SWIZZLE_X) {
314 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
315 } else if (swizzle[2] == VK_SWIZZLE_X) {
316 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
317 }
318
319 return bc_swizzle;
320 }
321
322 /**
323 * Build the sampler view descriptor for a texture.
324 */
325 static void
326 si_make_texture_descriptor(struct radv_device *device,
327 struct radv_image *image,
328 bool sampler,
329 VkImageViewType view_type,
330 VkFormat vk_format,
331 const VkComponentMapping *mapping,
332 unsigned first_level, unsigned last_level,
333 unsigned first_layer, unsigned last_layer,
334 unsigned width, unsigned height, unsigned depth,
335 uint32_t *state,
336 uint32_t *fmask_state)
337 {
338 const struct vk_format_description *desc;
339 enum vk_swizzle swizzle[4];
340 int first_non_void;
341 unsigned num_format, data_format, type;
342
343 desc = vk_format_description(vk_format);
344
345 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
346 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
347 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
348 } else {
349 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
350 }
351
352 first_non_void = vk_format_get_first_non_void_channel(vk_format);
353
354 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
355 if (num_format == ~0) {
356 num_format = 0;
357 }
358
359 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
360 if (data_format == ~0) {
361 data_format = 0;
362 }
363
364 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
365 (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
366 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
367 height = 1;
368 depth = image->info.array_size;
369 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
370 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
371 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
372 depth = image->info.array_size;
373 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
374 depth = image->info.array_size / 6;
375
376 state[0] = 0;
377 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
378 S_008F14_NUM_FORMAT_GFX6(num_format));
379 state[2] = (S_008F18_WIDTH(width - 1) |
380 S_008F18_HEIGHT(height - 1) |
381 S_008F18_PERF_MOD(4));
382 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
383 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
384 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
385 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
386 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
387 0 : first_level) |
388 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
389 util_logbase2(image->info.samples) :
390 last_level) |
391 S_008F1C_TYPE(type));
392 state[4] = 0;
393 state[5] = S_008F24_BASE_ARRAY(first_layer);
394 state[6] = 0;
395 state[7] = 0;
396
397 if (device->physical_device->rad_info.chip_class >= GFX9) {
398 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
399
400 /* Depth is the the last accessible layer on Gfx9.
401 * The hw doesn't need to know the total number of layers.
402 */
403 if (type == V_008F1C_SQ_RSRC_IMG_3D)
404 state[4] |= S_008F20_DEPTH(depth - 1);
405 else
406 state[4] |= S_008F20_DEPTH(last_layer);
407
408 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
409 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
410 util_logbase2(image->info.samples) :
411 last_level);
412 } else {
413 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
414 state[4] |= S_008F20_DEPTH(depth - 1);
415 state[5] |= S_008F24_LAST_ARRAY(last_layer);
416 }
417 if (image->dcc_offset) {
418 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
419
420 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
421 } else {
422 /* The last dword is unused by hw. The shader uses it to clear
423 * bits in the first dword of sampler state.
424 */
425 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
426 if (first_level == last_level)
427 state[7] = C_008F30_MAX_ANISO_RATIO;
428 else
429 state[7] = 0xffffffff;
430 }
431 }
432
433 /* Initialize the sampler view for FMASK. */
434 if (image->fmask.size) {
435 uint32_t fmask_format, num_format;
436 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
437 uint64_t va;
438
439 va = gpu_address + image->offset + image->fmask.offset;
440
441 if (device->physical_device->rad_info.chip_class >= GFX9) {
442 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
443 switch (image->info.samples) {
444 case 2:
445 num_format = V_008F14_IMG_FMASK_8_2_2;
446 break;
447 case 4:
448 num_format = V_008F14_IMG_FMASK_8_4_4;
449 break;
450 case 8:
451 num_format = V_008F14_IMG_FMASK_32_8_8;
452 break;
453 default:
454 unreachable("invalid nr_samples");
455 }
456 } else {
457 switch (image->info.samples) {
458 case 2:
459 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
460 break;
461 case 4:
462 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
463 break;
464 case 8:
465 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
466 break;
467 default:
468 assert(0);
469 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
470 }
471 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
472 }
473
474 fmask_state[0] = va >> 8;
475 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
476 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
477 S_008F14_NUM_FORMAT_GFX6(num_format);
478 fmask_state[2] = S_008F18_WIDTH(width - 1) |
479 S_008F18_HEIGHT(height - 1);
480 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
481 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
482 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
483 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
484 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
485 fmask_state[4] = 0;
486 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
487 fmask_state[6] = 0;
488 fmask_state[7] = 0;
489
490 if (device->physical_device->rad_info.chip_class >= GFX9) {
491 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
492 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
493 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
494 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
495 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
496 } else {
497 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
498 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
499 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
500 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
501 }
502 }
503 }
504
505 static void
506 radv_query_opaque_metadata(struct radv_device *device,
507 struct radv_image *image,
508 struct radeon_bo_metadata *md)
509 {
510 static const VkComponentMapping fixedmapping;
511 uint32_t desc[8], i;
512
513 /* Metadata image format format version 1:
514 * [0] = 1 (metadata format identifier)
515 * [1] = (VENDOR_ID << 16) | PCI_ID
516 * [2:9] = image descriptor for the whole resource
517 * [2] is always 0, because the base address is cleared
518 * [9] is the DCC offset bits [39:8] from the beginning of
519 * the buffer
520 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
521 */
522 md->metadata[0] = 1; /* metadata image format version 1 */
523
524 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
525 md->metadata[1] = si_get_bo_metadata_word1(device);
526
527
528 si_make_texture_descriptor(device, image, true,
529 (VkImageViewType)image->type, image->vk_format,
530 &fixedmapping, 0, image->info.levels - 1, 0,
531 image->info.array_size,
532 image->info.width, image->info.height,
533 image->info.depth,
534 desc, NULL);
535
536 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
537 image->surface.blk_w, false, desc);
538
539 /* Clear the base address and set the relative DCC offset. */
540 desc[0] = 0;
541 desc[1] &= C_008F14_BASE_ADDRESS_HI;
542 desc[7] = image->dcc_offset >> 8;
543
544 /* Dwords [2:9] contain the image descriptor. */
545 memcpy(&md->metadata[2], desc, sizeof(desc));
546
547 /* Dwords [10:..] contain the mipmap level offsets. */
548 for (i = 0; i <= image->info.levels - 1; i++)
549 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
550
551 md->size_metadata = (11 + image->info.levels - 1) * 4;
552 }
553
554 void
555 radv_init_metadata(struct radv_device *device,
556 struct radv_image *image,
557 struct radeon_bo_metadata *metadata)
558 {
559 struct radeon_surf *surface = &image->surface;
560
561 memset(metadata, 0, sizeof(*metadata));
562
563 if (device->physical_device->rad_info.chip_class >= GFX9) {
564 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
565 } else {
566 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
567 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
568 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
569 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
570 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
571 metadata->u.legacy.bankw = surface->u.legacy.bankw;
572 metadata->u.legacy.bankh = surface->u.legacy.bankh;
573 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
574 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
575 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
576 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
577 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
578 }
579 radv_query_opaque_metadata(device, image, metadata);
580 }
581
582 /* The number of samples can be specified independently of the texture. */
583 static void
584 radv_image_get_fmask_info(struct radv_device *device,
585 struct radv_image *image,
586 unsigned nr_samples,
587 struct radv_fmask_info *out)
588 {
589 /* FMASK is allocated like an ordinary texture. */
590 struct radeon_surf fmask = {};
591 struct ac_surf_info info = image->info;
592 memset(out, 0, sizeof(*out));
593
594 if (device->physical_device->rad_info.chip_class >= GFX9) {
595 out->alignment = image->surface.u.gfx9.fmask_alignment;
596 out->size = image->surface.u.gfx9.fmask_size;
597 return;
598 }
599
600 fmask.blk_w = image->surface.blk_w;
601 fmask.blk_h = image->surface.blk_h;
602 info.samples = 1;
603 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
604
605 /* Force 2D tiling if it wasn't set. This may occur when creating
606 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
607 * destination buffer must have an FMASK too. */
608 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
609 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
610
611 switch (nr_samples) {
612 case 2:
613 case 4:
614 fmask.bpe = 1;
615 break;
616 case 8:
617 fmask.bpe = 4;
618 break;
619 default:
620 return;
621 }
622
623 device->ws->surface_init(device->ws, &info, &fmask);
624 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
625
626 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
627 if (out->slice_tile_max)
628 out->slice_tile_max -= 1;
629
630 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
631 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
632 out->bank_height = fmask.u.legacy.bankh;
633 out->alignment = MAX2(256, fmask.surf_alignment);
634 out->size = fmask.surf_size;
635 }
636
637 static void
638 radv_image_alloc_fmask(struct radv_device *device,
639 struct radv_image *image)
640 {
641 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
642
643 image->fmask.offset = align64(image->size, image->fmask.alignment);
644 image->size = image->fmask.offset + image->fmask.size;
645 image->alignment = MAX2(image->alignment, image->fmask.alignment);
646 }
647
648 static void
649 radv_image_get_cmask_info(struct radv_device *device,
650 struct radv_image *image,
651 struct radv_cmask_info *out)
652 {
653 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
654 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
655 unsigned cl_width, cl_height;
656
657 if (device->physical_device->rad_info.chip_class >= GFX9) {
658 out->alignment = image->surface.u.gfx9.cmask_alignment;
659 out->size = image->surface.u.gfx9.cmask_size;
660 return;
661 }
662
663 switch (num_pipes) {
664 case 2:
665 cl_width = 32;
666 cl_height = 16;
667 break;
668 case 4:
669 cl_width = 32;
670 cl_height = 32;
671 break;
672 case 8:
673 cl_width = 64;
674 cl_height = 32;
675 break;
676 case 16: /* Hawaii */
677 cl_width = 64;
678 cl_height = 64;
679 break;
680 default:
681 assert(0);
682 return;
683 }
684
685 unsigned base_align = num_pipes * pipe_interleave_bytes;
686
687 unsigned width = align(image->info.width, cl_width*8);
688 unsigned height = align(image->info.height, cl_height*8);
689 unsigned slice_elements = (width * height) / (8*8);
690
691 /* Each element of CMASK is a nibble. */
692 unsigned slice_bytes = slice_elements / 2;
693
694 out->slice_tile_max = (width * height) / (128*128);
695 if (out->slice_tile_max)
696 out->slice_tile_max -= 1;
697
698 out->alignment = MAX2(256, base_align);
699 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
700 align(slice_bytes, base_align);
701 }
702
703 static void
704 radv_image_alloc_cmask(struct radv_device *device,
705 struct radv_image *image)
706 {
707 radv_image_get_cmask_info(device, image, &image->cmask);
708
709 image->cmask.offset = align64(image->size, image->cmask.alignment);
710 /* + 8 for storing the clear values */
711 image->clear_value_offset = image->cmask.offset + image->cmask.size;
712 image->size = image->cmask.offset + image->cmask.size + 8;
713 image->alignment = MAX2(image->alignment, image->cmask.alignment);
714 }
715
716 static void
717 radv_image_alloc_dcc(struct radv_device *device,
718 struct radv_image *image)
719 {
720 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
721 /* + 8 for storing the clear values */
722 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
723 image->size = image->dcc_offset + image->surface.dcc_size + 8;
724 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
725 }
726
727 static void
728 radv_image_alloc_htile(struct radv_device *device,
729 struct radv_image *image)
730 {
731 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
732 image->surface.htile_size = 0;
733 return;
734 }
735
736 image->htile_offset = align64(image->size, image->surface.htile_alignment);
737
738 /* + 8 for storing the clear values */
739 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
740 image->size = image->clear_value_offset + 8;
741 image->alignment = align64(image->alignment, image->surface.htile_alignment);
742 }
743
744 VkResult
745 radv_image_create(VkDevice _device,
746 const struct radv_image_create_info *create_info,
747 const VkAllocationCallbacks* alloc,
748 VkImage *pImage)
749 {
750 RADV_FROM_HANDLE(radv_device, device, _device);
751 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
752 struct radv_image *image = NULL;
753 bool can_cmask_dcc = false;
754 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
755
756 radv_assert(pCreateInfo->mipLevels > 0);
757 radv_assert(pCreateInfo->arrayLayers > 0);
758 radv_assert(pCreateInfo->samples > 0);
759 radv_assert(pCreateInfo->extent.width > 0);
760 radv_assert(pCreateInfo->extent.height > 0);
761 radv_assert(pCreateInfo->extent.depth > 0);
762
763 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
764 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
765 if (!image)
766 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
767
768 memset(image, 0, sizeof(*image));
769 image->type = pCreateInfo->imageType;
770 image->info.width = pCreateInfo->extent.width;
771 image->info.height = pCreateInfo->extent.height;
772 image->info.depth = pCreateInfo->extent.depth;
773 image->info.samples = pCreateInfo->samples;
774 image->info.array_size = pCreateInfo->arrayLayers;
775 image->info.levels = pCreateInfo->mipLevels;
776
777 image->vk_format = pCreateInfo->format;
778 image->tiling = pCreateInfo->tiling;
779 image->usage = pCreateInfo->usage;
780 image->flags = pCreateInfo->flags;
781
782 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
783 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
784 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
785 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHX)
786 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
787 else
788 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
789 }
790
791 radv_init_surface(device, &image->surface, create_info);
792
793 device->ws->surface_init(device->ws, &image->info, &image->surface);
794
795 image->size = image->surface.surf_size;
796 image->alignment = image->surface.surf_alignment;
797
798 if (image->exclusive || image->queue_family_mask == 1)
799 can_cmask_dcc = true;
800
801 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
802 image->surface.dcc_size && can_cmask_dcc)
803 radv_image_alloc_dcc(device, image);
804 else
805 image->surface.dcc_size = 0;
806
807 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
808 pCreateInfo->mipLevels == 1 &&
809 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
810 radv_image_alloc_cmask(device, image);
811 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
812 radv_image_alloc_fmask(device, image);
813 } else if (vk_format_is_depth(pCreateInfo->format)) {
814
815 radv_image_alloc_htile(device, image);
816 }
817
818 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
819 image->alignment = MAX2(image->alignment, 4096);
820 image->size = align64(image->size, image->alignment);
821 image->offset = 0;
822
823 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
824 0, RADEON_FLAG_VIRTUAL);
825 if (!image->bo) {
826 vk_free2(&device->alloc, alloc, image);
827 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
828 }
829 }
830
831 *pImage = radv_image_to_handle(image);
832
833 return VK_SUCCESS;
834 }
835
836 void
837 radv_image_view_init(struct radv_image_view *iview,
838 struct radv_device *device,
839 const VkImageViewCreateInfo* pCreateInfo,
840 struct radv_cmd_buffer *cmd_buffer,
841 VkImageUsageFlags usage_mask)
842 {
843 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
844 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
845 uint32_t blk_w;
846 bool is_stencil = false;
847 switch (image->type) {
848 case VK_IMAGE_TYPE_1D:
849 case VK_IMAGE_TYPE_2D:
850 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
851 break;
852 case VK_IMAGE_TYPE_3D:
853 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
854 <= radv_minify(image->info.depth, range->baseMipLevel));
855 break;
856 default:
857 unreachable("bad VkImageType");
858 }
859 iview->image = image;
860 iview->bo = image->bo;
861 iview->type = pCreateInfo->viewType;
862 iview->vk_format = pCreateInfo->format;
863 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
864
865 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
866 is_stencil = true;
867 iview->vk_format = vk_format_stencil_only(iview->vk_format);
868 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
869 iview->vk_format = vk_format_depth_only(iview->vk_format);
870 }
871
872 iview->extent = (VkExtent3D) {
873 .width = radv_minify(image->info.width , range->baseMipLevel),
874 .height = radv_minify(image->info.height, range->baseMipLevel),
875 .depth = radv_minify(image->info.depth , range->baseMipLevel),
876 };
877
878 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
879 vk_format_get_blockwidth(image->vk_format));
880 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
881 vk_format_get_blockheight(image->vk_format));
882
883 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
884 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
885 iview->base_layer = range->baseArrayLayer;
886 iview->layer_count = radv_get_layerCount(image, range);
887 iview->base_mip = range->baseMipLevel;
888
889 si_make_texture_descriptor(device, image, false,
890 iview->type,
891 iview->vk_format,
892 &pCreateInfo->components,
893 0, radv_get_levelCount(image, range) - 1,
894 range->baseArrayLayer,
895 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
896 iview->extent.width,
897 iview->extent.height,
898 iview->extent.depth,
899 iview->descriptor,
900 iview->fmask_descriptor);
901 si_set_mutable_tex_desc_fields(device, image,
902 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
903 : &image->surface.u.legacy.level[range->baseMipLevel],
904 range->baseMipLevel,
905 range->baseMipLevel,
906 blk_w, is_stencil, iview->descriptor);
907 }
908
909 bool radv_layout_has_htile(const struct radv_image *image,
910 VkImageLayout layout,
911 unsigned queue_mask)
912 {
913 return image->surface.htile_size &&
914 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
915 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
916 queue_mask == (1u << RADV_QUEUE_GENERAL);
917 }
918
919 bool radv_layout_is_htile_compressed(const struct radv_image *image,
920 VkImageLayout layout,
921 unsigned queue_mask)
922 {
923 return image->surface.htile_size &&
924 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
925 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
926 queue_mask == (1u << RADV_QUEUE_GENERAL);
927 }
928
929 bool radv_layout_can_fast_clear(const struct radv_image *image,
930 VkImageLayout layout,
931 unsigned queue_mask)
932 {
933 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
934 queue_mask == (1u << RADV_QUEUE_GENERAL);
935 }
936
937
938 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
939 {
940 if (!image->exclusive)
941 return image->queue_family_mask;
942 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHX)
943 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
944 if (family == VK_QUEUE_FAMILY_IGNORED)
945 return 1u << queue_family;
946 return 1u << family;
947 }
948
949 VkResult
950 radv_CreateImage(VkDevice device,
951 const VkImageCreateInfo *pCreateInfo,
952 const VkAllocationCallbacks *pAllocator,
953 VkImage *pImage)
954 {
955 return radv_image_create(device,
956 &(struct radv_image_create_info) {
957 .vk_info = pCreateInfo,
958 .scanout = false,
959 },
960 pAllocator,
961 pImage);
962 }
963
964 void
965 radv_DestroyImage(VkDevice _device, VkImage _image,
966 const VkAllocationCallbacks *pAllocator)
967 {
968 RADV_FROM_HANDLE(radv_device, device, _device);
969 RADV_FROM_HANDLE(radv_image, image, _image);
970
971 if (!image)
972 return;
973
974 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
975 device->ws->buffer_destroy(image->bo);
976
977 vk_free2(&device->alloc, pAllocator, image);
978 }
979
980 void radv_GetImageSubresourceLayout(
981 VkDevice device,
982 VkImage _image,
983 const VkImageSubresource* pSubresource,
984 VkSubresourceLayout* pLayout)
985 {
986 RADV_FROM_HANDLE(radv_image, image, _image);
987 int level = pSubresource->mipLevel;
988 int layer = pSubresource->arrayLayer;
989 struct radeon_surf *surface = &image->surface;
990
991 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
992 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
993 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
994 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
995 pLayout->size = surface->u.legacy.level[level].slice_size;
996 if (image->type == VK_IMAGE_TYPE_3D)
997 pLayout->size *= u_minify(image->info.depth, level);
998 }
999
1000
1001 VkResult
1002 radv_CreateImageView(VkDevice _device,
1003 const VkImageViewCreateInfo *pCreateInfo,
1004 const VkAllocationCallbacks *pAllocator,
1005 VkImageView *pView)
1006 {
1007 RADV_FROM_HANDLE(radv_device, device, _device);
1008 struct radv_image_view *view;
1009
1010 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1011 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1012 if (view == NULL)
1013 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1014
1015 radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
1016
1017 *pView = radv_image_view_to_handle(view);
1018
1019 return VK_SUCCESS;
1020 }
1021
1022 void
1023 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1024 const VkAllocationCallbacks *pAllocator)
1025 {
1026 RADV_FROM_HANDLE(radv_device, device, _device);
1027 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1028
1029 if (!iview)
1030 return;
1031 vk_free2(&device->alloc, pAllocator, iview);
1032 }
1033
1034 void radv_buffer_view_init(struct radv_buffer_view *view,
1035 struct radv_device *device,
1036 const VkBufferViewCreateInfo* pCreateInfo,
1037 struct radv_cmd_buffer *cmd_buffer)
1038 {
1039 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1040
1041 view->bo = buffer->bo;
1042 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1043 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1044 view->vk_format = pCreateInfo->format;
1045
1046 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1047 pCreateInfo->offset, view->range, view->state);
1048 }
1049
1050 VkResult
1051 radv_CreateBufferView(VkDevice _device,
1052 const VkBufferViewCreateInfo *pCreateInfo,
1053 const VkAllocationCallbacks *pAllocator,
1054 VkBufferView *pView)
1055 {
1056 RADV_FROM_HANDLE(radv_device, device, _device);
1057 struct radv_buffer_view *view;
1058
1059 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1060 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1061 if (!view)
1062 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1063
1064 radv_buffer_view_init(view, device, pCreateInfo, NULL);
1065
1066 *pView = radv_buffer_view_to_handle(view);
1067
1068 return VK_SUCCESS;
1069 }
1070
1071 void
1072 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1073 const VkAllocationCallbacks *pAllocator)
1074 {
1075 RADV_FROM_HANDLE(radv_device, device, _device);
1076 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1077
1078 if (!view)
1079 return;
1080
1081 vk_free2(&device->alloc, pAllocator, view);
1082 }