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radv: Always disable DCC on shareable images.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps and array layers. */
174 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
175 return false;
176
177 if (radv_surface_has_scanout(device, create_info))
178 return false;
179
180 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
181 * 2x can be enabled with an option.
182 */
183 if (pCreateInfo->samples > 2 ||
184 (pCreateInfo->samples == 2 &&
185 !device->physical_device->dcc_msaa_allowed))
186 return false;
187
188 /* Determine if the formats are DCC compatible. */
189 dcc_compatible_formats =
190 radv_is_colorbuffer_format_supported(pCreateInfo->format,
191 &blendable);
192
193 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
194 const struct VkImageFormatListCreateInfoKHR *format_list =
195 (const struct VkImageFormatListCreateInfoKHR *)
196 vk_find_struct_const(pCreateInfo->pNext,
197 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
198
199 /* We have to ignore the existence of the list if viewFormatCount = 0 */
200 if (format_list && format_list->viewFormatCount) {
201 /* compatibility is transitive, so we only need to check
202 * one format with everything else. */
203 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
204 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
205 continue;
206
207 if (!radv_dcc_formats_compatible(pCreateInfo->format,
208 format_list->pViewFormats[i]))
209 dcc_compatible_formats = false;
210 }
211 } else {
212 dcc_compatible_formats = false;
213 }
214 }
215
216 if (!dcc_compatible_formats)
217 return false;
218
219 return true;
220 }
221
222 static void
223 radv_prefill_surface_from_metadata(struct radv_device *device,
224 struct radeon_surf *surface,
225 const struct radv_image_create_info *create_info)
226 {
227 const struct radeon_bo_metadata *md = create_info->bo_metadata;
228 if (device->physical_device->rad_info.chip_class >= GFX9) {
229 if (md->u.gfx9.swizzle_mode > 0)
230 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
231 else
232 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
233
234 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
235 } else {
236 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
237 surface->u.legacy.bankw = md->u.legacy.bankw;
238 surface->u.legacy.bankh = md->u.legacy.bankh;
239 surface->u.legacy.tile_split = md->u.legacy.tile_split;
240 surface->u.legacy.mtilea = md->u.legacy.mtilea;
241 surface->u.legacy.num_banks = md->u.legacy.num_banks;
242
243 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
244 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
245 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
246 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
247 else
248 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
249
250 }
251 }
252
253 static int
254 radv_init_surface(struct radv_device *device,
255 const struct radv_image *image,
256 struct radeon_surf *surface,
257 unsigned plane_id,
258 const struct radv_image_create_info *create_info)
259 {
260 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
261 unsigned array_mode = radv_choose_tiling(device, create_info);
262 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
263 const struct vk_format_description *desc = vk_format_description(format);
264 bool is_depth, is_stencil;
265
266 is_depth = vk_format_has_depth(desc);
267 is_stencil = vk_format_has_stencil(desc);
268
269 surface->blk_w = vk_format_get_blockwidth(format);
270 surface->blk_h = vk_format_get_blockheight(format);
271
272 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
273 /* align byte per element on dword */
274 if (surface->bpe == 3) {
275 surface->bpe = 4;
276 }
277 if (create_info->bo_metadata) {
278 radv_prefill_surface_from_metadata(device, surface, create_info);
279 } else {
280 surface->flags = RADEON_SURF_SET(array_mode, MODE);
281 }
282
283 switch (pCreateInfo->imageType){
284 case VK_IMAGE_TYPE_1D:
285 if (pCreateInfo->arrayLayers > 1)
286 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
287 else
288 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
289 break;
290 case VK_IMAGE_TYPE_2D:
291 if (pCreateInfo->arrayLayers > 1)
292 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
293 else
294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
295 break;
296 case VK_IMAGE_TYPE_3D:
297 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
298 break;
299 default:
300 unreachable("unhandled image type");
301 }
302
303 if (is_depth) {
304 surface->flags |= RADEON_SURF_ZBUFFER;
305 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
306 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
307 }
308
309 if (is_stencil)
310 surface->flags |= RADEON_SURF_SBUFFER;
311
312 if (device->physical_device->rad_info.chip_class >= GFX9 &&
313 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
314 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
315 vk_format_is_compressed(pCreateInfo->format))
316 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
317
318 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
319
320 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
321 surface->flags |= RADEON_SURF_DISABLE_DCC;
322
323 if (radv_surface_has_scanout(device, create_info))
324 surface->flags |= RADEON_SURF_SCANOUT;
325
326 return 0;
327 }
328
329 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
330 {
331 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
332 }
333
334 static inline unsigned
335 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
336 {
337 if (stencil)
338 return plane->surface.u.legacy.stencil_tiling_index[level];
339 else
340 return plane->surface.u.legacy.tiling_index[level];
341 }
342
343 static unsigned radv_map_swizzle(unsigned swizzle)
344 {
345 switch (swizzle) {
346 case VK_SWIZZLE_Y:
347 return V_008F0C_SQ_SEL_Y;
348 case VK_SWIZZLE_Z:
349 return V_008F0C_SQ_SEL_Z;
350 case VK_SWIZZLE_W:
351 return V_008F0C_SQ_SEL_W;
352 case VK_SWIZZLE_0:
353 return V_008F0C_SQ_SEL_0;
354 case VK_SWIZZLE_1:
355 return V_008F0C_SQ_SEL_1;
356 default: /* VK_SWIZZLE_X */
357 return V_008F0C_SQ_SEL_X;
358 }
359 }
360
361 static void
362 radv_make_buffer_descriptor(struct radv_device *device,
363 struct radv_buffer *buffer,
364 VkFormat vk_format,
365 unsigned offset,
366 unsigned range,
367 uint32_t *state)
368 {
369 const struct vk_format_description *desc;
370 unsigned stride;
371 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
372 uint64_t va = gpu_address + buffer->offset;
373 unsigned num_format, data_format;
374 int first_non_void;
375 desc = vk_format_description(vk_format);
376 first_non_void = vk_format_get_first_non_void_channel(vk_format);
377 stride = desc->block.bits / 8;
378
379 num_format = radv_translate_buffer_numformat(desc, first_non_void);
380 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
381
382 va += offset;
383 state[0] = va;
384 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
385 S_008F04_STRIDE(stride);
386
387 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
388 range /= stride;
389 }
390
391 state[2] = range;
392 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
393 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
394 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
395 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
396 S_008F0C_NUM_FORMAT(num_format) |
397 S_008F0C_DATA_FORMAT(data_format);
398 }
399
400 static void
401 si_set_mutable_tex_desc_fields(struct radv_device *device,
402 struct radv_image *image,
403 const struct legacy_surf_level *base_level_info,
404 unsigned plane_id,
405 unsigned base_level, unsigned first_level,
406 unsigned block_width, bool is_stencil,
407 bool is_storage_image, uint32_t *state)
408 {
409 struct radv_image_plane *plane = &image->planes[plane_id];
410 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
411 uint64_t va = gpu_address + plane->offset;
412 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
413 uint64_t meta_va = 0;
414 if (chip_class >= GFX9) {
415 if (is_stencil)
416 va += plane->surface.u.gfx9.stencil_offset;
417 else
418 va += plane->surface.u.gfx9.surf_offset;
419 } else
420 va += base_level_info->offset;
421
422 state[0] = va >> 8;
423 if (chip_class >= GFX9 ||
424 base_level_info->mode == RADEON_SURF_MODE_2D)
425 state[0] |= plane->surface.tile_swizzle;
426 state[1] &= C_008F14_BASE_ADDRESS_HI;
427 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
428
429 if (chip_class >= GFX8) {
430 state[6] &= C_008F28_COMPRESSION_EN;
431 state[7] = 0;
432 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
433 meta_va = gpu_address + image->dcc_offset;
434 if (chip_class <= GFX8)
435 meta_va += base_level_info->dcc_offset;
436 } else if (!is_storage_image &&
437 radv_image_is_tc_compat_htile(image)) {
438 meta_va = gpu_address + image->htile_offset;
439 }
440
441 if (meta_va) {
442 state[6] |= S_008F28_COMPRESSION_EN(1);
443 state[7] = meta_va >> 8;
444 state[7] |= plane->surface.tile_swizzle;
445 }
446 }
447
448 if (chip_class >= GFX9) {
449 state[3] &= C_008F1C_SW_MODE;
450 state[4] &= C_008F20_PITCH;
451
452 if (is_stencil) {
453 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
454 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
455 } else {
456 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
457 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
458 }
459
460 state[5] &= C_008F24_META_DATA_ADDRESS &
461 C_008F24_META_PIPE_ALIGNED &
462 C_008F24_META_RB_ALIGNED;
463 if (meta_va) {
464 struct gfx9_surf_meta_flags meta;
465
466 if (image->dcc_offset)
467 meta = plane->surface.u.gfx9.dcc;
468 else
469 meta = plane->surface.u.gfx9.htile;
470
471 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
472 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
473 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
474 }
475 } else {
476 /* GFX6-GFX8 */
477 unsigned pitch = base_level_info->nblk_x * block_width;
478 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
479
480 state[3] &= C_008F1C_TILING_INDEX;
481 state[3] |= S_008F1C_TILING_INDEX(index);
482 state[4] &= C_008F20_PITCH;
483 state[4] |= S_008F20_PITCH(pitch - 1);
484 }
485 }
486
487 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
488 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
489 {
490 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
491 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
492
493 /* GFX9 allocates 1D textures as 2D. */
494 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
495 image_type = VK_IMAGE_TYPE_2D;
496 switch (image_type) {
497 case VK_IMAGE_TYPE_1D:
498 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
499 case VK_IMAGE_TYPE_2D:
500 if (nr_samples > 1)
501 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
502 else
503 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
504 case VK_IMAGE_TYPE_3D:
505 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
506 return V_008F1C_SQ_RSRC_IMG_3D;
507 else
508 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
509 default:
510 unreachable("illegal image type");
511 }
512 }
513
514 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
515 {
516 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
517
518 if (swizzle[3] == VK_SWIZZLE_X) {
519 /* For the pre-defined border color values (white, opaque
520 * black, transparent black), the only thing that matters is
521 * that the alpha channel winds up in the correct place
522 * (because the RGB channels are all the same) so either of
523 * these enumerations will work.
524 */
525 if (swizzle[2] == VK_SWIZZLE_Y)
526 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
527 else
528 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
529 } else if (swizzle[0] == VK_SWIZZLE_X) {
530 if (swizzle[1] == VK_SWIZZLE_Y)
531 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
532 else
533 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
534 } else if (swizzle[1] == VK_SWIZZLE_X) {
535 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
536 } else if (swizzle[2] == VK_SWIZZLE_X) {
537 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
538 }
539
540 return bc_swizzle;
541 }
542
543 /**
544 * Build the sampler view descriptor for a texture.
545 */
546 static void
547 si_make_texture_descriptor(struct radv_device *device,
548 struct radv_image *image,
549 bool is_storage_image,
550 VkImageViewType view_type,
551 VkFormat vk_format,
552 const VkComponentMapping *mapping,
553 unsigned first_level, unsigned last_level,
554 unsigned first_layer, unsigned last_layer,
555 unsigned width, unsigned height, unsigned depth,
556 uint32_t *state,
557 uint32_t *fmask_state)
558 {
559 const struct vk_format_description *desc;
560 enum vk_swizzle swizzle[4];
561 int first_non_void;
562 unsigned num_format, data_format, type;
563
564 desc = vk_format_description(vk_format);
565
566 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
567 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
568 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
569 } else {
570 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
571 }
572
573 first_non_void = vk_format_get_first_non_void_channel(vk_format);
574
575 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
576 if (num_format == ~0) {
577 num_format = 0;
578 }
579
580 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
581 if (data_format == ~0) {
582 data_format = 0;
583 }
584
585 /* S8 with either Z16 or Z32 HTILE need a special format. */
586 if (device->physical_device->rad_info.chip_class >= GFX9 &&
587 vk_format == VK_FORMAT_S8_UINT &&
588 radv_image_is_tc_compat_htile(image)) {
589 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
590 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
591 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
592 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
593 }
594 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
595 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
596 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
597 height = 1;
598 depth = image->info.array_size;
599 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
600 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
601 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
602 depth = image->info.array_size;
603 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
604 depth = image->info.array_size / 6;
605
606 state[0] = 0;
607 state[1] = (S_008F14_DATA_FORMAT(data_format) |
608 S_008F14_NUM_FORMAT(num_format));
609 state[2] = (S_008F18_WIDTH(width - 1) |
610 S_008F18_HEIGHT(height - 1) |
611 S_008F18_PERF_MOD(4));
612 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
613 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
614 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
615 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
616 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
617 0 : first_level) |
618 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
619 util_logbase2(image->info.samples) :
620 last_level) |
621 S_008F1C_TYPE(type));
622 state[4] = 0;
623 state[5] = S_008F24_BASE_ARRAY(first_layer);
624 state[6] = 0;
625 state[7] = 0;
626
627 if (device->physical_device->rad_info.chip_class >= GFX9) {
628 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
629
630 /* Depth is the last accessible layer on Gfx9.
631 * The hw doesn't need to know the total number of layers.
632 */
633 if (type == V_008F1C_SQ_RSRC_IMG_3D)
634 state[4] |= S_008F20_DEPTH(depth - 1);
635 else
636 state[4] |= S_008F20_DEPTH(last_layer);
637
638 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
639 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
640 util_logbase2(image->info.samples) :
641 image->info.levels - 1);
642 } else {
643 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
644 state[4] |= S_008F20_DEPTH(depth - 1);
645 state[5] |= S_008F24_LAST_ARRAY(last_layer);
646 }
647 if (image->dcc_offset) {
648 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
649
650 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
651 } else {
652 /* The last dword is unused by hw. The shader uses it to clear
653 * bits in the first dword of sampler state.
654 */
655 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
656 if (first_level == last_level)
657 state[7] = C_008F30_MAX_ANISO_RATIO;
658 else
659 state[7] = 0xffffffff;
660 }
661 }
662
663 /* Initialize the sampler view for FMASK. */
664 if (radv_image_has_fmask(image)) {
665 uint32_t fmask_format, num_format;
666 uint64_t gpu_address = radv_buffer_get_va(image->bo);
667 uint64_t va;
668
669 assert(image->plane_count == 1);
670
671 va = gpu_address + image->offset + image->fmask.offset;
672
673 if (device->physical_device->rad_info.chip_class >= GFX9) {
674 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
675 switch (image->info.samples) {
676 case 2:
677 num_format = V_008F14_IMG_FMASK_8_2_2;
678 break;
679 case 4:
680 num_format = V_008F14_IMG_FMASK_8_4_4;
681 break;
682 case 8:
683 num_format = V_008F14_IMG_FMASK_32_8_8;
684 break;
685 default:
686 unreachable("invalid nr_samples");
687 }
688 } else {
689 switch (image->info.samples) {
690 case 2:
691 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
692 break;
693 case 4:
694 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
695 break;
696 case 8:
697 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
698 break;
699 default:
700 assert(0);
701 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
702 }
703 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
704 }
705
706 fmask_state[0] = va >> 8;
707 fmask_state[0] |= image->fmask.tile_swizzle;
708 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
709 S_008F14_DATA_FORMAT(fmask_format) |
710 S_008F14_NUM_FORMAT(num_format);
711 fmask_state[2] = S_008F18_WIDTH(width - 1) |
712 S_008F18_HEIGHT(height - 1);
713 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
714 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
715 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
716 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
717 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
718 fmask_state[4] = 0;
719 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
720 fmask_state[6] = 0;
721 fmask_state[7] = 0;
722
723 if (device->physical_device->rad_info.chip_class >= GFX9) {
724 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
725 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
726 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
727 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
728 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
729 } else {
730 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
731 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
732 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
733 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
734 }
735 } else if (fmask_state)
736 memset(fmask_state, 0, 8 * 4);
737 }
738
739 static void
740 radv_query_opaque_metadata(struct radv_device *device,
741 struct radv_image *image,
742 struct radeon_bo_metadata *md)
743 {
744 static const VkComponentMapping fixedmapping;
745 uint32_t desc[8], i;
746
747 assert(image->plane_count == 1);
748
749 /* Metadata image format format version 1:
750 * [0] = 1 (metadata format identifier)
751 * [1] = (VENDOR_ID << 16) | PCI_ID
752 * [2:9] = image descriptor for the whole resource
753 * [2] is always 0, because the base address is cleared
754 * [9] is the DCC offset bits [39:8] from the beginning of
755 * the buffer
756 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
757 */
758 md->metadata[0] = 1; /* metadata image format version 1 */
759
760 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
761 md->metadata[1] = si_get_bo_metadata_word1(device);
762
763
764 si_make_texture_descriptor(device, image, false,
765 (VkImageViewType)image->type, image->vk_format,
766 &fixedmapping, 0, image->info.levels - 1, 0,
767 image->info.array_size - 1,
768 image->info.width, image->info.height,
769 image->info.depth,
770 desc, NULL);
771
772 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
773 image->planes[0].surface.blk_w, false, false, desc);
774
775 /* Clear the base address and set the relative DCC offset. */
776 desc[0] = 0;
777 desc[1] &= C_008F14_BASE_ADDRESS_HI;
778 desc[7] = image->dcc_offset >> 8;
779
780 /* Dwords [2:9] contain the image descriptor. */
781 memcpy(&md->metadata[2], desc, sizeof(desc));
782
783 /* Dwords [10:..] contain the mipmap level offsets. */
784 if (device->physical_device->rad_info.chip_class <= GFX8) {
785 for (i = 0; i <= image->info.levels - 1; i++)
786 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
787 md->size_metadata = (11 + image->info.levels - 1) * 4;
788 }
789 }
790
791 void
792 radv_init_metadata(struct radv_device *device,
793 struct radv_image *image,
794 struct radeon_bo_metadata *metadata)
795 {
796 struct radeon_surf *surface = &image->planes[0].surface;
797
798 memset(metadata, 0, sizeof(*metadata));
799
800 if (device->physical_device->rad_info.chip_class >= GFX9) {
801 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
802 } else {
803 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
804 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
805 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
806 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
807 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
808 metadata->u.legacy.bankw = surface->u.legacy.bankw;
809 metadata->u.legacy.bankh = surface->u.legacy.bankh;
810 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
811 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
812 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
813 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
814 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
815 }
816 radv_query_opaque_metadata(device, image, metadata);
817 }
818
819 void
820 radv_image_override_offset_stride(struct radv_device *device,
821 struct radv_image *image,
822 uint64_t offset, uint32_t stride)
823 {
824 struct radeon_surf *surface = &image->planes[0].surface;
825 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
826
827 if (device->physical_device->rad_info.chip_class >= GFX9) {
828 if (stride) {
829 surface->u.gfx9.surf_pitch = stride;
830 surface->u.gfx9.surf_slice_size =
831 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
832 }
833 surface->u.gfx9.surf_offset = offset;
834 } else {
835 surface->u.legacy.level[0].nblk_x = stride;
836 surface->u.legacy.level[0].slice_size_dw =
837 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
838
839 if (offset) {
840 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
841 surface->u.legacy.level[i].offset += offset;
842 }
843
844 }
845 }
846
847 /* The number of samples can be specified independently of the texture. */
848 static void
849 radv_image_get_fmask_info(struct radv_device *device,
850 struct radv_image *image,
851 unsigned nr_samples,
852 struct radv_fmask_info *out)
853 {
854 if (device->physical_device->rad_info.chip_class >= GFX9) {
855 out->alignment = image->planes[0].surface.fmask_alignment;
856 out->size = image->planes[0].surface.fmask_size;
857 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
858 return;
859 }
860
861 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
862 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
863 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
864 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
865 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
866 out->alignment = image->planes[0].surface.fmask_alignment;
867 out->size = image->planes[0].surface.fmask_size;
868
869 assert(!out->tile_swizzle || !image->shareable);
870 }
871
872 static void
873 radv_image_alloc_fmask(struct radv_device *device,
874 struct radv_image *image)
875 {
876 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
877
878 image->fmask.offset = align64(image->size, image->fmask.alignment);
879 image->size = image->fmask.offset + image->fmask.size;
880 image->alignment = MAX2(image->alignment, image->fmask.alignment);
881 }
882
883 static void
884 radv_image_get_cmask_info(struct radv_device *device,
885 struct radv_image *image,
886 struct radv_cmask_info *out)
887 {
888 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
889 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
890 unsigned cl_width, cl_height;
891
892 assert(image->plane_count == 1);
893
894 if (device->physical_device->rad_info.chip_class >= GFX9) {
895 out->alignment = image->planes[0].surface.cmask_alignment;
896 out->size = image->planes[0].surface.cmask_size;
897 return;
898 }
899
900 switch (num_pipes) {
901 case 2:
902 cl_width = 32;
903 cl_height = 16;
904 break;
905 case 4:
906 cl_width = 32;
907 cl_height = 32;
908 break;
909 case 8:
910 cl_width = 64;
911 cl_height = 32;
912 break;
913 case 16: /* Hawaii */
914 cl_width = 64;
915 cl_height = 64;
916 break;
917 default:
918 assert(0);
919 return;
920 }
921
922 unsigned base_align = num_pipes * pipe_interleave_bytes;
923
924 unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
925 unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
926 unsigned slice_elements = (width * height) / (8*8);
927
928 /* Each element of CMASK is a nibble. */
929 unsigned slice_bytes = slice_elements / 2;
930
931 out->slice_tile_max = (width * height) / (128*128);
932 if (out->slice_tile_max)
933 out->slice_tile_max -= 1;
934
935 out->alignment = MAX2(256, base_align);
936 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
937 align(slice_bytes, base_align);
938 }
939
940 static void
941 radv_image_alloc_cmask(struct radv_device *device,
942 struct radv_image *image)
943 {
944 uint32_t clear_value_size = 0;
945 radv_image_get_cmask_info(device, image, &image->cmask);
946
947 image->cmask.offset = align64(image->size, image->cmask.alignment);
948 /* + 8 for storing the clear values */
949 if (!image->clear_value_offset) {
950 image->clear_value_offset = image->cmask.offset + image->cmask.size;
951 clear_value_size = 8;
952 }
953 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
954 image->alignment = MAX2(image->alignment, image->cmask.alignment);
955 }
956
957 static void
958 radv_image_alloc_dcc(struct radv_image *image)
959 {
960 assert(image->plane_count == 1);
961
962 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
963 /* + 16 for storing the clear values + dcc pred */
964 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
965 image->fce_pred_offset = image->clear_value_offset + 8;
966 image->dcc_pred_offset = image->clear_value_offset + 16;
967 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
968 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
969 }
970
971 static void
972 radv_image_alloc_htile(struct radv_image *image)
973 {
974 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
975
976 /* + 8 for storing the clear values */
977 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
978 image->size = image->clear_value_offset + 8;
979 if (radv_image_is_tc_compat_htile(image)) {
980 /* Metadata for the TC-compatible HTILE hardware bug which
981 * have to be fixed by updating ZRANGE_PRECISION when doing
982 * fast depth clears to 0.0f.
983 */
984 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
985 image->size = image->clear_value_offset + 16;
986 }
987 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
988 }
989
990 static inline bool
991 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
992 {
993 if (image->info.samples <= 1 &&
994 image->info.width * image->info.height <= 512 * 512) {
995 /* Do not enable CMASK or DCC for small surfaces where the cost
996 * of the eliminate pass can be higher than the benefit of fast
997 * clear. RadeonSI does this, but the image threshold is
998 * different.
999 */
1000 return false;
1001 }
1002
1003 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1004 (image->exclusive || image->queue_family_mask == 1);
1005 }
1006
1007 static inline bool
1008 radv_image_can_enable_dcc(struct radv_image *image)
1009 {
1010 return radv_image_can_enable_dcc_or_cmask(image) &&
1011 radv_image_has_dcc(image);
1012 }
1013
1014 static inline bool
1015 radv_image_can_enable_cmask(struct radv_image *image)
1016 {
1017 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1018 /* Do not enable CMASK for non-MSAA images (fast color clear)
1019 * because 128 bit formats are not supported, but FMASK might
1020 * still be used.
1021 */
1022 return false;
1023 }
1024
1025 return radv_image_can_enable_dcc_or_cmask(image) &&
1026 image->info.levels == 1 &&
1027 image->info.depth == 1 &&
1028 !image->planes[0].surface.is_linear;
1029 }
1030
1031 static inline bool
1032 radv_image_can_enable_fmask(struct radv_image *image)
1033 {
1034 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1035 }
1036
1037 static inline bool
1038 radv_image_can_enable_htile(struct radv_image *image)
1039 {
1040 return radv_image_has_htile(image) &&
1041 image->info.levels == 1 &&
1042 image->info.width * image->info.height >= 8 * 8;
1043 }
1044
1045 static void radv_image_disable_dcc(struct radv_image *image)
1046 {
1047 for (unsigned i = 0; i < image->plane_count; ++i)
1048 image->planes[i].surface.dcc_size = 0;
1049 }
1050
1051 static void radv_image_disable_htile(struct radv_image *image)
1052 {
1053 for (unsigned i = 0; i < image->plane_count; ++i)
1054 image->planes[i].surface.htile_size = 0;
1055 }
1056
1057 VkResult
1058 radv_image_create(VkDevice _device,
1059 const struct radv_image_create_info *create_info,
1060 const VkAllocationCallbacks* alloc,
1061 VkImage *pImage)
1062 {
1063 RADV_FROM_HANDLE(radv_device, device, _device);
1064 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1065 struct radv_image *image = NULL;
1066 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1067
1068 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1069 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1070
1071 radv_assert(pCreateInfo->mipLevels > 0);
1072 radv_assert(pCreateInfo->arrayLayers > 0);
1073 radv_assert(pCreateInfo->samples > 0);
1074 radv_assert(pCreateInfo->extent.width > 0);
1075 radv_assert(pCreateInfo->extent.height > 0);
1076 radv_assert(pCreateInfo->extent.depth > 0);
1077
1078 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1079 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1080 if (!image)
1081 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1082
1083 image->type = pCreateInfo->imageType;
1084 image->info.width = pCreateInfo->extent.width;
1085 image->info.height = pCreateInfo->extent.height;
1086 image->info.depth = pCreateInfo->extent.depth;
1087 image->info.samples = pCreateInfo->samples;
1088 image->info.storage_samples = pCreateInfo->samples;
1089 image->info.array_size = pCreateInfo->arrayLayers;
1090 image->info.levels = pCreateInfo->mipLevels;
1091 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1092
1093 image->vk_format = pCreateInfo->format;
1094 image->tiling = pCreateInfo->tiling;
1095 image->usage = pCreateInfo->usage;
1096 image->flags = pCreateInfo->flags;
1097
1098 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1099 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1100 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1101 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1102 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1103 else
1104 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1105 }
1106
1107 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1108 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1109 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1110 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1111 image->info.surf_index = &device->image_mrt_offset_counter;
1112 }
1113
1114 image->plane_count = plane_count;
1115 image->size = 0;
1116 image->alignment = 1;
1117 for (unsigned plane = 0; plane < plane_count; ++plane) {
1118 struct ac_surf_info info = image->info;
1119 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1120
1121 if (plane) {
1122 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1123 assert(info.width % desc->width_divisor == 0);
1124 assert(info.height % desc->height_divisor == 0);
1125
1126 info.width /= desc->width_divisor;
1127 info.height /= desc->height_divisor;
1128 }
1129
1130 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1131
1132 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1133 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1134 image->alignment = image->planes[plane].surface.surf_alignment;
1135
1136 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1137 }
1138
1139 if (!create_info->no_metadata_planes) {
1140 /* Try to enable DCC first. */
1141 if (radv_image_can_enable_dcc(image)) {
1142 radv_image_alloc_dcc(image);
1143 if (image->info.samples > 1) {
1144 /* CMASK should be enabled because DCC fast
1145 * clear with MSAA needs it.
1146 */
1147 assert(radv_image_can_enable_cmask(image));
1148 radv_image_alloc_cmask(device, image);
1149 }
1150 } else {
1151 /* When DCC cannot be enabled, try CMASK. */
1152 radv_image_disable_dcc(image);
1153 if (radv_image_can_enable_cmask(image)) {
1154 radv_image_alloc_cmask(device, image);
1155 }
1156 }
1157
1158 /* Try to enable FMASK for multisampled images. */
1159 if (radv_image_can_enable_fmask(image)) {
1160 radv_image_alloc_fmask(device, image);
1161 } else {
1162 /* Otherwise, try to enable HTILE for depth surfaces. */
1163 if (radv_image_can_enable_htile(image) &&
1164 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1165 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1166 radv_image_alloc_htile(image);
1167 } else {
1168 radv_image_disable_htile(image);
1169 }
1170 }
1171 } else {
1172 radv_image_disable_dcc(image);
1173 radv_image_disable_htile(image);
1174 }
1175
1176 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1177 image->alignment = MAX2(image->alignment, 4096);
1178 image->size = align64(image->size, image->alignment);
1179 image->offset = 0;
1180
1181 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1182 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1183 if (!image->bo) {
1184 vk_free2(&device->alloc, alloc, image);
1185 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1186 }
1187 }
1188
1189 *pImage = radv_image_to_handle(image);
1190
1191 return VK_SUCCESS;
1192 }
1193
1194 static void
1195 radv_image_view_make_descriptor(struct radv_image_view *iview,
1196 struct radv_device *device,
1197 VkFormat vk_format,
1198 const VkComponentMapping *components,
1199 bool is_storage_image, unsigned plane_id,
1200 unsigned descriptor_plane_id)
1201 {
1202 struct radv_image *image = iview->image;
1203 struct radv_image_plane *plane = &image->planes[plane_id];
1204 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1205 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1206 uint32_t blk_w;
1207 union radv_descriptor *descriptor;
1208 uint32_t hw_level = 0;
1209
1210 if (is_storage_image) {
1211 descriptor = &iview->storage_descriptor;
1212 } else {
1213 descriptor = &iview->descriptor;
1214 }
1215
1216 assert(vk_format_get_plane_count(vk_format) == 1);
1217 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1218 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1219
1220 if (device->physical_device->rad_info.chip_class >= GFX9)
1221 hw_level = iview->base_mip;
1222 si_make_texture_descriptor(device, image, is_storage_image,
1223 iview->type,
1224 vk_format,
1225 components,
1226 hw_level, hw_level + iview->level_count - 1,
1227 iview->base_layer,
1228 iview->base_layer + iview->layer_count - 1,
1229 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1230 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1231 iview->extent.depth,
1232 descriptor->plane_descriptors[descriptor_plane_id],
1233 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1234
1235 const struct legacy_surf_level *base_level_info = NULL;
1236 if (device->physical_device->rad_info.chip_class <= GFX9) {
1237 if (is_stencil)
1238 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1239 else
1240 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1241 }
1242 si_set_mutable_tex_desc_fields(device, image,
1243 base_level_info,
1244 plane_id,
1245 iview->base_mip,
1246 iview->base_mip,
1247 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1248 }
1249
1250 static unsigned
1251 radv_plane_from_aspect(VkImageAspectFlags mask)
1252 {
1253 switch(mask) {
1254 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1255 return 1;
1256 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1257 return 2;
1258 default:
1259 return 0;
1260 }
1261 }
1262
1263 VkFormat
1264 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1265 {
1266 switch(mask) {
1267 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1268 return image->planes[0].format;
1269 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1270 return image->planes[1].format;
1271 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1272 return image->planes[2].format;
1273 case VK_IMAGE_ASPECT_STENCIL_BIT:
1274 return vk_format_stencil_only(image->vk_format);
1275 case VK_IMAGE_ASPECT_DEPTH_BIT:
1276 return vk_format_depth_only(image->vk_format);
1277 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1278 return vk_format_depth_only(image->vk_format);
1279 default:
1280 return image->vk_format;
1281 }
1282 }
1283
1284 void
1285 radv_image_view_init(struct radv_image_view *iview,
1286 struct radv_device *device,
1287 const VkImageViewCreateInfo* pCreateInfo)
1288 {
1289 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1290 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1291
1292 switch (image->type) {
1293 case VK_IMAGE_TYPE_1D:
1294 case VK_IMAGE_TYPE_2D:
1295 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1296 break;
1297 case VK_IMAGE_TYPE_3D:
1298 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1299 <= radv_minify(image->info.depth, range->baseMipLevel));
1300 break;
1301 default:
1302 unreachable("bad VkImageType");
1303 }
1304 iview->image = image;
1305 iview->bo = image->bo;
1306 iview->type = pCreateInfo->viewType;
1307 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1308 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1309 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1310 iview->vk_format = pCreateInfo->format;
1311
1312 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1313 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1314 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1315 iview->vk_format = vk_format_depth_only(iview->vk_format);
1316 }
1317
1318 if (device->physical_device->rad_info.chip_class >= GFX9) {
1319 iview->extent = (VkExtent3D) {
1320 .width = image->info.width,
1321 .height = image->info.height,
1322 .depth = image->info.depth,
1323 };
1324 } else {
1325 iview->extent = (VkExtent3D) {
1326 .width = radv_minify(image->info.width , range->baseMipLevel),
1327 .height = radv_minify(image->info.height, range->baseMipLevel),
1328 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1329 };
1330 }
1331
1332 if (iview->vk_format != image->planes[iview->plane_id].format) {
1333 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1334 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1335 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1336 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1337
1338 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1339 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1340
1341 /* Comment ported from amdvlk -
1342 * If we have the following image:
1343 * Uncompressed pixels Compressed block sizes (4x4)
1344 * mip0: 22 x 22 6 x 6
1345 * mip1: 11 x 11 3 x 3
1346 * mip2: 5 x 5 2 x 2
1347 * mip3: 2 x 2 1 x 1
1348 * mip4: 1 x 1 1 x 1
1349 *
1350 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1351 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1352 * divide-by-two integer math):
1353 * mip0: 6x6
1354 * mip1: 3x3
1355 * mip2: 1x1
1356 * mip3: 1x1
1357 *
1358 * This means that mip2 will be missing texels.
1359 *
1360 * Fix this by calculating the base mip's width and height, then convert that, and round it
1361 * back up to get the level 0 size.
1362 * Clamp the converted size between the original values, and next power of two, which
1363 * means we don't oversize the image.
1364 */
1365 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1366 vk_format_is_compressed(image->vk_format) &&
1367 !vk_format_is_compressed(iview->vk_format)) {
1368 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1369 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1370
1371 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1372 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1373
1374 lvl_width <<= range->baseMipLevel;
1375 lvl_height <<= range->baseMipLevel;
1376
1377 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1378 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1379 }
1380 }
1381
1382 iview->base_layer = range->baseArrayLayer;
1383 iview->layer_count = radv_get_layerCount(image, range);
1384 iview->base_mip = range->baseMipLevel;
1385 iview->level_count = radv_get_levelCount(image, range);
1386
1387 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1388 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1389 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1390 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1391 }
1392 }
1393
1394 bool radv_layout_has_htile(const struct radv_image *image,
1395 VkImageLayout layout,
1396 unsigned queue_mask)
1397 {
1398 if (radv_image_is_tc_compat_htile(image))
1399 return layout != VK_IMAGE_LAYOUT_GENERAL;
1400
1401 return radv_image_has_htile(image) &&
1402 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1403 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1404 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1405 }
1406
1407 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1408 VkImageLayout layout,
1409 unsigned queue_mask)
1410 {
1411 if (radv_image_is_tc_compat_htile(image))
1412 return layout != VK_IMAGE_LAYOUT_GENERAL;
1413
1414 return radv_image_has_htile(image) &&
1415 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1416 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1417 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1418 }
1419
1420 bool radv_layout_can_fast_clear(const struct radv_image *image,
1421 VkImageLayout layout,
1422 unsigned queue_mask)
1423 {
1424 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1425 }
1426
1427 bool radv_layout_dcc_compressed(const struct radv_image *image,
1428 VkImageLayout layout,
1429 unsigned queue_mask)
1430 {
1431 /* Don't compress compute transfer dst, as image stores are not supported. */
1432 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1433 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1434 return false;
1435
1436 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1437 }
1438
1439
1440 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1441 {
1442 if (!image->exclusive)
1443 return image->queue_family_mask;
1444 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1445 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1446 if (family == VK_QUEUE_FAMILY_IGNORED)
1447 return 1u << queue_family;
1448 return 1u << family;
1449 }
1450
1451 VkResult
1452 radv_CreateImage(VkDevice device,
1453 const VkImageCreateInfo *pCreateInfo,
1454 const VkAllocationCallbacks *pAllocator,
1455 VkImage *pImage)
1456 {
1457 #ifdef ANDROID
1458 const VkNativeBufferANDROID *gralloc_info =
1459 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1460
1461 if (gralloc_info)
1462 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1463 pAllocator, pImage);
1464 #endif
1465
1466 const struct wsi_image_create_info *wsi_info =
1467 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1468 bool scanout = wsi_info && wsi_info->scanout;
1469
1470 return radv_image_create(device,
1471 &(struct radv_image_create_info) {
1472 .vk_info = pCreateInfo,
1473 .scanout = scanout,
1474 },
1475 pAllocator,
1476 pImage);
1477 }
1478
1479 void
1480 radv_DestroyImage(VkDevice _device, VkImage _image,
1481 const VkAllocationCallbacks *pAllocator)
1482 {
1483 RADV_FROM_HANDLE(radv_device, device, _device);
1484 RADV_FROM_HANDLE(radv_image, image, _image);
1485
1486 if (!image)
1487 return;
1488
1489 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1490 device->ws->buffer_destroy(image->bo);
1491
1492 if (image->owned_memory != VK_NULL_HANDLE)
1493 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1494
1495 vk_free2(&device->alloc, pAllocator, image);
1496 }
1497
1498 void radv_GetImageSubresourceLayout(
1499 VkDevice _device,
1500 VkImage _image,
1501 const VkImageSubresource* pSubresource,
1502 VkSubresourceLayout* pLayout)
1503 {
1504 RADV_FROM_HANDLE(radv_image, image, _image);
1505 RADV_FROM_HANDLE(radv_device, device, _device);
1506 int level = pSubresource->mipLevel;
1507 int layer = pSubresource->arrayLayer;
1508
1509 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1510
1511 struct radv_image_plane *plane = &image->planes[plane_id];
1512 struct radeon_surf *surface = &plane->surface;
1513
1514 if (device->physical_device->rad_info.chip_class >= GFX9) {
1515 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1516 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1517 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1518 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1519 /* Adjust the number of bytes between each row because
1520 * the pitch is actually the number of components per
1521 * row.
1522 */
1523 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1524 } else {
1525 assert(util_is_power_of_two_nonzero(surface->bpe));
1526 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1527 }
1528
1529 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1530 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1531 pLayout->size = surface->u.gfx9.surf_slice_size;
1532 if (image->type == VK_IMAGE_TYPE_3D)
1533 pLayout->size *= u_minify(image->info.depth, level);
1534 } else {
1535 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1536 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1537 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1538 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1539 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1540 if (image->type == VK_IMAGE_TYPE_3D)
1541 pLayout->size *= u_minify(image->info.depth, level);
1542 }
1543 }
1544
1545
1546 VkResult
1547 radv_CreateImageView(VkDevice _device,
1548 const VkImageViewCreateInfo *pCreateInfo,
1549 const VkAllocationCallbacks *pAllocator,
1550 VkImageView *pView)
1551 {
1552 RADV_FROM_HANDLE(radv_device, device, _device);
1553 struct radv_image_view *view;
1554
1555 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1556 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1557 if (view == NULL)
1558 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1559
1560 radv_image_view_init(view, device, pCreateInfo);
1561
1562 *pView = radv_image_view_to_handle(view);
1563
1564 return VK_SUCCESS;
1565 }
1566
1567 void
1568 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1569 const VkAllocationCallbacks *pAllocator)
1570 {
1571 RADV_FROM_HANDLE(radv_device, device, _device);
1572 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1573
1574 if (!iview)
1575 return;
1576 vk_free2(&device->alloc, pAllocator, iview);
1577 }
1578
1579 void radv_buffer_view_init(struct radv_buffer_view *view,
1580 struct radv_device *device,
1581 const VkBufferViewCreateInfo* pCreateInfo)
1582 {
1583 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1584
1585 view->bo = buffer->bo;
1586 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1587 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1588 view->vk_format = pCreateInfo->format;
1589
1590 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1591 pCreateInfo->offset, view->range, view->state);
1592 }
1593
1594 VkResult
1595 radv_CreateBufferView(VkDevice _device,
1596 const VkBufferViewCreateInfo *pCreateInfo,
1597 const VkAllocationCallbacks *pAllocator,
1598 VkBufferView *pView)
1599 {
1600 RADV_FROM_HANDLE(radv_device, device, _device);
1601 struct radv_buffer_view *view;
1602
1603 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1604 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1605 if (!view)
1606 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1607
1608 radv_buffer_view_init(view, device, pCreateInfo);
1609
1610 *pView = radv_buffer_view_to_handle(view);
1611
1612 return VK_SUCCESS;
1613 }
1614
1615 void
1616 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1617 const VkAllocationCallbacks *pAllocator)
1618 {
1619 RADV_FROM_HANDLE(radv_device, device, _device);
1620 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1621
1622 if (!view)
1623 return;
1624
1625 vk_free2(&device->alloc, pAllocator, view);
1626 }