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radv: disable HTILE for very small depth surfaces
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
76 return false;
77
78 if (pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
79 VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
80 return false;
81
82 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
83 return false;
84
85 if (pCreateInfo->mipLevels > 1)
86 return false;
87
88 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
89 * tests - disable for now */
90 if (pCreateInfo->samples >= 2 &&
91 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 return true;
104 }
105
106 static bool
107 radv_use_dcc_for_image(struct radv_device *device,
108 const struct radv_image_create_info *create_info,
109 const VkImageCreateInfo *pCreateInfo)
110 {
111 bool dcc_compatible_formats;
112 bool blendable;
113 bool shareable = vk_find_struct_const(pCreateInfo->pNext,
114 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
115
116 /* DCC (Delta Color Compression) is only available for GFX8+. */
117 if (device->physical_device->rad_info.chip_class < VI)
118 return false;
119
120 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
121 return false;
122
123 /* FIXME: DCC is broken for shareable images starting with GFX9 */
124 if (device->physical_device->rad_info.chip_class >= GFX9 &&
125 shareable)
126 return false;
127
128 /* TODO: Enable DCC for storage images. */
129 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
130 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
131 return false;
132
133 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
134 return false;
135
136 /* TODO: Enable DCC for mipmaps and array layers. */
137 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
138 return false;
139
140 if (create_info->scanout)
141 return false;
142
143 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
144 * 2x can be enabled with an option.
145 */
146 if (pCreateInfo->samples > 2 ||
147 (pCreateInfo->samples == 2 &&
148 !device->physical_device->dcc_msaa_allowed))
149 return false;
150
151 /* Determine if the formats are DCC compatible. */
152 dcc_compatible_formats =
153 radv_is_colorbuffer_format_supported(pCreateInfo->format,
154 &blendable);
155
156 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
157 const struct VkImageFormatListCreateInfoKHR *format_list =
158 (const struct VkImageFormatListCreateInfoKHR *)
159 vk_find_struct_const(pCreateInfo->pNext,
160 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
161
162 /* We have to ignore the existence of the list if viewFormatCount = 0 */
163 if (format_list && format_list->viewFormatCount) {
164 /* compatibility is transitive, so we only need to check
165 * one format with everything else. */
166 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
167 if (!radv_dcc_formats_compatible(pCreateInfo->format,
168 format_list->pViewFormats[i]))
169 dcc_compatible_formats = false;
170 }
171 } else {
172 dcc_compatible_formats = false;
173 }
174 }
175
176 if (!dcc_compatible_formats)
177 return false;
178
179 return true;
180 }
181
182 static int
183 radv_init_surface(struct radv_device *device,
184 struct radeon_surf *surface,
185 const struct radv_image_create_info *create_info)
186 {
187 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
188 unsigned array_mode = radv_choose_tiling(device, create_info);
189 const struct vk_format_description *desc =
190 vk_format_description(pCreateInfo->format);
191 bool is_depth, is_stencil;
192
193 is_depth = vk_format_has_depth(desc);
194 is_stencil = vk_format_has_stencil(desc);
195
196 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
197 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
198
199 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
200 /* align byte per element on dword */
201 if (surface->bpe == 3) {
202 surface->bpe = 4;
203 }
204 surface->flags = RADEON_SURF_SET(array_mode, MODE);
205
206 switch (pCreateInfo->imageType){
207 case VK_IMAGE_TYPE_1D:
208 if (pCreateInfo->arrayLayers > 1)
209 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
210 else
211 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
212 break;
213 case VK_IMAGE_TYPE_2D:
214 if (pCreateInfo->arrayLayers > 1)
215 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
216 else
217 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
218 break;
219 case VK_IMAGE_TYPE_3D:
220 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
221 break;
222 default:
223 unreachable("unhandled image type");
224 }
225
226 if (is_depth) {
227 surface->flags |= RADEON_SURF_ZBUFFER;
228 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
229 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
230 }
231
232 if (is_stencil)
233 surface->flags |= RADEON_SURF_SBUFFER;
234
235 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
236
237 if (!radv_use_dcc_for_image(device, create_info, pCreateInfo))
238 surface->flags |= RADEON_SURF_DISABLE_DCC;
239
240 if (create_info->scanout)
241 surface->flags |= RADEON_SURF_SCANOUT;
242 return 0;
243 }
244
245 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
246 {
247 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
248 }
249
250 static inline unsigned
251 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
252 {
253 if (stencil)
254 return image->surface.u.legacy.stencil_tiling_index[level];
255 else
256 return image->surface.u.legacy.tiling_index[level];
257 }
258
259 static unsigned radv_map_swizzle(unsigned swizzle)
260 {
261 switch (swizzle) {
262 case VK_SWIZZLE_Y:
263 return V_008F0C_SQ_SEL_Y;
264 case VK_SWIZZLE_Z:
265 return V_008F0C_SQ_SEL_Z;
266 case VK_SWIZZLE_W:
267 return V_008F0C_SQ_SEL_W;
268 case VK_SWIZZLE_0:
269 return V_008F0C_SQ_SEL_0;
270 case VK_SWIZZLE_1:
271 return V_008F0C_SQ_SEL_1;
272 default: /* VK_SWIZZLE_X */
273 return V_008F0C_SQ_SEL_X;
274 }
275 }
276
277 static void
278 radv_make_buffer_descriptor(struct radv_device *device,
279 struct radv_buffer *buffer,
280 VkFormat vk_format,
281 unsigned offset,
282 unsigned range,
283 uint32_t *state)
284 {
285 const struct vk_format_description *desc;
286 unsigned stride;
287 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
288 uint64_t va = gpu_address + buffer->offset;
289 unsigned num_format, data_format;
290 int first_non_void;
291 desc = vk_format_description(vk_format);
292 first_non_void = vk_format_get_first_non_void_channel(vk_format);
293 stride = desc->block.bits / 8;
294
295 num_format = radv_translate_buffer_numformat(desc, first_non_void);
296 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
297
298 va += offset;
299 state[0] = va;
300 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
301 S_008F04_STRIDE(stride);
302
303 if (device->physical_device->rad_info.chip_class != VI && stride) {
304 range /= stride;
305 }
306
307 state[2] = range;
308 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
309 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
310 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
311 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
312 S_008F0C_NUM_FORMAT(num_format) |
313 S_008F0C_DATA_FORMAT(data_format);
314 }
315
316 static void
317 si_set_mutable_tex_desc_fields(struct radv_device *device,
318 struct radv_image *image,
319 const struct legacy_surf_level *base_level_info,
320 unsigned base_level, unsigned first_level,
321 unsigned block_width, bool is_stencil,
322 bool is_storage_image, uint32_t *state)
323 {
324 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
325 uint64_t va = gpu_address;
326 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
327 uint64_t meta_va = 0;
328 if (chip_class >= GFX9) {
329 if (is_stencil)
330 va += image->surface.u.gfx9.stencil_offset;
331 else
332 va += image->surface.u.gfx9.surf_offset;
333 } else
334 va += base_level_info->offset;
335
336 state[0] = va >> 8;
337 if (chip_class >= GFX9 ||
338 base_level_info->mode == RADEON_SURF_MODE_2D)
339 state[0] |= image->surface.tile_swizzle;
340 state[1] &= C_008F14_BASE_ADDRESS_HI;
341 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
342
343 if (chip_class >= VI) {
344 state[6] &= C_008F28_COMPRESSION_EN;
345 state[7] = 0;
346 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
347 meta_va = gpu_address + image->dcc_offset;
348 if (chip_class <= VI)
349 meta_va += base_level_info->dcc_offset;
350 } else if (!is_storage_image &&
351 radv_image_is_tc_compat_htile(image)) {
352 meta_va = gpu_address + image->htile_offset;
353 }
354
355 if (meta_va) {
356 state[6] |= S_008F28_COMPRESSION_EN(1);
357 state[7] = meta_va >> 8;
358 state[7] |= image->surface.tile_swizzle;
359 }
360 }
361
362 if (chip_class >= GFX9) {
363 state[3] &= C_008F1C_SW_MODE;
364 state[4] &= C_008F20_PITCH_GFX9;
365
366 if (is_stencil) {
367 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
368 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
369 } else {
370 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
371 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
372 }
373
374 state[5] &= C_008F24_META_DATA_ADDRESS &
375 C_008F24_META_PIPE_ALIGNED &
376 C_008F24_META_RB_ALIGNED;
377 if (meta_va) {
378 struct gfx9_surf_meta_flags meta;
379
380 if (image->dcc_offset)
381 meta = image->surface.u.gfx9.dcc;
382 else
383 meta = image->surface.u.gfx9.htile;
384
385 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
386 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
387 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
388 }
389 } else {
390 /* SI-CI-VI */
391 unsigned pitch = base_level_info->nblk_x * block_width;
392 unsigned index = si_tile_mode_index(image, base_level, is_stencil);
393
394 state[3] &= C_008F1C_TILING_INDEX;
395 state[3] |= S_008F1C_TILING_INDEX(index);
396 state[4] &= C_008F20_PITCH_GFX6;
397 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
398 }
399 }
400
401 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
402 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
403 {
404 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
405 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
406
407 /* GFX9 allocates 1D textures as 2D. */
408 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
409 image_type = VK_IMAGE_TYPE_2D;
410 switch (image_type) {
411 case VK_IMAGE_TYPE_1D:
412 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
413 case VK_IMAGE_TYPE_2D:
414 if (nr_samples > 1)
415 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
416 else
417 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
418 case VK_IMAGE_TYPE_3D:
419 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
420 return V_008F1C_SQ_RSRC_IMG_3D;
421 else
422 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
423 default:
424 unreachable("illegal image type");
425 }
426 }
427
428 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
429 {
430 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
431
432 if (swizzle[3] == VK_SWIZZLE_X) {
433 /* For the pre-defined border color values (white, opaque
434 * black, transparent black), the only thing that matters is
435 * that the alpha channel winds up in the correct place
436 * (because the RGB channels are all the same) so either of
437 * these enumerations will work.
438 */
439 if (swizzle[2] == VK_SWIZZLE_Y)
440 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
441 else
442 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
443 } else if (swizzle[0] == VK_SWIZZLE_X) {
444 if (swizzle[1] == VK_SWIZZLE_Y)
445 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
446 else
447 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
448 } else if (swizzle[1] == VK_SWIZZLE_X) {
449 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
450 } else if (swizzle[2] == VK_SWIZZLE_X) {
451 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
452 }
453
454 return bc_swizzle;
455 }
456
457 /**
458 * Build the sampler view descriptor for a texture.
459 */
460 static void
461 si_make_texture_descriptor(struct radv_device *device,
462 struct radv_image *image,
463 bool is_storage_image,
464 VkImageViewType view_type,
465 VkFormat vk_format,
466 const VkComponentMapping *mapping,
467 unsigned first_level, unsigned last_level,
468 unsigned first_layer, unsigned last_layer,
469 unsigned width, unsigned height, unsigned depth,
470 uint32_t *state,
471 uint32_t *fmask_state)
472 {
473 const struct vk_format_description *desc;
474 enum vk_swizzle swizzle[4];
475 int first_non_void;
476 unsigned num_format, data_format, type;
477
478 desc = vk_format_description(vk_format);
479
480 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
481 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
482 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
483 } else {
484 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
485 }
486
487 first_non_void = vk_format_get_first_non_void_channel(vk_format);
488
489 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
490 if (num_format == ~0) {
491 num_format = 0;
492 }
493
494 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
495 if (data_format == ~0) {
496 data_format = 0;
497 }
498
499 /* S8 with either Z16 or Z32 HTILE need a special format. */
500 if (device->physical_device->rad_info.chip_class >= GFX9 &&
501 vk_format == VK_FORMAT_S8_UINT &&
502 radv_image_is_tc_compat_htile(image)) {
503 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
504 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
505 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
506 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
507 }
508 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
509 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
510 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
511 height = 1;
512 depth = image->info.array_size;
513 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
514 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
515 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
516 depth = image->info.array_size;
517 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
518 depth = image->info.array_size / 6;
519
520 state[0] = 0;
521 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
522 S_008F14_NUM_FORMAT_GFX6(num_format));
523 state[2] = (S_008F18_WIDTH(width - 1) |
524 S_008F18_HEIGHT(height - 1) |
525 S_008F18_PERF_MOD(4));
526 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
527 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
528 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
529 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
530 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
531 0 : first_level) |
532 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
533 util_logbase2(image->info.samples) :
534 last_level) |
535 S_008F1C_TYPE(type));
536 state[4] = 0;
537 state[5] = S_008F24_BASE_ARRAY(first_layer);
538 state[6] = 0;
539 state[7] = 0;
540
541 if (device->physical_device->rad_info.chip_class >= GFX9) {
542 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
543
544 /* Depth is the last accessible layer on Gfx9.
545 * The hw doesn't need to know the total number of layers.
546 */
547 if (type == V_008F1C_SQ_RSRC_IMG_3D)
548 state[4] |= S_008F20_DEPTH(depth - 1);
549 else
550 state[4] |= S_008F20_DEPTH(last_layer);
551
552 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
553 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
554 util_logbase2(image->info.samples) :
555 image->info.levels - 1);
556 } else {
557 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
558 state[4] |= S_008F20_DEPTH(depth - 1);
559 state[5] |= S_008F24_LAST_ARRAY(last_layer);
560 }
561 if (image->dcc_offset) {
562 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
563
564 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
565 } else {
566 /* The last dword is unused by hw. The shader uses it to clear
567 * bits in the first dword of sampler state.
568 */
569 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
570 if (first_level == last_level)
571 state[7] = C_008F30_MAX_ANISO_RATIO;
572 else
573 state[7] = 0xffffffff;
574 }
575 }
576
577 /* Initialize the sampler view for FMASK. */
578 if (radv_image_has_fmask(image)) {
579 uint32_t fmask_format, num_format;
580 uint64_t gpu_address = radv_buffer_get_va(image->bo);
581 uint64_t va;
582
583 va = gpu_address + image->offset + image->fmask.offset;
584
585 if (device->physical_device->rad_info.chip_class >= GFX9) {
586 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
587 switch (image->info.samples) {
588 case 2:
589 num_format = V_008F14_IMG_FMASK_8_2_2;
590 break;
591 case 4:
592 num_format = V_008F14_IMG_FMASK_8_4_4;
593 break;
594 case 8:
595 num_format = V_008F14_IMG_FMASK_32_8_8;
596 break;
597 default:
598 unreachable("invalid nr_samples");
599 }
600 } else {
601 switch (image->info.samples) {
602 case 2:
603 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
604 break;
605 case 4:
606 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
607 break;
608 case 8:
609 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
610 break;
611 default:
612 assert(0);
613 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
614 }
615 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
616 }
617
618 fmask_state[0] = va >> 8;
619 fmask_state[0] |= image->fmask.tile_swizzle;
620 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
621 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
622 S_008F14_NUM_FORMAT_GFX6(num_format);
623 fmask_state[2] = S_008F18_WIDTH(width - 1) |
624 S_008F18_HEIGHT(height - 1);
625 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
626 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
627 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
628 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
629 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
630 fmask_state[4] = 0;
631 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
632 fmask_state[6] = 0;
633 fmask_state[7] = 0;
634
635 if (device->physical_device->rad_info.chip_class >= GFX9) {
636 fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
637 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
638 S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
639 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
640 S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
641 } else {
642 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
643 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
644 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
645 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
646 }
647 } else if (fmask_state)
648 memset(fmask_state, 0, 8 * 4);
649 }
650
651 static void
652 radv_query_opaque_metadata(struct radv_device *device,
653 struct radv_image *image,
654 struct radeon_bo_metadata *md)
655 {
656 static const VkComponentMapping fixedmapping;
657 uint32_t desc[8], i;
658
659 /* Metadata image format format version 1:
660 * [0] = 1 (metadata format identifier)
661 * [1] = (VENDOR_ID << 16) | PCI_ID
662 * [2:9] = image descriptor for the whole resource
663 * [2] is always 0, because the base address is cleared
664 * [9] is the DCC offset bits [39:8] from the beginning of
665 * the buffer
666 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
667 */
668 md->metadata[0] = 1; /* metadata image format version 1 */
669
670 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
671 md->metadata[1] = si_get_bo_metadata_word1(device);
672
673
674 si_make_texture_descriptor(device, image, false,
675 (VkImageViewType)image->type, image->vk_format,
676 &fixedmapping, 0, image->info.levels - 1, 0,
677 image->info.array_size,
678 image->info.width, image->info.height,
679 image->info.depth,
680 desc, NULL);
681
682 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
683 image->surface.blk_w, false, false, desc);
684
685 /* Clear the base address and set the relative DCC offset. */
686 desc[0] = 0;
687 desc[1] &= C_008F14_BASE_ADDRESS_HI;
688 desc[7] = image->dcc_offset >> 8;
689
690 /* Dwords [2:9] contain the image descriptor. */
691 memcpy(&md->metadata[2], desc, sizeof(desc));
692
693 /* Dwords [10:..] contain the mipmap level offsets. */
694 if (device->physical_device->rad_info.chip_class <= VI) {
695 for (i = 0; i <= image->info.levels - 1; i++)
696 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
697 md->size_metadata = (11 + image->info.levels - 1) * 4;
698 }
699 }
700
701 void
702 radv_init_metadata(struct radv_device *device,
703 struct radv_image *image,
704 struct radeon_bo_metadata *metadata)
705 {
706 struct radeon_surf *surface = &image->surface;
707
708 memset(metadata, 0, sizeof(*metadata));
709
710 if (device->physical_device->rad_info.chip_class >= GFX9) {
711 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
712 } else {
713 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
714 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
715 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
716 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
717 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
718 metadata->u.legacy.bankw = surface->u.legacy.bankw;
719 metadata->u.legacy.bankh = surface->u.legacy.bankh;
720 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
721 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
722 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
723 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
724 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
725 }
726 radv_query_opaque_metadata(device, image, metadata);
727 }
728
729 /* The number of samples can be specified independently of the texture. */
730 static void
731 radv_image_get_fmask_info(struct radv_device *device,
732 struct radv_image *image,
733 unsigned nr_samples,
734 struct radv_fmask_info *out)
735 {
736 if (device->physical_device->rad_info.chip_class >= GFX9) {
737 out->alignment = image->surface.fmask_alignment;
738 out->size = image->surface.fmask_size;
739 out->tile_swizzle = image->surface.fmask_tile_swizzle;
740 return;
741 }
742
743 out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
744 out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
745 out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
746 out->bank_height = image->surface.u.legacy.fmask.bankh;
747 out->tile_swizzle = image->surface.fmask_tile_swizzle;
748 out->alignment = image->surface.fmask_alignment;
749 out->size = image->surface.fmask_size;
750
751 assert(!out->tile_swizzle || !image->shareable);
752 }
753
754 static void
755 radv_image_alloc_fmask(struct radv_device *device,
756 struct radv_image *image)
757 {
758 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
759
760 image->fmask.offset = align64(image->size, image->fmask.alignment);
761 image->size = image->fmask.offset + image->fmask.size;
762 image->alignment = MAX2(image->alignment, image->fmask.alignment);
763 }
764
765 static void
766 radv_image_get_cmask_info(struct radv_device *device,
767 struct radv_image *image,
768 struct radv_cmask_info *out)
769 {
770 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
771 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
772 unsigned cl_width, cl_height;
773
774 if (device->physical_device->rad_info.chip_class >= GFX9) {
775 out->alignment = image->surface.cmask_alignment;
776 out->size = image->surface.cmask_size;
777 return;
778 }
779
780 switch (num_pipes) {
781 case 2:
782 cl_width = 32;
783 cl_height = 16;
784 break;
785 case 4:
786 cl_width = 32;
787 cl_height = 32;
788 break;
789 case 8:
790 cl_width = 64;
791 cl_height = 32;
792 break;
793 case 16: /* Hawaii */
794 cl_width = 64;
795 cl_height = 64;
796 break;
797 default:
798 assert(0);
799 return;
800 }
801
802 unsigned base_align = num_pipes * pipe_interleave_bytes;
803
804 unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
805 unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
806 unsigned slice_elements = (width * height) / (8*8);
807
808 /* Each element of CMASK is a nibble. */
809 unsigned slice_bytes = slice_elements / 2;
810
811 out->slice_tile_max = (width * height) / (128*128);
812 if (out->slice_tile_max)
813 out->slice_tile_max -= 1;
814
815 out->alignment = MAX2(256, base_align);
816 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
817 align(slice_bytes, base_align);
818 }
819
820 static void
821 radv_image_alloc_cmask(struct radv_device *device,
822 struct radv_image *image)
823 {
824 uint32_t clear_value_size = 0;
825 radv_image_get_cmask_info(device, image, &image->cmask);
826
827 image->cmask.offset = align64(image->size, image->cmask.alignment);
828 /* + 8 for storing the clear values */
829 if (!image->clear_value_offset) {
830 image->clear_value_offset = image->cmask.offset + image->cmask.size;
831 clear_value_size = 8;
832 }
833 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
834 image->alignment = MAX2(image->alignment, image->cmask.alignment);
835 }
836
837 static void
838 radv_image_alloc_dcc(struct radv_image *image)
839 {
840 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
841 /* + 16 for storing the clear values + dcc pred */
842 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
843 image->dcc_pred_offset = image->clear_value_offset + 8;
844 image->size = image->dcc_offset + image->surface.dcc_size + 16;
845 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
846 }
847
848 static void
849 radv_image_alloc_htile(struct radv_image *image)
850 {
851 image->htile_offset = align64(image->size, image->surface.htile_alignment);
852
853 /* + 8 for storing the clear values */
854 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
855 image->size = image->clear_value_offset + 8;
856 image->alignment = align64(image->alignment, image->surface.htile_alignment);
857 }
858
859 static inline bool
860 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
861 {
862 if (image->info.samples <= 1 &&
863 image->info.width * image->info.height <= 512 * 512) {
864 /* Do not enable CMASK or DCC for small surfaces where the cost
865 * of the eliminate pass can be higher than the benefit of fast
866 * clear. RadeonSI does this, but the image threshold is
867 * different.
868 */
869 return false;
870 }
871
872 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
873 (image->exclusive || image->queue_family_mask == 1);
874 }
875
876 static inline bool
877 radv_image_can_enable_dcc(struct radv_image *image)
878 {
879 return radv_image_can_enable_dcc_or_cmask(image) &&
880 radv_image_has_dcc(image);
881 }
882
883 static inline bool
884 radv_image_can_enable_cmask(struct radv_image *image)
885 {
886 if (image->surface.bpe > 8 && image->info.samples == 1) {
887 /* Do not enable CMASK for non-MSAA images (fast color clear)
888 * because 128 bit formats are not supported, but FMASK might
889 * still be used.
890 */
891 return false;
892 }
893
894 return radv_image_can_enable_dcc_or_cmask(image) &&
895 image->info.levels == 1 &&
896 image->info.depth == 1 &&
897 !image->surface.is_linear;
898 }
899
900 static inline bool
901 radv_image_can_enable_fmask(struct radv_image *image)
902 {
903 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
904 }
905
906 static inline bool
907 radv_image_can_enable_htile(struct radv_image *image)
908 {
909 return image->info.levels == 1 &&
910 vk_format_is_depth(image->vk_format) &&
911 image->info.width * image->info.height >= 8 * 8;
912 }
913
914 VkResult
915 radv_image_create(VkDevice _device,
916 const struct radv_image_create_info *create_info,
917 const VkAllocationCallbacks* alloc,
918 VkImage *pImage)
919 {
920 RADV_FROM_HANDLE(radv_device, device, _device);
921 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
922 struct radv_image *image = NULL;
923 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
924
925 radv_assert(pCreateInfo->mipLevels > 0);
926 radv_assert(pCreateInfo->arrayLayers > 0);
927 radv_assert(pCreateInfo->samples > 0);
928 radv_assert(pCreateInfo->extent.width > 0);
929 radv_assert(pCreateInfo->extent.height > 0);
930 radv_assert(pCreateInfo->extent.depth > 0);
931
932 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
933 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
934 if (!image)
935 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
936
937 image->type = pCreateInfo->imageType;
938 image->info.width = pCreateInfo->extent.width;
939 image->info.height = pCreateInfo->extent.height;
940 image->info.depth = pCreateInfo->extent.depth;
941 image->info.samples = pCreateInfo->samples;
942 image->info.storage_samples = pCreateInfo->samples;
943 image->info.array_size = pCreateInfo->arrayLayers;
944 image->info.levels = pCreateInfo->mipLevels;
945 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
946
947 image->vk_format = pCreateInfo->format;
948 image->tiling = pCreateInfo->tiling;
949 image->usage = pCreateInfo->usage;
950 image->flags = pCreateInfo->flags;
951
952 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
953 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
954 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
955 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
956 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
957 else
958 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
959 }
960
961 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
962 EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
963 if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
964 image->info.surf_index = &device->image_mrt_offset_counter;
965 }
966
967 radv_init_surface(device, &image->surface, create_info);
968
969 device->ws->surface_init(device->ws, &image->info, &image->surface);
970
971 image->size = image->surface.surf_size;
972 image->alignment = image->surface.surf_alignment;
973
974 if (!create_info->no_metadata_planes) {
975 /* Try to enable DCC first. */
976 if (radv_image_can_enable_dcc(image)) {
977 radv_image_alloc_dcc(image);
978 if (image->info.samples > 1) {
979 /* CMASK should be enabled because DCC fast
980 * clear with MSAA needs it.
981 */
982 assert(radv_image_can_enable_cmask(image));
983 radv_image_alloc_cmask(device, image);
984 }
985 } else {
986 /* When DCC cannot be enabled, try CMASK. */
987 image->surface.dcc_size = 0;
988 if (radv_image_can_enable_cmask(image)) {
989 radv_image_alloc_cmask(device, image);
990 }
991 }
992
993 /* Try to enable FMASK for multisampled images. */
994 if (radv_image_can_enable_fmask(image)) {
995 radv_image_alloc_fmask(device, image);
996 } else {
997 /* Otherwise, try to enable HTILE for depth surfaces. */
998 if (radv_image_can_enable_htile(image) &&
999 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1000 radv_image_alloc_htile(image);
1001 image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1002 } else {
1003 image->surface.htile_size = 0;
1004 }
1005 }
1006 } else {
1007 image->surface.dcc_size = 0;
1008 image->surface.htile_size = 0;
1009 }
1010
1011 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1012 image->alignment = MAX2(image->alignment, 4096);
1013 image->size = align64(image->size, image->alignment);
1014 image->offset = 0;
1015
1016 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1017 0, RADEON_FLAG_VIRTUAL);
1018 if (!image->bo) {
1019 vk_free2(&device->alloc, alloc, image);
1020 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1021 }
1022 }
1023
1024 *pImage = radv_image_to_handle(image);
1025
1026 return VK_SUCCESS;
1027 }
1028
1029 static void
1030 radv_image_view_make_descriptor(struct radv_image_view *iview,
1031 struct radv_device *device,
1032 const VkComponentMapping *components,
1033 bool is_storage_image)
1034 {
1035 struct radv_image *image = iview->image;
1036 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1037 uint32_t blk_w;
1038 uint32_t *descriptor;
1039 uint32_t hw_level = 0;
1040
1041 if (is_storage_image) {
1042 descriptor = iview->storage_descriptor;
1043 } else {
1044 descriptor = iview->descriptor;
1045 }
1046
1047 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
1048 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
1049
1050 if (device->physical_device->rad_info.chip_class >= GFX9)
1051 hw_level = iview->base_mip;
1052 si_make_texture_descriptor(device, image, is_storage_image,
1053 iview->type,
1054 iview->vk_format,
1055 components,
1056 hw_level, hw_level + iview->level_count - 1,
1057 iview->base_layer,
1058 iview->base_layer + iview->layer_count - 1,
1059 iview->extent.width,
1060 iview->extent.height,
1061 iview->extent.depth,
1062 descriptor,
1063 descriptor + 8);
1064
1065 const struct legacy_surf_level *base_level_info = NULL;
1066 if (device->physical_device->rad_info.chip_class <= GFX9) {
1067 if (is_stencil)
1068 base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
1069 else
1070 base_level_info = &image->surface.u.legacy.level[iview->base_mip];
1071 }
1072 si_set_mutable_tex_desc_fields(device, image,
1073 base_level_info,
1074 iview->base_mip,
1075 iview->base_mip,
1076 blk_w, is_stencil, is_storage_image, descriptor);
1077 }
1078
1079 void
1080 radv_image_view_init(struct radv_image_view *iview,
1081 struct radv_device *device,
1082 const VkImageViewCreateInfo* pCreateInfo)
1083 {
1084 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1085 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1086
1087 switch (image->type) {
1088 case VK_IMAGE_TYPE_1D:
1089 case VK_IMAGE_TYPE_2D:
1090 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1091 break;
1092 case VK_IMAGE_TYPE_3D:
1093 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1094 <= radv_minify(image->info.depth, range->baseMipLevel));
1095 break;
1096 default:
1097 unreachable("bad VkImageType");
1098 }
1099 iview->image = image;
1100 iview->bo = image->bo;
1101 iview->type = pCreateInfo->viewType;
1102 iview->vk_format = pCreateInfo->format;
1103 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1104
1105 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1106 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1107 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1108 iview->vk_format = vk_format_depth_only(iview->vk_format);
1109 }
1110
1111 if (device->physical_device->rad_info.chip_class >= GFX9) {
1112 iview->extent = (VkExtent3D) {
1113 .width = image->info.width,
1114 .height = image->info.height,
1115 .depth = image->info.depth,
1116 };
1117 } else {
1118 iview->extent = (VkExtent3D) {
1119 .width = radv_minify(image->info.width , range->baseMipLevel),
1120 .height = radv_minify(image->info.height, range->baseMipLevel),
1121 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1122 };
1123 }
1124
1125 if (iview->vk_format != image->vk_format) {
1126 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1127 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1128 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1129 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1130
1131 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1132 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1133
1134 /* Comment ported from amdvlk -
1135 * If we have the following image:
1136 * Uncompressed pixels Compressed block sizes (4x4)
1137 * mip0: 22 x 22 6 x 6
1138 * mip1: 11 x 11 3 x 3
1139 * mip2: 5 x 5 2 x 2
1140 * mip3: 2 x 2 1 x 1
1141 * mip4: 1 x 1 1 x 1
1142 *
1143 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1144 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1145 * divide-by-two integer math):
1146 * mip0: 6x6
1147 * mip1: 3x3
1148 * mip2: 1x1
1149 * mip3: 1x1
1150 *
1151 * This means that mip2 will be missing texels.
1152 *
1153 * Fix this by calculating the base mip's width and height, then convert that, and round it
1154 * back up to get the level 0 size.
1155 * Clamp the converted size between the original values, and next power of two, which
1156 * means we don't oversize the image.
1157 */
1158 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1159 vk_format_is_compressed(image->vk_format) &&
1160 !vk_format_is_compressed(iview->vk_format)) {
1161 unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
1162 unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
1163 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1164 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1165
1166 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1167 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1168
1169 lvl_width <<= range->baseMipLevel;
1170 lvl_height <<= range->baseMipLevel;
1171
1172 iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
1173 iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
1174 }
1175 }
1176
1177 iview->base_layer = range->baseArrayLayer;
1178 iview->layer_count = radv_get_layerCount(image, range);
1179 iview->base_mip = range->baseMipLevel;
1180 iview->level_count = radv_get_levelCount(image, range);
1181
1182 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
1183 radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
1184 }
1185
1186 bool radv_layout_has_htile(const struct radv_image *image,
1187 VkImageLayout layout,
1188 unsigned queue_mask)
1189 {
1190 if (radv_image_is_tc_compat_htile(image))
1191 return layout != VK_IMAGE_LAYOUT_GENERAL;
1192
1193 return radv_image_has_htile(image) &&
1194 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1195 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1196 queue_mask == (1u << RADV_QUEUE_GENERAL);
1197 }
1198
1199 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1200 VkImageLayout layout,
1201 unsigned queue_mask)
1202 {
1203 if (radv_image_is_tc_compat_htile(image))
1204 return layout != VK_IMAGE_LAYOUT_GENERAL;
1205
1206 return radv_image_has_htile(image) &&
1207 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1208 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
1209 queue_mask == (1u << RADV_QUEUE_GENERAL);
1210 }
1211
1212 bool radv_layout_can_fast_clear(const struct radv_image *image,
1213 VkImageLayout layout,
1214 unsigned queue_mask)
1215 {
1216 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
1217 queue_mask == (1u << RADV_QUEUE_GENERAL);
1218 }
1219
1220 bool radv_layout_dcc_compressed(const struct radv_image *image,
1221 VkImageLayout layout,
1222 unsigned queue_mask)
1223 {
1224 /* Don't compress compute transfer dst, as image stores are not supported. */
1225 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1226 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1227 return false;
1228
1229 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1230 }
1231
1232
1233 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1234 {
1235 if (!image->exclusive)
1236 return image->queue_family_mask;
1237 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
1238 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1239 if (family == VK_QUEUE_FAMILY_IGNORED)
1240 return 1u << queue_family;
1241 return 1u << family;
1242 }
1243
1244 VkResult
1245 radv_CreateImage(VkDevice device,
1246 const VkImageCreateInfo *pCreateInfo,
1247 const VkAllocationCallbacks *pAllocator,
1248 VkImage *pImage)
1249 {
1250 #ifdef ANDROID
1251 const VkNativeBufferANDROID *gralloc_info =
1252 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1253
1254 if (gralloc_info)
1255 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1256 pAllocator, pImage);
1257 #endif
1258
1259 const struct wsi_image_create_info *wsi_info =
1260 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1261 bool scanout = wsi_info && wsi_info->scanout;
1262
1263 return radv_image_create(device,
1264 &(struct radv_image_create_info) {
1265 .vk_info = pCreateInfo,
1266 .scanout = scanout,
1267 },
1268 pAllocator,
1269 pImage);
1270 }
1271
1272 void
1273 radv_DestroyImage(VkDevice _device, VkImage _image,
1274 const VkAllocationCallbacks *pAllocator)
1275 {
1276 RADV_FROM_HANDLE(radv_device, device, _device);
1277 RADV_FROM_HANDLE(radv_image, image, _image);
1278
1279 if (!image)
1280 return;
1281
1282 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1283 device->ws->buffer_destroy(image->bo);
1284
1285 if (image->owned_memory != VK_NULL_HANDLE)
1286 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1287
1288 vk_free2(&device->alloc, pAllocator, image);
1289 }
1290
1291 void radv_GetImageSubresourceLayout(
1292 VkDevice _device,
1293 VkImage _image,
1294 const VkImageSubresource* pSubresource,
1295 VkSubresourceLayout* pLayout)
1296 {
1297 RADV_FROM_HANDLE(radv_image, image, _image);
1298 RADV_FROM_HANDLE(radv_device, device, _device);
1299 int level = pSubresource->mipLevel;
1300 int layer = pSubresource->arrayLayer;
1301 struct radeon_surf *surface = &image->surface;
1302
1303 if (device->physical_device->rad_info.chip_class >= GFX9) {
1304 pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1305 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1306 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1307 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1308 pLayout->size = surface->u.gfx9.surf_slice_size;
1309 if (image->type == VK_IMAGE_TYPE_3D)
1310 pLayout->size *= u_minify(image->info.depth, level);
1311 } else {
1312 pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1313 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1314 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1315 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1316 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1317 if (image->type == VK_IMAGE_TYPE_3D)
1318 pLayout->size *= u_minify(image->info.depth, level);
1319 }
1320 }
1321
1322
1323 VkResult
1324 radv_CreateImageView(VkDevice _device,
1325 const VkImageViewCreateInfo *pCreateInfo,
1326 const VkAllocationCallbacks *pAllocator,
1327 VkImageView *pView)
1328 {
1329 RADV_FROM_HANDLE(radv_device, device, _device);
1330 struct radv_image_view *view;
1331
1332 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1333 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1334 if (view == NULL)
1335 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1336
1337 radv_image_view_init(view, device, pCreateInfo);
1338
1339 *pView = radv_image_view_to_handle(view);
1340
1341 return VK_SUCCESS;
1342 }
1343
1344 void
1345 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1346 const VkAllocationCallbacks *pAllocator)
1347 {
1348 RADV_FROM_HANDLE(radv_device, device, _device);
1349 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1350
1351 if (!iview)
1352 return;
1353 vk_free2(&device->alloc, pAllocator, iview);
1354 }
1355
1356 void radv_buffer_view_init(struct radv_buffer_view *view,
1357 struct radv_device *device,
1358 const VkBufferViewCreateInfo* pCreateInfo)
1359 {
1360 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1361
1362 view->bo = buffer->bo;
1363 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1364 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1365 view->vk_format = pCreateInfo->format;
1366
1367 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1368 pCreateInfo->offset, view->range, view->state);
1369 }
1370
1371 VkResult
1372 radv_CreateBufferView(VkDevice _device,
1373 const VkBufferViewCreateInfo *pCreateInfo,
1374 const VkAllocationCallbacks *pAllocator,
1375 VkBufferView *pView)
1376 {
1377 RADV_FROM_HANDLE(radv_device, device, _device);
1378 struct radv_buffer_view *view;
1379
1380 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1381 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1382 if (!view)
1383 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1384
1385 radv_buffer_view_init(view, device, pCreateInfo);
1386
1387 *pView = radv_buffer_view_to_handle(view);
1388
1389 return VK_SUCCESS;
1390 }
1391
1392 void
1393 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1394 const VkAllocationCallbacks *pAllocator)
1395 {
1396 RADV_FROM_HANDLE(radv_device, device, _device);
1397 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1398
1399 if (!view)
1400 return;
1401
1402 vk_free2(&device->alloc, pAllocator, view);
1403 }