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radv: remove radeon_surf_level::nblk_z
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
31 #include "sid.h"
32 #include "util/debug.h"
33 static unsigned
34 radv_choose_tiling(struct radv_device *Device,
35 const struct radv_image_create_info *create_info)
36 {
37 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
38
39 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
40 assert(pCreateInfo->samples <= 1);
41 return RADEON_SURF_MODE_LINEAR_ALIGNED;
42 }
43
44 /* Textures with a very small height are recommended to be linear. */
45 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
46 /* Only very thin and long 2D textures should benefit from
47 * linear_aligned. */
48 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
49 return RADEON_SURF_MODE_LINEAR_ALIGNED;
50
51 /* MSAA resources must be 2D tiled. */
52 if (pCreateInfo->samples > 1)
53 return RADEON_SURF_MODE_2D;
54
55 return RADEON_SURF_MODE_2D;
56 }
57 static int
58 radv_init_surface(struct radv_device *device,
59 struct radeon_surf *surface,
60 const struct radv_image_create_info *create_info)
61 {
62 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
63 unsigned array_mode = radv_choose_tiling(device, create_info);
64 const struct vk_format_description *desc =
65 vk_format_description(pCreateInfo->format);
66 bool is_depth, is_stencil, blendable;
67
68 is_depth = vk_format_has_depth(desc);
69 is_stencil = vk_format_has_stencil(desc);
70
71 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
72 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
73
74 surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
75 /* align byte per element on dword */
76 if (surface->bpe == 3) {
77 surface->bpe = 4;
78 }
79 surface->flags = RADEON_SURF_SET(array_mode, MODE);
80
81 switch (pCreateInfo->imageType){
82 case VK_IMAGE_TYPE_1D:
83 if (pCreateInfo->arrayLayers > 1)
84 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
85 else
86 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
87 break;
88 case VK_IMAGE_TYPE_2D:
89 if (pCreateInfo->arrayLayers > 1)
90 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
91 else
92 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
93 break;
94 case VK_IMAGE_TYPE_3D:
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
96 break;
97 default:
98 unreachable("unhandled image type");
99 }
100
101 if (is_depth) {
102 surface->flags |= RADEON_SURF_ZBUFFER;
103 }
104
105 if (is_stencil)
106 surface->flags |= RADEON_SURF_SBUFFER |
107 RADEON_SURF_HAS_SBUFFER_MIPTREE;
108
109 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
110
111 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
112 VK_IMAGE_USAGE_STORAGE_BIT)) ||
113 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
114 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
115 device->physical_device->rad_info.chip_class < VI ||
116 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
117 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
118 surface->flags |= RADEON_SURF_DISABLE_DCC;
119 if (create_info->scanout)
120 surface->flags |= RADEON_SURF_SCANOUT;
121 return 0;
122 }
123 #define ATI_VENDOR_ID 0x1002
124 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
125 {
126 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
127 }
128
129 static inline unsigned
130 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
131 {
132 if (stencil)
133 return image->surface.stencil_tiling_index[level];
134 else
135 return image->surface.tiling_index[level];
136 }
137
138 static unsigned radv_map_swizzle(unsigned swizzle)
139 {
140 switch (swizzle) {
141 case VK_SWIZZLE_Y:
142 return V_008F0C_SQ_SEL_Y;
143 case VK_SWIZZLE_Z:
144 return V_008F0C_SQ_SEL_Z;
145 case VK_SWIZZLE_W:
146 return V_008F0C_SQ_SEL_W;
147 case VK_SWIZZLE_0:
148 return V_008F0C_SQ_SEL_0;
149 case VK_SWIZZLE_1:
150 return V_008F0C_SQ_SEL_1;
151 default: /* VK_SWIZZLE_X */
152 return V_008F0C_SQ_SEL_X;
153 }
154 }
155
156 static void
157 radv_make_buffer_descriptor(struct radv_device *device,
158 struct radv_buffer *buffer,
159 VkFormat vk_format,
160 unsigned offset,
161 unsigned range,
162 uint32_t *state)
163 {
164 const struct vk_format_description *desc;
165 unsigned stride;
166 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
167 uint64_t va = gpu_address + buffer->offset;
168 unsigned num_format, data_format;
169 int first_non_void;
170 desc = vk_format_description(vk_format);
171 first_non_void = vk_format_get_first_non_void_channel(vk_format);
172 stride = desc->block.bits / 8;
173
174 num_format = radv_translate_buffer_numformat(desc, first_non_void);
175 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
176
177 va += offset;
178 state[0] = va;
179 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
180 S_008F04_STRIDE(stride);
181 state[2] = range;
182 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
183 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
184 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
185 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
186 S_008F0C_NUM_FORMAT(num_format) |
187 S_008F0C_DATA_FORMAT(data_format);
188 }
189
190 static void
191 si_set_mutable_tex_desc_fields(struct radv_device *device,
192 struct radv_image *image,
193 const struct radeon_surf_level *base_level_info,
194 unsigned base_level, unsigned first_level,
195 unsigned block_width, bool is_stencil,
196 uint32_t *state)
197 {
198 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
199 uint64_t va = gpu_address + base_level_info->offset;
200 unsigned pitch = base_level_info->nblk_x * block_width;
201
202 state[1] &= C_008F14_BASE_ADDRESS_HI;
203 state[3] &= C_008F1C_TILING_INDEX;
204 state[4] &= C_008F20_PITCH_GFX6;
205 state[6] &= C_008F28_COMPRESSION_EN;
206
207 assert(!(va & 255));
208
209 state[0] = va >> 8;
210 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
211 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
212 is_stencil));
213 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
214
215 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
216 state[6] |= S_008F28_COMPRESSION_EN(1);
217 state[7] = (gpu_address +
218 image->dcc_offset +
219 base_level_info->dcc_offset) >> 8;
220 }
221 }
222
223 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
224 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
225 {
226 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
227 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
228 switch (image_type) {
229 case VK_IMAGE_TYPE_1D:
230 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
231 case VK_IMAGE_TYPE_2D:
232 if (nr_samples > 1)
233 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
234 else
235 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
236 case VK_IMAGE_TYPE_3D:
237 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
238 return V_008F1C_SQ_RSRC_IMG_3D;
239 else
240 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
241 default:
242 unreachable("illegale image type");
243 }
244 }
245 /**
246 * Build the sampler view descriptor for a texture.
247 */
248 static void
249 si_make_texture_descriptor(struct radv_device *device,
250 struct radv_image *image,
251 bool sampler,
252 VkImageViewType view_type,
253 VkFormat vk_format,
254 const VkComponentMapping *mapping,
255 unsigned first_level, unsigned last_level,
256 unsigned first_layer, unsigned last_layer,
257 unsigned width, unsigned height, unsigned depth,
258 uint32_t *state,
259 uint32_t *fmask_state)
260 {
261 const struct vk_format_description *desc;
262 enum vk_swizzle swizzle[4];
263 int first_non_void;
264 unsigned num_format, data_format, type;
265
266 desc = vk_format_description(vk_format);
267
268 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
269 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
270 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
271 } else {
272 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
273 }
274
275 first_non_void = vk_format_get_first_non_void_channel(vk_format);
276
277 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
278 if (num_format == ~0) {
279 num_format = 0;
280 }
281
282 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
283 if (data_format == ~0) {
284 data_format = 0;
285 }
286
287 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
288 (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
289 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
290 height = 1;
291 depth = image->info.array_size;
292 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
293 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
294 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
295 depth = image->info.array_size;
296 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
297 depth = image->info.array_size / 6;
298
299 state[0] = 0;
300 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
301 S_008F14_NUM_FORMAT_GFX6(num_format));
302 state[2] = (S_008F18_WIDTH(width - 1) |
303 S_008F18_HEIGHT(height - 1) |
304 S_008F18_PERF_MOD(4));
305 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
306 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
307 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
308 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
309 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
310 0 : first_level) |
311 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
312 util_logbase2(image->info.samples) :
313 last_level) |
314 S_008F1C_POW2_PAD(image->info.levels > 1) |
315 S_008F1C_TYPE(type));
316 state[4] = S_008F20_DEPTH(depth - 1);
317 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
318 S_008F24_LAST_ARRAY(last_layer));
319 state[6] = 0;
320 state[7] = 0;
321
322 if (image->dcc_offset) {
323 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
324
325 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
326 } else {
327 /* The last dword is unused by hw. The shader uses it to clear
328 * bits in the first dword of sampler state.
329 */
330 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
331 if (first_level == last_level)
332 state[7] = C_008F30_MAX_ANISO_RATIO;
333 else
334 state[7] = 0xffffffff;
335 }
336 }
337
338 /* Initialize the sampler view for FMASK. */
339 if (image->fmask.size) {
340 uint32_t fmask_format;
341 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
342 uint64_t va;
343
344 va = gpu_address + image->offset + image->fmask.offset;
345
346 switch (image->info.samples) {
347 case 2:
348 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
349 break;
350 case 4:
351 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
352 break;
353 case 8:
354 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
355 break;
356 default:
357 assert(0);
358 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
359 }
360
361 fmask_state[0] = va >> 8;
362 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
363 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
364 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_UINT);
365 fmask_state[2] = S_008F18_WIDTH(width - 1) |
366 S_008F18_HEIGHT(height - 1);
367 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
368 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
369 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
370 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
371 S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) |
372 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
373 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
374 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
375 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
376 S_008F24_LAST_ARRAY(last_layer);
377 fmask_state[6] = 0;
378 fmask_state[7] = 0;
379 }
380 }
381
382 static void
383 radv_query_opaque_metadata(struct radv_device *device,
384 struct radv_image *image,
385 struct radeon_bo_metadata *md)
386 {
387 static const VkComponentMapping fixedmapping;
388 uint32_t desc[8], i;
389
390 /* Metadata image format format version 1:
391 * [0] = 1 (metadata format identifier)
392 * [1] = (VENDOR_ID << 16) | PCI_ID
393 * [2:9] = image descriptor for the whole resource
394 * [2] is always 0, because the base address is cleared
395 * [9] is the DCC offset bits [39:8] from the beginning of
396 * the buffer
397 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
398 */
399 md->metadata[0] = 1; /* metadata image format version 1 */
400
401 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
402 md->metadata[1] = si_get_bo_metadata_word1(device);
403
404
405 si_make_texture_descriptor(device, image, true,
406 (VkImageViewType)image->type, image->vk_format,
407 &fixedmapping, 0, image->info.levels - 1, 0,
408 image->info.array_size,
409 image->info.width, image->info.height,
410 image->info.depth,
411 desc, NULL);
412
413 si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0], 0, 0,
414 image->surface.blk_w, false, desc);
415
416 /* Clear the base address and set the relative DCC offset. */
417 desc[0] = 0;
418 desc[1] &= C_008F14_BASE_ADDRESS_HI;
419 desc[7] = image->dcc_offset >> 8;
420
421 /* Dwords [2:9] contain the image descriptor. */
422 memcpy(&md->metadata[2], desc, sizeof(desc));
423
424 /* Dwords [10:..] contain the mipmap level offsets. */
425 for (i = 0; i <= image->info.levels - 1; i++)
426 md->metadata[10+i] = image->surface.level[i].offset >> 8;
427
428 md->size_metadata = (11 + image->info.levels - 1) * 4;
429 }
430
431 void
432 radv_init_metadata(struct radv_device *device,
433 struct radv_image *image,
434 struct radeon_bo_metadata *metadata)
435 {
436 struct radeon_surf *surface = &image->surface;
437
438 memset(metadata, 0, sizeof(*metadata));
439 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
440 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
441 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
442 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
443 metadata->pipe_config = surface->pipe_config;
444 metadata->bankw = surface->bankw;
445 metadata->bankh = surface->bankh;
446 metadata->tile_split = surface->tile_split;
447 metadata->mtilea = surface->mtilea;
448 metadata->num_banks = surface->num_banks;
449 metadata->stride = surface->level[0].nblk_x * surface->bpe;
450 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
451
452 radv_query_opaque_metadata(device, image, metadata);
453 }
454
455 /* The number of samples can be specified independently of the texture. */
456 static void
457 radv_image_get_fmask_info(struct radv_device *device,
458 struct radv_image *image,
459 unsigned nr_samples,
460 struct radv_fmask_info *out)
461 {
462 /* FMASK is allocated like an ordinary texture. */
463 struct radeon_surf fmask = image->surface;
464 struct radeon_surf_info info = image->info;
465 memset(out, 0, sizeof(*out));
466
467 fmask.bo_alignment = 0;
468 fmask.bo_size = 0;
469 fmask.flags |= RADEON_SURF_FMASK;
470 info.samples = 1;
471 /* Force 2D tiling if it wasn't set. This may occur when creating
472 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
473 * destination buffer must have an FMASK too. */
474 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
475 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
476
477 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
478
479 switch (nr_samples) {
480 case 2:
481 case 4:
482 fmask.bpe = 1;
483 break;
484 case 8:
485 fmask.bpe = 4;
486 break;
487 default:
488 return;
489 }
490
491 device->ws->surface_init(device->ws, &info, &fmask);
492 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
493
494 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
495 if (out->slice_tile_max)
496 out->slice_tile_max -= 1;
497
498 out->tile_mode_index = fmask.tiling_index[0];
499 out->pitch_in_pixels = fmask.level[0].nblk_x;
500 out->bank_height = fmask.bankh;
501 out->alignment = MAX2(256, fmask.bo_alignment);
502 out->size = fmask.bo_size;
503 }
504
505 static void
506 radv_image_alloc_fmask(struct radv_device *device,
507 struct radv_image *image)
508 {
509 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
510
511 image->fmask.offset = align64(image->size, image->fmask.alignment);
512 image->size = image->fmask.offset + image->fmask.size;
513 image->alignment = MAX2(image->alignment, image->fmask.alignment);
514 }
515
516 static void
517 radv_image_get_cmask_info(struct radv_device *device,
518 struct radv_image *image,
519 struct radv_cmask_info *out)
520 {
521 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
522 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
523 unsigned cl_width, cl_height;
524
525 switch (num_pipes) {
526 case 2:
527 cl_width = 32;
528 cl_height = 16;
529 break;
530 case 4:
531 cl_width = 32;
532 cl_height = 32;
533 break;
534 case 8:
535 cl_width = 64;
536 cl_height = 32;
537 break;
538 case 16: /* Hawaii */
539 cl_width = 64;
540 cl_height = 64;
541 break;
542 default:
543 assert(0);
544 return;
545 }
546
547 unsigned base_align = num_pipes * pipe_interleave_bytes;
548
549 unsigned width = align(image->info.width, cl_width*8);
550 unsigned height = align(image->info.height, cl_height*8);
551 unsigned slice_elements = (width * height) / (8*8);
552
553 /* Each element of CMASK is a nibble. */
554 unsigned slice_bytes = slice_elements / 2;
555
556 out->slice_tile_max = (width * height) / (128*128);
557 if (out->slice_tile_max)
558 out->slice_tile_max -= 1;
559
560 out->alignment = MAX2(256, base_align);
561 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
562 align(slice_bytes, base_align);
563 }
564
565 static void
566 radv_image_alloc_cmask(struct radv_device *device,
567 struct radv_image *image)
568 {
569 radv_image_get_cmask_info(device, image, &image->cmask);
570
571 image->cmask.offset = align64(image->size, image->cmask.alignment);
572 /* + 8 for storing the clear values */
573 image->clear_value_offset = image->cmask.offset + image->cmask.size;
574 image->size = image->cmask.offset + image->cmask.size + 8;
575 image->alignment = MAX2(image->alignment, image->cmask.alignment);
576 }
577
578 static void
579 radv_image_alloc_dcc(struct radv_device *device,
580 struct radv_image *image)
581 {
582 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
583 /* + 8 for storing the clear values */
584 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
585 image->size = image->dcc_offset + image->surface.dcc_size + 8;
586 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
587 }
588
589 static void
590 radv_image_alloc_htile(struct radv_device *device,
591 struct radv_image *image)
592 {
593 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
594 image->surface.htile_size = 0;
595 return;
596 }
597
598 image->htile_offset = align64(image->size, image->surface.htile_alignment);
599
600 /* + 8 for storing the clear values */
601 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
602 image->size = image->clear_value_offset + 8;
603 image->alignment = align64(image->alignment, image->surface.htile_alignment);
604 }
605
606 VkResult
607 radv_image_create(VkDevice _device,
608 const struct radv_image_create_info *create_info,
609 const VkAllocationCallbacks* alloc,
610 VkImage *pImage)
611 {
612 RADV_FROM_HANDLE(radv_device, device, _device);
613 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
614 struct radv_image *image = NULL;
615 bool can_cmask_dcc = false;
616 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
617
618 radv_assert(pCreateInfo->mipLevels > 0);
619 radv_assert(pCreateInfo->arrayLayers > 0);
620 radv_assert(pCreateInfo->samples > 0);
621 radv_assert(pCreateInfo->extent.width > 0);
622 radv_assert(pCreateInfo->extent.height > 0);
623 radv_assert(pCreateInfo->extent.depth > 0);
624
625 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
626 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
627 if (!image)
628 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
629
630 memset(image, 0, sizeof(*image));
631 image->type = pCreateInfo->imageType;
632 image->info.width = pCreateInfo->extent.width;
633 image->info.height = pCreateInfo->extent.height;
634 image->info.depth = pCreateInfo->extent.depth;
635 image->info.samples = pCreateInfo->samples;
636 image->info.array_size = pCreateInfo->arrayLayers;
637 image->info.levels = pCreateInfo->mipLevels;
638
639 image->vk_format = pCreateInfo->format;
640 image->tiling = pCreateInfo->tiling;
641 image->usage = pCreateInfo->usage;
642 image->flags = pCreateInfo->flags;
643
644 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
645 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
646 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
647 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHX)
648 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
649 else
650 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
651 }
652
653 radv_init_surface(device, &image->surface, create_info);
654
655 device->ws->surface_init(device->ws, &image->info, &image->surface);
656
657 image->size = image->surface.bo_size;
658 image->alignment = image->surface.bo_alignment;
659
660 if (image->exclusive || image->queue_family_mask == 1)
661 can_cmask_dcc = true;
662
663 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
664 image->surface.dcc_size && can_cmask_dcc)
665 radv_image_alloc_dcc(device, image);
666 else
667 image->surface.dcc_size = 0;
668
669 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
670 pCreateInfo->mipLevels == 1 &&
671 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
672 radv_image_alloc_cmask(device, image);
673 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
674 radv_image_alloc_fmask(device, image);
675 } else if (vk_format_is_depth(pCreateInfo->format)) {
676
677 radv_image_alloc_htile(device, image);
678 }
679
680 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
681 image->alignment = MAX2(image->alignment, 4096);
682 image->size = align64(image->size, image->alignment);
683 image->offset = 0;
684
685 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
686 0, RADEON_FLAG_VIRTUAL);
687 if (!image->bo) {
688 vk_free2(&device->alloc, alloc, image);
689 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
690 }
691 }
692
693 *pImage = radv_image_to_handle(image);
694
695 return VK_SUCCESS;
696 }
697
698 void
699 radv_image_view_init(struct radv_image_view *iview,
700 struct radv_device *device,
701 const VkImageViewCreateInfo* pCreateInfo,
702 struct radv_cmd_buffer *cmd_buffer,
703 VkImageUsageFlags usage_mask)
704 {
705 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
706 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
707 uint32_t blk_w;
708 bool is_stencil = false;
709 switch (image->type) {
710 case VK_IMAGE_TYPE_1D:
711 case VK_IMAGE_TYPE_2D:
712 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
713 break;
714 case VK_IMAGE_TYPE_3D:
715 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
716 <= radv_minify(image->info.depth, range->baseMipLevel));
717 break;
718 default:
719 unreachable("bad VkImageType");
720 }
721 iview->image = image;
722 iview->bo = image->bo;
723 iview->type = pCreateInfo->viewType;
724 iview->vk_format = pCreateInfo->format;
725 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
726
727 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
728 is_stencil = true;
729 iview->vk_format = vk_format_stencil_only(iview->vk_format);
730 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
731 iview->vk_format = vk_format_depth_only(iview->vk_format);
732 }
733
734 iview->extent = (VkExtent3D) {
735 .width = radv_minify(image->info.width , range->baseMipLevel),
736 .height = radv_minify(image->info.height, range->baseMipLevel),
737 .depth = radv_minify(image->info.depth , range->baseMipLevel),
738 };
739
740 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
741 vk_format_get_blockwidth(image->vk_format));
742 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
743 vk_format_get_blockheight(image->vk_format));
744
745 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
746 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
747 iview->base_layer = range->baseArrayLayer;
748 iview->layer_count = radv_get_layerCount(image, range);
749 iview->base_mip = range->baseMipLevel;
750
751 si_make_texture_descriptor(device, image, false,
752 iview->type,
753 iview->vk_format,
754 &pCreateInfo->components,
755 0, radv_get_levelCount(image, range) - 1,
756 range->baseArrayLayer,
757 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
758 iview->extent.width,
759 iview->extent.height,
760 iview->extent.depth,
761 iview->descriptor,
762 iview->fmask_descriptor);
763 si_set_mutable_tex_desc_fields(device, image,
764 is_stencil ? &image->surface.stencil_level[range->baseMipLevel] : &image->surface.level[range->baseMipLevel], range->baseMipLevel,
765 range->baseMipLevel,
766 blk_w, is_stencil, iview->descriptor);
767 }
768
769 bool radv_layout_has_htile(const struct radv_image *image,
770 VkImageLayout layout,
771 unsigned queue_mask)
772 {
773 return image->surface.htile_size &&
774 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
775 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
776 queue_mask == (1u << RADV_QUEUE_GENERAL);
777 }
778
779 bool radv_layout_is_htile_compressed(const struct radv_image *image,
780 VkImageLayout layout,
781 unsigned queue_mask)
782 {
783 return image->surface.htile_size &&
784 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
785 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
786 queue_mask == (1u << RADV_QUEUE_GENERAL);
787 }
788
789 bool radv_layout_can_fast_clear(const struct radv_image *image,
790 VkImageLayout layout,
791 unsigned queue_mask)
792 {
793 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
794 queue_mask == (1u << RADV_QUEUE_GENERAL);
795 }
796
797
798 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
799 {
800 if (!image->exclusive)
801 return image->queue_family_mask;
802 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHX)
803 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
804 if (family == VK_QUEUE_FAMILY_IGNORED)
805 return 1u << queue_family;
806 return 1u << family;
807 }
808
809 VkResult
810 radv_CreateImage(VkDevice device,
811 const VkImageCreateInfo *pCreateInfo,
812 const VkAllocationCallbacks *pAllocator,
813 VkImage *pImage)
814 {
815 return radv_image_create(device,
816 &(struct radv_image_create_info) {
817 .vk_info = pCreateInfo,
818 .scanout = false,
819 },
820 pAllocator,
821 pImage);
822 }
823
824 void
825 radv_DestroyImage(VkDevice _device, VkImage _image,
826 const VkAllocationCallbacks *pAllocator)
827 {
828 RADV_FROM_HANDLE(radv_device, device, _device);
829 RADV_FROM_HANDLE(radv_image, image, _image);
830
831 if (!image)
832 return;
833
834 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
835 device->ws->buffer_destroy(image->bo);
836
837 vk_free2(&device->alloc, pAllocator, image);
838 }
839
840 void radv_GetImageSubresourceLayout(
841 VkDevice device,
842 VkImage _image,
843 const VkImageSubresource* pSubresource,
844 VkSubresourceLayout* pLayout)
845 {
846 RADV_FROM_HANDLE(radv_image, image, _image);
847 int level = pSubresource->mipLevel;
848 int layer = pSubresource->arrayLayer;
849 struct radeon_surf *surface = &image->surface;
850
851 pLayout->offset = surface->level[level].offset + surface->level[level].slice_size * layer;
852 pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
853 pLayout->arrayPitch = surface->level[level].slice_size;
854 pLayout->depthPitch = surface->level[level].slice_size;
855 pLayout->size = surface->level[level].slice_size;
856 if (image->type == VK_IMAGE_TYPE_3D)
857 pLayout->size *= u_minify(image->info.depth, level);
858 }
859
860
861 VkResult
862 radv_CreateImageView(VkDevice _device,
863 const VkImageViewCreateInfo *pCreateInfo,
864 const VkAllocationCallbacks *pAllocator,
865 VkImageView *pView)
866 {
867 RADV_FROM_HANDLE(radv_device, device, _device);
868 struct radv_image_view *view;
869
870 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
871 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
872 if (view == NULL)
873 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
874
875 radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
876
877 *pView = radv_image_view_to_handle(view);
878
879 return VK_SUCCESS;
880 }
881
882 void
883 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
884 const VkAllocationCallbacks *pAllocator)
885 {
886 RADV_FROM_HANDLE(radv_device, device, _device);
887 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
888
889 if (!iview)
890 return;
891 vk_free2(&device->alloc, pAllocator, iview);
892 }
893
894 void radv_buffer_view_init(struct radv_buffer_view *view,
895 struct radv_device *device,
896 const VkBufferViewCreateInfo* pCreateInfo,
897 struct radv_cmd_buffer *cmd_buffer)
898 {
899 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
900
901 view->bo = buffer->bo;
902 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
903 buffer->size - pCreateInfo->offset : pCreateInfo->range;
904 view->vk_format = pCreateInfo->format;
905
906 radv_make_buffer_descriptor(device, buffer, view->vk_format,
907 pCreateInfo->offset, view->range, view->state);
908 }
909
910 VkResult
911 radv_CreateBufferView(VkDevice _device,
912 const VkBufferViewCreateInfo *pCreateInfo,
913 const VkAllocationCallbacks *pAllocator,
914 VkBufferView *pView)
915 {
916 RADV_FROM_HANDLE(radv_device, device, _device);
917 struct radv_buffer_view *view;
918
919 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
920 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
921 if (!view)
922 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
923
924 radv_buffer_view_init(view, device, pCreateInfo, NULL);
925
926 *pView = radv_buffer_view_to_handle(view);
927
928 return VK_SUCCESS;
929 }
930
931 void
932 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
933 const VkAllocationCallbacks *pAllocator)
934 {
935 RADV_FROM_HANDLE(radv_device, device, _device);
936 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
937
938 if (!view)
939 return;
940
941 vk_free2(&device->alloc, pAllocator, view);
942 }