2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "radv_meta.h"
34 radv_meta_save_novertex(struct radv_meta_saved_state
*state
,
35 const struct radv_cmd_buffer
*cmd_buffer
,
36 uint32_t dynamic_mask
)
38 state
->old_pipeline
= cmd_buffer
->state
.pipeline
;
39 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
41 state
->dynamic_mask
= dynamic_mask
;
42 radv_dynamic_state_copy(&state
->dynamic
, &cmd_buffer
->state
.dynamic
,
45 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
46 state
->vertex_saved
= false;
50 radv_meta_restore(const struct radv_meta_saved_state
*state
,
51 struct radv_cmd_buffer
*cmd_buffer
)
53 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
), VK_PIPELINE_BIND_POINT_GRAPHICS
,
54 radv_pipeline_to_handle(state
->old_pipeline
));
55 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
56 if (state
->vertex_saved
) {
57 memcpy(cmd_buffer
->state
.vertex_bindings
, state
->old_vertex_bindings
,
58 sizeof(state
->old_vertex_bindings
));
59 cmd_buffer
->state
.vb_dirty
|= (1 << RADV_META_VERTEX_BINDING_COUNT
) - 1;
62 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
64 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
, &state
->dynamic
,
66 cmd_buffer
->state
.dirty
|= state
->dynamic_mask
;
68 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
69 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_ALL_GRAPHICS
| VK_SHADER_STAGE_COMPUTE_BIT
;
73 radv_meta_save_pass(struct radv_meta_saved_pass_state
*state
,
74 const struct radv_cmd_buffer
*cmd_buffer
)
76 state
->pass
= cmd_buffer
->state
.pass
;
77 state
->subpass
= cmd_buffer
->state
.subpass
;
78 state
->framebuffer
= cmd_buffer
->state
.framebuffer
;
79 state
->attachments
= cmd_buffer
->state
.attachments
;
80 state
->render_area
= cmd_buffer
->state
.render_area
;
84 radv_meta_restore_pass(const struct radv_meta_saved_pass_state
*state
,
85 struct radv_cmd_buffer
*cmd_buffer
)
87 cmd_buffer
->state
.pass
= state
->pass
;
88 cmd_buffer
->state
.subpass
= state
->subpass
;
89 cmd_buffer
->state
.framebuffer
= state
->framebuffer
;
90 cmd_buffer
->state
.attachments
= state
->attachments
;
91 cmd_buffer
->state
.render_area
= state
->render_area
;
93 radv_emit_framebuffer_state(cmd_buffer
);
97 radv_meta_save_compute(struct radv_meta_saved_compute_state
*state
,
98 const struct radv_cmd_buffer
*cmd_buffer
,
99 unsigned push_constant_size
)
101 state
->old_pipeline
= cmd_buffer
->state
.compute_pipeline
;
102 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
104 if (push_constant_size
)
105 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, push_constant_size
);
109 radv_meta_restore_compute(const struct radv_meta_saved_compute_state
*state
,
110 struct radv_cmd_buffer
*cmd_buffer
,
111 unsigned push_constant_size
)
113 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
), VK_PIPELINE_BIND_POINT_COMPUTE
,
114 radv_pipeline_to_handle(state
->old_pipeline
));
116 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
118 if (push_constant_size
) {
119 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, push_constant_size
);
120 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
125 radv_meta_get_view_type(const struct radv_image
*image
)
127 switch (image
->type
) {
128 case VK_IMAGE_TYPE_1D
: return VK_IMAGE_VIEW_TYPE_1D
;
129 case VK_IMAGE_TYPE_2D
: return VK_IMAGE_VIEW_TYPE_2D
;
130 case VK_IMAGE_TYPE_3D
: return VK_IMAGE_VIEW_TYPE_3D
;
132 unreachable("bad VkImageViewType");
137 * When creating a destination VkImageView, this function provides the needed
138 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
141 radv_meta_get_iview_layer(const struct radv_image
*dest_image
,
142 const VkImageSubresourceLayers
*dest_subresource
,
143 const VkOffset3D
*dest_offset
)
145 switch (dest_image
->type
) {
146 case VK_IMAGE_TYPE_1D
:
147 case VK_IMAGE_TYPE_2D
:
148 return dest_subresource
->baseArrayLayer
;
149 case VK_IMAGE_TYPE_3D
:
150 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
151 * but meta does it anyway. When doing so, we translate the
152 * destination's z offset into an array offset.
154 return dest_offset
->z
;
156 assert(!"bad VkImageType");
162 meta_alloc(void* _device
, size_t size
, size_t alignment
,
163 VkSystemAllocationScope allocationScope
)
165 struct radv_device
*device
= _device
;
166 return device
->alloc
.pfnAllocation(device
->alloc
.pUserData
, size
, alignment
,
167 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
171 meta_realloc(void* _device
, void *original
, size_t size
, size_t alignment
,
172 VkSystemAllocationScope allocationScope
)
174 struct radv_device
*device
= _device
;
175 return device
->alloc
.pfnReallocation(device
->alloc
.pUserData
, original
,
177 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
181 meta_free(void* _device
, void *data
)
183 struct radv_device
*device
= _device
;
184 return device
->alloc
.pfnFree(device
->alloc
.pUserData
, data
);
188 radv_builtin_cache_path(char *path
)
190 char *xdg_cache_home
= getenv("XDG_CACHE_HOME");
191 const char *suffix
= "/radv_builtin_shaders";
192 const char *suffix2
= "/.cache/radv_builtin_shaders";
193 struct passwd pwd
, *result
;
194 char path2
[PATH_MAX
+ 1]; /* PATH_MAX is not a real max,but suffices here. */
196 if (xdg_cache_home
) {
198 if (strlen(xdg_cache_home
) + strlen(suffix
) > PATH_MAX
)
201 strcpy(path
, xdg_cache_home
);
202 strcat(path
, suffix
);
206 getpwuid_r(getuid(), &pwd
, path2
, PATH_MAX
- strlen(suffix2
), &result
);
210 strcpy(path
, pwd
.pw_dir
);
211 strcat(path
, "/.cache");
214 strcat(path
, suffix
);
219 radv_load_meta_pipeline(struct radv_device
*device
)
221 char path
[PATH_MAX
+ 1];
225 if (!radv_builtin_cache_path(path
))
228 int fd
= open(path
, O_RDONLY
);
233 data
= malloc(st
.st_size
);
236 if(read(fd
, data
, st
.st_size
) == -1)
239 radv_pipeline_cache_load(&device
->meta_state
.cache
, data
, st
.st_size
);
246 radv_store_meta_pipeline(struct radv_device
*device
)
248 char path
[PATH_MAX
+ 1], path2
[PATH_MAX
+ 7];
252 if (!device
->meta_state
.cache
.modified
)
255 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
256 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
260 if (!radv_builtin_cache_path(path
))
264 strcat(path2
, "XXXXXX");
265 int fd
= mkstemp(path2
);//open(path, O_WRONLY | O_CREAT, 0600);
272 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
273 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
276 if(write(fd
, data
, size
) == -1)
287 radv_device_init_meta(struct radv_device
*device
)
291 device
->meta_state
.alloc
= (VkAllocationCallbacks
) {
293 .pfnAllocation
= meta_alloc
,
294 .pfnReallocation
= meta_realloc
,
295 .pfnFree
= meta_free
,
298 device
->meta_state
.cache
.alloc
= device
->meta_state
.alloc
;
299 radv_pipeline_cache_init(&device
->meta_state
.cache
, device
);
300 radv_load_meta_pipeline(device
);
302 result
= radv_device_init_meta_clear_state(device
);
303 if (result
!= VK_SUCCESS
)
306 result
= radv_device_init_meta_resolve_state(device
);
307 if (result
!= VK_SUCCESS
)
310 result
= radv_device_init_meta_blit_state(device
);
311 if (result
!= VK_SUCCESS
)
314 result
= radv_device_init_meta_blit2d_state(device
);
315 if (result
!= VK_SUCCESS
)
318 result
= radv_device_init_meta_bufimage_state(device
);
319 if (result
!= VK_SUCCESS
)
322 result
= radv_device_init_meta_depth_decomp_state(device
);
323 if (result
!= VK_SUCCESS
)
324 goto fail_depth_decomp
;
326 result
= radv_device_init_meta_buffer_state(device
);
327 if (result
!= VK_SUCCESS
)
330 result
= radv_device_init_meta_query_state(device
);
331 if (result
!= VK_SUCCESS
)
334 result
= radv_device_init_meta_fast_clear_flush_state(device
);
335 if (result
!= VK_SUCCESS
)
336 goto fail_fast_clear
;
338 result
= radv_device_init_meta_resolve_compute_state(device
);
339 if (result
!= VK_SUCCESS
)
340 goto fail_resolve_compute
;
342 result
= radv_device_init_meta_resolve_fragment_state(device
);
343 if (result
!= VK_SUCCESS
)
344 goto fail_resolve_fragment
;
347 fail_resolve_fragment
:
348 radv_device_finish_meta_resolve_compute_state(device
);
349 fail_resolve_compute
:
350 radv_device_finish_meta_fast_clear_flush_state(device
);
352 radv_device_finish_meta_buffer_state(device
);
354 radv_device_finish_meta_query_state(device
);
356 radv_device_finish_meta_depth_decomp_state(device
);
358 radv_device_finish_meta_bufimage_state(device
);
360 radv_device_finish_meta_blit2d_state(device
);
362 radv_device_finish_meta_blit_state(device
);
364 radv_device_finish_meta_resolve_state(device
);
366 radv_device_finish_meta_clear_state(device
);
368 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
373 radv_device_finish_meta(struct radv_device
*device
)
375 radv_device_finish_meta_clear_state(device
);
376 radv_device_finish_meta_resolve_state(device
);
377 radv_device_finish_meta_blit_state(device
);
378 radv_device_finish_meta_blit2d_state(device
);
379 radv_device_finish_meta_bufimage_state(device
);
380 radv_device_finish_meta_depth_decomp_state(device
);
381 radv_device_finish_meta_query_state(device
);
382 radv_device_finish_meta_buffer_state(device
);
383 radv_device_finish_meta_fast_clear_flush_state(device
);
384 radv_device_finish_meta_resolve_compute_state(device
);
385 radv_device_finish_meta_resolve_fragment_state(device
);
387 radv_store_meta_pipeline(device
);
388 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
392 * The most common meta operations all want to have the viewport
393 * reset and any scissors disabled. The rest of the dynamic state
394 * should have no effect.
397 radv_meta_save_graphics_reset_vport_scissor_novertex(struct radv_meta_saved_state
*saved_state
,
398 struct radv_cmd_buffer
*cmd_buffer
)
400 uint32_t dirty_state
= (1 << VK_DYNAMIC_STATE_VIEWPORT
) | (1 << VK_DYNAMIC_STATE_SCISSOR
);
401 radv_meta_save_novertex(saved_state
, cmd_buffer
, dirty_state
);
402 cmd_buffer
->state
.dynamic
.viewport
.count
= 0;
403 cmd_buffer
->state
.dynamic
.scissor
.count
= 0;
404 cmd_buffer
->state
.dirty
|= dirty_state
;
407 nir_ssa_def
*radv_meta_gen_rect_vertices_comp2(nir_builder
*vs_b
, nir_ssa_def
*comp2
)
410 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(vs_b
->shader
, nir_intrinsic_load_vertex_id_zero_base
);
411 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
412 nir_builder_instr_insert(vs_b
, &vertex_id
->instr
);
414 /* vertex 0 - -1.0, -1.0 */
415 /* vertex 1 - -1.0, 1.0 */
416 /* vertex 2 - 1.0, -1.0 */
417 /* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
418 channel 1 is vertex id != 1 ? -1.0 : 1.0 */
420 nir_ssa_def
*c0cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
421 nir_imm_int(vs_b
, 2));
422 nir_ssa_def
*c1cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
423 nir_imm_int(vs_b
, 1));
425 nir_ssa_def
*comp
[4];
426 comp
[0] = nir_bcsel(vs_b
, c0cmp
,
427 nir_imm_float(vs_b
, -1.0),
428 nir_imm_float(vs_b
, 1.0));
430 comp
[1] = nir_bcsel(vs_b
, c1cmp
,
431 nir_imm_float(vs_b
, -1.0),
432 nir_imm_float(vs_b
, 1.0));
434 comp
[3] = nir_imm_float(vs_b
, 1.0);
435 nir_ssa_def
*outvec
= nir_vec(vs_b
, comp
, 4);
440 nir_ssa_def
*radv_meta_gen_rect_vertices(nir_builder
*vs_b
)
442 return radv_meta_gen_rect_vertices_comp2(vs_b
, nir_imm_float(vs_b
, 0.0));
445 /* vertex shader that generates vertices */
447 radv_meta_build_nir_vs_generate_vertices(void)
449 const struct glsl_type
*vec4
= glsl_vec4_type();
452 nir_variable
*v_position
;
454 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
455 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_vs_gen_verts");
457 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
459 v_position
= nir_variable_create(b
.shader
, nir_var_shader_out
, vec4
,
461 v_position
->data
.location
= VARYING_SLOT_POS
;
463 nir_store_var(&b
, v_position
, outvec
, 0xf);
469 radv_meta_build_nir_fs_noop(void)
473 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
474 b
.shader
->info
.name
= ralloc_asprintf(b
.shader
,
480 void radv_meta_build_resolve_shader_core(nir_builder
*b
,
483 nir_variable
*input_img
,
485 nir_ssa_def
*img_coord
)
487 /* do a txf_ms on each sample */
489 nir_if
*outer_if
= NULL
;
491 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
492 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
493 tex
->op
= nir_texop_txf_ms
;
494 tex
->src
[0].src_type
= nir_tex_src_coord
;
495 tex
->src
[0].src
= nir_src_for_ssa(img_coord
);
496 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
497 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
498 tex
->dest_type
= nir_type_float
;
499 tex
->is_array
= false;
500 tex
->coord_components
= 2;
501 tex
->texture
= nir_deref_var_create(tex
, input_img
);
504 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
505 nir_builder_instr_insert(b
, &tex
->instr
);
507 tmp
= &tex
->dest
.ssa
;
509 if (!is_integer
&& samples
> 1) {
510 nir_tex_instr
*tex_all_same
= nir_tex_instr_create(b
->shader
, 1);
511 tex_all_same
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
512 tex_all_same
->op
= nir_texop_samples_identical
;
513 tex_all_same
->src
[0].src_type
= nir_tex_src_coord
;
514 tex_all_same
->src
[0].src
= nir_src_for_ssa(img_coord
);
515 tex_all_same
->dest_type
= nir_type_float
;
516 tex_all_same
->is_array
= false;
517 tex_all_same
->coord_components
= 2;
518 tex_all_same
->texture
= nir_deref_var_create(tex_all_same
, input_img
);
519 tex_all_same
->sampler
= NULL
;
521 nir_ssa_dest_init(&tex_all_same
->instr
, &tex_all_same
->dest
, 1, 32, "tex");
522 nir_builder_instr_insert(b
, &tex_all_same
->instr
);
524 nir_ssa_def
*all_same
= nir_ine(b
, &tex_all_same
->dest
.ssa
, nir_imm_int(b
, 0));
525 nir_if
*if_stmt
= nir_if_create(b
->shader
);
526 if_stmt
->condition
= nir_src_for_ssa(all_same
);
527 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
529 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
530 for (int i
= 1; i
< samples
; i
++) {
531 nir_tex_instr
*tex_add
= nir_tex_instr_create(b
->shader
, 2);
532 tex_add
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
533 tex_add
->op
= nir_texop_txf_ms
;
534 tex_add
->src
[0].src_type
= nir_tex_src_coord
;
535 tex_add
->src
[0].src
= nir_src_for_ssa(img_coord
);
536 tex_add
->src
[1].src_type
= nir_tex_src_ms_index
;
537 tex_add
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, i
));
538 tex_add
->dest_type
= nir_type_float
;
539 tex_add
->is_array
= false;
540 tex_add
->coord_components
= 2;
541 tex_add
->texture
= nir_deref_var_create(tex_add
, input_img
);
542 tex_add
->sampler
= NULL
;
544 nir_ssa_dest_init(&tex_add
->instr
, &tex_add
->dest
, 4, 32, "tex");
545 nir_builder_instr_insert(b
, &tex_add
->instr
);
547 tmp
= nir_fadd(b
, tmp
, &tex_add
->dest
.ssa
);
550 tmp
= nir_fdiv(b
, tmp
, nir_imm_float(b
, samples
));
551 nir_store_var(b
, color
, tmp
, 0xf);
552 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
555 nir_store_var(b
, color
, &tex
->dest
.ssa
, 0xf);
558 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);