radv: rework dynamic viewports/scissors support
[mesa.git] / src / amd / vulkan / radv_meta.c
1 /*
2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include "radv_meta.h"
27
28 #include <fcntl.h>
29 #include <limits.h>
30 #include <pwd.h>
31 #include <sys/stat.h>
32
33 void
34 radv_meta_save(struct radv_meta_saved_state *state,
35 struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
36 {
37 VkPipelineBindPoint bind_point =
38 flags & RADV_META_SAVE_GRAPHICS_PIPELINE ?
39 VK_PIPELINE_BIND_POINT_GRAPHICS :
40 VK_PIPELINE_BIND_POINT_COMPUTE;
41 struct radv_descriptor_state *descriptors_state =
42 radv_get_descriptors_state(cmd_buffer, bind_point);
43
44 assert(flags & (RADV_META_SAVE_GRAPHICS_PIPELINE |
45 RADV_META_SAVE_COMPUTE_PIPELINE));
46
47 state->flags = flags;
48
49 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
50 assert(!(state->flags & RADV_META_SAVE_COMPUTE_PIPELINE));
51
52 state->old_pipeline = cmd_buffer->state.pipeline;
53
54 /* Save all viewports. */
55 state->viewport.count = cmd_buffer->state.dynamic.viewport.count;
56 typed_memcpy(state->viewport.viewports,
57 cmd_buffer->state.dynamic.viewport.viewports,
58 MAX_VIEWPORTS);
59
60 /* Save all scissors. */
61 state->scissor.count = cmd_buffer->state.dynamic.scissor.count;
62 typed_memcpy(state->scissor.scissors,
63 cmd_buffer->state.dynamic.scissor.scissors,
64 MAX_SCISSORS);
65 }
66
67 if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
68 typed_memcpy(&state->sample_location,
69 &cmd_buffer->state.dynamic.sample_location, 1);
70 }
71
72 if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
73 assert(!(state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE));
74
75 state->old_pipeline = cmd_buffer->state.compute_pipeline;
76 }
77
78 if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
79 state->old_descriptor_set0 = descriptors_state->sets[0];
80 if (!(descriptors_state->valid & 1) || !state->old_descriptor_set0)
81 state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
82 }
83
84 if (state->flags & RADV_META_SAVE_CONSTANTS) {
85 memcpy(state->push_constants, cmd_buffer->push_constants,
86 MAX_PUSH_CONSTANTS_SIZE);
87 }
88
89 if (state->flags & RADV_META_SAVE_PASS) {
90 state->pass = cmd_buffer->state.pass;
91 state->subpass = cmd_buffer->state.subpass;
92 state->framebuffer = cmd_buffer->state.framebuffer;
93 state->attachments = cmd_buffer->state.attachments;
94 state->render_area = cmd_buffer->state.render_area;
95 }
96 }
97
98 void
99 radv_meta_restore(const struct radv_meta_saved_state *state,
100 struct radv_cmd_buffer *cmd_buffer)
101 {
102 VkPipelineBindPoint bind_point =
103 state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE ?
104 VK_PIPELINE_BIND_POINT_GRAPHICS :
105 VK_PIPELINE_BIND_POINT_COMPUTE;
106
107 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
108 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
109 VK_PIPELINE_BIND_POINT_GRAPHICS,
110 radv_pipeline_to_handle(state->old_pipeline));
111
112 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
113
114 /* Restore all viewports. */
115 cmd_buffer->state.dynamic.viewport.count = state->viewport.count;
116 typed_memcpy(cmd_buffer->state.dynamic.viewport.viewports,
117 state->viewport.viewports,
118 MAX_VIEWPORTS);
119
120 /* Restore all scissors. */
121 cmd_buffer->state.dynamic.scissor.count = state->scissor.count;
122 typed_memcpy(cmd_buffer->state.dynamic.scissor.scissors,
123 state->scissor.scissors,
124 MAX_SCISSORS);
125
126 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
127 RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
128 }
129
130 if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
131 typed_memcpy(&cmd_buffer->state.dynamic.sample_location.locations,
132 &state->sample_location.locations, 1);
133
134 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
135 }
136
137 if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
138 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
139 VK_PIPELINE_BIND_POINT_COMPUTE,
140 radv_pipeline_to_handle(state->old_pipeline));
141 }
142
143 if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
144 radv_set_descriptor_set(cmd_buffer, bind_point,
145 state->old_descriptor_set0, 0);
146 }
147
148 if (state->flags & RADV_META_SAVE_CONSTANTS) {
149 VkShaderStageFlags stages = VK_SHADER_STAGE_COMPUTE_BIT;
150
151 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE)
152 stages |= VK_SHADER_STAGE_ALL_GRAPHICS;
153
154 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
155 VK_NULL_HANDLE, stages, 0,
156 MAX_PUSH_CONSTANTS_SIZE,
157 state->push_constants);
158 }
159
160 if (state->flags & RADV_META_SAVE_PASS) {
161 cmd_buffer->state.pass = state->pass;
162 cmd_buffer->state.subpass = state->subpass;
163 cmd_buffer->state.framebuffer = state->framebuffer;
164 cmd_buffer->state.attachments = state->attachments;
165 cmd_buffer->state.render_area = state->render_area;
166 if (state->subpass)
167 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
168 }
169 }
170
171 VkImageViewType
172 radv_meta_get_view_type(const struct radv_image *image)
173 {
174 switch (image->type) {
175 case VK_IMAGE_TYPE_1D: return VK_IMAGE_VIEW_TYPE_1D;
176 case VK_IMAGE_TYPE_2D: return VK_IMAGE_VIEW_TYPE_2D;
177 case VK_IMAGE_TYPE_3D: return VK_IMAGE_VIEW_TYPE_3D;
178 default:
179 unreachable("bad VkImageViewType");
180 }
181 }
182
183 /**
184 * When creating a destination VkImageView, this function provides the needed
185 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
186 */
187 uint32_t
188 radv_meta_get_iview_layer(const struct radv_image *dest_image,
189 const VkImageSubresourceLayers *dest_subresource,
190 const VkOffset3D *dest_offset)
191 {
192 switch (dest_image->type) {
193 case VK_IMAGE_TYPE_1D:
194 case VK_IMAGE_TYPE_2D:
195 return dest_subresource->baseArrayLayer;
196 case VK_IMAGE_TYPE_3D:
197 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
198 * but meta does it anyway. When doing so, we translate the
199 * destination's z offset into an array offset.
200 */
201 return dest_offset->z;
202 default:
203 assert(!"bad VkImageType");
204 return 0;
205 }
206 }
207
208 static void *
209 meta_alloc(void* _device, size_t size, size_t alignment,
210 VkSystemAllocationScope allocationScope)
211 {
212 struct radv_device *device = _device;
213 return device->vk.alloc.pfnAllocation(device->vk.alloc.pUserData, size, alignment,
214 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
215 }
216
217 static void *
218 meta_realloc(void* _device, void *original, size_t size, size_t alignment,
219 VkSystemAllocationScope allocationScope)
220 {
221 struct radv_device *device = _device;
222 return device->vk.alloc.pfnReallocation(device->vk.alloc.pUserData, original,
223 size, alignment,
224 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
225 }
226
227 static void
228 meta_free(void* _device, void *data)
229 {
230 struct radv_device *device = _device;
231 return device->vk.alloc.pfnFree(device->vk.alloc.pUserData, data);
232 }
233
234 static bool
235 radv_builtin_cache_path(char *path)
236 {
237 char *xdg_cache_home = getenv("XDG_CACHE_HOME");
238 const char *suffix = "/radv_builtin_shaders";
239 const char *suffix2 = "/.cache/radv_builtin_shaders";
240 struct passwd pwd, *result;
241 char path2[PATH_MAX + 1]; /* PATH_MAX is not a real max,but suffices here. */
242 int ret;
243
244 if (xdg_cache_home) {
245 ret = snprintf(path, PATH_MAX + 1, "%s%s%zd",
246 xdg_cache_home, suffix, sizeof(void *) * 8);
247 return ret > 0 && ret < PATH_MAX + 1;
248 }
249
250 getpwuid_r(getuid(), &pwd, path2, PATH_MAX - strlen(suffix2), &result);
251 if (!result)
252 return false;
253
254 strcpy(path, pwd.pw_dir);
255 strcat(path, "/.cache");
256 if (mkdir(path, 0755) && errno != EEXIST)
257 return false;
258
259 ret = snprintf(path, PATH_MAX + 1, "%s%s%zd",
260 pwd.pw_dir, suffix2, sizeof(void *) * 8);
261 return ret > 0 && ret < PATH_MAX + 1;
262 }
263
264 static bool
265 radv_load_meta_pipeline(struct radv_device *device)
266 {
267 char path[PATH_MAX + 1];
268 struct stat st;
269 void *data = NULL;
270 bool ret = false;
271
272 if (!radv_builtin_cache_path(path))
273 return false;
274
275 int fd = open(path, O_RDONLY);
276 if (fd < 0)
277 return false;
278 if (fstat(fd, &st))
279 goto fail;
280 data = malloc(st.st_size);
281 if (!data)
282 goto fail;
283 if(read(fd, data, st.st_size) == -1)
284 goto fail;
285
286 ret = radv_pipeline_cache_load(&device->meta_state.cache, data, st.st_size);
287 fail:
288 free(data);
289 close(fd);
290 return ret;
291 }
292
293 static void
294 radv_store_meta_pipeline(struct radv_device *device)
295 {
296 char path[PATH_MAX + 1], path2[PATH_MAX + 7];
297 size_t size;
298 void *data = NULL;
299
300 if (!device->meta_state.cache.modified)
301 return;
302
303 if (radv_GetPipelineCacheData(radv_device_to_handle(device),
304 radv_pipeline_cache_to_handle(&device->meta_state.cache),
305 &size, NULL))
306 return;
307
308 if (!radv_builtin_cache_path(path))
309 return;
310
311 strcpy(path2, path);
312 strcat(path2, "XXXXXX");
313 int fd = mkstemp(path2);//open(path, O_WRONLY | O_CREAT, 0600);
314 if (fd < 0)
315 return;
316 data = malloc(size);
317 if (!data)
318 goto fail;
319
320 if (radv_GetPipelineCacheData(radv_device_to_handle(device),
321 radv_pipeline_cache_to_handle(&device->meta_state.cache),
322 &size, data))
323 goto fail;
324 if(write(fd, data, size) == -1)
325 goto fail;
326
327 rename(path2, path);
328 fail:
329 free(data);
330 close(fd);
331 unlink(path2);
332 }
333
334 VkResult
335 radv_device_init_meta(struct radv_device *device)
336 {
337 VkResult result;
338
339 memset(&device->meta_state, 0, sizeof(device->meta_state));
340
341 device->meta_state.alloc = (VkAllocationCallbacks) {
342 .pUserData = device,
343 .pfnAllocation = meta_alloc,
344 .pfnReallocation = meta_realloc,
345 .pfnFree = meta_free,
346 };
347
348 device->meta_state.cache.alloc = device->meta_state.alloc;
349 radv_pipeline_cache_init(&device->meta_state.cache, device);
350 bool loaded_cache = radv_load_meta_pipeline(device);
351 bool on_demand = !loaded_cache;
352
353 mtx_init(&device->meta_state.mtx, mtx_plain);
354
355 result = radv_device_init_meta_clear_state(device, on_demand);
356 if (result != VK_SUCCESS)
357 goto fail_clear;
358
359 result = radv_device_init_meta_resolve_state(device, on_demand);
360 if (result != VK_SUCCESS)
361 goto fail_resolve;
362
363 result = radv_device_init_meta_blit_state(device, on_demand);
364 if (result != VK_SUCCESS)
365 goto fail_blit;
366
367 result = radv_device_init_meta_blit2d_state(device, on_demand);
368 if (result != VK_SUCCESS)
369 goto fail_blit2d;
370
371 result = radv_device_init_meta_bufimage_state(device);
372 if (result != VK_SUCCESS)
373 goto fail_bufimage;
374
375 result = radv_device_init_meta_depth_decomp_state(device, on_demand);
376 if (result != VK_SUCCESS)
377 goto fail_depth_decomp;
378
379 result = radv_device_init_meta_buffer_state(device);
380 if (result != VK_SUCCESS)
381 goto fail_buffer;
382
383 result = radv_device_init_meta_query_state(device, on_demand);
384 if (result != VK_SUCCESS)
385 goto fail_query;
386
387 result = radv_device_init_meta_fast_clear_flush_state(device, on_demand);
388 if (result != VK_SUCCESS)
389 goto fail_fast_clear;
390
391 result = radv_device_init_meta_resolve_compute_state(device, on_demand);
392 if (result != VK_SUCCESS)
393 goto fail_resolve_compute;
394
395 result = radv_device_init_meta_resolve_fragment_state(device, on_demand);
396 if (result != VK_SUCCESS)
397 goto fail_resolve_fragment;
398
399 result = radv_device_init_meta_fmask_expand_state(device);
400 if (result != VK_SUCCESS)
401 goto fail_fmask_expand;
402
403 return VK_SUCCESS;
404
405 fail_fmask_expand:
406 radv_device_finish_meta_resolve_fragment_state(device);
407 fail_resolve_fragment:
408 radv_device_finish_meta_resolve_compute_state(device);
409 fail_resolve_compute:
410 radv_device_finish_meta_fast_clear_flush_state(device);
411 fail_fast_clear:
412 radv_device_finish_meta_query_state(device);
413 fail_query:
414 radv_device_finish_meta_buffer_state(device);
415 fail_buffer:
416 radv_device_finish_meta_depth_decomp_state(device);
417 fail_depth_decomp:
418 radv_device_finish_meta_bufimage_state(device);
419 fail_bufimage:
420 radv_device_finish_meta_blit2d_state(device);
421 fail_blit2d:
422 radv_device_finish_meta_blit_state(device);
423 fail_blit:
424 radv_device_finish_meta_resolve_state(device);
425 fail_resolve:
426 radv_device_finish_meta_clear_state(device);
427 fail_clear:
428 mtx_destroy(&device->meta_state.mtx);
429 radv_pipeline_cache_finish(&device->meta_state.cache);
430 return result;
431 }
432
433 void
434 radv_device_finish_meta(struct radv_device *device)
435 {
436 radv_device_finish_meta_clear_state(device);
437 radv_device_finish_meta_resolve_state(device);
438 radv_device_finish_meta_blit_state(device);
439 radv_device_finish_meta_blit2d_state(device);
440 radv_device_finish_meta_bufimage_state(device);
441 radv_device_finish_meta_depth_decomp_state(device);
442 radv_device_finish_meta_query_state(device);
443 radv_device_finish_meta_buffer_state(device);
444 radv_device_finish_meta_fast_clear_flush_state(device);
445 radv_device_finish_meta_resolve_compute_state(device);
446 radv_device_finish_meta_resolve_fragment_state(device);
447 radv_device_finish_meta_fmask_expand_state(device);
448
449 radv_store_meta_pipeline(device);
450 radv_pipeline_cache_finish(&device->meta_state.cache);
451 mtx_destroy(&device->meta_state.mtx);
452 }
453
454 nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2)
455 {
456
457 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(vs_b->shader, nir_intrinsic_load_vertex_id_zero_base);
458 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
459 nir_builder_instr_insert(vs_b, &vertex_id->instr);
460
461 /* vertex 0 - -1.0, -1.0 */
462 /* vertex 1 - -1.0, 1.0 */
463 /* vertex 2 - 1.0, -1.0 */
464 /* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
465 channel 1 is vertex id != 1 ? -1.0 : 1.0 */
466
467 nir_ssa_def *c0cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
468 nir_imm_int(vs_b, 2));
469 nir_ssa_def *c1cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
470 nir_imm_int(vs_b, 1));
471
472 nir_ssa_def *comp[4];
473 comp[0] = nir_bcsel(vs_b, c0cmp,
474 nir_imm_float(vs_b, -1.0),
475 nir_imm_float(vs_b, 1.0));
476
477 comp[1] = nir_bcsel(vs_b, c1cmp,
478 nir_imm_float(vs_b, -1.0),
479 nir_imm_float(vs_b, 1.0));
480 comp[2] = comp2;
481 comp[3] = nir_imm_float(vs_b, 1.0);
482 nir_ssa_def *outvec = nir_vec(vs_b, comp, 4);
483
484 return outvec;
485 }
486
487 nir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b)
488 {
489 return radv_meta_gen_rect_vertices_comp2(vs_b, nir_imm_float(vs_b, 0.0));
490 }
491
492 /* vertex shader that generates vertices */
493 nir_shader *
494 radv_meta_build_nir_vs_generate_vertices(void)
495 {
496 const struct glsl_type *vec4 = glsl_vec4_type();
497
498 nir_builder b;
499 nir_variable *v_position;
500
501 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
502 b.shader->info.name = ralloc_strdup(b.shader, "meta_vs_gen_verts");
503
504 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
505
506 v_position = nir_variable_create(b.shader, nir_var_shader_out, vec4,
507 "gl_Position");
508 v_position->data.location = VARYING_SLOT_POS;
509
510 nir_store_var(&b, v_position, outvec, 0xf);
511
512 return b.shader;
513 }
514
515 nir_shader *
516 radv_meta_build_nir_fs_noop(void)
517 {
518 nir_builder b;
519
520 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
521 b.shader->info.name = ralloc_asprintf(b.shader,
522 "meta_noop_fs");
523
524 return b.shader;
525 }
526
527 void radv_meta_build_resolve_shader_core(nir_builder *b,
528 bool is_integer,
529 int samples,
530 nir_variable *input_img,
531 nir_variable *color,
532 nir_ssa_def *img_coord)
533 {
534 /* do a txf_ms on each sample */
535 nir_ssa_def *tmp;
536 nir_if *outer_if = NULL;
537
538 nir_ssa_def *input_img_deref = &nir_build_deref_var(b, input_img)->dest.ssa;
539
540 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 3);
541 tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
542 tex->op = nir_texop_txf_ms;
543 tex->src[0].src_type = nir_tex_src_coord;
544 tex->src[0].src = nir_src_for_ssa(img_coord);
545 tex->src[1].src_type = nir_tex_src_ms_index;
546 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
547 tex->src[2].src_type = nir_tex_src_texture_deref;
548 tex->src[2].src = nir_src_for_ssa(input_img_deref);
549 tex->dest_type = nir_type_float;
550 tex->is_array = false;
551 tex->coord_components = 2;
552
553 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
554 nir_builder_instr_insert(b, &tex->instr);
555
556 tmp = &tex->dest.ssa;
557
558 if (!is_integer && samples > 1) {
559 nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 2);
560 tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
561 tex_all_same->op = nir_texop_samples_identical;
562 tex_all_same->src[0].src_type = nir_tex_src_coord;
563 tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
564 tex_all_same->src[1].src_type = nir_tex_src_texture_deref;
565 tex_all_same->src[1].src = nir_src_for_ssa(input_img_deref);
566 tex_all_same->dest_type = nir_type_float;
567 tex_all_same->is_array = false;
568 tex_all_same->coord_components = 2;
569
570 nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
571 nir_builder_instr_insert(b, &tex_all_same->instr);
572
573 nir_ssa_def *all_same = nir_ieq(b, &tex_all_same->dest.ssa, nir_imm_int(b, 0));
574 nir_if *if_stmt = nir_if_create(b->shader);
575 if_stmt->condition = nir_src_for_ssa(all_same);
576 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
577
578 b->cursor = nir_after_cf_list(&if_stmt->then_list);
579 for (int i = 1; i < samples; i++) {
580 nir_tex_instr *tex_add = nir_tex_instr_create(b->shader, 3);
581 tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
582 tex_add->op = nir_texop_txf_ms;
583 tex_add->src[0].src_type = nir_tex_src_coord;
584 tex_add->src[0].src = nir_src_for_ssa(img_coord);
585 tex_add->src[1].src_type = nir_tex_src_ms_index;
586 tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(b, i));
587 tex_add->src[2].src_type = nir_tex_src_texture_deref;
588 tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
589 tex_add->dest_type = nir_type_float;
590 tex_add->is_array = false;
591 tex_add->coord_components = 2;
592
593 nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
594 nir_builder_instr_insert(b, &tex_add->instr);
595
596 tmp = nir_fadd(b, tmp, &tex_add->dest.ssa);
597 }
598
599 tmp = nir_fdiv(b, tmp, nir_imm_float(b, samples));
600 nir_store_var(b, color, tmp, 0xf);
601 b->cursor = nir_after_cf_list(&if_stmt->else_list);
602 outer_if = if_stmt;
603 }
604 nir_store_var(b, color, &tex->dest.ssa, 0xf);
605
606 if (outer_if)
607 b->cursor = nir_after_cf_node(&outer_if->cf_node);
608 }