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amd/common: add declare_vs_input_vgprs() helper
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 tex->sampler_dim = tex_dim;
136 tex->op = nir_texop_tex;
137 tex->src[0].src_type = nir_tex_src_coord;
138 tex->src[0].src = nir_src_for_ssa(tex_pos);
139 tex->dest_type = nir_type_float; /* TODO */
140 tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 tex->coord_components = tex_pos->num_components;
142 tex->texture = nir_deref_var_create(tex, sampler);
143 tex->sampler = nir_deref_var_create(tex, sampler);
144
145 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 nir_builder_instr_insert(&b, &tex->instr);
147
148 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 vec4, "f_color");
150 color_out->data.location = FRAG_RESULT_DATA0;
151 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152
153 return b.shader;
154 }
155
156 static nir_shader *
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 char shader_name[64];
160 const struct glsl_type *vec4 = glsl_vec4_type();
161 nir_builder b;
162
163 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164
165 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
167
168 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 vec4, "v_tex_pos");
170 tex_pos_in->data.location = VARYING_SLOT_VAR0;
171
172 /* Swizzle the array index which comes in as Z coordinate into the right
173 * position.
174 */
175 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 nir_ssa_def *const tex_pos =
177 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179
180 const struct glsl_type *sampler_type =
181 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 glsl_get_base_type(vec4));
183 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 sampler_type, "s_tex");
185 sampler->data.descriptor_set = 0;
186 sampler->data.binding = 0;
187
188 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 tex->sampler_dim = tex_dim;
190 tex->op = nir_texop_tex;
191 tex->src[0].src_type = nir_tex_src_coord;
192 tex->src[0].src = nir_src_for_ssa(tex_pos);
193 tex->dest_type = nir_type_float; /* TODO */
194 tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 tex->coord_components = tex_pos->num_components;
196 tex->texture = nir_deref_var_create(tex, sampler);
197 tex->sampler = nir_deref_var_create(tex, sampler);
198
199 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 nir_builder_instr_insert(&b, &tex->instr);
201
202 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 vec4, "f_color");
204 color_out->data.location = FRAG_RESULT_DEPTH;
205 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206
207 return b.shader;
208 }
209
210 static nir_shader *
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 char shader_name[64];
214 const struct glsl_type *vec4 = glsl_vec4_type();
215 nir_builder b;
216
217 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218
219 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
221
222 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 vec4, "v_tex_pos");
224 tex_pos_in->data.location = VARYING_SLOT_VAR0;
225
226 /* Swizzle the array index which comes in as Z coordinate into the right
227 * position.
228 */
229 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 nir_ssa_def *const tex_pos =
231 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233
234 const struct glsl_type *sampler_type =
235 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 glsl_get_base_type(vec4));
237 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 sampler_type, "s_tex");
239 sampler->data.descriptor_set = 0;
240 sampler->data.binding = 0;
241
242 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 tex->sampler_dim = tex_dim;
244 tex->op = nir_texop_tex;
245 tex->src[0].src_type = nir_tex_src_coord;
246 tex->src[0].src = nir_src_for_ssa(tex_pos);
247 tex->dest_type = nir_type_float; /* TODO */
248 tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 tex->coord_components = tex_pos->num_components;
250 tex->texture = nir_deref_var_create(tex, sampler);
251 tex->sampler = nir_deref_var_create(tex, sampler);
252
253 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 nir_builder_instr_insert(&b, &tex->instr);
255
256 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 vec4, "f_color");
258 color_out->data.location = FRAG_RESULT_STENCIL;
259 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260
261 return b.shader;
262 }
263
264 static void
265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266 struct radv_image *src_image,
267 struct radv_image_view *src_iview,
268 VkImageLayout src_image_layout,
269 VkOffset3D src_offset_0,
270 VkOffset3D src_offset_1,
271 struct radv_image *dest_image,
272 struct radv_image_view *dest_iview,
273 VkImageLayout dest_image_layout,
274 VkOffset2D dest_offset_0,
275 VkOffset2D dest_offset_1,
276 VkRect2D dest_box,
277 VkFilter blit_filter)
278 {
279 struct radv_device *device = cmd_buffer->device;
280 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
281 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
282 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
283 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
284 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
285
286 assert(src_image->info.samples == dest_image->info.samples);
287
288 float vertex_push_constants[5] = {
289 (float)src_offset_0.x / (float)src_width,
290 (float)src_offset_0.y / (float)src_height,
291 (float)src_offset_1.x / (float)src_width,
292 (float)src_offset_1.y / (float)src_height,
293 (float)src_offset_0.z / (float)src_depth,
294 };
295
296 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
297 device->meta_state.blit.pipeline_layout,
298 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
299 vertex_push_constants);
300
301 VkSampler sampler;
302 radv_CreateSampler(radv_device_to_handle(device),
303 &(VkSamplerCreateInfo) {
304 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
305 .magFilter = blit_filter,
306 .minFilter = blit_filter,
307 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
309 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
310 }, &cmd_buffer->pool->alloc, &sampler);
311
312 VkFramebuffer fb;
313 radv_CreateFramebuffer(radv_device_to_handle(device),
314 &(VkFramebufferCreateInfo) {
315 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
316 .attachmentCount = 1,
317 .pAttachments = (VkImageView[]) {
318 radv_image_view_to_handle(dest_iview),
319 },
320 .width = dst_width,
321 .height = dst_height,
322 .layers = 1,
323 }, &cmd_buffer->pool->alloc, &fb);
324 VkPipeline pipeline;
325 switch (src_iview->aspect_mask) {
326 case VK_IMAGE_ASPECT_COLOR_BIT: {
327 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
328
329 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
330 &(VkRenderPassBeginInfo) {
331 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
332 .renderPass = device->meta_state.blit.render_pass[fs_key],
333 .framebuffer = fb,
334 .renderArea = {
335 .offset = { dest_box.offset.x, dest_box.offset.y },
336 .extent = { dest_box.extent.width, dest_box.extent.height },
337 },
338 .clearValueCount = 0,
339 .pClearValues = NULL,
340 }, VK_SUBPASS_CONTENTS_INLINE);
341 switch (src_image->type) {
342 case VK_IMAGE_TYPE_1D:
343 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
344 break;
345 case VK_IMAGE_TYPE_2D:
346 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
347 break;
348 case VK_IMAGE_TYPE_3D:
349 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
350 break;
351 default:
352 unreachable(!"bad VkImageType");
353 }
354 break;
355 }
356 case VK_IMAGE_ASPECT_DEPTH_BIT: {
357 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
358 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
359 &(VkRenderPassBeginInfo) {
360 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
361 .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
362 .framebuffer = fb,
363 .renderArea = {
364 .offset = { dest_box.offset.x, dest_box.offset.y },
365 .extent = { dest_box.extent.width, dest_box.extent.height },
366 },
367 .clearValueCount = 0,
368 .pClearValues = NULL,
369 }, VK_SUBPASS_CONTENTS_INLINE);
370 switch (src_image->type) {
371 case VK_IMAGE_TYPE_1D:
372 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
373 break;
374 case VK_IMAGE_TYPE_2D:
375 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
376 break;
377 case VK_IMAGE_TYPE_3D:
378 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
379 break;
380 default:
381 unreachable(!"bad VkImageType");
382 }
383 break;
384 }
385 case VK_IMAGE_ASPECT_STENCIL_BIT: {
386 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
387 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
388 &(VkRenderPassBeginInfo) {
389 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
390 .renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
391 .framebuffer = fb,
392 .renderArea = {
393 .offset = { dest_box.offset.x, dest_box.offset.y },
394 .extent = { dest_box.extent.width, dest_box.extent.height },
395 },
396 .clearValueCount = 0,
397 .pClearValues = NULL,
398 }, VK_SUBPASS_CONTENTS_INLINE);
399 switch (src_image->type) {
400 case VK_IMAGE_TYPE_1D:
401 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
402 break;
403 case VK_IMAGE_TYPE_2D:
404 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
405 break;
406 case VK_IMAGE_TYPE_3D:
407 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
408 break;
409 default:
410 unreachable(!"bad VkImageType");
411 }
412 break;
413 }
414 default:
415 unreachable(!"bad VkImageType");
416 }
417
418 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
419 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
420
421 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
422 device->meta_state.blit.pipeline_layout,
423 0, /* set */
424 1, /* descriptorWriteCount */
425 (VkWriteDescriptorSet[]) {
426 {
427 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
428 .dstBinding = 0,
429 .dstArrayElement = 0,
430 .descriptorCount = 1,
431 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
432 .pImageInfo = (VkDescriptorImageInfo[]) {
433 {
434 .sampler = sampler,
435 .imageView = radv_image_view_to_handle(src_iview),
436 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
437 },
438 }
439 }
440 });
441
442 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
443 .x = dest_offset_0.x,
444 .y = dest_offset_0.y,
445 .width = dest_offset_1.x - dest_offset_0.x,
446 .height = dest_offset_1.y - dest_offset_0.y,
447 .minDepth = 0.0f,
448 .maxDepth = 1.0f
449 });
450
451 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
452 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
453 .extent = (VkExtent2D) {
454 abs(dest_offset_1.x - dest_offset_0.x),
455 abs(dest_offset_1.y - dest_offset_0.y)
456 },
457 });
458
459 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
460
461 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
462
463 /* At the point where we emit the draw call, all data from the
464 * descriptor sets, etc. has been used. We are free to delete it.
465 */
466 /* TODO: above comment is not valid for at least descriptor sets/pools,
467 * as we may not free them till after execution finishes. Check others. */
468
469 radv_DestroySampler(radv_device_to_handle(device), sampler,
470 &cmd_buffer->pool->alloc);
471 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
472 &cmd_buffer->pool->alloc);
473 }
474
475 static bool
476 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
477 {
478 bool flip = false;
479 if (*src0 > *src1) {
480 unsigned tmp = *src0;
481 *src0 = *src1;
482 *src1 = tmp;
483 flip = !flip;
484 }
485
486 if (*dst0 > *dst1) {
487 unsigned tmp = *dst0;
488 *dst0 = *dst1;
489 *dst1 = tmp;
490 flip = !flip;
491 }
492 return flip;
493 }
494
495 void radv_CmdBlitImage(
496 VkCommandBuffer commandBuffer,
497 VkImage srcImage,
498 VkImageLayout srcImageLayout,
499 VkImage destImage,
500 VkImageLayout destImageLayout,
501 uint32_t regionCount,
502 const VkImageBlit* pRegions,
503 VkFilter filter)
504
505 {
506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
507 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
508 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
509 struct radv_meta_saved_state saved_state;
510
511 /* From the Vulkan 1.0 spec:
512 *
513 * vkCmdBlitImage must not be used for multisampled source or
514 * destination images. Use vkCmdResolveImage for this purpose.
515 */
516 assert(src_image->info.samples == 1);
517 assert(dest_image->info.samples == 1);
518
519 radv_meta_save(&saved_state, cmd_buffer,
520 RADV_META_SAVE_GRAPHICS_PIPELINE |
521 RADV_META_SAVE_CONSTANTS |
522 RADV_META_SAVE_DESCRIPTORS);
523
524 for (unsigned r = 0; r < regionCount; r++) {
525 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
526 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
527
528 unsigned dst_start, dst_end;
529 if (dest_image->type == VK_IMAGE_TYPE_3D) {
530 assert(dst_res->baseArrayLayer == 0);
531 dst_start = pRegions[r].dstOffsets[0].z;
532 dst_end = pRegions[r].dstOffsets[1].z;
533 } else {
534 dst_start = dst_res->baseArrayLayer;
535 dst_end = dst_start + dst_res->layerCount;
536 }
537
538 unsigned src_start, src_end;
539 if (src_image->type == VK_IMAGE_TYPE_3D) {
540 assert(src_res->baseArrayLayer == 0);
541 src_start = pRegions[r].srcOffsets[0].z;
542 src_end = pRegions[r].srcOffsets[1].z;
543 } else {
544 src_start = src_res->baseArrayLayer;
545 src_end = src_start + src_res->layerCount;
546 }
547
548 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
549 float src_z_step = (float)(src_end + 1 - src_start) /
550 (float)(dst_end + 1 - dst_start);
551
552 if (flip_z) {
553 src_start = src_end;
554 src_z_step *= -1;
555 }
556
557 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
558 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
559 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
560 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
561
562 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
563 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
564 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
565 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
566
567 VkRect2D dest_box;
568 dest_box.offset.x = MIN2(dst_x0, dst_x1);
569 dest_box.offset.y = MIN2(dst_y0, dst_y1);
570 dest_box.extent.width = abs(dst_x1 - dst_x0);
571 dest_box.extent.height = abs(dst_y1 - dst_y0);
572
573 const unsigned num_layers = dst_end - dst_start;
574 for (unsigned i = 0; i < num_layers; i++) {
575 struct radv_image_view dest_iview, src_iview;
576
577 const VkOffset2D dest_offset_0 = {
578 .x = dst_x0,
579 .y = dst_y0,
580 };
581 const VkOffset2D dest_offset_1 = {
582 .x = dst_x1,
583 .y = dst_y1,
584 };
585 VkOffset3D src_offset_0 = {
586 .x = src_x0,
587 .y = src_y0,
588 .z = src_start + i * src_z_step,
589 };
590 VkOffset3D src_offset_1 = {
591 .x = src_x1,
592 .y = src_y1,
593 .z = src_start + i * src_z_step,
594 };
595 const uint32_t dest_array_slice = dst_start + i;
596
597 /* 3D images have just 1 layer */
598 const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
599
600 radv_image_view_init(&dest_iview, cmd_buffer->device,
601 &(VkImageViewCreateInfo) {
602 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
603 .image = destImage,
604 .viewType = radv_meta_get_view_type(dest_image),
605 .format = dest_image->vk_format,
606 .subresourceRange = {
607 .aspectMask = dst_res->aspectMask,
608 .baseMipLevel = dst_res->mipLevel,
609 .levelCount = 1,
610 .baseArrayLayer = dest_array_slice,
611 .layerCount = 1
612 },
613 });
614 radv_image_view_init(&src_iview, cmd_buffer->device,
615 &(VkImageViewCreateInfo) {
616 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
617 .image = srcImage,
618 .viewType = radv_meta_get_view_type(src_image),
619 .format = src_image->vk_format,
620 .subresourceRange = {
621 .aspectMask = src_res->aspectMask,
622 .baseMipLevel = src_res->mipLevel,
623 .levelCount = 1,
624 .baseArrayLayer = src_array_slice,
625 .layerCount = 1
626 },
627 });
628 meta_emit_blit(cmd_buffer,
629 src_image, &src_iview, srcImageLayout,
630 src_offset_0, src_offset_1,
631 dest_image, &dest_iview, destImageLayout,
632 dest_offset_0, dest_offset_1,
633 dest_box,
634 filter);
635 }
636 }
637
638 radv_meta_restore(&saved_state, cmd_buffer);
639 }
640
641 void
642 radv_device_finish_meta_blit_state(struct radv_device *device)
643 {
644 struct radv_meta_state *state = &device->meta_state;
645
646 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
647 radv_DestroyRenderPass(radv_device_to_handle(device),
648 state->blit.render_pass[i],
649 &state->alloc);
650 radv_DestroyPipeline(radv_device_to_handle(device),
651 state->blit.pipeline_1d_src[i],
652 &state->alloc);
653 radv_DestroyPipeline(radv_device_to_handle(device),
654 state->blit.pipeline_2d_src[i],
655 &state->alloc);
656 radv_DestroyPipeline(radv_device_to_handle(device),
657 state->blit.pipeline_3d_src[i],
658 &state->alloc);
659 }
660
661 for (enum radv_blit_ds_layout i = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; i < RADV_BLIT_DS_LAYOUT_COUNT; i++) {
662 radv_DestroyRenderPass(radv_device_to_handle(device),
663 state->blit.depth_only_rp[i], &state->alloc);
664 radv_DestroyRenderPass(radv_device_to_handle(device),
665 state->blit.stencil_only_rp[i], &state->alloc);
666 }
667
668 radv_DestroyPipeline(radv_device_to_handle(device),
669 state->blit.depth_only_1d_pipeline, &state->alloc);
670 radv_DestroyPipeline(radv_device_to_handle(device),
671 state->blit.depth_only_2d_pipeline, &state->alloc);
672 radv_DestroyPipeline(radv_device_to_handle(device),
673 state->blit.depth_only_3d_pipeline, &state->alloc);
674
675 radv_DestroyPipeline(radv_device_to_handle(device),
676 state->blit.stencil_only_1d_pipeline,
677 &state->alloc);
678 radv_DestroyPipeline(radv_device_to_handle(device),
679 state->blit.stencil_only_2d_pipeline,
680 &state->alloc);
681 radv_DestroyPipeline(radv_device_to_handle(device),
682 state->blit.stencil_only_3d_pipeline,
683 &state->alloc);
684
685
686 radv_DestroyPipelineLayout(radv_device_to_handle(device),
687 state->blit.pipeline_layout, &state->alloc);
688 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
689 state->blit.ds_layout, &state->alloc);
690 }
691
692 static VkFormat pipeline_formats[] = {
693 VK_FORMAT_R8G8B8A8_UNORM,
694 VK_FORMAT_R8G8B8A8_UINT,
695 VK_FORMAT_R8G8B8A8_SINT,
696 VK_FORMAT_A2R10G10B10_UINT_PACK32,
697 VK_FORMAT_A2R10G10B10_SINT_PACK32,
698 VK_FORMAT_R16G16B16A16_UNORM,
699 VK_FORMAT_R16G16B16A16_SNORM,
700 VK_FORMAT_R16G16B16A16_UINT,
701 VK_FORMAT_R16G16B16A16_SINT,
702 VK_FORMAT_R32_SFLOAT,
703 VK_FORMAT_R32G32_SFLOAT,
704 VK_FORMAT_R32G32B32A32_SFLOAT
705 };
706
707 static VkResult
708 radv_device_init_meta_blit_color(struct radv_device *device,
709 struct radv_shader_module *vs)
710 {
711 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
712 VkResult result;
713
714 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
715 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
716 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
717
718 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
719 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
720 result = radv_CreateRenderPass(radv_device_to_handle(device),
721 &(VkRenderPassCreateInfo) {
722 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
723 .attachmentCount = 1,
724 .pAttachments = &(VkAttachmentDescription) {
725 .format = pipeline_formats[i],
726 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
727 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
728 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
729 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
730 },
731 .subpassCount = 1,
732 .pSubpasses = &(VkSubpassDescription) {
733 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
734 .inputAttachmentCount = 0,
735 .colorAttachmentCount = 1,
736 .pColorAttachments = &(VkAttachmentReference) {
737 .attachment = 0,
738 .layout = VK_IMAGE_LAYOUT_GENERAL,
739 },
740 .pResolveAttachments = NULL,
741 .pDepthStencilAttachment = &(VkAttachmentReference) {
742 .attachment = VK_ATTACHMENT_UNUSED,
743 .layout = VK_IMAGE_LAYOUT_GENERAL,
744 },
745 .preserveAttachmentCount = 1,
746 .pPreserveAttachments = (uint32_t[]) { 0 },
747 },
748 .dependencyCount = 0,
749 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
750 if (result != VK_SUCCESS)
751 goto fail;
752
753 VkPipelineVertexInputStateCreateInfo vi_create_info = {
754 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
755 .vertexBindingDescriptionCount = 0,
756 .vertexAttributeDescriptionCount = 0,
757 };
758
759 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
760 {
761 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
762 .stage = VK_SHADER_STAGE_VERTEX_BIT,
763 .module = radv_shader_module_to_handle(vs),
764 .pName = "main",
765 .pSpecializationInfo = NULL
766 }, {
767 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
768 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
769 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
770 .pName = "main",
771 .pSpecializationInfo = NULL
772 },
773 };
774
775 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
776 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
777 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
778 .pStages = pipeline_shader_stages,
779 .pVertexInputState = &vi_create_info,
780 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
781 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
782 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
783 .primitiveRestartEnable = false,
784 },
785 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
786 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
787 .viewportCount = 1,
788 .scissorCount = 1,
789 },
790 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
791 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
792 .rasterizerDiscardEnable = false,
793 .polygonMode = VK_POLYGON_MODE_FILL,
794 .cullMode = VK_CULL_MODE_NONE,
795 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
796 },
797 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
798 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
799 .rasterizationSamples = 1,
800 .sampleShadingEnable = false,
801 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
802 },
803 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
804 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
805 .attachmentCount = 1,
806 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
807 { .colorWriteMask =
808 VK_COLOR_COMPONENT_A_BIT |
809 VK_COLOR_COMPONENT_R_BIT |
810 VK_COLOR_COMPONENT_G_BIT |
811 VK_COLOR_COMPONENT_B_BIT },
812 }
813 },
814 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
815 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
816 .dynamicStateCount = 4,
817 .pDynamicStates = (VkDynamicState[]) {
818 VK_DYNAMIC_STATE_VIEWPORT,
819 VK_DYNAMIC_STATE_SCISSOR,
820 VK_DYNAMIC_STATE_LINE_WIDTH,
821 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
822 },
823 },
824 .flags = 0,
825 .layout = device->meta_state.blit.pipeline_layout,
826 .renderPass = device->meta_state.blit.render_pass[key],
827 .subpass = 0,
828 };
829
830 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
831 .use_rectlist = true
832 };
833
834 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
835 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
836 radv_pipeline_cache_to_handle(&device->meta_state.cache),
837 &vk_pipeline_info, &radv_pipeline_info,
838 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
839 if (result != VK_SUCCESS)
840 goto fail;
841
842 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
843 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
844 radv_pipeline_cache_to_handle(&device->meta_state.cache),
845 &vk_pipeline_info, &radv_pipeline_info,
846 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
847 if (result != VK_SUCCESS)
848 goto fail;
849
850 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
851 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
852 radv_pipeline_cache_to_handle(&device->meta_state.cache),
853 &vk_pipeline_info, &radv_pipeline_info,
854 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
855 if (result != VK_SUCCESS)
856 goto fail;
857
858 }
859
860 result = VK_SUCCESS;
861 fail:
862 ralloc_free(fs_1d.nir);
863 ralloc_free(fs_2d.nir);
864 ralloc_free(fs_3d.nir);
865 return result;
866 }
867
868 static VkResult
869 radv_device_init_meta_blit_depth(struct radv_device *device,
870 struct radv_shader_module *vs)
871 {
872 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
873 VkResult result;
874
875 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
876 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
877 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
878
879 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
880 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
881 result = radv_CreateRenderPass(radv_device_to_handle(device),
882 &(VkRenderPassCreateInfo) {
883 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
884 .attachmentCount = 1,
885 .pAttachments = &(VkAttachmentDescription) {
886 .format = VK_FORMAT_D32_SFLOAT,
887 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
888 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
889 .initialLayout = layout,
890 .finalLayout = layout,
891 },
892 .subpassCount = 1,
893 .pSubpasses = &(VkSubpassDescription) {
894 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
895 .inputAttachmentCount = 0,
896 .colorAttachmentCount = 0,
897 .pColorAttachments = NULL,
898 .pResolveAttachments = NULL,
899 .pDepthStencilAttachment = &(VkAttachmentReference) {
900 .attachment = 0,
901 .layout = layout,
902 },
903 .preserveAttachmentCount = 1,
904 .pPreserveAttachments = (uint32_t[]) { 0 },
905 },
906 .dependencyCount = 0,
907 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
908 if (result != VK_SUCCESS)
909 goto fail;
910 }
911
912 VkPipelineVertexInputStateCreateInfo vi_create_info = {
913 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
914 .vertexBindingDescriptionCount = 0,
915 .vertexAttributeDescriptionCount = 0,
916 };
917
918 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
919 {
920 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
921 .stage = VK_SHADER_STAGE_VERTEX_BIT,
922 .module = radv_shader_module_to_handle(vs),
923 .pName = "main",
924 .pSpecializationInfo = NULL
925 }, {
926 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
927 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
928 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
929 .pName = "main",
930 .pSpecializationInfo = NULL
931 },
932 };
933
934 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
935 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
936 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
937 .pStages = pipeline_shader_stages,
938 .pVertexInputState = &vi_create_info,
939 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
940 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
941 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
942 .primitiveRestartEnable = false,
943 },
944 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
945 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
946 .viewportCount = 1,
947 .scissorCount = 1,
948 },
949 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
950 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
951 .rasterizerDiscardEnable = false,
952 .polygonMode = VK_POLYGON_MODE_FILL,
953 .cullMode = VK_CULL_MODE_NONE,
954 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
955 },
956 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
957 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
958 .rasterizationSamples = 1,
959 .sampleShadingEnable = false,
960 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
961 },
962 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
963 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
964 .attachmentCount = 0,
965 .pAttachments = NULL,
966 },
967 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
968 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
969 .depthTestEnable = true,
970 .depthWriteEnable = true,
971 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
972 },
973 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
974 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
975 .dynamicStateCount = 9,
976 .pDynamicStates = (VkDynamicState[]) {
977 VK_DYNAMIC_STATE_VIEWPORT,
978 VK_DYNAMIC_STATE_SCISSOR,
979 VK_DYNAMIC_STATE_LINE_WIDTH,
980 VK_DYNAMIC_STATE_DEPTH_BIAS,
981 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
982 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
983 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
984 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
985 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
986 },
987 },
988 .flags = 0,
989 .layout = device->meta_state.blit.pipeline_layout,
990 .renderPass = device->meta_state.blit.depth_only_rp[0],
991 .subpass = 0,
992 };
993
994 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
995 .use_rectlist = true
996 };
997
998 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
999 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1000 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1001 &vk_pipeline_info, &radv_pipeline_info,
1002 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1003 if (result != VK_SUCCESS)
1004 goto fail;
1005
1006 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1007 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1008 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1009 &vk_pipeline_info, &radv_pipeline_info,
1010 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1011 if (result != VK_SUCCESS)
1012 goto fail;
1013
1014 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1015 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1016 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1017 &vk_pipeline_info, &radv_pipeline_info,
1018 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1019 if (result != VK_SUCCESS)
1020 goto fail;
1021
1022 fail:
1023 ralloc_free(fs_1d.nir);
1024 ralloc_free(fs_2d.nir);
1025 ralloc_free(fs_3d.nir);
1026 return result;
1027 }
1028
1029 static VkResult
1030 radv_device_init_meta_blit_stencil(struct radv_device *device,
1031 struct radv_shader_module *vs)
1032 {
1033 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1034 VkResult result;
1035
1036 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1037 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1038 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1039
1040 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1041 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1042 result = radv_CreateRenderPass(radv_device_to_handle(device),
1043 &(VkRenderPassCreateInfo) {
1044 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1045 .attachmentCount = 1,
1046 .pAttachments = &(VkAttachmentDescription) {
1047 .format = VK_FORMAT_S8_UINT,
1048 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1049 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1050 .initialLayout = layout,
1051 .finalLayout = layout,
1052 },
1053 .subpassCount = 1,
1054 .pSubpasses = &(VkSubpassDescription) {
1055 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1056 .inputAttachmentCount = 0,
1057 .colorAttachmentCount = 0,
1058 .pColorAttachments = NULL,
1059 .pResolveAttachments = NULL,
1060 .pDepthStencilAttachment = &(VkAttachmentReference) {
1061 .attachment = 0,
1062 .layout = layout,
1063 },
1064 .preserveAttachmentCount = 1,
1065 .pPreserveAttachments = (uint32_t[]) { 0 },
1066 },
1067 .dependencyCount = 0,
1068 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
1069 }
1070 if (result != VK_SUCCESS)
1071 goto fail;
1072
1073 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1074 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1075 .vertexBindingDescriptionCount = 0,
1076 .vertexAttributeDescriptionCount = 0,
1077 };
1078
1079 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1080 {
1081 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1082 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1083 .module = radv_shader_module_to_handle(vs),
1084 .pName = "main",
1085 .pSpecializationInfo = NULL
1086 }, {
1087 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1088 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1089 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1090 .pName = "main",
1091 .pSpecializationInfo = NULL
1092 },
1093 };
1094
1095 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1096 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1097 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1098 .pStages = pipeline_shader_stages,
1099 .pVertexInputState = &vi_create_info,
1100 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1101 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1102 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1103 .primitiveRestartEnable = false,
1104 },
1105 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1106 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1107 .viewportCount = 1,
1108 .scissorCount = 1,
1109 },
1110 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1111 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1112 .rasterizerDiscardEnable = false,
1113 .polygonMode = VK_POLYGON_MODE_FILL,
1114 .cullMode = VK_CULL_MODE_NONE,
1115 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1116 },
1117 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1118 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1119 .rasterizationSamples = 1,
1120 .sampleShadingEnable = false,
1121 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1122 },
1123 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1124 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1125 .attachmentCount = 0,
1126 .pAttachments = NULL,
1127 },
1128 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1129 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1130 .depthTestEnable = false,
1131 .depthWriteEnable = false,
1132 .stencilTestEnable = true,
1133 .front = {
1134 .failOp = VK_STENCIL_OP_REPLACE,
1135 .passOp = VK_STENCIL_OP_REPLACE,
1136 .depthFailOp = VK_STENCIL_OP_REPLACE,
1137 .compareOp = VK_COMPARE_OP_ALWAYS,
1138 .compareMask = 0xff,
1139 .writeMask = 0xff,
1140 .reference = 0
1141 },
1142 .back = {
1143 .failOp = VK_STENCIL_OP_REPLACE,
1144 .passOp = VK_STENCIL_OP_REPLACE,
1145 .depthFailOp = VK_STENCIL_OP_REPLACE,
1146 .compareOp = VK_COMPARE_OP_ALWAYS,
1147 .compareMask = 0xff,
1148 .writeMask = 0xff,
1149 .reference = 0
1150 },
1151 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1152 },
1153 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1154 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1155 .dynamicStateCount = 6,
1156 .pDynamicStates = (VkDynamicState[]) {
1157 VK_DYNAMIC_STATE_VIEWPORT,
1158 VK_DYNAMIC_STATE_SCISSOR,
1159 VK_DYNAMIC_STATE_LINE_WIDTH,
1160 VK_DYNAMIC_STATE_DEPTH_BIAS,
1161 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1162 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1163 },
1164 },
1165 .flags = 0,
1166 .layout = device->meta_state.blit.pipeline_layout,
1167 .renderPass = device->meta_state.blit.stencil_only_rp[0],
1168 .subpass = 0,
1169 };
1170
1171 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1172 .use_rectlist = true
1173 };
1174
1175 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1176 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1177 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1178 &vk_pipeline_info, &radv_pipeline_info,
1179 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1180 if (result != VK_SUCCESS)
1181 goto fail;
1182
1183 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1184 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1185 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1186 &vk_pipeline_info, &radv_pipeline_info,
1187 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1188 if (result != VK_SUCCESS)
1189 goto fail;
1190
1191 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1192 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1193 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1194 &vk_pipeline_info, &radv_pipeline_info,
1195 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1196 if (result != VK_SUCCESS)
1197 goto fail;
1198
1199
1200 fail:
1201 ralloc_free(fs_1d.nir);
1202 ralloc_free(fs_2d.nir);
1203 ralloc_free(fs_3d.nir);
1204 return result;
1205 }
1206
1207 VkResult
1208 radv_device_init_meta_blit_state(struct radv_device *device)
1209 {
1210 VkResult result;
1211 struct radv_shader_module vs = {0};
1212
1213 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1214 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1215 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1216 .bindingCount = 1,
1217 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1218 {
1219 .binding = 0,
1220 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1221 .descriptorCount = 1,
1222 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1223 .pImmutableSamplers = NULL
1224 },
1225 }
1226 };
1227 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1228 &ds_layout_info,
1229 &device->meta_state.alloc,
1230 &device->meta_state.blit.ds_layout);
1231 if (result != VK_SUCCESS)
1232 goto fail;
1233
1234 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1235
1236 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1237 &(VkPipelineLayoutCreateInfo) {
1238 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1239 .setLayoutCount = 1,
1240 .pSetLayouts = &device->meta_state.blit.ds_layout,
1241 .pushConstantRangeCount = 1,
1242 .pPushConstantRanges = &push_constant_range,
1243 },
1244 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1245 if (result != VK_SUCCESS)
1246 goto fail;
1247
1248 vs.nir = build_nir_vertex_shader();
1249
1250 result = radv_device_init_meta_blit_color(device, &vs);
1251 if (result != VK_SUCCESS)
1252 goto fail;
1253
1254 result = radv_device_init_meta_blit_depth(device, &vs);
1255 if (result != VK_SUCCESS)
1256 goto fail;
1257
1258 result = radv_device_init_meta_blit_stencil(device, &vs);
1259
1260 fail:
1261 ralloc_free(vs.nir);
1262 if (result != VK_SUCCESS)
1263 radv_device_finish_meta_blit_state(device);
1264 return result;
1265 }