2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
28 VkOffset3D src_offset
;
29 VkExtent3D src_extent
;
30 VkOffset3D dest_offset
;
31 VkExtent3D dest_extent
;
35 build_nir_vertex_shader(void)
37 const struct glsl_type
*vec4
= glsl_vec4_type();
40 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
41 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit_vs");
43 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
45 pos_out
->data
.location
= VARYING_SLOT_POS
;
47 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
49 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
50 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
52 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
54 nir_store_var(&b
, pos_out
, outvec
, 0xf);
56 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
57 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
58 nir_intrinsic_set_base(src_box
, 0);
59 nir_intrinsic_set_range(src_box
, 16);
60 src_box
->num_components
= 4;
61 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
62 nir_builder_instr_insert(&b
, &src_box
->instr
);
64 nir_intrinsic_instr
*src0_z
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
65 src0_z
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
66 nir_intrinsic_set_base(src0_z
, 16);
67 nir_intrinsic_set_range(src0_z
, 4);
68 src0_z
->num_components
= 1;
69 nir_ssa_dest_init(&src0_z
->instr
, &src0_z
->dest
, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b
, &src0_z
->instr
);
72 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
73 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
82 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
84 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
88 comp
[0] = nir_bcsel(&b
, c0cmp
,
89 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
90 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
92 comp
[1] = nir_bcsel(&b
, c1cmp
,
93 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
94 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
95 comp
[2] = &src0_z
->dest
.ssa
;
96 comp
[3] = nir_imm_float(&b
, 1.0);
97 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 4);
98 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0xf);
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim
)
105 char shader_name
[64];
106 const struct glsl_type
*vec4
= glsl_vec4_type();
109 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
111 sprintf(shader_name
, "meta_blit_fs.%d", tex_dim
);
112 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
114 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
116 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
118 /* Swizzle the array index which comes in as Z coordinate into the right
121 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
122 nir_ssa_def
*const tex_pos
=
123 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
124 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
126 const struct glsl_type
*sampler_type
=
127 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
128 glsl_get_base_type(vec4
));
129 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
130 sampler_type
, "s_tex");
131 sampler
->data
.descriptor_set
= 0;
132 sampler
->data
.binding
= 0;
134 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
135 tex
->sampler_dim
= tex_dim
;
136 tex
->op
= nir_texop_tex
;
137 tex
->src
[0].src_type
= nir_tex_src_coord
;
138 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
139 tex
->dest_type
= nir_type_float
; /* TODO */
140 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
141 tex
->coord_components
= tex_pos
->num_components
;
142 tex
->texture
= nir_deref_var_create(tex
, sampler
);
143 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
145 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
146 nir_builder_instr_insert(&b
, &tex
->instr
);
148 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
150 color_out
->data
.location
= FRAG_RESULT_DATA0
;
151 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0xf);
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim
)
159 char shader_name
[64];
160 const struct glsl_type
*vec4
= glsl_vec4_type();
163 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
165 sprintf(shader_name
, "meta_blit_depth_fs.%d", tex_dim
);
166 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
168 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
170 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
172 /* Swizzle the array index which comes in as Z coordinate into the right
175 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
176 nir_ssa_def
*const tex_pos
=
177 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
178 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
180 const struct glsl_type
*sampler_type
=
181 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
182 glsl_get_base_type(vec4
));
183 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
184 sampler_type
, "s_tex");
185 sampler
->data
.descriptor_set
= 0;
186 sampler
->data
.binding
= 0;
188 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
189 tex
->sampler_dim
= tex_dim
;
190 tex
->op
= nir_texop_tex
;
191 tex
->src
[0].src_type
= nir_tex_src_coord
;
192 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
193 tex
->dest_type
= nir_type_float
; /* TODO */
194 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
195 tex
->coord_components
= tex_pos
->num_components
;
196 tex
->texture
= nir_deref_var_create(tex
, sampler
);
197 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
199 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
200 nir_builder_instr_insert(&b
, &tex
->instr
);
202 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
204 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
205 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim
)
213 char shader_name
[64];
214 const struct glsl_type
*vec4
= glsl_vec4_type();
217 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
219 sprintf(shader_name
, "meta_blit_stencil_fs.%d", tex_dim
);
220 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
222 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
224 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
226 /* Swizzle the array index which comes in as Z coordinate into the right
229 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
230 nir_ssa_def
*const tex_pos
=
231 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
232 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
234 const struct glsl_type
*sampler_type
=
235 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
236 glsl_get_base_type(vec4
));
237 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
238 sampler_type
, "s_tex");
239 sampler
->data
.descriptor_set
= 0;
240 sampler
->data
.binding
= 0;
242 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
243 tex
->sampler_dim
= tex_dim
;
244 tex
->op
= nir_texop_tex
;
245 tex
->src
[0].src_type
= nir_tex_src_coord
;
246 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
247 tex
->dest_type
= nir_type_float
; /* TODO */
248 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
249 tex
->coord_components
= tex_pos
->num_components
;
250 tex
->texture
= nir_deref_var_create(tex
, sampler
);
251 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
253 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
254 nir_builder_instr_insert(&b
, &tex
->instr
);
256 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
258 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
259 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
265 meta_emit_blit(struct radv_cmd_buffer
*cmd_buffer
,
266 struct radv_image
*src_image
,
267 struct radv_image_view
*src_iview
,
268 VkOffset3D src_offset_0
,
269 VkOffset3D src_offset_1
,
270 struct radv_image
*dest_image
,
271 struct radv_image_view
*dest_iview
,
272 VkOffset3D dest_offset_0
,
273 VkOffset3D dest_offset_1
,
275 VkFilter blit_filter
)
277 struct radv_device
*device
= cmd_buffer
->device
;
279 assert(src_image
->info
.samples
== dest_image
->info
.samples
);
281 float vertex_push_constants
[5] = {
282 (float)src_offset_0
.x
/ (float)src_iview
->extent
.width
,
283 (float)src_offset_0
.y
/ (float)src_iview
->extent
.height
,
284 (float)src_offset_1
.x
/ (float)src_iview
->extent
.width
,
285 (float)src_offset_1
.y
/ (float)src_iview
->extent
.height
,
286 (float)src_offset_0
.z
/ (float)src_iview
->extent
.depth
,
289 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
290 device
->meta_state
.blit
.pipeline_layout
,
291 VK_SHADER_STAGE_VERTEX_BIT
, 0, 20,
292 vertex_push_constants
);
295 radv_CreateSampler(radv_device_to_handle(device
),
296 &(VkSamplerCreateInfo
) {
297 .sType
= VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
,
298 .magFilter
= blit_filter
,
299 .minFilter
= blit_filter
,
300 .addressModeU
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
301 .addressModeV
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
302 .addressModeW
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
303 }, &cmd_buffer
->pool
->alloc
, &sampler
);
306 radv_CreateFramebuffer(radv_device_to_handle(device
),
307 &(VkFramebufferCreateInfo
) {
308 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
309 .attachmentCount
= 1,
310 .pAttachments
= (VkImageView
[]) {
311 radv_image_view_to_handle(dest_iview
),
313 .width
= dest_iview
->extent
.width
,
314 .height
= dest_iview
->extent
.height
,
316 }, &cmd_buffer
->pool
->alloc
, &fb
);
318 switch (src_iview
->aspect_mask
) {
319 case VK_IMAGE_ASPECT_COLOR_BIT
: {
320 unsigned fs_key
= radv_format_meta_fs_key(dest_image
->vk_format
);
322 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
323 &(VkRenderPassBeginInfo
) {
324 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
325 .renderPass
= device
->meta_state
.blit
.render_pass
[fs_key
],
328 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
329 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
331 .clearValueCount
= 0,
332 .pClearValues
= NULL
,
333 }, VK_SUBPASS_CONTENTS_INLINE
);
334 switch (src_image
->type
) {
335 case VK_IMAGE_TYPE_1D
:
336 pipeline
= device
->meta_state
.blit
.pipeline_1d_src
[fs_key
];
338 case VK_IMAGE_TYPE_2D
:
339 pipeline
= device
->meta_state
.blit
.pipeline_2d_src
[fs_key
];
341 case VK_IMAGE_TYPE_3D
:
342 pipeline
= device
->meta_state
.blit
.pipeline_3d_src
[fs_key
];
345 unreachable(!"bad VkImageType");
349 case VK_IMAGE_ASPECT_DEPTH_BIT
:
350 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
351 &(VkRenderPassBeginInfo
) {
352 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
353 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
356 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
357 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
359 .clearValueCount
= 0,
360 .pClearValues
= NULL
,
361 }, VK_SUBPASS_CONTENTS_INLINE
);
362 switch (src_image
->type
) {
363 case VK_IMAGE_TYPE_1D
:
364 pipeline
= device
->meta_state
.blit
.depth_only_1d_pipeline
;
366 case VK_IMAGE_TYPE_2D
:
367 pipeline
= device
->meta_state
.blit
.depth_only_2d_pipeline
;
369 case VK_IMAGE_TYPE_3D
:
370 pipeline
= device
->meta_state
.blit
.depth_only_3d_pipeline
;
373 unreachable(!"bad VkImageType");
376 case VK_IMAGE_ASPECT_STENCIL_BIT
:
377 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
378 &(VkRenderPassBeginInfo
) {
379 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
380 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
383 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
384 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
386 .clearValueCount
= 0,
387 .pClearValues
= NULL
,
388 }, VK_SUBPASS_CONTENTS_INLINE
);
389 switch (src_image
->type
) {
390 case VK_IMAGE_TYPE_1D
:
391 pipeline
= device
->meta_state
.blit
.stencil_only_1d_pipeline
;
393 case VK_IMAGE_TYPE_2D
:
394 pipeline
= device
->meta_state
.blit
.stencil_only_2d_pipeline
;
396 case VK_IMAGE_TYPE_3D
:
397 pipeline
= device
->meta_state
.blit
.stencil_only_3d_pipeline
;
400 unreachable(!"bad VkImageType");
404 unreachable(!"bad VkImageType");
407 if (cmd_buffer
->state
.pipeline
!= radv_pipeline_from_handle(pipeline
)) {
408 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
409 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
412 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
413 device
->meta_state
.blit
.pipeline_layout
,
415 1, /* descriptorWriteCount */
416 (VkWriteDescriptorSet
[]) {
418 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
420 .dstArrayElement
= 0,
421 .descriptorCount
= 1,
422 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
423 .pImageInfo
= (VkDescriptorImageInfo
[]) {
426 .imageView
= radv_image_view_to_handle(src_iview
),
427 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
433 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
434 .x
= dest_offset_0
.x
,
435 .y
= dest_offset_0
.y
,
436 .width
= dest_offset_1
.x
- dest_offset_0
.x
,
437 .height
= dest_offset_1
.y
- dest_offset_0
.y
,
442 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
443 .offset
= (VkOffset2D
) { MIN2(dest_offset_0
.x
, dest_offset_1
.x
), MIN2(dest_offset_0
.y
, dest_offset_1
.y
) },
444 .extent
= (VkExtent2D
) {
445 abs(dest_offset_1
.x
- dest_offset_0
.x
),
446 abs(dest_offset_1
.y
- dest_offset_0
.y
)
450 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
452 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
454 /* At the point where we emit the draw call, all data from the
455 * descriptor sets, etc. has been used. We are free to delete it.
457 /* TODO: above comment is not valid for at least descriptor sets/pools,
458 * as we may not free them till after execution finishes. Check others. */
460 radv_DestroySampler(radv_device_to_handle(device
), sampler
,
461 &cmd_buffer
->pool
->alloc
);
462 radv_DestroyFramebuffer(radv_device_to_handle(device
), fb
,
463 &cmd_buffer
->pool
->alloc
);
467 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
471 unsigned tmp
= *src0
;
478 unsigned tmp
= *dst0
;
486 void radv_CmdBlitImage(
487 VkCommandBuffer commandBuffer
,
489 VkImageLayout srcImageLayout
,
491 VkImageLayout destImageLayout
,
492 uint32_t regionCount
,
493 const VkImageBlit
* pRegions
,
497 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
498 RADV_FROM_HANDLE(radv_image
, src_image
, srcImage
);
499 RADV_FROM_HANDLE(radv_image
, dest_image
, destImage
);
500 struct radv_meta_saved_state saved_state
;
502 /* From the Vulkan 1.0 spec:
504 * vkCmdBlitImage must not be used for multisampled source or
505 * destination images. Use vkCmdResolveImage for this purpose.
507 assert(src_image
->info
.samples
== 1);
508 assert(dest_image
->info
.samples
== 1);
510 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
, cmd_buffer
);
512 for (unsigned r
= 0; r
< regionCount
; r
++) {
513 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
514 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
515 struct radv_image_view src_iview
;
516 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
517 &(VkImageViewCreateInfo
) {
518 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
520 .viewType
= radv_meta_get_view_type(src_image
),
521 .format
= src_image
->vk_format
,
522 .subresourceRange
= {
523 .aspectMask
= src_res
->aspectMask
,
524 .baseMipLevel
= src_res
->mipLevel
,
526 .baseArrayLayer
= src_res
->baseArrayLayer
,
531 unsigned dst_start
, dst_end
;
532 if (dest_image
->type
== VK_IMAGE_TYPE_3D
) {
533 assert(dst_res
->baseArrayLayer
== 0);
534 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
535 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
537 dst_start
= dst_res
->baseArrayLayer
;
538 dst_end
= dst_start
+ dst_res
->layerCount
;
541 unsigned src_start
, src_end
;
542 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
543 assert(src_res
->baseArrayLayer
== 0);
544 src_start
= pRegions
[r
].srcOffsets
[0].z
;
545 src_end
= pRegions
[r
].srcOffsets
[1].z
;
547 src_start
= src_res
->baseArrayLayer
;
548 src_end
= src_start
+ src_res
->layerCount
;
551 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
552 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
553 (float)(dst_end
+ 1 - dst_start
);
560 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
561 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
562 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
563 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
565 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
566 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
567 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
568 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
571 dest_box
.offset
.x
= MIN2(dst_x0
, dst_x1
);
572 dest_box
.offset
.y
= MIN2(dst_y0
, dst_y1
);
573 dest_box
.extent
.width
= abs(dst_x1
- dst_x0
);
574 dest_box
.extent
.height
= abs(dst_y1
- dst_y0
);
576 struct radv_image_view dest_iview
;
577 const unsigned num_layers
= dst_end
- dst_start
;
578 for (unsigned i
= 0; i
< num_layers
; i
++) {
579 const VkOffset3D dest_offset_0
= {
584 const VkOffset3D dest_offset_1
= {
589 VkOffset3D src_offset_0
= {
592 .z
= src_start
+ i
* src_z_step
,
594 VkOffset3D src_offset_1
= {
597 .z
= src_start
+ i
* src_z_step
,
599 const uint32_t dest_array_slice
=
600 radv_meta_get_iview_layer(dest_image
, dst_res
,
603 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
604 &(VkImageViewCreateInfo
) {
605 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
607 .viewType
= radv_meta_get_view_type(dest_image
),
608 .format
= dest_image
->vk_format
,
609 .subresourceRange
= {
610 .aspectMask
= dst_res
->aspectMask
,
611 .baseMipLevel
= dst_res
->mipLevel
,
613 .baseArrayLayer
= dest_array_slice
,
617 meta_emit_blit(cmd_buffer
,
618 src_image
, &src_iview
,
619 src_offset_0
, src_offset_1
,
620 dest_image
, &dest_iview
,
621 dest_offset_0
, dest_offset_1
,
627 radv_meta_restore(&saved_state
, cmd_buffer
);
631 radv_device_finish_meta_blit_state(struct radv_device
*device
)
633 for (unsigned i
= 0; i
< NUM_META_FS_KEYS
; ++i
) {
634 if (device
->meta_state
.blit
.render_pass
[i
])
635 radv_DestroyRenderPass(radv_device_to_handle(device
),
636 device
->meta_state
.blit
.render_pass
[i
],
637 &device
->meta_state
.alloc
);
638 if (device
->meta_state
.blit
.pipeline_1d_src
[i
])
639 radv_DestroyPipeline(radv_device_to_handle(device
),
640 device
->meta_state
.blit
.pipeline_1d_src
[i
],
641 &device
->meta_state
.alloc
);
642 if (device
->meta_state
.blit
.pipeline_2d_src
[i
])
643 radv_DestroyPipeline(radv_device_to_handle(device
),
644 device
->meta_state
.blit
.pipeline_2d_src
[i
],
645 &device
->meta_state
.alloc
);
646 if (device
->meta_state
.blit
.pipeline_3d_src
[i
])
647 radv_DestroyPipeline(radv_device_to_handle(device
),
648 device
->meta_state
.blit
.pipeline_3d_src
[i
],
649 &device
->meta_state
.alloc
);
652 if (device
->meta_state
.blit
.depth_only_rp
)
653 radv_DestroyRenderPass(radv_device_to_handle(device
),
654 device
->meta_state
.blit
.depth_only_rp
,
655 &device
->meta_state
.alloc
);
656 if (device
->meta_state
.blit
.depth_only_1d_pipeline
)
657 radv_DestroyPipeline(radv_device_to_handle(device
),
658 device
->meta_state
.blit
.depth_only_1d_pipeline
,
659 &device
->meta_state
.alloc
);
660 if (device
->meta_state
.blit
.depth_only_2d_pipeline
)
661 radv_DestroyPipeline(radv_device_to_handle(device
),
662 device
->meta_state
.blit
.depth_only_2d_pipeline
,
663 &device
->meta_state
.alloc
);
664 if (device
->meta_state
.blit
.depth_only_3d_pipeline
)
665 radv_DestroyPipeline(radv_device_to_handle(device
),
666 device
->meta_state
.blit
.depth_only_3d_pipeline
,
667 &device
->meta_state
.alloc
);
668 if (device
->meta_state
.blit
.stencil_only_rp
)
669 radv_DestroyRenderPass(radv_device_to_handle(device
),
670 device
->meta_state
.blit
.stencil_only_rp
,
671 &device
->meta_state
.alloc
);
672 if (device
->meta_state
.blit
.stencil_only_1d_pipeline
)
673 radv_DestroyPipeline(radv_device_to_handle(device
),
674 device
->meta_state
.blit
.stencil_only_1d_pipeline
,
675 &device
->meta_state
.alloc
);
676 if (device
->meta_state
.blit
.stencil_only_2d_pipeline
)
677 radv_DestroyPipeline(radv_device_to_handle(device
),
678 device
->meta_state
.blit
.stencil_only_2d_pipeline
,
679 &device
->meta_state
.alloc
);
680 if (device
->meta_state
.blit
.stencil_only_3d_pipeline
)
681 radv_DestroyPipeline(radv_device_to_handle(device
),
682 device
->meta_state
.blit
.stencil_only_3d_pipeline
,
683 &device
->meta_state
.alloc
);
684 if (device
->meta_state
.blit
.pipeline_layout
)
685 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
686 device
->meta_state
.blit
.pipeline_layout
,
687 &device
->meta_state
.alloc
);
688 if (device
->meta_state
.blit
.ds_layout
)
689 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
690 device
->meta_state
.blit
.ds_layout
,
691 &device
->meta_state
.alloc
);
694 static VkFormat pipeline_formats
[] = {
695 VK_FORMAT_R8G8B8A8_UNORM
,
696 VK_FORMAT_R8G8B8A8_UINT
,
697 VK_FORMAT_R8G8B8A8_SINT
,
698 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
699 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
700 VK_FORMAT_R16G16B16A16_UNORM
,
701 VK_FORMAT_R16G16B16A16_SNORM
,
702 VK_FORMAT_R16G16B16A16_UINT
,
703 VK_FORMAT_R16G16B16A16_SINT
,
704 VK_FORMAT_R32_SFLOAT
,
705 VK_FORMAT_R32G32_SFLOAT
,
706 VK_FORMAT_R32G32B32A32_SFLOAT
710 radv_device_init_meta_blit_color(struct radv_device
*device
,
711 struct radv_shader_module
*vs
)
713 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
716 fs_1d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D
);
717 fs_2d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D
);
718 fs_3d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D
);
720 for (unsigned i
= 0; i
< ARRAY_SIZE(pipeline_formats
); ++i
) {
721 unsigned key
= radv_format_meta_fs_key(pipeline_formats
[i
]);
722 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
723 &(VkRenderPassCreateInfo
) {
724 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
725 .attachmentCount
= 1,
726 .pAttachments
= &(VkAttachmentDescription
) {
727 .format
= pipeline_formats
[i
],
728 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
729 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
730 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
731 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
734 .pSubpasses
= &(VkSubpassDescription
) {
735 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
736 .inputAttachmentCount
= 0,
737 .colorAttachmentCount
= 1,
738 .pColorAttachments
= &(VkAttachmentReference
) {
740 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
742 .pResolveAttachments
= NULL
,
743 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
744 .attachment
= VK_ATTACHMENT_UNUSED
,
745 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
747 .preserveAttachmentCount
= 1,
748 .pPreserveAttachments
= (uint32_t[]) { 0 },
750 .dependencyCount
= 0,
751 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.render_pass
[key
]);
752 if (result
!= VK_SUCCESS
)
755 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
756 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
757 .vertexBindingDescriptionCount
= 0,
758 .vertexAttributeDescriptionCount
= 0,
761 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
763 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
764 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
765 .module
= radv_shader_module_to_handle(vs
),
767 .pSpecializationInfo
= NULL
769 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
770 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
771 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
773 .pSpecializationInfo
= NULL
777 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
778 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
779 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
780 .pStages
= pipeline_shader_stages
,
781 .pVertexInputState
= &vi_create_info
,
782 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
783 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
784 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
785 .primitiveRestartEnable
= false,
787 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
788 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
792 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
793 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
794 .rasterizerDiscardEnable
= false,
795 .polygonMode
= VK_POLYGON_MODE_FILL
,
796 .cullMode
= VK_CULL_MODE_NONE
,
797 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
799 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
800 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
801 .rasterizationSamples
= 1,
802 .sampleShadingEnable
= false,
803 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
805 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
806 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
807 .attachmentCount
= 1,
808 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
810 VK_COLOR_COMPONENT_A_BIT
|
811 VK_COLOR_COMPONENT_R_BIT
|
812 VK_COLOR_COMPONENT_G_BIT
|
813 VK_COLOR_COMPONENT_B_BIT
},
816 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
817 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
818 .dynamicStateCount
= 4,
819 .pDynamicStates
= (VkDynamicState
[]) {
820 VK_DYNAMIC_STATE_VIEWPORT
,
821 VK_DYNAMIC_STATE_SCISSOR
,
822 VK_DYNAMIC_STATE_LINE_WIDTH
,
823 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
827 .layout
= device
->meta_state
.blit
.pipeline_layout
,
828 .renderPass
= device
->meta_state
.blit
.render_pass
[key
],
832 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
836 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
837 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
838 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
839 &vk_pipeline_info
, &radv_pipeline_info
,
840 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_1d_src
[key
]);
841 if (result
!= VK_SUCCESS
)
844 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
845 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
846 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
847 &vk_pipeline_info
, &radv_pipeline_info
,
848 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_2d_src
[key
]);
849 if (result
!= VK_SUCCESS
)
852 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
853 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
854 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
855 &vk_pipeline_info
, &radv_pipeline_info
,
856 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_3d_src
[key
]);
857 if (result
!= VK_SUCCESS
)
864 ralloc_free(fs_1d
.nir
);
865 ralloc_free(fs_2d
.nir
);
866 ralloc_free(fs_3d
.nir
);
871 radv_device_init_meta_blit_depth(struct radv_device
*device
,
872 struct radv_shader_module
*vs
)
874 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
877 fs_1d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D
);
878 fs_2d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D
);
879 fs_3d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D
);
881 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
882 &(VkRenderPassCreateInfo
) {
883 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
884 .attachmentCount
= 1,
885 .pAttachments
= &(VkAttachmentDescription
) {
886 .format
= VK_FORMAT_D32_SFLOAT
,
887 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
888 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
889 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
890 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
893 .pSubpasses
= &(VkSubpassDescription
) {
894 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
895 .inputAttachmentCount
= 0,
896 .colorAttachmentCount
= 0,
897 .pColorAttachments
= NULL
,
898 .pResolveAttachments
= NULL
,
899 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
901 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
903 .preserveAttachmentCount
= 1,
904 .pPreserveAttachments
= (uint32_t[]) { 0 },
906 .dependencyCount
= 0,
907 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_rp
);
908 if (result
!= VK_SUCCESS
)
911 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
912 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
913 .vertexBindingDescriptionCount
= 0,
914 .vertexAttributeDescriptionCount
= 0,
917 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
919 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
920 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
921 .module
= radv_shader_module_to_handle(vs
),
923 .pSpecializationInfo
= NULL
925 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
926 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
927 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
929 .pSpecializationInfo
= NULL
933 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
934 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
935 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
936 .pStages
= pipeline_shader_stages
,
937 .pVertexInputState
= &vi_create_info
,
938 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
939 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
940 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
941 .primitiveRestartEnable
= false,
943 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
944 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
948 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
949 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
950 .rasterizerDiscardEnable
= false,
951 .polygonMode
= VK_POLYGON_MODE_FILL
,
952 .cullMode
= VK_CULL_MODE_NONE
,
953 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
955 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
956 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
957 .rasterizationSamples
= 1,
958 .sampleShadingEnable
= false,
959 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
961 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
962 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
963 .attachmentCount
= 0,
964 .pAttachments
= NULL
,
966 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
967 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
968 .depthTestEnable
= true,
969 .depthWriteEnable
= true,
970 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
972 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
973 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
974 .dynamicStateCount
= 9,
975 .pDynamicStates
= (VkDynamicState
[]) {
976 VK_DYNAMIC_STATE_VIEWPORT
,
977 VK_DYNAMIC_STATE_SCISSOR
,
978 VK_DYNAMIC_STATE_LINE_WIDTH
,
979 VK_DYNAMIC_STATE_DEPTH_BIAS
,
980 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
981 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
982 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
983 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
984 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
988 .layout
= device
->meta_state
.blit
.pipeline_layout
,
989 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
993 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
997 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
998 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
999 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1000 &vk_pipeline_info
, &radv_pipeline_info
,
1001 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_1d_pipeline
);
1002 if (result
!= VK_SUCCESS
)
1005 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
1006 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1007 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1008 &vk_pipeline_info
, &radv_pipeline_info
,
1009 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_2d_pipeline
);
1010 if (result
!= VK_SUCCESS
)
1013 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1014 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1015 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1016 &vk_pipeline_info
, &radv_pipeline_info
,
1017 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_3d_pipeline
);
1018 if (result
!= VK_SUCCESS
)
1022 ralloc_free(fs_1d
.nir
);
1023 ralloc_free(fs_2d
.nir
);
1024 ralloc_free(fs_3d
.nir
);
1029 radv_device_init_meta_blit_stencil(struct radv_device
*device
,
1030 struct radv_shader_module
*vs
)
1032 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
1035 fs_1d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D
);
1036 fs_2d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D
);
1037 fs_3d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D
);
1039 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1040 &(VkRenderPassCreateInfo
) {
1041 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1042 .attachmentCount
= 1,
1043 .pAttachments
= &(VkAttachmentDescription
) {
1044 .format
= VK_FORMAT_S8_UINT
,
1045 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1046 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1047 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1048 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1051 .pSubpasses
= &(VkSubpassDescription
) {
1052 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1053 .inputAttachmentCount
= 0,
1054 .colorAttachmentCount
= 0,
1055 .pColorAttachments
= NULL
,
1056 .pResolveAttachments
= NULL
,
1057 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1059 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
1061 .preserveAttachmentCount
= 1,
1062 .pPreserveAttachments
= (uint32_t[]) { 0 },
1064 .dependencyCount
= 0,
1065 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_rp
);
1066 if (result
!= VK_SUCCESS
)
1069 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
1070 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
1071 .vertexBindingDescriptionCount
= 0,
1072 .vertexAttributeDescriptionCount
= 0,
1075 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1077 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1078 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1079 .module
= radv_shader_module_to_handle(vs
),
1081 .pSpecializationInfo
= NULL
1083 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1084 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1085 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
1087 .pSpecializationInfo
= NULL
1091 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1092 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1093 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1094 .pStages
= pipeline_shader_stages
,
1095 .pVertexInputState
= &vi_create_info
,
1096 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1097 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1098 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1099 .primitiveRestartEnable
= false,
1101 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1102 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1106 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1107 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1108 .rasterizerDiscardEnable
= false,
1109 .polygonMode
= VK_POLYGON_MODE_FILL
,
1110 .cullMode
= VK_CULL_MODE_NONE
,
1111 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1113 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1114 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1115 .rasterizationSamples
= 1,
1116 .sampleShadingEnable
= false,
1117 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1119 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1120 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1121 .attachmentCount
= 0,
1122 .pAttachments
= NULL
,
1124 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1125 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1126 .depthTestEnable
= false,
1127 .depthWriteEnable
= false,
1128 .stencilTestEnable
= true,
1130 .failOp
= VK_STENCIL_OP_REPLACE
,
1131 .passOp
= VK_STENCIL_OP_REPLACE
,
1132 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1133 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1134 .compareMask
= 0xff,
1139 .failOp
= VK_STENCIL_OP_REPLACE
,
1140 .passOp
= VK_STENCIL_OP_REPLACE
,
1141 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1142 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1143 .compareMask
= 0xff,
1147 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1150 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1151 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1152 .dynamicStateCount
= 6,
1153 .pDynamicStates
= (VkDynamicState
[]) {
1154 VK_DYNAMIC_STATE_VIEWPORT
,
1155 VK_DYNAMIC_STATE_SCISSOR
,
1156 VK_DYNAMIC_STATE_LINE_WIDTH
,
1157 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1158 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1159 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1163 .layout
= device
->meta_state
.blit
.pipeline_layout
,
1164 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
1168 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1169 .use_rectlist
= true
1172 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
1173 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1174 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1175 &vk_pipeline_info
, &radv_pipeline_info
,
1176 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_1d_pipeline
);
1177 if (result
!= VK_SUCCESS
)
1180 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
1181 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1182 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1183 &vk_pipeline_info
, &radv_pipeline_info
,
1184 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_2d_pipeline
);
1185 if (result
!= VK_SUCCESS
)
1188 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1189 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1190 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1191 &vk_pipeline_info
, &radv_pipeline_info
,
1192 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_3d_pipeline
);
1193 if (result
!= VK_SUCCESS
)
1197 ralloc_free(fs_1d
.nir
);
1198 ralloc_free(fs_2d
.nir
);
1199 ralloc_free(fs_3d
.nir
);
1204 radv_device_init_meta_blit_state(struct radv_device
*device
)
1207 struct radv_shader_module vs
= {0};
1208 zero(device
->meta_state
.blit
);
1210 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1211 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1212 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1214 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1217 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
1218 .descriptorCount
= 1,
1219 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1220 .pImmutableSamplers
= NULL
1224 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1226 &device
->meta_state
.alloc
,
1227 &device
->meta_state
.blit
.ds_layout
);
1228 if (result
!= VK_SUCCESS
)
1231 const VkPushConstantRange push_constant_range
= {VK_SHADER_STAGE_VERTEX_BIT
, 0, 20};
1233 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1234 &(VkPipelineLayoutCreateInfo
) {
1235 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1236 .setLayoutCount
= 1,
1237 .pSetLayouts
= &device
->meta_state
.blit
.ds_layout
,
1238 .pushConstantRangeCount
= 1,
1239 .pPushConstantRanges
= &push_constant_range
,
1241 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_layout
);
1242 if (result
!= VK_SUCCESS
)
1245 vs
.nir
= build_nir_vertex_shader();
1247 result
= radv_device_init_meta_blit_color(device
, &vs
);
1248 if (result
!= VK_SUCCESS
)
1251 result
= radv_device_init_meta_blit_depth(device
, &vs
);
1252 if (result
!= VK_SUCCESS
)
1255 result
= radv_device_init_meta_blit_stencil(device
, &vs
);
1258 ralloc_free(vs
.nir
);
1259 if (result
!= VK_SUCCESS
)
1260 radv_device_finish_meta_blit_state(device
);