2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
28 VkOffset3D src_offset
;
29 VkExtent3D src_extent
;
30 VkOffset3D dest_offset
;
31 VkExtent3D dest_extent
;
35 build_nir_vertex_shader(void)
37 const struct glsl_type
*vec4
= glsl_vec4_type();
40 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
41 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit_vs");
43 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
45 pos_out
->data
.location
= VARYING_SLOT_POS
;
47 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
49 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
50 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
52 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
54 nir_store_var(&b
, pos_out
, outvec
, 0xf);
56 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
57 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
58 nir_intrinsic_set_base(src_box
, 0);
59 nir_intrinsic_set_range(src_box
, 16);
60 src_box
->num_components
= 4;
61 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
62 nir_builder_instr_insert(&b
, &src_box
->instr
);
64 nir_intrinsic_instr
*src0_z
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
65 src0_z
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
66 nir_intrinsic_set_base(src0_z
, 16);
67 nir_intrinsic_set_range(src0_z
, 4);
68 src0_z
->num_components
= 1;
69 nir_ssa_dest_init(&src0_z
->instr
, &src0_z
->dest
, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b
, &src0_z
->instr
);
72 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
73 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
82 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
84 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
88 comp
[0] = nir_bcsel(&b
, c0cmp
,
89 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
90 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
92 comp
[1] = nir_bcsel(&b
, c1cmp
,
93 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
94 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
95 comp
[2] = &src0_z
->dest
.ssa
;
96 comp
[3] = nir_imm_float(&b
, 1.0);
97 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 4);
98 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0xf);
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim
)
105 char shader_name
[64];
106 const struct glsl_type
*vec4
= glsl_vec4_type();
109 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
111 sprintf(shader_name
, "meta_blit_fs.%d", tex_dim
);
112 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
114 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
116 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
118 /* Swizzle the array index which comes in as Z coordinate into the right
121 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
122 nir_ssa_def
*const tex_pos
=
123 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
124 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
126 const struct glsl_type
*sampler_type
=
127 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
128 glsl_get_base_type(vec4
));
129 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
130 sampler_type
, "s_tex");
131 sampler
->data
.descriptor_set
= 0;
132 sampler
->data
.binding
= 0;
134 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
135 tex
->sampler_dim
= tex_dim
;
136 tex
->op
= nir_texop_tex
;
137 tex
->src
[0].src_type
= nir_tex_src_coord
;
138 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
139 tex
->dest_type
= nir_type_float
; /* TODO */
140 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
141 tex
->coord_components
= tex_pos
->num_components
;
142 tex
->texture
= nir_deref_var_create(tex
, sampler
);
143 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
145 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
146 nir_builder_instr_insert(&b
, &tex
->instr
);
148 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
150 color_out
->data
.location
= FRAG_RESULT_DATA0
;
151 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0xf);
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim
)
159 char shader_name
[64];
160 const struct glsl_type
*vec4
= glsl_vec4_type();
163 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
165 sprintf(shader_name
, "meta_blit_depth_fs.%d", tex_dim
);
166 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
168 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
170 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
172 /* Swizzle the array index which comes in as Z coordinate into the right
175 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
176 nir_ssa_def
*const tex_pos
=
177 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
178 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
180 const struct glsl_type
*sampler_type
=
181 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
182 glsl_get_base_type(vec4
));
183 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
184 sampler_type
, "s_tex");
185 sampler
->data
.descriptor_set
= 0;
186 sampler
->data
.binding
= 0;
188 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
189 tex
->sampler_dim
= tex_dim
;
190 tex
->op
= nir_texop_tex
;
191 tex
->src
[0].src_type
= nir_tex_src_coord
;
192 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
193 tex
->dest_type
= nir_type_float
; /* TODO */
194 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
195 tex
->coord_components
= tex_pos
->num_components
;
196 tex
->texture
= nir_deref_var_create(tex
, sampler
);
197 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
199 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
200 nir_builder_instr_insert(&b
, &tex
->instr
);
202 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
204 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
205 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim
)
213 char shader_name
[64];
214 const struct glsl_type
*vec4
= glsl_vec4_type();
217 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
219 sprintf(shader_name
, "meta_blit_stencil_fs.%d", tex_dim
);
220 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
222 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
224 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
226 /* Swizzle the array index which comes in as Z coordinate into the right
229 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
230 nir_ssa_def
*const tex_pos
=
231 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
232 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
234 const struct glsl_type
*sampler_type
=
235 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
236 glsl_get_base_type(vec4
));
237 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
238 sampler_type
, "s_tex");
239 sampler
->data
.descriptor_set
= 0;
240 sampler
->data
.binding
= 0;
242 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
243 tex
->sampler_dim
= tex_dim
;
244 tex
->op
= nir_texop_tex
;
245 tex
->src
[0].src_type
= nir_tex_src_coord
;
246 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
247 tex
->dest_type
= nir_type_float
; /* TODO */
248 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
249 tex
->coord_components
= tex_pos
->num_components
;
250 tex
->texture
= nir_deref_var_create(tex
, sampler
);
251 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
253 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
254 nir_builder_instr_insert(&b
, &tex
->instr
);
256 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
258 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
259 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
265 meta_emit_blit(struct radv_cmd_buffer
*cmd_buffer
,
266 struct radv_image
*src_image
,
267 struct radv_image_view
*src_iview
,
268 VkOffset3D src_offset_0
,
269 VkOffset3D src_offset_1
,
270 struct radv_image
*dest_image
,
271 struct radv_image_view
*dest_iview
,
272 VkOffset2D dest_offset_0
,
273 VkOffset2D dest_offset_1
,
275 VkFilter blit_filter
)
277 struct radv_device
*device
= cmd_buffer
->device
;
278 uint32_t src_width
= radv_minify(src_iview
->image
->info
.width
, src_iview
->base_mip
);
279 uint32_t src_height
= radv_minify(src_iview
->image
->info
.height
, src_iview
->base_mip
);
280 uint32_t src_depth
= radv_minify(src_iview
->image
->info
.depth
, src_iview
->base_mip
);
281 uint32_t dst_width
= radv_minify(dest_iview
->image
->info
.width
, dest_iview
->base_mip
);
282 uint32_t dst_height
= radv_minify(dest_iview
->image
->info
.height
, dest_iview
->base_mip
);
284 assert(src_image
->info
.samples
== dest_image
->info
.samples
);
286 float vertex_push_constants
[5] = {
287 (float)src_offset_0
.x
/ (float)src_width
,
288 (float)src_offset_0
.y
/ (float)src_height
,
289 (float)src_offset_1
.x
/ (float)src_width
,
290 (float)src_offset_1
.y
/ (float)src_height
,
291 (float)src_offset_0
.z
/ (float)src_depth
,
294 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
295 device
->meta_state
.blit
.pipeline_layout
,
296 VK_SHADER_STAGE_VERTEX_BIT
, 0, 20,
297 vertex_push_constants
);
300 radv_CreateSampler(radv_device_to_handle(device
),
301 &(VkSamplerCreateInfo
) {
302 .sType
= VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
,
303 .magFilter
= blit_filter
,
304 .minFilter
= blit_filter
,
305 .addressModeU
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
306 .addressModeV
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
307 .addressModeW
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
308 }, &cmd_buffer
->pool
->alloc
, &sampler
);
311 radv_CreateFramebuffer(radv_device_to_handle(device
),
312 &(VkFramebufferCreateInfo
) {
313 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
314 .attachmentCount
= 1,
315 .pAttachments
= (VkImageView
[]) {
316 radv_image_view_to_handle(dest_iview
),
319 .height
= dst_height
,
321 }, &cmd_buffer
->pool
->alloc
, &fb
);
323 switch (src_iview
->aspect_mask
) {
324 case VK_IMAGE_ASPECT_COLOR_BIT
: {
325 unsigned fs_key
= radv_format_meta_fs_key(dest_image
->vk_format
);
327 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
328 &(VkRenderPassBeginInfo
) {
329 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
330 .renderPass
= device
->meta_state
.blit
.render_pass
[fs_key
],
333 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
334 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
336 .clearValueCount
= 0,
337 .pClearValues
= NULL
,
338 }, VK_SUBPASS_CONTENTS_INLINE
);
339 switch (src_image
->type
) {
340 case VK_IMAGE_TYPE_1D
:
341 pipeline
= device
->meta_state
.blit
.pipeline_1d_src
[fs_key
];
343 case VK_IMAGE_TYPE_2D
:
344 pipeline
= device
->meta_state
.blit
.pipeline_2d_src
[fs_key
];
346 case VK_IMAGE_TYPE_3D
:
347 pipeline
= device
->meta_state
.blit
.pipeline_3d_src
[fs_key
];
350 unreachable(!"bad VkImageType");
354 case VK_IMAGE_ASPECT_DEPTH_BIT
:
355 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
356 &(VkRenderPassBeginInfo
) {
357 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
358 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
361 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
362 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
364 .clearValueCount
= 0,
365 .pClearValues
= NULL
,
366 }, VK_SUBPASS_CONTENTS_INLINE
);
367 switch (src_image
->type
) {
368 case VK_IMAGE_TYPE_1D
:
369 pipeline
= device
->meta_state
.blit
.depth_only_1d_pipeline
;
371 case VK_IMAGE_TYPE_2D
:
372 pipeline
= device
->meta_state
.blit
.depth_only_2d_pipeline
;
374 case VK_IMAGE_TYPE_3D
:
375 pipeline
= device
->meta_state
.blit
.depth_only_3d_pipeline
;
378 unreachable(!"bad VkImageType");
381 case VK_IMAGE_ASPECT_STENCIL_BIT
:
382 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
383 &(VkRenderPassBeginInfo
) {
384 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
385 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
388 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
389 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
391 .clearValueCount
= 0,
392 .pClearValues
= NULL
,
393 }, VK_SUBPASS_CONTENTS_INLINE
);
394 switch (src_image
->type
) {
395 case VK_IMAGE_TYPE_1D
:
396 pipeline
= device
->meta_state
.blit
.stencil_only_1d_pipeline
;
398 case VK_IMAGE_TYPE_2D
:
399 pipeline
= device
->meta_state
.blit
.stencil_only_2d_pipeline
;
401 case VK_IMAGE_TYPE_3D
:
402 pipeline
= device
->meta_state
.blit
.stencil_only_3d_pipeline
;
405 unreachable(!"bad VkImageType");
409 unreachable(!"bad VkImageType");
412 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
413 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
415 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
416 device
->meta_state
.blit
.pipeline_layout
,
418 1, /* descriptorWriteCount */
419 (VkWriteDescriptorSet
[]) {
421 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
423 .dstArrayElement
= 0,
424 .descriptorCount
= 1,
425 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
426 .pImageInfo
= (VkDescriptorImageInfo
[]) {
429 .imageView
= radv_image_view_to_handle(src_iview
),
430 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
436 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
437 .x
= dest_offset_0
.x
,
438 .y
= dest_offset_0
.y
,
439 .width
= dest_offset_1
.x
- dest_offset_0
.x
,
440 .height
= dest_offset_1
.y
- dest_offset_0
.y
,
445 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
446 .offset
= (VkOffset2D
) { MIN2(dest_offset_0
.x
, dest_offset_1
.x
), MIN2(dest_offset_0
.y
, dest_offset_1
.y
) },
447 .extent
= (VkExtent2D
) {
448 abs(dest_offset_1
.x
- dest_offset_0
.x
),
449 abs(dest_offset_1
.y
- dest_offset_0
.y
)
453 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
455 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
457 /* At the point where we emit the draw call, all data from the
458 * descriptor sets, etc. has been used. We are free to delete it.
460 /* TODO: above comment is not valid for at least descriptor sets/pools,
461 * as we may not free them till after execution finishes. Check others. */
463 radv_DestroySampler(radv_device_to_handle(device
), sampler
,
464 &cmd_buffer
->pool
->alloc
);
465 radv_DestroyFramebuffer(radv_device_to_handle(device
), fb
,
466 &cmd_buffer
->pool
->alloc
);
470 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
474 unsigned tmp
= *src0
;
481 unsigned tmp
= *dst0
;
489 void radv_CmdBlitImage(
490 VkCommandBuffer commandBuffer
,
492 VkImageLayout srcImageLayout
,
494 VkImageLayout destImageLayout
,
495 uint32_t regionCount
,
496 const VkImageBlit
* pRegions
,
500 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
501 RADV_FROM_HANDLE(radv_image
, src_image
, srcImage
);
502 RADV_FROM_HANDLE(radv_image
, dest_image
, destImage
);
503 struct radv_meta_saved_state saved_state
;
505 /* From the Vulkan 1.0 spec:
507 * vkCmdBlitImage must not be used for multisampled source or
508 * destination images. Use vkCmdResolveImage for this purpose.
510 assert(src_image
->info
.samples
== 1);
511 assert(dest_image
->info
.samples
== 1);
513 radv_meta_save(&saved_state
, cmd_buffer
,
514 RADV_META_SAVE_GRAPHICS_PIPELINE
|
515 RADV_META_SAVE_CONSTANTS
|
516 RADV_META_SAVE_DESCRIPTORS
);
518 for (unsigned r
= 0; r
< regionCount
; r
++) {
519 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
520 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
522 unsigned dst_start
, dst_end
;
523 if (dest_image
->type
== VK_IMAGE_TYPE_3D
) {
524 assert(dst_res
->baseArrayLayer
== 0);
525 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
526 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
528 dst_start
= dst_res
->baseArrayLayer
;
529 dst_end
= dst_start
+ dst_res
->layerCount
;
532 unsigned src_start
, src_end
;
533 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
534 assert(src_res
->baseArrayLayer
== 0);
535 src_start
= pRegions
[r
].srcOffsets
[0].z
;
536 src_end
= pRegions
[r
].srcOffsets
[1].z
;
538 src_start
= src_res
->baseArrayLayer
;
539 src_end
= src_start
+ src_res
->layerCount
;
542 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
543 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
544 (float)(dst_end
+ 1 - dst_start
);
551 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
552 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
553 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
554 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
556 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
557 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
558 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
559 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
562 dest_box
.offset
.x
= MIN2(dst_x0
, dst_x1
);
563 dest_box
.offset
.y
= MIN2(dst_y0
, dst_y1
);
564 dest_box
.extent
.width
= abs(dst_x1
- dst_x0
);
565 dest_box
.extent
.height
= abs(dst_y1
- dst_y0
);
567 const unsigned num_layers
= dst_end
- dst_start
;
568 for (unsigned i
= 0; i
< num_layers
; i
++) {
569 struct radv_image_view dest_iview
, src_iview
;
571 const VkOffset2D dest_offset_0
= {
575 const VkOffset2D dest_offset_1
= {
579 VkOffset3D src_offset_0
= {
582 .z
= src_start
+ i
* src_z_step
,
584 VkOffset3D src_offset_1
= {
587 .z
= src_start
+ i
* src_z_step
,
589 const uint32_t dest_array_slice
= dst_start
+ i
;
591 /* 3D images have just 1 layer */
592 const uint32_t src_array_slice
= src_image
->type
== VK_IMAGE_TYPE_3D
? 0 : src_start
+ i
;
594 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
595 &(VkImageViewCreateInfo
) {
596 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
598 .viewType
= radv_meta_get_view_type(dest_image
),
599 .format
= dest_image
->vk_format
,
600 .subresourceRange
= {
601 .aspectMask
= dst_res
->aspectMask
,
602 .baseMipLevel
= dst_res
->mipLevel
,
604 .baseArrayLayer
= dest_array_slice
,
608 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
609 &(VkImageViewCreateInfo
) {
610 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
612 .viewType
= radv_meta_get_view_type(src_image
),
613 .format
= src_image
->vk_format
,
614 .subresourceRange
= {
615 .aspectMask
= src_res
->aspectMask
,
616 .baseMipLevel
= src_res
->mipLevel
,
618 .baseArrayLayer
= src_array_slice
,
622 meta_emit_blit(cmd_buffer
,
623 src_image
, &src_iview
,
624 src_offset_0
, src_offset_1
,
625 dest_image
, &dest_iview
,
626 dest_offset_0
, dest_offset_1
,
632 radv_meta_restore(&saved_state
, cmd_buffer
);
636 radv_device_finish_meta_blit_state(struct radv_device
*device
)
638 struct radv_meta_state
*state
= &device
->meta_state
;
640 for (unsigned i
= 0; i
< NUM_META_FS_KEYS
; ++i
) {
641 radv_DestroyRenderPass(radv_device_to_handle(device
),
642 state
->blit
.render_pass
[i
],
644 radv_DestroyPipeline(radv_device_to_handle(device
),
645 state
->blit
.pipeline_1d_src
[i
],
647 radv_DestroyPipeline(radv_device_to_handle(device
),
648 state
->blit
.pipeline_2d_src
[i
],
650 radv_DestroyPipeline(radv_device_to_handle(device
),
651 state
->blit
.pipeline_3d_src
[i
],
655 radv_DestroyRenderPass(radv_device_to_handle(device
),
656 state
->blit
.depth_only_rp
, &state
->alloc
);
657 radv_DestroyPipeline(radv_device_to_handle(device
),
658 state
->blit
.depth_only_1d_pipeline
, &state
->alloc
);
659 radv_DestroyPipeline(radv_device_to_handle(device
),
660 state
->blit
.depth_only_2d_pipeline
, &state
->alloc
);
661 radv_DestroyPipeline(radv_device_to_handle(device
),
662 state
->blit
.depth_only_3d_pipeline
, &state
->alloc
);
664 radv_DestroyRenderPass(radv_device_to_handle(device
),
665 state
->blit
.stencil_only_rp
, &state
->alloc
);
666 radv_DestroyPipeline(radv_device_to_handle(device
),
667 state
->blit
.stencil_only_1d_pipeline
,
669 radv_DestroyPipeline(radv_device_to_handle(device
),
670 state
->blit
.stencil_only_2d_pipeline
,
672 radv_DestroyPipeline(radv_device_to_handle(device
),
673 state
->blit
.stencil_only_3d_pipeline
,
676 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
677 state
->blit
.pipeline_layout
, &state
->alloc
);
678 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
679 state
->blit
.ds_layout
, &state
->alloc
);
682 static VkFormat pipeline_formats
[] = {
683 VK_FORMAT_R8G8B8A8_UNORM
,
684 VK_FORMAT_R8G8B8A8_UINT
,
685 VK_FORMAT_R8G8B8A8_SINT
,
686 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
687 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
688 VK_FORMAT_R16G16B16A16_UNORM
,
689 VK_FORMAT_R16G16B16A16_SNORM
,
690 VK_FORMAT_R16G16B16A16_UINT
,
691 VK_FORMAT_R16G16B16A16_SINT
,
692 VK_FORMAT_R32_SFLOAT
,
693 VK_FORMAT_R32G32_SFLOAT
,
694 VK_FORMAT_R32G32B32A32_SFLOAT
698 radv_device_init_meta_blit_color(struct radv_device
*device
,
699 struct radv_shader_module
*vs
)
701 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
704 fs_1d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D
);
705 fs_2d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D
);
706 fs_3d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D
);
708 for (unsigned i
= 0; i
< ARRAY_SIZE(pipeline_formats
); ++i
) {
709 unsigned key
= radv_format_meta_fs_key(pipeline_formats
[i
]);
710 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
711 &(VkRenderPassCreateInfo
) {
712 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
713 .attachmentCount
= 1,
714 .pAttachments
= &(VkAttachmentDescription
) {
715 .format
= pipeline_formats
[i
],
716 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
717 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
718 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
719 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
722 .pSubpasses
= &(VkSubpassDescription
) {
723 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
724 .inputAttachmentCount
= 0,
725 .colorAttachmentCount
= 1,
726 .pColorAttachments
= &(VkAttachmentReference
) {
728 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
730 .pResolveAttachments
= NULL
,
731 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
732 .attachment
= VK_ATTACHMENT_UNUSED
,
733 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
735 .preserveAttachmentCount
= 1,
736 .pPreserveAttachments
= (uint32_t[]) { 0 },
738 .dependencyCount
= 0,
739 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.render_pass
[key
]);
740 if (result
!= VK_SUCCESS
)
743 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
744 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
745 .vertexBindingDescriptionCount
= 0,
746 .vertexAttributeDescriptionCount
= 0,
749 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
751 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
752 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
753 .module
= radv_shader_module_to_handle(vs
),
755 .pSpecializationInfo
= NULL
757 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
758 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
759 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
761 .pSpecializationInfo
= NULL
765 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
766 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
767 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
768 .pStages
= pipeline_shader_stages
,
769 .pVertexInputState
= &vi_create_info
,
770 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
771 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
772 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
773 .primitiveRestartEnable
= false,
775 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
776 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
780 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
781 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
782 .rasterizerDiscardEnable
= false,
783 .polygonMode
= VK_POLYGON_MODE_FILL
,
784 .cullMode
= VK_CULL_MODE_NONE
,
785 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
787 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
788 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
789 .rasterizationSamples
= 1,
790 .sampleShadingEnable
= false,
791 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
793 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
794 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
795 .attachmentCount
= 1,
796 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
798 VK_COLOR_COMPONENT_A_BIT
|
799 VK_COLOR_COMPONENT_R_BIT
|
800 VK_COLOR_COMPONENT_G_BIT
|
801 VK_COLOR_COMPONENT_B_BIT
},
804 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
805 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
806 .dynamicStateCount
= 4,
807 .pDynamicStates
= (VkDynamicState
[]) {
808 VK_DYNAMIC_STATE_VIEWPORT
,
809 VK_DYNAMIC_STATE_SCISSOR
,
810 VK_DYNAMIC_STATE_LINE_WIDTH
,
811 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
815 .layout
= device
->meta_state
.blit
.pipeline_layout
,
816 .renderPass
= device
->meta_state
.blit
.render_pass
[key
],
820 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
824 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
825 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
826 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
827 &vk_pipeline_info
, &radv_pipeline_info
,
828 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_1d_src
[key
]);
829 if (result
!= VK_SUCCESS
)
832 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
833 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
834 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
835 &vk_pipeline_info
, &radv_pipeline_info
,
836 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_2d_src
[key
]);
837 if (result
!= VK_SUCCESS
)
840 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
841 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
842 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
843 &vk_pipeline_info
, &radv_pipeline_info
,
844 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_3d_src
[key
]);
845 if (result
!= VK_SUCCESS
)
852 ralloc_free(fs_1d
.nir
);
853 ralloc_free(fs_2d
.nir
);
854 ralloc_free(fs_3d
.nir
);
859 radv_device_init_meta_blit_depth(struct radv_device
*device
,
860 struct radv_shader_module
*vs
)
862 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
865 fs_1d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D
);
866 fs_2d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D
);
867 fs_3d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D
);
869 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
870 &(VkRenderPassCreateInfo
) {
871 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
872 .attachmentCount
= 1,
873 .pAttachments
= &(VkAttachmentDescription
) {
874 .format
= VK_FORMAT_D32_SFLOAT
,
875 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
876 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
877 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
878 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
881 .pSubpasses
= &(VkSubpassDescription
) {
882 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
883 .inputAttachmentCount
= 0,
884 .colorAttachmentCount
= 0,
885 .pColorAttachments
= NULL
,
886 .pResolveAttachments
= NULL
,
887 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
889 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
891 .preserveAttachmentCount
= 1,
892 .pPreserveAttachments
= (uint32_t[]) { 0 },
894 .dependencyCount
= 0,
895 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_rp
);
896 if (result
!= VK_SUCCESS
)
899 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
900 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
901 .vertexBindingDescriptionCount
= 0,
902 .vertexAttributeDescriptionCount
= 0,
905 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
907 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
908 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
909 .module
= radv_shader_module_to_handle(vs
),
911 .pSpecializationInfo
= NULL
913 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
914 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
915 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
917 .pSpecializationInfo
= NULL
921 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
922 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
923 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
924 .pStages
= pipeline_shader_stages
,
925 .pVertexInputState
= &vi_create_info
,
926 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
927 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
928 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
929 .primitiveRestartEnable
= false,
931 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
932 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
936 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
937 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
938 .rasterizerDiscardEnable
= false,
939 .polygonMode
= VK_POLYGON_MODE_FILL
,
940 .cullMode
= VK_CULL_MODE_NONE
,
941 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
943 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
944 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
945 .rasterizationSamples
= 1,
946 .sampleShadingEnable
= false,
947 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
949 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
950 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
951 .attachmentCount
= 0,
952 .pAttachments
= NULL
,
954 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
955 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
956 .depthTestEnable
= true,
957 .depthWriteEnable
= true,
958 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
960 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
961 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
962 .dynamicStateCount
= 9,
963 .pDynamicStates
= (VkDynamicState
[]) {
964 VK_DYNAMIC_STATE_VIEWPORT
,
965 VK_DYNAMIC_STATE_SCISSOR
,
966 VK_DYNAMIC_STATE_LINE_WIDTH
,
967 VK_DYNAMIC_STATE_DEPTH_BIAS
,
968 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
969 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
970 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
971 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
972 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
976 .layout
= device
->meta_state
.blit
.pipeline_layout
,
977 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
981 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
985 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
986 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
987 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
988 &vk_pipeline_info
, &radv_pipeline_info
,
989 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_1d_pipeline
);
990 if (result
!= VK_SUCCESS
)
993 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
994 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
995 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
996 &vk_pipeline_info
, &radv_pipeline_info
,
997 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_2d_pipeline
);
998 if (result
!= VK_SUCCESS
)
1001 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1002 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1003 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1004 &vk_pipeline_info
, &radv_pipeline_info
,
1005 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_3d_pipeline
);
1006 if (result
!= VK_SUCCESS
)
1010 ralloc_free(fs_1d
.nir
);
1011 ralloc_free(fs_2d
.nir
);
1012 ralloc_free(fs_3d
.nir
);
1017 radv_device_init_meta_blit_stencil(struct radv_device
*device
,
1018 struct radv_shader_module
*vs
)
1020 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
1023 fs_1d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D
);
1024 fs_2d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D
);
1025 fs_3d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D
);
1027 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1028 &(VkRenderPassCreateInfo
) {
1029 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1030 .attachmentCount
= 1,
1031 .pAttachments
= &(VkAttachmentDescription
) {
1032 .format
= VK_FORMAT_S8_UINT
,
1033 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1034 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1035 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1036 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1039 .pSubpasses
= &(VkSubpassDescription
) {
1040 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1041 .inputAttachmentCount
= 0,
1042 .colorAttachmentCount
= 0,
1043 .pColorAttachments
= NULL
,
1044 .pResolveAttachments
= NULL
,
1045 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1047 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
1049 .preserveAttachmentCount
= 1,
1050 .pPreserveAttachments
= (uint32_t[]) { 0 },
1052 .dependencyCount
= 0,
1053 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_rp
);
1054 if (result
!= VK_SUCCESS
)
1057 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
1058 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
1059 .vertexBindingDescriptionCount
= 0,
1060 .vertexAttributeDescriptionCount
= 0,
1063 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1065 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1066 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1067 .module
= radv_shader_module_to_handle(vs
),
1069 .pSpecializationInfo
= NULL
1071 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1072 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1073 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
1075 .pSpecializationInfo
= NULL
1079 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1080 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1081 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1082 .pStages
= pipeline_shader_stages
,
1083 .pVertexInputState
= &vi_create_info
,
1084 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1085 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1086 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1087 .primitiveRestartEnable
= false,
1089 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1090 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1094 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1095 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1096 .rasterizerDiscardEnable
= false,
1097 .polygonMode
= VK_POLYGON_MODE_FILL
,
1098 .cullMode
= VK_CULL_MODE_NONE
,
1099 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1101 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1102 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1103 .rasterizationSamples
= 1,
1104 .sampleShadingEnable
= false,
1105 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1107 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1108 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1109 .attachmentCount
= 0,
1110 .pAttachments
= NULL
,
1112 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1113 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1114 .depthTestEnable
= false,
1115 .depthWriteEnable
= false,
1116 .stencilTestEnable
= true,
1118 .failOp
= VK_STENCIL_OP_REPLACE
,
1119 .passOp
= VK_STENCIL_OP_REPLACE
,
1120 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1121 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1122 .compareMask
= 0xff,
1127 .failOp
= VK_STENCIL_OP_REPLACE
,
1128 .passOp
= VK_STENCIL_OP_REPLACE
,
1129 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1130 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1131 .compareMask
= 0xff,
1135 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1138 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1139 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1140 .dynamicStateCount
= 6,
1141 .pDynamicStates
= (VkDynamicState
[]) {
1142 VK_DYNAMIC_STATE_VIEWPORT
,
1143 VK_DYNAMIC_STATE_SCISSOR
,
1144 VK_DYNAMIC_STATE_LINE_WIDTH
,
1145 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1146 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1147 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1151 .layout
= device
->meta_state
.blit
.pipeline_layout
,
1152 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
1156 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1157 .use_rectlist
= true
1160 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
1161 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1162 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1163 &vk_pipeline_info
, &radv_pipeline_info
,
1164 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_1d_pipeline
);
1165 if (result
!= VK_SUCCESS
)
1168 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
1169 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1170 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1171 &vk_pipeline_info
, &radv_pipeline_info
,
1172 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_2d_pipeline
);
1173 if (result
!= VK_SUCCESS
)
1176 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1177 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1178 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1179 &vk_pipeline_info
, &radv_pipeline_info
,
1180 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_3d_pipeline
);
1181 if (result
!= VK_SUCCESS
)
1185 ralloc_free(fs_1d
.nir
);
1186 ralloc_free(fs_2d
.nir
);
1187 ralloc_free(fs_3d
.nir
);
1192 radv_device_init_meta_blit_state(struct radv_device
*device
)
1195 struct radv_shader_module vs
= {0};
1197 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1198 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1199 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1201 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1204 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
1205 .descriptorCount
= 1,
1206 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1207 .pImmutableSamplers
= NULL
1211 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1213 &device
->meta_state
.alloc
,
1214 &device
->meta_state
.blit
.ds_layout
);
1215 if (result
!= VK_SUCCESS
)
1218 const VkPushConstantRange push_constant_range
= {VK_SHADER_STAGE_VERTEX_BIT
, 0, 20};
1220 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1221 &(VkPipelineLayoutCreateInfo
) {
1222 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1223 .setLayoutCount
= 1,
1224 .pSetLayouts
= &device
->meta_state
.blit
.ds_layout
,
1225 .pushConstantRangeCount
= 1,
1226 .pPushConstantRanges
= &push_constant_range
,
1228 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_layout
);
1229 if (result
!= VK_SUCCESS
)
1232 vs
.nir
= build_nir_vertex_shader();
1234 result
= radv_device_init_meta_blit_color(device
, &vs
);
1235 if (result
!= VK_SUCCESS
)
1238 result
= radv_device_init_meta_blit_depth(device
, &vs
);
1239 if (result
!= VK_SUCCESS
)
1242 result
= radv_device_init_meta_blit_stencil(device
, &vs
);
1245 ralloc_free(vs
.nir
);
1246 if (result
!= VK_SUCCESS
)
1247 radv_device_finish_meta_blit_state(device
);